Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OMAP2 McSPI controller driver |
| 3 | * |
| 4 | * Copyright (C) 2005, 2006 Nokia Corporation |
| 5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and |
| 6 | * Juha Yrjölä <juha.yrjola@nokia.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/device.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/dma-mapping.h> |
| 31 | #include <linux/platform_device.h> |
| 32 | #include <linux/err.h> |
| 33 | #include <linux/clk.h> |
| 34 | #include <linux/io.h> |
| 35 | |
| 36 | #include <linux/spi/spi.h> |
| 37 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 38 | #include <mach/dma.h> |
| 39 | #include <mach/clock.h> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 40 | |
| 41 | |
| 42 | #define OMAP2_MCSPI_MAX_FREQ 48000000 |
| 43 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 44 | /* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */ |
| 45 | #define OMAP2_MCSPI_MAX_CTRL 4 |
| 46 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 47 | #define OMAP2_MCSPI_REVISION 0x00 |
| 48 | #define OMAP2_MCSPI_SYSCONFIG 0x10 |
| 49 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
| 50 | #define OMAP2_MCSPI_IRQSTATUS 0x18 |
| 51 | #define OMAP2_MCSPI_IRQENABLE 0x1c |
| 52 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 |
| 53 | #define OMAP2_MCSPI_SYST 0x24 |
| 54 | #define OMAP2_MCSPI_MODULCTRL 0x28 |
| 55 | |
| 56 | /* per-channel banks, 0x14 bytes each, first is: */ |
| 57 | #define OMAP2_MCSPI_CHCONF0 0x2c |
| 58 | #define OMAP2_MCSPI_CHSTAT0 0x30 |
| 59 | #define OMAP2_MCSPI_CHCTRL0 0x34 |
| 60 | #define OMAP2_MCSPI_TX0 0x38 |
| 61 | #define OMAP2_MCSPI_RX0 0x3c |
| 62 | |
| 63 | /* per-register bitmasks: */ |
| 64 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 65 | #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4) |
| 66 | #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) |
| 67 | #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) |
| 68 | #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 69 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 70 | #define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 71 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 72 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
| 73 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) |
| 74 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 75 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 76 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
| 77 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 78 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 79 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 80 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 81 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
| 82 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 83 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 84 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
| 85 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) |
| 86 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) |
| 87 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) |
| 88 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) |
| 89 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) |
| 90 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 91 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 92 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
| 93 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) |
| 94 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 95 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 96 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 97 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 98 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 99 | |
| 100 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
| 101 | struct omap2_mcspi_dma { |
| 102 | int dma_tx_channel; |
| 103 | int dma_rx_channel; |
| 104 | |
| 105 | int dma_tx_sync_dev; |
| 106 | int dma_rx_sync_dev; |
| 107 | |
| 108 | struct completion dma_tx_completion; |
| 109 | struct completion dma_rx_completion; |
| 110 | }; |
| 111 | |
| 112 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and |
| 113 | * cache operations; better heuristics consider wordsize and bitrate. |
| 114 | */ |
| 115 | #define DMA_MIN_BYTES 8 |
| 116 | |
| 117 | |
| 118 | struct omap2_mcspi { |
| 119 | struct work_struct work; |
| 120 | /* lock protects queue and registers */ |
| 121 | spinlock_t lock; |
| 122 | struct list_head msg_queue; |
| 123 | struct spi_master *master; |
| 124 | struct clk *ick; |
| 125 | struct clk *fck; |
| 126 | /* Virtual base address of the controller */ |
| 127 | void __iomem *base; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 128 | unsigned long phys; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 129 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
| 130 | struct omap2_mcspi_dma *dma_channels; |
| 131 | }; |
| 132 | |
| 133 | struct omap2_mcspi_cs { |
| 134 | void __iomem *base; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 135 | unsigned long phys; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 136 | int word_len; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 137 | /* Context save and restore shadow register */ |
| 138 | u32 chconf0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 139 | }; |
| 140 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 141 | /* used for context save and restore, structure members to be updated whenever |
| 142 | * corresponding registers are modified. |
| 143 | */ |
| 144 | struct omap2_mcspi_regs { |
| 145 | u32 sysconfig; |
| 146 | u32 modulctrl; |
| 147 | u32 wakeupenable; |
| 148 | }; |
| 149 | |
| 150 | static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL]; |
| 151 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 152 | static struct workqueue_struct *omap2_mcspi_wq; |
| 153 | |
| 154 | #define MOD_REG_BIT(val, mask, set) do { \ |
| 155 | if (set) \ |
| 156 | val |= mask; \ |
| 157 | else \ |
| 158 | val &= ~mask; \ |
| 159 | } while (0) |
| 160 | |
| 161 | static inline void mcspi_write_reg(struct spi_master *master, |
| 162 | int idx, u32 val) |
| 163 | { |
| 164 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 165 | |
| 166 | __raw_writel(val, mcspi->base + idx); |
| 167 | } |
| 168 | |
| 169 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) |
| 170 | { |
| 171 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 172 | |
| 173 | return __raw_readl(mcspi->base + idx); |
| 174 | } |
| 175 | |
| 176 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, |
| 177 | int idx, u32 val) |
| 178 | { |
| 179 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 180 | |
| 181 | __raw_writel(val, cs->base + idx); |
| 182 | } |
| 183 | |
| 184 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) |
| 185 | { |
| 186 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 187 | |
| 188 | return __raw_readl(cs->base + idx); |
| 189 | } |
| 190 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 191 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
| 192 | { |
| 193 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 194 | |
| 195 | return cs->chconf0; |
| 196 | } |
| 197 | |
| 198 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) |
| 199 | { |
| 200 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 201 | |
| 202 | cs->chconf0 = val; |
| 203 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); |
| 204 | } |
| 205 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 206 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
| 207 | int is_read, int enable) |
| 208 | { |
| 209 | u32 l, rw; |
| 210 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 211 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 212 | |
| 213 | if (is_read) /* 1 is read, 0 write */ |
| 214 | rw = OMAP2_MCSPI_CHCONF_DMAR; |
| 215 | else |
| 216 | rw = OMAP2_MCSPI_CHCONF_DMAW; |
| 217 | |
| 218 | MOD_REG_BIT(l, rw, enable); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 219 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 220 | } |
| 221 | |
| 222 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) |
| 223 | { |
| 224 | u32 l; |
| 225 | |
| 226 | l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; |
| 227 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); |
| 228 | } |
| 229 | |
| 230 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) |
| 231 | { |
| 232 | u32 l; |
| 233 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 234 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 235 | MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 236 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 237 | } |
| 238 | |
| 239 | static void omap2_mcspi_set_master_mode(struct spi_master *master) |
| 240 | { |
| 241 | u32 l; |
| 242 | |
| 243 | /* setup when switching from (reset default) slave mode |
| 244 | * to single-channel master mode |
| 245 | */ |
| 246 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); |
| 247 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0); |
| 248 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0); |
| 249 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1); |
| 250 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 251 | |
| 252 | omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l; |
| 253 | } |
| 254 | |
| 255 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
| 256 | { |
| 257 | struct spi_master *spi_cntrl; |
| 258 | spi_cntrl = mcspi->master; |
| 259 | |
| 260 | /* McSPI: context restore */ |
| 261 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, |
| 262 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl); |
| 263 | |
| 264 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG, |
| 265 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig); |
| 266 | |
| 267 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, |
| 268 | omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable); |
| 269 | } |
| 270 | static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) |
| 271 | { |
| 272 | clk_disable(mcspi->ick); |
| 273 | clk_disable(mcspi->fck); |
| 274 | } |
| 275 | |
| 276 | static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) |
| 277 | { |
| 278 | if (clk_enable(mcspi->ick)) |
| 279 | return -ENODEV; |
| 280 | if (clk_enable(mcspi->fck)) |
| 281 | return -ENODEV; |
| 282 | |
| 283 | omap2_mcspi_restore_ctx(mcspi); |
| 284 | |
| 285 | return 0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 286 | } |
| 287 | |
| 288 | static unsigned |
| 289 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) |
| 290 | { |
| 291 | struct omap2_mcspi *mcspi; |
| 292 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 293 | struct omap2_mcspi_dma *mcspi_dma; |
| 294 | unsigned int count, c; |
| 295 | unsigned long base, tx_reg, rx_reg; |
| 296 | int word_len, data_type, element_count; |
| 297 | u8 * rx; |
| 298 | const u8 * tx; |
| 299 | |
| 300 | mcspi = spi_master_get_devdata(spi->master); |
| 301 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 302 | |
| 303 | count = xfer->len; |
| 304 | c = count; |
| 305 | word_len = cs->word_len; |
| 306 | |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 307 | base = cs->phys; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 308 | tx_reg = base + OMAP2_MCSPI_TX0; |
| 309 | rx_reg = base + OMAP2_MCSPI_RX0; |
| 310 | rx = xfer->rx_buf; |
| 311 | tx = xfer->tx_buf; |
| 312 | |
| 313 | if (word_len <= 8) { |
| 314 | data_type = OMAP_DMA_DATA_TYPE_S8; |
| 315 | element_count = count; |
| 316 | } else if (word_len <= 16) { |
| 317 | data_type = OMAP_DMA_DATA_TYPE_S16; |
| 318 | element_count = count >> 1; |
| 319 | } else /* word_len <= 32 */ { |
| 320 | data_type = OMAP_DMA_DATA_TYPE_S32; |
| 321 | element_count = count >> 2; |
| 322 | } |
| 323 | |
| 324 | if (tx != NULL) { |
| 325 | omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel, |
| 326 | data_type, element_count, 1, |
| 327 | OMAP_DMA_SYNC_ELEMENT, |
| 328 | mcspi_dma->dma_tx_sync_dev, 0); |
| 329 | |
| 330 | omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0, |
| 331 | OMAP_DMA_AMODE_CONSTANT, |
| 332 | tx_reg, 0, 0); |
| 333 | |
| 334 | omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0, |
| 335 | OMAP_DMA_AMODE_POST_INC, |
| 336 | xfer->tx_dma, 0, 0); |
| 337 | } |
| 338 | |
| 339 | if (rx != NULL) { |
| 340 | omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel, |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 341 | data_type, element_count - 1, 1, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 342 | OMAP_DMA_SYNC_ELEMENT, |
| 343 | mcspi_dma->dma_rx_sync_dev, 1); |
| 344 | |
| 345 | omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0, |
| 346 | OMAP_DMA_AMODE_CONSTANT, |
| 347 | rx_reg, 0, 0); |
| 348 | |
| 349 | omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0, |
| 350 | OMAP_DMA_AMODE_POST_INC, |
| 351 | xfer->rx_dma, 0, 0); |
| 352 | } |
| 353 | |
| 354 | if (tx != NULL) { |
| 355 | omap_start_dma(mcspi_dma->dma_tx_channel); |
| 356 | omap2_mcspi_set_dma_req(spi, 0, 1); |
| 357 | } |
| 358 | |
| 359 | if (rx != NULL) { |
| 360 | omap_start_dma(mcspi_dma->dma_rx_channel); |
| 361 | omap2_mcspi_set_dma_req(spi, 1, 1); |
| 362 | } |
| 363 | |
| 364 | if (tx != NULL) { |
| 365 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
| 366 | dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE); |
| 367 | } |
| 368 | |
| 369 | if (rx != NULL) { |
| 370 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
| 371 | dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE); |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 372 | omap2_mcspi_set_enable(spi, 0); |
| 373 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
| 374 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
| 375 | u32 w; |
| 376 | |
| 377 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); |
| 378 | if (word_len <= 8) |
| 379 | ((u8 *)xfer->rx_buf)[element_count - 1] = w; |
| 380 | else if (word_len <= 16) |
| 381 | ((u16 *)xfer->rx_buf)[element_count - 1] = w; |
| 382 | else /* word_len <= 32 */ |
| 383 | ((u32 *)xfer->rx_buf)[element_count - 1] = w; |
| 384 | } else { |
| 385 | dev_err(&spi->dev, "DMA RX last word empty"); |
| 386 | count -= (word_len <= 8) ? 1 : |
| 387 | (word_len <= 16) ? 2 : |
| 388 | /* word_len <= 32 */ 4; |
| 389 | } |
| 390 | omap2_mcspi_set_enable(spi, 1); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 391 | } |
| 392 | return count; |
| 393 | } |
| 394 | |
| 395 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
| 396 | { |
| 397 | unsigned long timeout; |
| 398 | |
| 399 | timeout = jiffies + msecs_to_jiffies(1000); |
| 400 | while (!(__raw_readl(reg) & bit)) { |
| 401 | if (time_after(jiffies, timeout)) |
| 402 | return -1; |
| 403 | cpu_relax(); |
| 404 | } |
| 405 | return 0; |
| 406 | } |
| 407 | |
| 408 | static unsigned |
| 409 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) |
| 410 | { |
| 411 | struct omap2_mcspi *mcspi; |
| 412 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 413 | unsigned int count, c; |
| 414 | u32 l; |
| 415 | void __iomem *base = cs->base; |
| 416 | void __iomem *tx_reg; |
| 417 | void __iomem *rx_reg; |
| 418 | void __iomem *chstat_reg; |
| 419 | int word_len; |
| 420 | |
| 421 | mcspi = spi_master_get_devdata(spi->master); |
| 422 | count = xfer->len; |
| 423 | c = count; |
| 424 | word_len = cs->word_len; |
| 425 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 426 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 427 | l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; |
| 428 | |
| 429 | /* We store the pre-calculated register addresses on stack to speed |
| 430 | * up the transfer loop. */ |
| 431 | tx_reg = base + OMAP2_MCSPI_TX0; |
| 432 | rx_reg = base + OMAP2_MCSPI_RX0; |
| 433 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; |
| 434 | |
| 435 | if (word_len <= 8) { |
| 436 | u8 *rx; |
| 437 | const u8 *tx; |
| 438 | |
| 439 | rx = xfer->rx_buf; |
| 440 | tx = xfer->tx_buf; |
| 441 | |
| 442 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 443 | c -= 1; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 444 | if (tx != NULL) { |
| 445 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 446 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 447 | dev_err(&spi->dev, "TXS timed out\n"); |
| 448 | goto out; |
| 449 | } |
| 450 | #ifdef VERBOSE |
| 451 | dev_dbg(&spi->dev, "write-%d %02x\n", |
| 452 | word_len, *tx); |
| 453 | #endif |
| 454 | __raw_writel(*tx++, tx_reg); |
| 455 | } |
| 456 | if (rx != NULL) { |
| 457 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 458 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 459 | dev_err(&spi->dev, "RXS timed out\n"); |
| 460 | goto out; |
| 461 | } |
| 462 | /* prevent last RX_ONLY read from triggering |
| 463 | * more word i/o: switch to rx+tx |
| 464 | */ |
| 465 | if (c == 0 && tx == NULL) |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 466 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 467 | *rx++ = __raw_readl(rx_reg); |
| 468 | #ifdef VERBOSE |
| 469 | dev_dbg(&spi->dev, "read-%d %02x\n", |
| 470 | word_len, *(rx - 1)); |
| 471 | #endif |
| 472 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 473 | } while (c); |
| 474 | } else if (word_len <= 16) { |
| 475 | u16 *rx; |
| 476 | const u16 *tx; |
| 477 | |
| 478 | rx = xfer->rx_buf; |
| 479 | tx = xfer->tx_buf; |
| 480 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 481 | c -= 2; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 482 | if (tx != NULL) { |
| 483 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 484 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 485 | dev_err(&spi->dev, "TXS timed out\n"); |
| 486 | goto out; |
| 487 | } |
| 488 | #ifdef VERBOSE |
| 489 | dev_dbg(&spi->dev, "write-%d %04x\n", |
| 490 | word_len, *tx); |
| 491 | #endif |
| 492 | __raw_writel(*tx++, tx_reg); |
| 493 | } |
| 494 | if (rx != NULL) { |
| 495 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 496 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 497 | dev_err(&spi->dev, "RXS timed out\n"); |
| 498 | goto out; |
| 499 | } |
| 500 | /* prevent last RX_ONLY read from triggering |
| 501 | * more word i/o: switch to rx+tx |
| 502 | */ |
| 503 | if (c == 0 && tx == NULL) |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 504 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 505 | *rx++ = __raw_readl(rx_reg); |
| 506 | #ifdef VERBOSE |
| 507 | dev_dbg(&spi->dev, "read-%d %04x\n", |
| 508 | word_len, *(rx - 1)); |
| 509 | #endif |
| 510 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 511 | } while (c); |
| 512 | } else if (word_len <= 32) { |
| 513 | u32 *rx; |
| 514 | const u32 *tx; |
| 515 | |
| 516 | rx = xfer->rx_buf; |
| 517 | tx = xfer->tx_buf; |
| 518 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 519 | c -= 4; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 520 | if (tx != NULL) { |
| 521 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 522 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 523 | dev_err(&spi->dev, "TXS timed out\n"); |
| 524 | goto out; |
| 525 | } |
| 526 | #ifdef VERBOSE |
| 527 | dev_dbg(&spi->dev, "write-%d %04x\n", |
| 528 | word_len, *tx); |
| 529 | #endif |
| 530 | __raw_writel(*tx++, tx_reg); |
| 531 | } |
| 532 | if (rx != NULL) { |
| 533 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 534 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 535 | dev_err(&spi->dev, "RXS timed out\n"); |
| 536 | goto out; |
| 537 | } |
| 538 | /* prevent last RX_ONLY read from triggering |
| 539 | * more word i/o: switch to rx+tx |
| 540 | */ |
| 541 | if (c == 0 && tx == NULL) |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 542 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 543 | *rx++ = __raw_readl(rx_reg); |
| 544 | #ifdef VERBOSE |
| 545 | dev_dbg(&spi->dev, "read-%d %04x\n", |
| 546 | word_len, *(rx - 1)); |
| 547 | #endif |
| 548 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 549 | } while (c); |
| 550 | } |
| 551 | |
| 552 | /* for TX_ONLY mode, be sure all words have shifted out */ |
| 553 | if (xfer->rx_buf == NULL) { |
| 554 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 555 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 556 | dev_err(&spi->dev, "TXS timed out\n"); |
| 557 | } else if (mcspi_wait_for_reg_bit(chstat_reg, |
| 558 | OMAP2_MCSPI_CHSTAT_EOT) < 0) |
| 559 | dev_err(&spi->dev, "EOT timed out\n"); |
| 560 | } |
| 561 | out: |
| 562 | return count - c; |
| 563 | } |
| 564 | |
| 565 | /* called only when no transfer is active to this device */ |
| 566 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, |
| 567 | struct spi_transfer *t) |
| 568 | { |
| 569 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 570 | struct omap2_mcspi *mcspi; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 571 | struct spi_master *spi_cntrl; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 572 | u32 l = 0, div = 0; |
| 573 | u8 word_len = spi->bits_per_word; |
| 574 | |
| 575 | mcspi = spi_master_get_devdata(spi->master); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 576 | spi_cntrl = mcspi->master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 577 | |
| 578 | if (t != NULL && t->bits_per_word) |
| 579 | word_len = t->bits_per_word; |
| 580 | |
| 581 | cs->word_len = word_len; |
| 582 | |
| 583 | if (spi->max_speed_hz) { |
| 584 | while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div)) |
| 585 | > spi->max_speed_hz) |
| 586 | div++; |
| 587 | } else |
| 588 | div = 15; |
| 589 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 590 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 591 | |
| 592 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS |
| 593 | * REVISIT: this controller could support SPI_3WIRE mode. |
| 594 | */ |
| 595 | l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1); |
| 596 | l |= OMAP2_MCSPI_CHCONF_DPE0; |
| 597 | |
| 598 | /* wordlength */ |
| 599 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; |
| 600 | l |= (word_len - 1) << 7; |
| 601 | |
| 602 | /* set chipselect polarity; manage with FORCE */ |
| 603 | if (!(spi->mode & SPI_CS_HIGH)) |
| 604 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ |
| 605 | else |
| 606 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; |
| 607 | |
| 608 | /* set clock divisor */ |
| 609 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; |
| 610 | l |= div << 2; |
| 611 | |
| 612 | /* set SPI mode 0..3 */ |
| 613 | if (spi->mode & SPI_CPOL) |
| 614 | l |= OMAP2_MCSPI_CHCONF_POL; |
| 615 | else |
| 616 | l &= ~OMAP2_MCSPI_CHCONF_POL; |
| 617 | if (spi->mode & SPI_CPHA) |
| 618 | l |= OMAP2_MCSPI_CHCONF_PHA; |
| 619 | else |
| 620 | l &= ~OMAP2_MCSPI_CHCONF_PHA; |
| 621 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 622 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 623 | |
| 624 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", |
| 625 | OMAP2_MCSPI_MAX_FREQ / (1 << div), |
| 626 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
| 627 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); |
| 628 | |
| 629 | return 0; |
| 630 | } |
| 631 | |
| 632 | static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data) |
| 633 | { |
| 634 | struct spi_device *spi = data; |
| 635 | struct omap2_mcspi *mcspi; |
| 636 | struct omap2_mcspi_dma *mcspi_dma; |
| 637 | |
| 638 | mcspi = spi_master_get_devdata(spi->master); |
| 639 | mcspi_dma = &(mcspi->dma_channels[spi->chip_select]); |
| 640 | |
| 641 | complete(&mcspi_dma->dma_rx_completion); |
| 642 | |
| 643 | /* We must disable the DMA RX request */ |
| 644 | omap2_mcspi_set_dma_req(spi, 1, 0); |
| 645 | } |
| 646 | |
| 647 | static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data) |
| 648 | { |
| 649 | struct spi_device *spi = data; |
| 650 | struct omap2_mcspi *mcspi; |
| 651 | struct omap2_mcspi_dma *mcspi_dma; |
| 652 | |
| 653 | mcspi = spi_master_get_devdata(spi->master); |
| 654 | mcspi_dma = &(mcspi->dma_channels[spi->chip_select]); |
| 655 | |
| 656 | complete(&mcspi_dma->dma_tx_completion); |
| 657 | |
| 658 | /* We must disable the DMA TX request */ |
| 659 | omap2_mcspi_set_dma_req(spi, 0, 0); |
| 660 | } |
| 661 | |
| 662 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
| 663 | { |
| 664 | struct spi_master *master = spi->master; |
| 665 | struct omap2_mcspi *mcspi; |
| 666 | struct omap2_mcspi_dma *mcspi_dma; |
| 667 | |
| 668 | mcspi = spi_master_get_devdata(master); |
| 669 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
| 670 | |
| 671 | if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX", |
| 672 | omap2_mcspi_dma_rx_callback, spi, |
| 673 | &mcspi_dma->dma_rx_channel)) { |
| 674 | dev_err(&spi->dev, "no RX DMA channel for McSPI\n"); |
| 675 | return -EAGAIN; |
| 676 | } |
| 677 | |
| 678 | if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX", |
| 679 | omap2_mcspi_dma_tx_callback, spi, |
| 680 | &mcspi_dma->dma_tx_channel)) { |
| 681 | omap_free_dma(mcspi_dma->dma_rx_channel); |
| 682 | mcspi_dma->dma_rx_channel = -1; |
| 683 | dev_err(&spi->dev, "no TX DMA channel for McSPI\n"); |
| 684 | return -EAGAIN; |
| 685 | } |
| 686 | |
| 687 | init_completion(&mcspi_dma->dma_rx_completion); |
| 688 | init_completion(&mcspi_dma->dma_tx_completion); |
| 689 | |
| 690 | return 0; |
| 691 | } |
| 692 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 693 | static int omap2_mcspi_setup(struct spi_device *spi) |
| 694 | { |
| 695 | int ret; |
| 696 | struct omap2_mcspi *mcspi; |
| 697 | struct omap2_mcspi_dma *mcspi_dma; |
| 698 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 699 | |
David Brownell | 7d07719 | 2009-06-17 16:26:03 -0700 | [diff] [blame] | 700 | if (spi->bits_per_word < 4 || spi->bits_per_word > 32) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 701 | dev_dbg(&spi->dev, "setup: unsupported %d bit words\n", |
| 702 | spi->bits_per_word); |
| 703 | return -EINVAL; |
| 704 | } |
| 705 | |
| 706 | mcspi = spi_master_get_devdata(spi->master); |
| 707 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 708 | |
| 709 | if (!cs) { |
| 710 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
| 711 | if (!cs) |
| 712 | return -ENOMEM; |
| 713 | cs->base = mcspi->base + spi->chip_select * 0x14; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 714 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 715 | cs->chconf0 = 0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 716 | spi->controller_state = cs; |
| 717 | } |
| 718 | |
| 719 | if (mcspi_dma->dma_rx_channel == -1 |
| 720 | || mcspi_dma->dma_tx_channel == -1) { |
| 721 | ret = omap2_mcspi_request_dma(spi); |
| 722 | if (ret < 0) |
| 723 | return ret; |
| 724 | } |
| 725 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 726 | if (omap2_mcspi_enable_clocks(mcspi)) |
| 727 | return -ENODEV; |
| 728 | |
Kyungmin Park | 86eeb6f | 2007-10-16 01:27:45 -0700 | [diff] [blame] | 729 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 730 | omap2_mcspi_disable_clocks(mcspi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 731 | |
| 732 | return ret; |
| 733 | } |
| 734 | |
| 735 | static void omap2_mcspi_cleanup(struct spi_device *spi) |
| 736 | { |
| 737 | struct omap2_mcspi *mcspi; |
| 738 | struct omap2_mcspi_dma *mcspi_dma; |
| 739 | |
| 740 | mcspi = spi_master_get_devdata(spi->master); |
| 741 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 742 | |
| 743 | kfree(spi->controller_state); |
| 744 | |
| 745 | if (mcspi_dma->dma_rx_channel != -1) { |
| 746 | omap_free_dma(mcspi_dma->dma_rx_channel); |
| 747 | mcspi_dma->dma_rx_channel = -1; |
| 748 | } |
| 749 | if (mcspi_dma->dma_tx_channel != -1) { |
| 750 | omap_free_dma(mcspi_dma->dma_tx_channel); |
| 751 | mcspi_dma->dma_tx_channel = -1; |
| 752 | } |
| 753 | } |
| 754 | |
| 755 | static void omap2_mcspi_work(struct work_struct *work) |
| 756 | { |
| 757 | struct omap2_mcspi *mcspi; |
| 758 | |
| 759 | mcspi = container_of(work, struct omap2_mcspi, work); |
| 760 | spin_lock_irq(&mcspi->lock); |
| 761 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 762 | if (omap2_mcspi_enable_clocks(mcspi)) |
| 763 | goto out; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 764 | |
| 765 | /* We only enable one channel at a time -- the one whose message is |
| 766 | * at the head of the queue -- although this controller would gladly |
| 767 | * arbitrate among multiple channels. This corresponds to "single |
| 768 | * channel" master mode. As a side effect, we need to manage the |
| 769 | * chipselect with the FORCE bit ... CS != channel enable. |
| 770 | */ |
| 771 | while (!list_empty(&mcspi->msg_queue)) { |
| 772 | struct spi_message *m; |
| 773 | struct spi_device *spi; |
| 774 | struct spi_transfer *t = NULL; |
| 775 | int cs_active = 0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 776 | struct omap2_mcspi_cs *cs; |
| 777 | int par_override = 0; |
| 778 | int status = 0; |
| 779 | u32 chconf; |
| 780 | |
| 781 | m = container_of(mcspi->msg_queue.next, struct spi_message, |
| 782 | queue); |
| 783 | |
| 784 | list_del_init(&m->queue); |
| 785 | spin_unlock_irq(&mcspi->lock); |
| 786 | |
| 787 | spi = m->spi; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 788 | cs = spi->controller_state; |
| 789 | |
| 790 | omap2_mcspi_set_enable(spi, 1); |
| 791 | list_for_each_entry(t, &m->transfers, transfer_list) { |
| 792 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { |
| 793 | status = -EINVAL; |
| 794 | break; |
| 795 | } |
| 796 | if (par_override || t->speed_hz || t->bits_per_word) { |
| 797 | par_override = 1; |
| 798 | status = omap2_mcspi_setup_transfer(spi, t); |
| 799 | if (status < 0) |
| 800 | break; |
| 801 | if (!t->speed_hz && !t->bits_per_word) |
| 802 | par_override = 0; |
| 803 | } |
| 804 | |
| 805 | if (!cs_active) { |
| 806 | omap2_mcspi_force_cs(spi, 1); |
| 807 | cs_active = 1; |
| 808 | } |
| 809 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 810 | chconf = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 811 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; |
| 812 | if (t->tx_buf == NULL) |
| 813 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; |
| 814 | else if (t->rx_buf == NULL) |
| 815 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 816 | mcspi_write_chconf0(spi, chconf); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 817 | |
| 818 | if (t->len) { |
| 819 | unsigned count; |
| 820 | |
| 821 | /* RX_ONLY mode needs dummy data in TX reg */ |
| 822 | if (t->tx_buf == NULL) |
| 823 | __raw_writel(0, cs->base |
| 824 | + OMAP2_MCSPI_TX0); |
| 825 | |
| 826 | if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES) |
| 827 | count = omap2_mcspi_txrx_dma(spi, t); |
| 828 | else |
| 829 | count = omap2_mcspi_txrx_pio(spi, t); |
| 830 | m->actual_length += count; |
| 831 | |
| 832 | if (count != t->len) { |
| 833 | status = -EIO; |
| 834 | break; |
| 835 | } |
| 836 | } |
| 837 | |
| 838 | if (t->delay_usecs) |
| 839 | udelay(t->delay_usecs); |
| 840 | |
| 841 | /* ignore the "leave it on after last xfer" hint */ |
| 842 | if (t->cs_change) { |
| 843 | omap2_mcspi_force_cs(spi, 0); |
| 844 | cs_active = 0; |
| 845 | } |
| 846 | } |
| 847 | |
| 848 | /* Restore defaults if they were overriden */ |
| 849 | if (par_override) { |
| 850 | par_override = 0; |
| 851 | status = omap2_mcspi_setup_transfer(spi, NULL); |
| 852 | } |
| 853 | |
| 854 | if (cs_active) |
| 855 | omap2_mcspi_force_cs(spi, 0); |
| 856 | |
| 857 | omap2_mcspi_set_enable(spi, 0); |
| 858 | |
| 859 | m->status = status; |
| 860 | m->complete(m->context); |
| 861 | |
| 862 | spin_lock_irq(&mcspi->lock); |
| 863 | } |
| 864 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 865 | omap2_mcspi_disable_clocks(mcspi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 866 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 867 | out: |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 868 | spin_unlock_irq(&mcspi->lock); |
| 869 | } |
| 870 | |
| 871 | static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m) |
| 872 | { |
| 873 | struct omap2_mcspi *mcspi; |
| 874 | unsigned long flags; |
| 875 | struct spi_transfer *t; |
| 876 | |
| 877 | m->actual_length = 0; |
| 878 | m->status = 0; |
| 879 | |
| 880 | /* reject invalid messages and transfers */ |
| 881 | if (list_empty(&m->transfers) || !m->complete) |
| 882 | return -EINVAL; |
| 883 | list_for_each_entry(t, &m->transfers, transfer_list) { |
| 884 | const void *tx_buf = t->tx_buf; |
| 885 | void *rx_buf = t->rx_buf; |
| 886 | unsigned len = t->len; |
| 887 | |
| 888 | if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ |
| 889 | || (len && !(rx_buf || tx_buf)) |
| 890 | || (t->bits_per_word && |
| 891 | ( t->bits_per_word < 4 |
| 892 | || t->bits_per_word > 32))) { |
| 893 | dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
| 894 | t->speed_hz, |
| 895 | len, |
| 896 | tx_buf ? "tx" : "", |
| 897 | rx_buf ? "rx" : "", |
| 898 | t->bits_per_word); |
| 899 | return -EINVAL; |
| 900 | } |
| 901 | if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) { |
| 902 | dev_dbg(&spi->dev, "%d Hz max exceeds %d\n", |
| 903 | t->speed_hz, |
| 904 | OMAP2_MCSPI_MAX_FREQ/(1<<16)); |
| 905 | return -EINVAL; |
| 906 | } |
| 907 | |
| 908 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) |
| 909 | continue; |
| 910 | |
| 911 | /* Do DMA mapping "early" for better error reporting and |
| 912 | * dcache use. Note that if dma_unmap_single() ever starts |
| 913 | * to do real work on ARM, we'd need to clean up mappings |
| 914 | * for previous transfers on *ALL* exits of this loop... |
| 915 | */ |
| 916 | if (tx_buf != NULL) { |
| 917 | t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf, |
| 918 | len, DMA_TO_DEVICE); |
FUJITA Tomonori | 8d8bb39 | 2008-07-25 19:44:49 -0700 | [diff] [blame] | 919 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 920 | dev_dbg(&spi->dev, "dma %cX %d bytes error\n", |
| 921 | 'T', len); |
| 922 | return -EINVAL; |
| 923 | } |
| 924 | } |
| 925 | if (rx_buf != NULL) { |
| 926 | t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len, |
| 927 | DMA_FROM_DEVICE); |
FUJITA Tomonori | 8d8bb39 | 2008-07-25 19:44:49 -0700 | [diff] [blame] | 928 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 929 | dev_dbg(&spi->dev, "dma %cX %d bytes error\n", |
| 930 | 'R', len); |
| 931 | if (tx_buf != NULL) |
| 932 | dma_unmap_single(NULL, t->tx_dma, |
| 933 | len, DMA_TO_DEVICE); |
| 934 | return -EINVAL; |
| 935 | } |
| 936 | } |
| 937 | } |
| 938 | |
| 939 | mcspi = spi_master_get_devdata(spi->master); |
| 940 | |
| 941 | spin_lock_irqsave(&mcspi->lock, flags); |
| 942 | list_add_tail(&m->queue, &mcspi->msg_queue); |
| 943 | queue_work(omap2_mcspi_wq, &mcspi->work); |
| 944 | spin_unlock_irqrestore(&mcspi->lock, flags); |
| 945 | |
| 946 | return 0; |
| 947 | } |
| 948 | |
| 949 | static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi) |
| 950 | { |
| 951 | struct spi_master *master = mcspi->master; |
| 952 | u32 tmp; |
| 953 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 954 | if (omap2_mcspi_enable_clocks(mcspi)) |
| 955 | return -1; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 956 | |
| 957 | mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, |
| 958 | OMAP2_MCSPI_SYSCONFIG_SOFTRESET); |
| 959 | do { |
| 960 | tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS); |
| 961 | } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE)); |
| 962 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 963 | tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE | |
| 964 | OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP | |
| 965 | OMAP2_MCSPI_SYSCONFIG_SMARTIDLE; |
| 966 | mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp); |
| 967 | omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp; |
Jouni Hogander | ddb2219 | 2009-07-29 15:02:11 -0700 | [diff] [blame] | 968 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 969 | tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
| 970 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp); |
| 971 | omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 972 | |
| 973 | omap2_mcspi_set_master_mode(master); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame^] | 974 | omap2_mcspi_disable_clocks(mcspi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 975 | return 0; |
| 976 | } |
| 977 | |
| 978 | static u8 __initdata spi1_rxdma_id [] = { |
| 979 | OMAP24XX_DMA_SPI1_RX0, |
| 980 | OMAP24XX_DMA_SPI1_RX1, |
| 981 | OMAP24XX_DMA_SPI1_RX2, |
| 982 | OMAP24XX_DMA_SPI1_RX3, |
| 983 | }; |
| 984 | |
| 985 | static u8 __initdata spi1_txdma_id [] = { |
| 986 | OMAP24XX_DMA_SPI1_TX0, |
| 987 | OMAP24XX_DMA_SPI1_TX1, |
| 988 | OMAP24XX_DMA_SPI1_TX2, |
| 989 | OMAP24XX_DMA_SPI1_TX3, |
| 990 | }; |
| 991 | |
| 992 | static u8 __initdata spi2_rxdma_id[] = { |
| 993 | OMAP24XX_DMA_SPI2_RX0, |
| 994 | OMAP24XX_DMA_SPI2_RX1, |
| 995 | }; |
| 996 | |
| 997 | static u8 __initdata spi2_txdma_id[] = { |
| 998 | OMAP24XX_DMA_SPI2_TX0, |
| 999 | OMAP24XX_DMA_SPI2_TX1, |
| 1000 | }; |
| 1001 | |
Girish | ccc7bae | 2008-02-06 01:38:16 -0800 | [diff] [blame] | 1002 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) |
| 1003 | static u8 __initdata spi3_rxdma_id[] = { |
| 1004 | OMAP24XX_DMA_SPI3_RX0, |
| 1005 | OMAP24XX_DMA_SPI3_RX1, |
| 1006 | }; |
| 1007 | |
| 1008 | static u8 __initdata spi3_txdma_id[] = { |
| 1009 | OMAP24XX_DMA_SPI3_TX0, |
| 1010 | OMAP24XX_DMA_SPI3_TX1, |
| 1011 | }; |
| 1012 | #endif |
| 1013 | |
| 1014 | #ifdef CONFIG_ARCH_OMAP3 |
| 1015 | static u8 __initdata spi4_rxdma_id[] = { |
| 1016 | OMAP34XX_DMA_SPI4_RX0, |
| 1017 | }; |
| 1018 | |
| 1019 | static u8 __initdata spi4_txdma_id[] = { |
| 1020 | OMAP34XX_DMA_SPI4_TX0, |
| 1021 | }; |
| 1022 | #endif |
| 1023 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1024 | static int __init omap2_mcspi_probe(struct platform_device *pdev) |
| 1025 | { |
| 1026 | struct spi_master *master; |
| 1027 | struct omap2_mcspi *mcspi; |
| 1028 | struct resource *r; |
| 1029 | int status = 0, i; |
| 1030 | const u8 *rxdma_id, *txdma_id; |
| 1031 | unsigned num_chipselect; |
| 1032 | |
| 1033 | switch (pdev->id) { |
| 1034 | case 1: |
| 1035 | rxdma_id = spi1_rxdma_id; |
| 1036 | txdma_id = spi1_txdma_id; |
| 1037 | num_chipselect = 4; |
| 1038 | break; |
| 1039 | case 2: |
| 1040 | rxdma_id = spi2_rxdma_id; |
| 1041 | txdma_id = spi2_txdma_id; |
| 1042 | num_chipselect = 2; |
| 1043 | break; |
Girish | ccc7bae | 2008-02-06 01:38:16 -0800 | [diff] [blame] | 1044 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) |
| 1045 | case 3: |
| 1046 | rxdma_id = spi3_rxdma_id; |
| 1047 | txdma_id = spi3_txdma_id; |
| 1048 | num_chipselect = 2; |
| 1049 | break; |
| 1050 | #endif |
| 1051 | #ifdef CONFIG_ARCH_OMAP3 |
| 1052 | case 4: |
| 1053 | rxdma_id = spi4_rxdma_id; |
| 1054 | txdma_id = spi4_txdma_id; |
| 1055 | num_chipselect = 1; |
| 1056 | break; |
| 1057 | #endif |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1058 | default: |
| 1059 | return -EINVAL; |
| 1060 | } |
| 1061 | |
| 1062 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); |
| 1063 | if (master == NULL) { |
| 1064 | dev_dbg(&pdev->dev, "master allocation failed\n"); |
| 1065 | return -ENOMEM; |
| 1066 | } |
| 1067 | |
David Brownell | e7db06b | 2009-06-17 16:26:04 -0700 | [diff] [blame] | 1068 | /* the spi->mode bits understood by this driver: */ |
| 1069 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
| 1070 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1071 | if (pdev->id != -1) |
| 1072 | master->bus_num = pdev->id; |
| 1073 | |
| 1074 | master->setup = omap2_mcspi_setup; |
| 1075 | master->transfer = omap2_mcspi_transfer; |
| 1076 | master->cleanup = omap2_mcspi_cleanup; |
| 1077 | master->num_chipselect = num_chipselect; |
| 1078 | |
| 1079 | dev_set_drvdata(&pdev->dev, master); |
| 1080 | |
| 1081 | mcspi = spi_master_get_devdata(master); |
| 1082 | mcspi->master = master; |
| 1083 | |
| 1084 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1085 | if (r == NULL) { |
| 1086 | status = -ENODEV; |
| 1087 | goto err1; |
| 1088 | } |
| 1089 | if (!request_mem_region(r->start, (r->end - r->start) + 1, |
Kay Sievers | 6c7377a | 2009-03-24 16:38:21 -0700 | [diff] [blame] | 1090 | dev_name(&pdev->dev))) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1091 | status = -EBUSY; |
| 1092 | goto err1; |
| 1093 | } |
| 1094 | |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 1095 | mcspi->phys = r->start; |
Russell King | 55c381e | 2008-09-04 14:07:22 +0100 | [diff] [blame] | 1096 | mcspi->base = ioremap(r->start, r->end - r->start + 1); |
| 1097 | if (!mcspi->base) { |
| 1098 | dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); |
| 1099 | status = -ENOMEM; |
| 1100 | goto err1aa; |
| 1101 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1102 | |
| 1103 | INIT_WORK(&mcspi->work, omap2_mcspi_work); |
| 1104 | |
| 1105 | spin_lock_init(&mcspi->lock); |
| 1106 | INIT_LIST_HEAD(&mcspi->msg_queue); |
| 1107 | |
Russell King | 1b5715e | 2009-01-19 20:49:37 +0000 | [diff] [blame] | 1108 | mcspi->ick = clk_get(&pdev->dev, "ick"); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1109 | if (IS_ERR(mcspi->ick)) { |
| 1110 | dev_dbg(&pdev->dev, "can't get mcspi_ick\n"); |
| 1111 | status = PTR_ERR(mcspi->ick); |
| 1112 | goto err1a; |
| 1113 | } |
Russell King | 1b5715e | 2009-01-19 20:49:37 +0000 | [diff] [blame] | 1114 | mcspi->fck = clk_get(&pdev->dev, "fck"); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1115 | if (IS_ERR(mcspi->fck)) { |
| 1116 | dev_dbg(&pdev->dev, "can't get mcspi_fck\n"); |
| 1117 | status = PTR_ERR(mcspi->fck); |
| 1118 | goto err2; |
| 1119 | } |
| 1120 | |
| 1121 | mcspi->dma_channels = kcalloc(master->num_chipselect, |
| 1122 | sizeof(struct omap2_mcspi_dma), |
| 1123 | GFP_KERNEL); |
| 1124 | |
| 1125 | if (mcspi->dma_channels == NULL) |
| 1126 | goto err3; |
| 1127 | |
| 1128 | for (i = 0; i < num_chipselect; i++) { |
| 1129 | mcspi->dma_channels[i].dma_rx_channel = -1; |
| 1130 | mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i]; |
| 1131 | mcspi->dma_channels[i].dma_tx_channel = -1; |
| 1132 | mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i]; |
| 1133 | } |
| 1134 | |
| 1135 | if (omap2_mcspi_reset(mcspi) < 0) |
| 1136 | goto err4; |
| 1137 | |
| 1138 | status = spi_register_master(master); |
| 1139 | if (status < 0) |
| 1140 | goto err4; |
| 1141 | |
| 1142 | return status; |
| 1143 | |
| 1144 | err4: |
| 1145 | kfree(mcspi->dma_channels); |
| 1146 | err3: |
| 1147 | clk_put(mcspi->fck); |
| 1148 | err2: |
| 1149 | clk_put(mcspi->ick); |
| 1150 | err1a: |
Russell King | 55c381e | 2008-09-04 14:07:22 +0100 | [diff] [blame] | 1151 | iounmap(mcspi->base); |
| 1152 | err1aa: |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1153 | release_mem_region(r->start, (r->end - r->start) + 1); |
| 1154 | err1: |
| 1155 | spi_master_put(master); |
| 1156 | return status; |
| 1157 | } |
| 1158 | |
| 1159 | static int __exit omap2_mcspi_remove(struct platform_device *pdev) |
| 1160 | { |
| 1161 | struct spi_master *master; |
| 1162 | struct omap2_mcspi *mcspi; |
| 1163 | struct omap2_mcspi_dma *dma_channels; |
| 1164 | struct resource *r; |
Russell King | 55c381e | 2008-09-04 14:07:22 +0100 | [diff] [blame] | 1165 | void __iomem *base; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1166 | |
| 1167 | master = dev_get_drvdata(&pdev->dev); |
| 1168 | mcspi = spi_master_get_devdata(master); |
| 1169 | dma_channels = mcspi->dma_channels; |
| 1170 | |
| 1171 | clk_put(mcspi->fck); |
| 1172 | clk_put(mcspi->ick); |
| 1173 | |
| 1174 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1175 | release_mem_region(r->start, (r->end - r->start) + 1); |
| 1176 | |
Russell King | 55c381e | 2008-09-04 14:07:22 +0100 | [diff] [blame] | 1177 | base = mcspi->base; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1178 | spi_unregister_master(master); |
Russell King | 55c381e | 2008-09-04 14:07:22 +0100 | [diff] [blame] | 1179 | iounmap(base); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1180 | kfree(dma_channels); |
| 1181 | |
| 1182 | return 0; |
| 1183 | } |
| 1184 | |
Kay Sievers | 7e38c3c | 2008-04-10 21:29:20 -0700 | [diff] [blame] | 1185 | /* work with hotplug and coldplug */ |
| 1186 | MODULE_ALIAS("platform:omap2_mcspi"); |
| 1187 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1188 | static struct platform_driver omap2_mcspi_driver = { |
| 1189 | .driver = { |
| 1190 | .name = "omap2_mcspi", |
| 1191 | .owner = THIS_MODULE, |
| 1192 | }, |
| 1193 | .remove = __exit_p(omap2_mcspi_remove), |
| 1194 | }; |
| 1195 | |
| 1196 | |
| 1197 | static int __init omap2_mcspi_init(void) |
| 1198 | { |
| 1199 | omap2_mcspi_wq = create_singlethread_workqueue( |
| 1200 | omap2_mcspi_driver.driver.name); |
| 1201 | if (omap2_mcspi_wq == NULL) |
| 1202 | return -1; |
| 1203 | return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe); |
| 1204 | } |
| 1205 | subsys_initcall(omap2_mcspi_init); |
| 1206 | |
| 1207 | static void __exit omap2_mcspi_exit(void) |
| 1208 | { |
| 1209 | platform_driver_unregister(&omap2_mcspi_driver); |
| 1210 | |
| 1211 | destroy_workqueue(omap2_mcspi_wq); |
| 1212 | } |
| 1213 | module_exit(omap2_mcspi_exit); |
| 1214 | |
| 1215 | MODULE_LICENSE("GPL"); |