Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1 | /* Intel 7 core Memory Controller kernel module (Nehalem) |
| 2 | * |
| 3 | * This file may be distributed under the terms of the |
| 4 | * GNU General Public License version 2 only. |
| 5 | * |
| 6 | * Copyright (c) 2009 by: |
| 7 | * Mauro Carvalho Chehab <mchehab@redhat.com> |
| 8 | * |
| 9 | * Red Hat Inc. http://www.redhat.com |
| 10 | * |
| 11 | * Forked and adapted from the i5400_edac driver |
| 12 | * |
| 13 | * Based on the following public Intel datasheets: |
| 14 | * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor |
| 15 | * Datasheet, Volume 2: |
| 16 | * http://download.intel.com/design/processor/datashts/320835.pdf |
| 17 | * Intel Xeon Processor 5500 Series Datasheet Volume 2 |
| 18 | * http://www.intel.com/Assets/PDF/datasheet/321322.pdf |
| 19 | * also available at: |
| 20 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf |
| 21 | */ |
| 22 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 23 | #include <linux/module.h> |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/pci.h> |
| 26 | #include <linux/pci_ids.h> |
| 27 | #include <linux/slab.h> |
| 28 | #include <linux/edac.h> |
| 29 | #include <linux/mmzone.h> |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 30 | #include <linux/edac_mce.h> |
| 31 | #include <linux/spinlock.h> |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 32 | #include <linux/smp.h> |
Mauro Carvalho Chehab | 14d2c08 | 2009-09-02 23:52:36 -0300 | [diff] [blame] | 33 | #include <asm/processor.h> |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 34 | |
| 35 | #include "edac_core.h" |
| 36 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 37 | /* |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 38 | * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core |
| 39 | * registers start at bus 255, and are not reported by BIOS. |
| 40 | * We currently find devices with only 2 sockets. In order to support more QPI |
| 41 | * Quick Path Interconnect, just increment this number. |
| 42 | */ |
| 43 | #define MAX_SOCKET_BUSES 2 |
| 44 | |
| 45 | |
| 46 | /* |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 47 | * Alter this version for the module when modifications are made |
| 48 | */ |
| 49 | #define I7CORE_REVISION " Ver: 1.0.0 " __DATE__ |
| 50 | #define EDAC_MOD_STR "i7core_edac" |
| 51 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 52 | /* |
| 53 | * Debug macros |
| 54 | */ |
| 55 | #define i7core_printk(level, fmt, arg...) \ |
| 56 | edac_printk(level, "i7core", fmt, ##arg) |
| 57 | |
| 58 | #define i7core_mc_printk(mci, level, fmt, arg...) \ |
| 59 | edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg) |
| 60 | |
| 61 | /* |
| 62 | * i7core Memory Controller Registers |
| 63 | */ |
| 64 | |
Mauro Carvalho Chehab | e9bd2e7 | 2009-07-09 22:14:35 -0300 | [diff] [blame] | 65 | /* OFFSETS for Device 0 Function 0 */ |
| 66 | |
| 67 | #define MC_CFG_CONTROL 0x90 |
| 68 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 69 | /* OFFSETS for Device 3 Function 0 */ |
| 70 | |
| 71 | #define MC_CONTROL 0x48 |
| 72 | #define MC_STATUS 0x4c |
| 73 | #define MC_MAX_DOD 0x64 |
| 74 | |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 75 | /* |
| 76 | * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet: |
| 77 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf |
| 78 | */ |
| 79 | |
| 80 | #define MC_TEST_ERR_RCV1 0x60 |
| 81 | #define DIMM2_COR_ERR(r) ((r) & 0x7fff) |
| 82 | |
| 83 | #define MC_TEST_ERR_RCV0 0x64 |
| 84 | #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff) |
| 85 | #define DIMM0_COR_ERR(r) ((r) & 0x7fff) |
| 86 | |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 87 | /* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */ |
| 88 | #define MC_COR_ECC_CNT_0 0x80 |
| 89 | #define MC_COR_ECC_CNT_1 0x84 |
| 90 | #define MC_COR_ECC_CNT_2 0x88 |
| 91 | #define MC_COR_ECC_CNT_3 0x8c |
| 92 | #define MC_COR_ECC_CNT_4 0x90 |
| 93 | #define MC_COR_ECC_CNT_5 0x94 |
| 94 | |
| 95 | #define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff) |
| 96 | #define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff) |
| 97 | |
| 98 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 99 | /* OFFSETS for Devices 4,5 and 6 Function 0 */ |
| 100 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 101 | #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58 |
| 102 | #define THREE_DIMMS_PRESENT (1 << 24) |
| 103 | #define SINGLE_QUAD_RANK_PRESENT (1 << 23) |
| 104 | #define QUAD_RANK_PRESENT (1 << 22) |
| 105 | #define REGISTERED_DIMM (1 << 15) |
| 106 | |
Mauro Carvalho Chehab | f122a89 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 107 | #define MC_CHANNEL_MAPPER 0x60 |
| 108 | #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1) |
| 109 | #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1) |
| 110 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 111 | #define MC_CHANNEL_RANK_PRESENT 0x7c |
| 112 | #define RANK_PRESENT_MASK 0xffff |
| 113 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 114 | #define MC_CHANNEL_ADDR_MATCH 0xf0 |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 115 | #define MC_CHANNEL_ERROR_MASK 0xf8 |
| 116 | #define MC_CHANNEL_ERROR_INJECT 0xfc |
| 117 | #define INJECT_ADDR_PARITY 0x10 |
| 118 | #define INJECT_ECC 0x08 |
| 119 | #define MASK_CACHELINE 0x06 |
| 120 | #define MASK_FULL_CACHELINE 0x06 |
| 121 | #define MASK_MSB32_CACHELINE 0x04 |
| 122 | #define MASK_LSB32_CACHELINE 0x02 |
| 123 | #define NO_MASK_CACHELINE 0x00 |
| 124 | #define REPEAT_EN 0x01 |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 125 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 126 | /* OFFSETS for Devices 4,5 and 6 Function 1 */ |
Mauro Carvalho Chehab | b990538 | 2009-08-05 21:36:35 -0300 | [diff] [blame] | 127 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 128 | #define MC_DOD_CH_DIMM0 0x48 |
| 129 | #define MC_DOD_CH_DIMM1 0x4c |
| 130 | #define MC_DOD_CH_DIMM2 0x50 |
| 131 | #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10)) |
| 132 | #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10) |
| 133 | #define DIMM_PRESENT_MASK (1 << 9) |
| 134 | #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9) |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 135 | #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7)) |
| 136 | #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7) |
| 137 | #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5)) |
| 138 | #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5) |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 139 | #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2)) |
Mauro Carvalho Chehab | 5566cb7 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 140 | #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2) |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 141 | #define MC_DOD_NUMCOL_MASK 3 |
| 142 | #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK) |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 143 | |
Mauro Carvalho Chehab | f122a89 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 144 | #define MC_RANK_PRESENT 0x7c |
| 145 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 146 | #define MC_SAG_CH_0 0x80 |
| 147 | #define MC_SAG_CH_1 0x84 |
| 148 | #define MC_SAG_CH_2 0x88 |
| 149 | #define MC_SAG_CH_3 0x8c |
| 150 | #define MC_SAG_CH_4 0x90 |
| 151 | #define MC_SAG_CH_5 0x94 |
| 152 | #define MC_SAG_CH_6 0x98 |
| 153 | #define MC_SAG_CH_7 0x9c |
| 154 | |
| 155 | #define MC_RIR_LIMIT_CH_0 0x40 |
| 156 | #define MC_RIR_LIMIT_CH_1 0x44 |
| 157 | #define MC_RIR_LIMIT_CH_2 0x48 |
| 158 | #define MC_RIR_LIMIT_CH_3 0x4C |
| 159 | #define MC_RIR_LIMIT_CH_4 0x50 |
| 160 | #define MC_RIR_LIMIT_CH_5 0x54 |
| 161 | #define MC_RIR_LIMIT_CH_6 0x58 |
| 162 | #define MC_RIR_LIMIT_CH_7 0x5C |
| 163 | #define MC_RIR_LIMIT_MASK ((1 << 10) - 1) |
| 164 | |
| 165 | #define MC_RIR_WAY_CH 0x80 |
| 166 | #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7) |
| 167 | #define MC_RIR_WAY_RANK_MASK 0x7 |
| 168 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 169 | /* |
| 170 | * i7core structs |
| 171 | */ |
| 172 | |
| 173 | #define NUM_CHANS 3 |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 174 | #define MAX_DIMMS 3 /* Max DIMMS per channel */ |
| 175 | #define MAX_MCR_FUNC 4 |
| 176 | #define MAX_CHAN_FUNC 3 |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 177 | |
| 178 | struct i7core_info { |
| 179 | u32 mc_control; |
| 180 | u32 mc_status; |
| 181 | u32 max_dod; |
Mauro Carvalho Chehab | f122a89 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 182 | u32 ch_map; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 183 | }; |
| 184 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 185 | |
| 186 | struct i7core_inject { |
| 187 | int enable; |
| 188 | |
| 189 | u32 section; |
| 190 | u32 type; |
| 191 | u32 eccmask; |
| 192 | |
| 193 | /* Error address mask */ |
| 194 | int channel, dimm, rank, bank, page, col; |
| 195 | }; |
| 196 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 197 | struct i7core_channel { |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 198 | u32 ranks; |
| 199 | u32 dimms; |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 200 | }; |
| 201 | |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 202 | struct pci_id_descr { |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 203 | int dev; |
| 204 | int func; |
| 205 | int dev_id; |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 206 | }; |
| 207 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 208 | struct i7core_dev { |
| 209 | struct list_head list; |
| 210 | u8 socket; |
| 211 | struct pci_dev **pdev; |
| 212 | struct mem_ctl_info *mci; |
| 213 | }; |
| 214 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 215 | struct i7core_pvt { |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 216 | struct pci_dev *pci_noncore; |
| 217 | struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1]; |
| 218 | struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1]; |
| 219 | |
| 220 | struct i7core_dev *i7core_dev; |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 221 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 222 | struct i7core_info info; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 223 | struct i7core_inject inject; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 224 | struct i7core_channel channel[NUM_CHANS]; |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 225 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 226 | int channels; /* Number of active channels */ |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 227 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 228 | int ce_count_available; |
| 229 | int csrow_map[NUM_CHANS][MAX_DIMMS]; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 230 | |
| 231 | /* ECC corrected errors counts per udimm */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 232 | unsigned long udimm_ce_count[MAX_DIMMS]; |
| 233 | int udimm_last_ce_count[MAX_DIMMS]; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 234 | /* ECC corrected errors counts per rdimm */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 235 | unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS]; |
| 236 | int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS]; |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 237 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 238 | unsigned int is_registered; |
Mauro Carvalho Chehab | 14d2c08 | 2009-09-02 23:52:36 -0300 | [diff] [blame] | 239 | |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 240 | /* mcelog glue */ |
| 241 | struct edac_mce edac_mce; |
| 242 | struct mce mce_entry[MCE_LOG_LEN]; |
| 243 | unsigned mce_count; |
| 244 | spinlock_t mce_lock; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 245 | }; |
| 246 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 247 | /* Static vars */ |
| 248 | static LIST_HEAD(i7core_edac_list); |
| 249 | static DEFINE_MUTEX(i7core_edac_lock); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 250 | |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 251 | #define PCI_DESCR(device, function, device_id) \ |
| 252 | .dev = (device), \ |
| 253 | .func = (function), \ |
| 254 | .dev_id = (device_id) |
| 255 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 256 | struct pci_id_descr pci_dev_descr[] = { |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 257 | /* Memory controller */ |
| 258 | { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) }, |
| 259 | { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) }, |
Mauro Carvalho Chehab | b990538 | 2009-08-05 21:36:35 -0300 | [diff] [blame] | 260 | { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS) }, /* if RDIMM */ |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 261 | { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) }, |
| 262 | |
| 263 | /* Channel 0 */ |
| 264 | { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) }, |
| 265 | { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) }, |
| 266 | { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) }, |
| 267 | { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) }, |
| 268 | |
| 269 | /* Channel 1 */ |
| 270 | { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) }, |
| 271 | { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) }, |
| 272 | { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) }, |
| 273 | { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) }, |
| 274 | |
| 275 | /* Channel 2 */ |
| 276 | { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) }, |
| 277 | { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) }, |
| 278 | { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) }, |
| 279 | { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) }, |
Mauro Carvalho Chehab | 310cbb7 | 2009-07-17 00:09:10 -0300 | [diff] [blame] | 280 | |
| 281 | /* Generic Non-core registers */ |
| 282 | /* |
| 283 | * This is the PCI device on i7core and on Xeon 35xx (8086:2c41) |
| 284 | * On Xeon 55xx, however, it has a different id (8086:2c40). So, |
| 285 | * the probing code needs to test for the other address in case of |
| 286 | * failure of this one |
| 287 | */ |
| 288 | { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NOCORE) }, |
| 289 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 290 | }; |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 291 | #define N_DEVS ARRAY_SIZE(pci_dev_descr) |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 292 | |
| 293 | /* |
| 294 | * pci_device_id table for which devices we are looking for |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 295 | */ |
| 296 | static const struct pci_device_id i7core_pci_tbl[] __devinitdata = { |
Mauro Carvalho Chehab | d1fd4fb | 2009-07-10 18:39:53 -0300 | [diff] [blame] | 297 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)}, |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 298 | {0,} /* 0 terminated list. */ |
| 299 | }; |
| 300 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 301 | static struct edac_pci_ctl_info *i7core_pci; |
| 302 | |
| 303 | /**************************************************************************** |
| 304 | Anciliary status routines |
| 305 | ****************************************************************************/ |
| 306 | |
| 307 | /* MC_CONTROL bits */ |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 308 | #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch))) |
| 309 | #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1)) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 310 | |
| 311 | /* MC_STATUS bits */ |
Keith Mannthey | 61053fd | 2009-09-02 23:46:59 -0300 | [diff] [blame] | 312 | #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4)) |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 313 | #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch)) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 314 | |
| 315 | /* MC_MAX_DOD read functions */ |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 316 | static inline int numdimms(u32 dimms) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 317 | { |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 318 | return (dimms & 0x3) + 1; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 319 | } |
| 320 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 321 | static inline int numrank(u32 rank) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 322 | { |
| 323 | static int ranks[4] = { 1, 2, 4, -EINVAL }; |
| 324 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 325 | return ranks[rank & 0x3]; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 326 | } |
| 327 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 328 | static inline int numbank(u32 bank) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 329 | { |
| 330 | static int banks[4] = { 4, 8, 16, -EINVAL }; |
| 331 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 332 | return banks[bank & 0x3]; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 333 | } |
| 334 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 335 | static inline int numrow(u32 row) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 336 | { |
| 337 | static int rows[8] = { |
| 338 | 1 << 12, 1 << 13, 1 << 14, 1 << 15, |
| 339 | 1 << 16, -EINVAL, -EINVAL, -EINVAL, |
| 340 | }; |
| 341 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 342 | return rows[row & 0x7]; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 343 | } |
| 344 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 345 | static inline int numcol(u32 col) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 346 | { |
| 347 | static int cols[8] = { |
| 348 | 1 << 10, 1 << 11, 1 << 12, -EINVAL, |
| 349 | }; |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 350 | return cols[col & 0x3]; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 351 | } |
| 352 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 353 | static struct i7core_dev *get_i7core_dev(u8 socket) |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 354 | { |
| 355 | struct i7core_dev *i7core_dev; |
| 356 | |
| 357 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) { |
| 358 | if (i7core_dev->socket == socket) |
| 359 | return i7core_dev; |
| 360 | } |
| 361 | |
| 362 | return NULL; |
| 363 | } |
| 364 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 365 | /**************************************************************************** |
| 366 | Memory check routines |
| 367 | ****************************************************************************/ |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 368 | static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot, |
| 369 | unsigned func) |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 370 | { |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 371 | struct i7core_dev *i7core_dev = get_i7core_dev(socket); |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 372 | int i; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 373 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 374 | if (!i7core_dev) |
| 375 | return NULL; |
| 376 | |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 377 | for (i = 0; i < N_DEVS; i++) { |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 378 | if (!i7core_dev->pdev[i]) |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 379 | continue; |
| 380 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 381 | if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot && |
| 382 | PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) { |
| 383 | return i7core_dev->pdev[i]; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 384 | } |
| 385 | } |
| 386 | |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 387 | return NULL; |
| 388 | } |
| 389 | |
Mauro Carvalho Chehab | ec6df24 | 2009-07-18 10:44:30 -0300 | [diff] [blame] | 390 | /** |
| 391 | * i7core_get_active_channels() - gets the number of channels and csrows |
| 392 | * @socket: Quick Path Interconnect socket |
| 393 | * @channels: Number of channels that will be returned |
| 394 | * @csrows: Number of csrows found |
| 395 | * |
| 396 | * Since EDAC core needs to know in advance the number of available channels |
| 397 | * and csrows, in order to allocate memory for csrows/channels, it is needed |
| 398 | * to run two similar steps. At the first step, implemented on this function, |
| 399 | * it checks the number of csrows/channels present at one socket. |
| 400 | * this is used in order to properly allocate the size of mci components. |
| 401 | * |
| 402 | * It should be noticed that none of the current available datasheets explain |
| 403 | * or even mention how csrows are seen by the memory controller. So, we need |
| 404 | * to add a fake description for csrows. |
| 405 | * So, this driver is attributing one DIMM memory for one csrow. |
| 406 | */ |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 407 | static int i7core_get_active_channels(u8 socket, unsigned *channels, |
| 408 | unsigned *csrows) |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 409 | { |
| 410 | struct pci_dev *pdev = NULL; |
| 411 | int i, j; |
| 412 | u32 status, control; |
| 413 | |
| 414 | *channels = 0; |
| 415 | *csrows = 0; |
| 416 | |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 417 | pdev = get_pdev_slot_func(socket, 3, 0); |
Mauro Carvalho Chehab | b7c7615 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 418 | if (!pdev) { |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 419 | i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n", |
| 420 | socket); |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 421 | return -ENODEV; |
Mauro Carvalho Chehab | b7c7615 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 422 | } |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 423 | |
| 424 | /* Device 3 function 0 reads */ |
| 425 | pci_read_config_dword(pdev, MC_STATUS, &status); |
| 426 | pci_read_config_dword(pdev, MC_CONTROL, &control); |
| 427 | |
| 428 | for (i = 0; i < NUM_CHANS; i++) { |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 429 | u32 dimm_dod[3]; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 430 | /* Check if the channel is active */ |
| 431 | if (!(control & (1 << (8 + i)))) |
| 432 | continue; |
| 433 | |
| 434 | /* Check if the channel is disabled */ |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 435 | if (status & (1 << i)) |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 436 | continue; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 437 | |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 438 | pdev = get_pdev_slot_func(socket, i + 4, 1); |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 439 | if (!pdev) { |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 440 | i7core_printk(KERN_ERR, "Couldn't find socket %d " |
| 441 | "fn %d.%d!!!\n", |
| 442 | socket, i + 4, 1); |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 443 | return -ENODEV; |
| 444 | } |
| 445 | /* Devices 4-6 function 1 */ |
| 446 | pci_read_config_dword(pdev, |
| 447 | MC_DOD_CH_DIMM0, &dimm_dod[0]); |
| 448 | pci_read_config_dword(pdev, |
| 449 | MC_DOD_CH_DIMM1, &dimm_dod[1]); |
| 450 | pci_read_config_dword(pdev, |
| 451 | MC_DOD_CH_DIMM2, &dimm_dod[2]); |
| 452 | |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 453 | (*channels)++; |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 454 | |
| 455 | for (j = 0; j < 3; j++) { |
| 456 | if (!DIMM_PRESENT(dimm_dod[j])) |
| 457 | continue; |
| 458 | (*csrows)++; |
| 459 | } |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 460 | } |
| 461 | |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 462 | debugf0("Number of active channels on socket %d: %d\n", |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 463 | socket, *channels); |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 464 | |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 465 | return 0; |
| 466 | } |
| 467 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 468 | static int get_dimm_config(struct mem_ctl_info *mci, int *csrow) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 469 | { |
| 470 | struct i7core_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 471 | struct csrow_info *csr; |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 472 | struct pci_dev *pdev; |
Mauro Carvalho Chehab | ba6c5c6 | 2009-07-15 09:02:32 -0300 | [diff] [blame] | 473 | int i, j; |
Mauro Carvalho Chehab | 5566cb7 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 474 | unsigned long last_page = 0; |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 475 | enum edac_type mode; |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 476 | enum mem_type mtype; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 477 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 478 | /* Get data from the MC register, function 0 */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 479 | pdev = pvt->pci_mcr[0]; |
Mauro Carvalho Chehab | 7dd6953 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 480 | if (!pdev) |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 481 | return -ENODEV; |
| 482 | |
Mauro Carvalho Chehab | f122a89 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 483 | /* Device 3 function 0 reads */ |
Mauro Carvalho Chehab | 7dd6953 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 484 | pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control); |
| 485 | pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status); |
| 486 | pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod); |
| 487 | pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map); |
Mauro Carvalho Chehab | f122a89 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 488 | |
Mauro Carvalho Chehab | 17cb7b0 | 2009-07-20 18:48:18 -0300 | [diff] [blame] | 489 | debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n", |
Mauro Carvalho Chehab | 4af9188 | 2009-09-24 09:58:26 -0300 | [diff] [blame] | 490 | pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status, |
Mauro Carvalho Chehab | f122a89 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 491 | pvt->info.max_dod, pvt->info.ch_map); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 492 | |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 493 | if (ECC_ENABLED(pvt)) { |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 494 | debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4); |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 495 | if (ECCx8(pvt)) |
| 496 | mode = EDAC_S8ECD8ED; |
| 497 | else |
| 498 | mode = EDAC_S4ECD4ED; |
| 499 | } else { |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 500 | debugf0("ECC disabled\n"); |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 501 | mode = EDAC_NONE; |
| 502 | } |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 503 | |
| 504 | /* FIXME: need to handle the error codes */ |
Mauro Carvalho Chehab | 17cb7b0 | 2009-07-20 18:48:18 -0300 | [diff] [blame] | 505 | debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked " |
| 506 | "x%x x 0x%x\n", |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 507 | numdimms(pvt->info.max_dod), |
| 508 | numrank(pvt->info.max_dod >> 2), |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 509 | numbank(pvt->info.max_dod >> 4), |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 510 | numrow(pvt->info.max_dod >> 6), |
| 511 | numcol(pvt->info.max_dod >> 9)); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 512 | |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 513 | for (i = 0; i < NUM_CHANS; i++) { |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 514 | u32 data, dimm_dod[3], value[8]; |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 515 | |
| 516 | if (!CH_ACTIVE(pvt, i)) { |
| 517 | debugf0("Channel %i is not active\n", i); |
| 518 | continue; |
| 519 | } |
| 520 | if (CH_DISABLED(pvt, i)) { |
| 521 | debugf0("Channel %i is disabled\n", i); |
| 522 | continue; |
| 523 | } |
| 524 | |
Mauro Carvalho Chehab | f122a89 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 525 | /* Devices 4-6 function 0 */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 526 | pci_read_config_dword(pvt->pci_ch[i][0], |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 527 | MC_CHANNEL_DIMM_INIT_PARAMS, &data); |
| 528 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 529 | pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ? |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 530 | 4 : 2; |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 531 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 532 | if (data & REGISTERED_DIMM) |
| 533 | mtype = MEM_RDDR3; |
Mauro Carvalho Chehab | 14d2c08 | 2009-09-02 23:52:36 -0300 | [diff] [blame] | 534 | else |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 535 | mtype = MEM_DDR3; |
| 536 | #if 0 |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 537 | if (data & THREE_DIMMS_PRESENT) |
| 538 | pvt->channel[i].dimms = 3; |
| 539 | else if (data & SINGLE_QUAD_RANK_PRESENT) |
| 540 | pvt->channel[i].dimms = 1; |
| 541 | else |
| 542 | pvt->channel[i].dimms = 2; |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 543 | #endif |
| 544 | |
| 545 | /* Devices 4-6 function 1 */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 546 | pci_read_config_dword(pvt->pci_ch[i][1], |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 547 | MC_DOD_CH_DIMM0, &dimm_dod[0]); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 548 | pci_read_config_dword(pvt->pci_ch[i][1], |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 549 | MC_DOD_CH_DIMM1, &dimm_dod[1]); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 550 | pci_read_config_dword(pvt->pci_ch[i][1], |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 551 | MC_DOD_CH_DIMM2, &dimm_dod[2]); |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 552 | |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 553 | debugf0("Ch%d phy rd%d, wr%d (0x%08x): " |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 554 | "%d ranks, %cDIMMs\n", |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 555 | i, |
| 556 | RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i), |
| 557 | data, |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 558 | pvt->channel[i].ranks, |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 559 | (data & REGISTERED_DIMM) ? 'R' : 'U'); |
Mauro Carvalho Chehab | 7dd6953 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 560 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 561 | for (j = 0; j < 3; j++) { |
| 562 | u32 banks, ranks, rows, cols; |
Mauro Carvalho Chehab | 5566cb7 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 563 | u32 size, npages; |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 564 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 565 | if (!DIMM_PRESENT(dimm_dod[j])) |
| 566 | continue; |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 567 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 568 | banks = numbank(MC_DOD_NUMBANK(dimm_dod[j])); |
| 569 | ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j])); |
| 570 | rows = numrow(MC_DOD_NUMROW(dimm_dod[j])); |
| 571 | cols = numcol(MC_DOD_NUMCOL(dimm_dod[j])); |
Mauro Carvalho Chehab | 1c6fed8 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 572 | |
Mauro Carvalho Chehab | 5566cb7 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 573 | /* DDR3 has 8 I/O banks */ |
| 574 | size = (rows * cols * banks * ranks) >> (20 - 3); |
| 575 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 576 | pvt->channel[i].dimms++; |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 577 | |
Mauro Carvalho Chehab | 17cb7b0 | 2009-07-20 18:48:18 -0300 | [diff] [blame] | 578 | debugf0("\tdimm %d %d Mb offset: %x, " |
| 579 | "bank: %d, rank: %d, row: %#x, col: %#x\n", |
| 580 | j, size, |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 581 | RANKOFFSET(dimm_dod[j]), |
| 582 | banks, ranks, rows, cols); |
| 583 | |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 584 | #if PAGE_SHIFT > 20 |
| 585 | npages = size >> (PAGE_SHIFT - 20); |
| 586 | #else |
| 587 | npages = size << (20 - PAGE_SHIFT); |
| 588 | #endif |
Mauro Carvalho Chehab | 5566cb7 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 589 | |
Mauro Carvalho Chehab | ba6c5c6 | 2009-07-15 09:02:32 -0300 | [diff] [blame] | 590 | csr = &mci->csrows[*csrow]; |
Mauro Carvalho Chehab | 5566cb7 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 591 | csr->first_page = last_page + 1; |
| 592 | last_page += npages; |
| 593 | csr->last_page = last_page; |
| 594 | csr->nr_pages = npages; |
| 595 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 596 | csr->page_mask = 0; |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 597 | csr->grain = 8; |
Mauro Carvalho Chehab | ba6c5c6 | 2009-07-15 09:02:32 -0300 | [diff] [blame] | 598 | csr->csrow_idx = *csrow; |
Mauro Carvalho Chehab | eb94fc4 | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 599 | csr->nr_channels = 1; |
| 600 | |
| 601 | csr->channels[0].chan_idx = i; |
| 602 | csr->channels[0].ce_count = 0; |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 603 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 604 | pvt->csrow_map[i][j] = *csrow; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 605 | |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 606 | switch (banks) { |
| 607 | case 4: |
| 608 | csr->dtype = DEV_X4; |
| 609 | break; |
| 610 | case 8: |
| 611 | csr->dtype = DEV_X8; |
| 612 | break; |
| 613 | case 16: |
| 614 | csr->dtype = DEV_X16; |
| 615 | break; |
| 616 | default: |
| 617 | csr->dtype = DEV_UNKNOWN; |
| 618 | } |
| 619 | |
| 620 | csr->edac_mode = mode; |
| 621 | csr->mtype = mtype; |
| 622 | |
Mauro Carvalho Chehab | ba6c5c6 | 2009-07-15 09:02:32 -0300 | [diff] [blame] | 623 | (*csrow)++; |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 624 | } |
| 625 | |
| 626 | pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]); |
| 627 | pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]); |
| 628 | pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]); |
| 629 | pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]); |
| 630 | pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]); |
| 631 | pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]); |
| 632 | pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]); |
| 633 | pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]); |
Mauro Carvalho Chehab | 17cb7b0 | 2009-07-20 18:48:18 -0300 | [diff] [blame] | 634 | debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i); |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 635 | for (j = 0; j < 8; j++) |
Mauro Carvalho Chehab | 17cb7b0 | 2009-07-20 18:48:18 -0300 | [diff] [blame] | 636 | debugf1("\t\t%#x\t%#x\t%#x\n", |
Mauro Carvalho Chehab | 854d334 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 637 | (value[j] >> 27) & 0x1, |
| 638 | (value[j] >> 24) & 0x7, |
| 639 | (value[j] && ((1 << 24) - 1))); |
Mauro Carvalho Chehab | 0b2b7b7 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 640 | } |
| 641 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 642 | return 0; |
| 643 | } |
| 644 | |
| 645 | /**************************************************************************** |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 646 | Error insertion routines |
| 647 | ****************************************************************************/ |
| 648 | |
| 649 | /* The i7core has independent error injection features per channel. |
| 650 | However, to have a simpler code, we don't allow enabling error injection |
| 651 | on more than one channel. |
| 652 | Also, since a change at an inject parameter will be applied only at enable, |
| 653 | we're disabling error injection on all write calls to the sysfs nodes that |
| 654 | controls the error code injection. |
| 655 | */ |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 656 | static int disable_inject(struct mem_ctl_info *mci) |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 657 | { |
| 658 | struct i7core_pvt *pvt = mci->pvt_info; |
| 659 | |
| 660 | pvt->inject.enable = 0; |
| 661 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 662 | if (!pvt->pci_ch[pvt->inject.channel][0]) |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 663 | return -ENODEV; |
| 664 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 665 | pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], |
Mauro Carvalho Chehab | 4157d9f | 2009-08-05 20:27:15 -0300 | [diff] [blame] | 666 | MC_CHANNEL_ERROR_INJECT, 0); |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 667 | |
| 668 | return 0; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 669 | } |
| 670 | |
| 671 | /* |
| 672 | * i7core inject inject.section |
| 673 | * |
| 674 | * accept and store error injection inject.section value |
| 675 | * bit 0 - refers to the lower 32-byte half cacheline |
| 676 | * bit 1 - refers to the upper 32-byte half cacheline |
| 677 | */ |
| 678 | static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci, |
| 679 | const char *data, size_t count) |
| 680 | { |
| 681 | struct i7core_pvt *pvt = mci->pvt_info; |
| 682 | unsigned long value; |
| 683 | int rc; |
| 684 | |
| 685 | if (pvt->inject.enable) |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 686 | disable_inject(mci); |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 687 | |
| 688 | rc = strict_strtoul(data, 10, &value); |
| 689 | if ((rc < 0) || (value > 3)) |
Mauro Carvalho Chehab | 2068def | 2009-08-05 19:28:27 -0300 | [diff] [blame] | 690 | return -EIO; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 691 | |
| 692 | pvt->inject.section = (u32) value; |
| 693 | return count; |
| 694 | } |
| 695 | |
| 696 | static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci, |
| 697 | char *data) |
| 698 | { |
| 699 | struct i7core_pvt *pvt = mci->pvt_info; |
| 700 | return sprintf(data, "0x%08x\n", pvt->inject.section); |
| 701 | } |
| 702 | |
| 703 | /* |
| 704 | * i7core inject.type |
| 705 | * |
| 706 | * accept and store error injection inject.section value |
| 707 | * bit 0 - repeat enable - Enable error repetition |
| 708 | * bit 1 - inject ECC error |
| 709 | * bit 2 - inject parity error |
| 710 | */ |
| 711 | static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci, |
| 712 | const char *data, size_t count) |
| 713 | { |
| 714 | struct i7core_pvt *pvt = mci->pvt_info; |
| 715 | unsigned long value; |
| 716 | int rc; |
| 717 | |
| 718 | if (pvt->inject.enable) |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 719 | disable_inject(mci); |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 720 | |
| 721 | rc = strict_strtoul(data, 10, &value); |
| 722 | if ((rc < 0) || (value > 7)) |
Mauro Carvalho Chehab | 2068def | 2009-08-05 19:28:27 -0300 | [diff] [blame] | 723 | return -EIO; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 724 | |
| 725 | pvt->inject.type = (u32) value; |
| 726 | return count; |
| 727 | } |
| 728 | |
| 729 | static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci, |
| 730 | char *data) |
| 731 | { |
| 732 | struct i7core_pvt *pvt = mci->pvt_info; |
| 733 | return sprintf(data, "0x%08x\n", pvt->inject.type); |
| 734 | } |
| 735 | |
| 736 | /* |
| 737 | * i7core_inject_inject.eccmask_store |
| 738 | * |
| 739 | * The type of error (UE/CE) will depend on the inject.eccmask value: |
| 740 | * Any bits set to a 1 will flip the corresponding ECC bit |
| 741 | * Correctable errors can be injected by flipping 1 bit or the bits within |
| 742 | * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or |
| 743 | * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an |
| 744 | * uncorrectable error to be injected. |
| 745 | */ |
| 746 | static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci, |
| 747 | const char *data, size_t count) |
| 748 | { |
| 749 | struct i7core_pvt *pvt = mci->pvt_info; |
| 750 | unsigned long value; |
| 751 | int rc; |
| 752 | |
| 753 | if (pvt->inject.enable) |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 754 | disable_inject(mci); |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 755 | |
| 756 | rc = strict_strtoul(data, 10, &value); |
| 757 | if (rc < 0) |
Mauro Carvalho Chehab | 2068def | 2009-08-05 19:28:27 -0300 | [diff] [blame] | 758 | return -EIO; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 759 | |
| 760 | pvt->inject.eccmask = (u32) value; |
| 761 | return count; |
| 762 | } |
| 763 | |
| 764 | static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci, |
| 765 | char *data) |
| 766 | { |
| 767 | struct i7core_pvt *pvt = mci->pvt_info; |
| 768 | return sprintf(data, "0x%08x\n", pvt->inject.eccmask); |
| 769 | } |
| 770 | |
| 771 | /* |
| 772 | * i7core_addrmatch |
| 773 | * |
| 774 | * The type of error (UE/CE) will depend on the inject.eccmask value: |
| 775 | * Any bits set to a 1 will flip the corresponding ECC bit |
| 776 | * Correctable errors can be injected by flipping 1 bit or the bits within |
| 777 | * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or |
| 778 | * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an |
| 779 | * uncorrectable error to be injected. |
| 780 | */ |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 781 | |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame^] | 782 | #define DECLARE_ADDR_MATCH(param, limit) \ |
| 783 | static ssize_t i7core_inject_store_##param( \ |
| 784 | struct mem_ctl_info *mci, \ |
| 785 | const char *data, size_t count) \ |
| 786 | { \ |
| 787 | struct i7core_pvt *pvt = mci->pvt_info; \ |
| 788 | long value; \ |
| 789 | int rc; \ |
| 790 | \ |
| 791 | if (pvt->inject.enable) \ |
| 792 | disable_inject(mci); \ |
| 793 | \ |
| 794 | if (!strcasecmp(data, "any")) \ |
| 795 | value = -1; \ |
| 796 | else { \ |
| 797 | rc = strict_strtoul(data, 10, &value); \ |
| 798 | if ((rc < 0) || (value >= limit)) \ |
| 799 | return -EIO; \ |
| 800 | } \ |
| 801 | \ |
| 802 | pvt->inject.param = value; \ |
| 803 | \ |
| 804 | return count; \ |
| 805 | } \ |
| 806 | \ |
| 807 | static ssize_t i7core_inject_show_##param( \ |
| 808 | struct mem_ctl_info *mci, \ |
| 809 | char *data) \ |
| 810 | { \ |
| 811 | struct i7core_pvt *pvt = mci->pvt_info; \ |
| 812 | if (pvt->inject.param < 0) \ |
| 813 | return sprintf(data, "any\n"); \ |
| 814 | else \ |
| 815 | return sprintf(data, "%d\n", pvt->inject.param);\ |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 816 | } |
| 817 | |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame^] | 818 | #define ATTR_ADDR_MATCH(param) \ |
| 819 | { \ |
| 820 | .attr = { \ |
| 821 | .name = #param, \ |
| 822 | .mode = (S_IRUGO | S_IWUSR) \ |
| 823 | }, \ |
| 824 | .show = i7core_inject_show_##param, \ |
| 825 | .store = i7core_inject_store_##param, \ |
| 826 | } |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 827 | |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame^] | 828 | DECLARE_ADDR_MATCH(channel, 3); |
| 829 | DECLARE_ADDR_MATCH(dimm, 3); |
| 830 | DECLARE_ADDR_MATCH(rank, 4); |
| 831 | DECLARE_ADDR_MATCH(bank, 32); |
| 832 | DECLARE_ADDR_MATCH(page, 0x10000); |
| 833 | DECLARE_ADDR_MATCH(col, 0x4000); |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 834 | |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 835 | static int write_and_test(struct pci_dev *dev, int where, u32 val) |
| 836 | { |
| 837 | u32 read; |
| 838 | int count; |
| 839 | |
Mauro Carvalho Chehab | 4157d9f | 2009-08-05 20:27:15 -0300 | [diff] [blame] | 840 | debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n", |
| 841 | dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), |
| 842 | where, val); |
| 843 | |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 844 | for (count = 0; count < 10; count++) { |
| 845 | if (count) |
Mauro Carvalho Chehab | b990538 | 2009-08-05 21:36:35 -0300 | [diff] [blame] | 846 | msleep(100); |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 847 | pci_write_config_dword(dev, where, val); |
| 848 | pci_read_config_dword(dev, where, &read); |
| 849 | |
| 850 | if (read == val) |
| 851 | return 0; |
| 852 | } |
| 853 | |
Mauro Carvalho Chehab | 4157d9f | 2009-08-05 20:27:15 -0300 | [diff] [blame] | 854 | i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x " |
| 855 | "write=%08x. Read=%08x\n", |
| 856 | dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), |
| 857 | where, val, read); |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 858 | |
| 859 | return -EINVAL; |
| 860 | } |
| 861 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 862 | /* |
| 863 | * This routine prepares the Memory Controller for error injection. |
| 864 | * The error will be injected when some process tries to write to the |
| 865 | * memory that matches the given criteria. |
| 866 | * The criteria can be set in terms of a mask where dimm, rank, bank, page |
| 867 | * and col can be specified. |
| 868 | * A -1 value for any of the mask items will make the MCU to ignore |
| 869 | * that matching criteria for error injection. |
| 870 | * |
| 871 | * It should be noticed that the error will only happen after a write operation |
| 872 | * on a memory that matches the condition. if REPEAT_EN is not enabled at |
| 873 | * inject mask, then it will produce just one error. Otherwise, it will repeat |
| 874 | * until the injectmask would be cleaned. |
| 875 | * |
| 876 | * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD |
| 877 | * is reliable enough to check if the MC is using the |
| 878 | * three channels. However, this is not clear at the datasheet. |
| 879 | */ |
| 880 | static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci, |
| 881 | const char *data, size_t count) |
| 882 | { |
| 883 | struct i7core_pvt *pvt = mci->pvt_info; |
| 884 | u32 injectmask; |
| 885 | u64 mask = 0; |
| 886 | int rc; |
| 887 | long enable; |
| 888 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 889 | if (!pvt->pci_ch[pvt->inject.channel][0]) |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 890 | return 0; |
| 891 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 892 | rc = strict_strtoul(data, 10, &enable); |
| 893 | if ((rc < 0)) |
| 894 | return 0; |
| 895 | |
| 896 | if (enable) { |
| 897 | pvt->inject.enable = 1; |
| 898 | } else { |
| 899 | disable_inject(mci); |
| 900 | return count; |
| 901 | } |
| 902 | |
| 903 | /* Sets pvt->inject.dimm mask */ |
| 904 | if (pvt->inject.dimm < 0) |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 905 | mask |= 1L << 41; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 906 | else { |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 907 | if (pvt->channel[pvt->inject.channel].dimms > 2) |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 908 | mask |= (pvt->inject.dimm & 0x3L) << 35; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 909 | else |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 910 | mask |= (pvt->inject.dimm & 0x1L) << 36; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 911 | } |
| 912 | |
| 913 | /* Sets pvt->inject.rank mask */ |
| 914 | if (pvt->inject.rank < 0) |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 915 | mask |= 1L << 40; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 916 | else { |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 917 | if (pvt->channel[pvt->inject.channel].dimms > 2) |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 918 | mask |= (pvt->inject.rank & 0x1L) << 34; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 919 | else |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 920 | mask |= (pvt->inject.rank & 0x3L) << 34; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 921 | } |
| 922 | |
| 923 | /* Sets pvt->inject.bank mask */ |
| 924 | if (pvt->inject.bank < 0) |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 925 | mask |= 1L << 39; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 926 | else |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 927 | mask |= (pvt->inject.bank & 0x15L) << 30; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 928 | |
| 929 | /* Sets pvt->inject.page mask */ |
| 930 | if (pvt->inject.page < 0) |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 931 | mask |= 1L << 38; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 932 | else |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 933 | mask |= (pvt->inject.page & 0xffffL) << 14; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 934 | |
| 935 | /* Sets pvt->inject.column mask */ |
| 936 | if (pvt->inject.col < 0) |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 937 | mask |= 1L << 37; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 938 | else |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 939 | mask |= (pvt->inject.col & 0x3fffL); |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 940 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 941 | /* |
| 942 | * bit 0: REPEAT_EN |
| 943 | * bits 1-2: MASK_HALF_CACHELINE |
| 944 | * bit 3: INJECT_ECC |
| 945 | * bit 4: INJECT_ADDR_PARITY |
| 946 | */ |
| 947 | |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 948 | injectmask = (pvt->inject.type & 1) | |
| 949 | (pvt->inject.section & 0x3) << 1 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 950 | (pvt->inject.type & 0x6) << (3 - 1); |
| 951 | |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 952 | /* Unlock writes to registers - this register is write only */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 953 | pci_write_config_dword(pvt->pci_noncore, |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 954 | MC_CFG_CONTROL, 0x2); |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 955 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 956 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 957 | MC_CHANNEL_ADDR_MATCH, mask); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 958 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 959 | MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L); |
| 960 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 961 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 962 | MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask); |
| 963 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 964 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
Mauro Carvalho Chehab | 4157d9f | 2009-08-05 20:27:15 -0300 | [diff] [blame] | 965 | MC_CHANNEL_ERROR_INJECT, injectmask); |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 966 | |
| 967 | /* |
| 968 | * This is something undocumented, based on my tests |
| 969 | * Without writing 8 to this register, errors aren't injected. Not sure |
| 970 | * why. |
| 971 | */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 972 | pci_write_config_dword(pvt->pci_noncore, |
Mauro Carvalho Chehab | 276b824 | 2009-07-22 21:45:50 -0300 | [diff] [blame] | 973 | MC_CFG_CONTROL, 8); |
| 974 | |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 975 | debugf0("Error inject addr match 0x%016llx, ecc 0x%08x," |
| 976 | " inject 0x%08x\n", |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 977 | mask, pvt->inject.eccmask, injectmask); |
| 978 | |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 979 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 980 | return count; |
| 981 | } |
| 982 | |
| 983 | static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci, |
| 984 | char *data) |
| 985 | { |
| 986 | struct i7core_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 987 | u32 injectmask; |
| 988 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 989 | pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0], |
Mauro Carvalho Chehab | 4157d9f | 2009-08-05 20:27:15 -0300 | [diff] [blame] | 990 | MC_CHANNEL_ERROR_INJECT, &injectmask); |
Mauro Carvalho Chehab | 7b029d0 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 991 | |
| 992 | debugf0("Inject error read: 0x%018x\n", injectmask); |
| 993 | |
| 994 | if (injectmask & 0x0c) |
| 995 | pvt->inject.enable = 1; |
| 996 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 997 | return sprintf(data, "%d\n", pvt->inject.enable); |
| 998 | } |
| 999 | |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1000 | static ssize_t i7core_ce_regs_show(struct mem_ctl_info *mci, char *data) |
| 1001 | { |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1002 | unsigned i, count, total = 0; |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1003 | struct i7core_pvt *pvt = mci->pvt_info; |
| 1004 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1005 | if (!pvt->ce_count_available) { |
| 1006 | count = sprintf(data, "data unavailable\n"); |
| 1007 | return 0; |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 1008 | } |
Mauro Carvalho Chehab | d88b850 | 2009-09-05 05:10:31 -0300 | [diff] [blame] | 1009 | if (!pvt->is_registered) { |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1010 | count = sprintf(data, "all channels " |
| 1011 | "UDIMM0: %lu UDIMM1: %lu UDIMM2: %lu\n", |
| 1012 | pvt->udimm_ce_count[0], |
| 1013 | pvt->udimm_ce_count[1], |
| 1014 | pvt->udimm_ce_count[2]); |
Mauro Carvalho Chehab | d88b850 | 2009-09-05 05:10:31 -0300 | [diff] [blame] | 1015 | data += count; |
| 1016 | total += count; |
| 1017 | } else { |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1018 | for (i = 0; i < NUM_CHANS; i++) { |
| 1019 | count = sprintf(data, "channel %d RDIMM0: %lu " |
| 1020 | "RDIMM1: %lu RDIMM2: %lu\n", |
| 1021 | i, |
| 1022 | pvt->rdimm_ce_count[i][0], |
| 1023 | pvt->rdimm_ce_count[i][1], |
| 1024 | pvt->rdimm_ce_count[i][2]); |
Mauro Carvalho Chehab | d88b850 | 2009-09-05 05:10:31 -0300 | [diff] [blame] | 1025 | data += count; |
| 1026 | total += count; |
| 1027 | } |
| 1028 | } |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1029 | |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 1030 | return total; |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1031 | } |
| 1032 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1033 | /* |
| 1034 | * Sysfs struct |
| 1035 | */ |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame^] | 1036 | |
| 1037 | |
| 1038 | static struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = { |
| 1039 | ATTR_ADDR_MATCH(channel), |
| 1040 | ATTR_ADDR_MATCH(dimm), |
| 1041 | ATTR_ADDR_MATCH(rank), |
| 1042 | ATTR_ADDR_MATCH(bank), |
| 1043 | ATTR_ADDR_MATCH(page), |
| 1044 | ATTR_ADDR_MATCH(col), |
| 1045 | { .attr = { .name = NULL } } |
| 1046 | }; |
| 1047 | |
| 1048 | |
| 1049 | static struct mcidev_sysfs_group i7core_inject_addrmatch = { |
| 1050 | .name = "inject_addrmatch", |
| 1051 | .mcidev_attr = i7core_addrmatch_attrs, |
| 1052 | }; |
| 1053 | |
| 1054 | static struct mcidev_sysfs_attribute i7core_sysfs_attrs[] = { |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1055 | { |
| 1056 | .attr = { |
| 1057 | .name = "inject_section", |
| 1058 | .mode = (S_IRUGO | S_IWUSR) |
| 1059 | }, |
| 1060 | .show = i7core_inject_section_show, |
| 1061 | .store = i7core_inject_section_store, |
| 1062 | }, { |
| 1063 | .attr = { |
| 1064 | .name = "inject_type", |
| 1065 | .mode = (S_IRUGO | S_IWUSR) |
| 1066 | }, |
| 1067 | .show = i7core_inject_type_show, |
| 1068 | .store = i7core_inject_type_store, |
| 1069 | }, { |
| 1070 | .attr = { |
| 1071 | .name = "inject_eccmask", |
| 1072 | .mode = (S_IRUGO | S_IWUSR) |
| 1073 | }, |
| 1074 | .show = i7core_inject_eccmask_show, |
| 1075 | .store = i7core_inject_eccmask_store, |
| 1076 | }, { |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame^] | 1077 | .grp = &i7core_inject_addrmatch, |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1078 | }, { |
| 1079 | .attr = { |
| 1080 | .name = "inject_enable", |
| 1081 | .mode = (S_IRUGO | S_IWUSR) |
| 1082 | }, |
| 1083 | .show = i7core_inject_enable_show, |
| 1084 | .store = i7core_inject_enable_store, |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1085 | }, { |
| 1086 | .attr = { |
| 1087 | .name = "corrected_error_counts", |
| 1088 | .mode = (S_IRUGO | S_IWUSR) |
| 1089 | }, |
| 1090 | .show = i7core_ce_regs_show, |
| 1091 | .store = NULL, |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1092 | }, |
Mauro Carvalho Chehab | 4253868 | 2009-09-24 09:59:13 -0300 | [diff] [blame] | 1093 | { .attr = { .name = NULL } } |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1094 | }; |
| 1095 | |
| 1096 | /**************************************************************************** |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1097 | Device initialization routines: put/get, init/exit |
| 1098 | ****************************************************************************/ |
| 1099 | |
| 1100 | /* |
| 1101 | * i7core_put_devices 'put' all the devices that we have |
| 1102 | * reserved via 'get' |
| 1103 | */ |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1104 | static void i7core_put_devices(struct i7core_dev *i7core_dev) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1105 | { |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1106 | int i; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1107 | |
Mauro Carvalho Chehab | 22e6bcb | 2009-09-05 23:06:50 -0300 | [diff] [blame] | 1108 | debugf0(__FILE__ ": %s()\n", __func__); |
| 1109 | for (i = 0; i < N_DEVS; i++) { |
| 1110 | struct pci_dev *pdev = i7core_dev->pdev[i]; |
| 1111 | if (!pdev) |
| 1112 | continue; |
| 1113 | debugf0("Removing dev %02x:%02x.%d\n", |
| 1114 | pdev->bus->number, |
| 1115 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); |
| 1116 | pci_dev_put(pdev); |
| 1117 | } |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1118 | kfree(i7core_dev->pdev); |
Mauro Carvalho Chehab | 22e6bcb | 2009-09-05 23:06:50 -0300 | [diff] [blame] | 1119 | list_del(&i7core_dev->list); |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1120 | kfree(i7core_dev); |
| 1121 | } |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1122 | |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1123 | static void i7core_put_all_devices(void) |
| 1124 | { |
Mauro Carvalho Chehab | 4253868 | 2009-09-24 09:59:13 -0300 | [diff] [blame] | 1125 | struct i7core_dev *i7core_dev, *tmp; |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1126 | |
Mauro Carvalho Chehab | 4253868 | 2009-09-24 09:59:13 -0300 | [diff] [blame] | 1127 | list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1128 | i7core_put_devices(i7core_dev); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1129 | } |
| 1130 | |
Keith Mannthey | bc2d724 | 2009-09-03 00:05:05 -0300 | [diff] [blame] | 1131 | static void i7core_xeon_pci_fixup(void) |
| 1132 | { |
| 1133 | struct pci_dev *pdev = NULL; |
| 1134 | int i; |
| 1135 | /* |
| 1136 | * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses |
| 1137 | * aren't announced by acpi. So, we need to use a legacy scan probing |
| 1138 | * to detect them |
| 1139 | */ |
| 1140 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1141 | pci_dev_descr[0].dev_id, NULL); |
Keith Mannthey | bc2d724 | 2009-09-03 00:05:05 -0300 | [diff] [blame] | 1142 | if (unlikely(!pdev)) { |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1143 | for (i = 0; i < MAX_SOCKET_BUSES; i++) |
Keith Mannthey | bc2d724 | 2009-09-03 00:05:05 -0300 | [diff] [blame] | 1144 | pcibios_scan_specific_bus(255-i); |
| 1145 | } |
| 1146 | } |
| 1147 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1148 | /* |
| 1149 | * i7core_get_devices Find and perform 'get' operation on the MCH's |
| 1150 | * device/functions we want to reference for this driver |
| 1151 | * |
| 1152 | * Need to 'get' device 16 func 1 and func 2 |
| 1153 | */ |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1154 | int i7core_get_onedevice(struct pci_dev **prev, int devno) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1155 | { |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1156 | struct i7core_dev *i7core_dev; |
| 1157 | |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1158 | struct pci_dev *pdev = NULL; |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 1159 | u8 bus = 0; |
| 1160 | u8 socket = 0; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1161 | |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1162 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1163 | pci_dev_descr[devno].dev_id, *prev); |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1164 | |
| 1165 | /* |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1166 | * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs |
| 1167 | * is at addr 8086:2c40, instead of 8086:2c41. So, we need |
| 1168 | * to probe for the alternate address in case of failure |
| 1169 | */ |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1170 | if (pci_dev_descr[devno].dev_id == PCI_DEVICE_ID_INTEL_I7_NOCORE && !pdev) |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1171 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 1172 | PCI_DEVICE_ID_INTEL_I7_NOCORE_ALT, *prev); |
Mauro Carvalho Chehab | d1fd4fb | 2009-07-10 18:39:53 -0300 | [diff] [blame] | 1173 | |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1174 | if (!pdev) { |
| 1175 | if (*prev) { |
| 1176 | *prev = pdev; |
| 1177 | return 0; |
Mauro Carvalho Chehab | d1fd4fb | 2009-07-10 18:39:53 -0300 | [diff] [blame] | 1178 | } |
| 1179 | |
Mauro Carvalho Chehab | 310cbb7 | 2009-07-17 00:09:10 -0300 | [diff] [blame] | 1180 | /* |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1181 | * Dev 3 function 2 only exists on chips with RDIMMs |
| 1182 | * so, it is ok to not found it |
Mauro Carvalho Chehab | 310cbb7 | 2009-07-17 00:09:10 -0300 | [diff] [blame] | 1183 | */ |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1184 | if ((pci_dev_descr[devno].dev == 3) && (pci_dev_descr[devno].func == 2)) { |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1185 | *prev = pdev; |
| 1186 | return 0; |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1187 | } |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1188 | |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1189 | i7core_printk(KERN_ERR, |
| 1190 | "Device not found: dev %02x.%d PCI ID %04x:%04x\n", |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1191 | pci_dev_descr[devno].dev, pci_dev_descr[devno].func, |
| 1192 | PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id); |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1193 | |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1194 | /* End of list, leave */ |
| 1195 | return -ENODEV; |
| 1196 | } |
| 1197 | bus = pdev->bus->number; |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1198 | |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1199 | if (bus == 0x3f) |
| 1200 | socket = 0; |
| 1201 | else |
| 1202 | socket = 255 - bus; |
| 1203 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1204 | i7core_dev = get_i7core_dev(socket); |
| 1205 | if (!i7core_dev) { |
| 1206 | i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL); |
| 1207 | if (!i7core_dev) |
| 1208 | return -ENOMEM; |
| 1209 | i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * N_DEVS, |
| 1210 | GFP_KERNEL); |
| 1211 | if (!i7core_dev->pdev) |
| 1212 | return -ENOMEM; |
| 1213 | i7core_dev->socket = socket; |
| 1214 | list_add_tail(&i7core_dev->list, &i7core_edac_list); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1215 | } |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1216 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1217 | if (i7core_dev->pdev[devno]) { |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1218 | i7core_printk(KERN_ERR, |
| 1219 | "Duplicated device for " |
| 1220 | "dev %02x:%02x.%d PCI ID %04x:%04x\n", |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1221 | bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func, |
| 1222 | PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id); |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1223 | pci_dev_put(pdev); |
| 1224 | return -ENODEV; |
| 1225 | } |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1226 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1227 | i7core_dev->pdev[devno] = pdev; |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1228 | |
| 1229 | /* Sanity check */ |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1230 | if (unlikely(PCI_SLOT(pdev->devfn) != pci_dev_descr[devno].dev || |
| 1231 | PCI_FUNC(pdev->devfn) != pci_dev_descr[devno].func)) { |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1232 | i7core_printk(KERN_ERR, |
| 1233 | "Device PCI ID %04x:%04x " |
| 1234 | "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n", |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1235 | PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id, |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1236 | bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1237 | bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func); |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1238 | return -ENODEV; |
| 1239 | } |
| 1240 | |
| 1241 | /* Be sure that the device is enabled */ |
| 1242 | if (unlikely(pci_enable_device(pdev) < 0)) { |
| 1243 | i7core_printk(KERN_ERR, |
| 1244 | "Couldn't enable " |
| 1245 | "dev %02x:%02x.%d PCI ID %04x:%04x\n", |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1246 | bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func, |
| 1247 | PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id); |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1248 | return -ENODEV; |
| 1249 | } |
| 1250 | |
Mauro Carvalho Chehab | d4c2779 | 2009-09-05 04:12:02 -0300 | [diff] [blame] | 1251 | debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n", |
| 1252 | socket, bus, pci_dev_descr[devno].dev, |
| 1253 | pci_dev_descr[devno].func, |
| 1254 | PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id); |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1255 | |
| 1256 | *prev = pdev; |
| 1257 | |
| 1258 | return 0; |
| 1259 | } |
| 1260 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1261 | static int i7core_get_devices(void) |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1262 | { |
| 1263 | int i; |
| 1264 | struct pci_dev *pdev = NULL; |
| 1265 | |
| 1266 | for (i = 0; i < N_DEVS; i++) { |
| 1267 | pdev = NULL; |
| 1268 | do { |
| 1269 | if (i7core_get_onedevice(&pdev, i) < 0) { |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1270 | i7core_put_all_devices(); |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1271 | return -ENODEV; |
| 1272 | } |
| 1273 | } while (pdev); |
| 1274 | } |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1275 | |
Mauro Carvalho Chehab | c77720b | 2009-07-18 10:43:08 -0300 | [diff] [blame] | 1276 | return 0; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1277 | } |
| 1278 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1279 | static int mci_bind_devs(struct mem_ctl_info *mci, |
| 1280 | struct i7core_dev *i7core_dev) |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1281 | { |
| 1282 | struct i7core_pvt *pvt = mci->pvt_info; |
| 1283 | struct pci_dev *pdev; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1284 | int i, func, slot; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1285 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1286 | /* Associates i7core_dev and mci for future usage */ |
| 1287 | pvt->i7core_dev = i7core_dev; |
| 1288 | i7core_dev->mci = mci; |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1289 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1290 | pvt->is_registered = 0; |
| 1291 | for (i = 0; i < N_DEVS; i++) { |
| 1292 | pdev = i7core_dev->pdev[i]; |
| 1293 | if (!pdev) |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1294 | continue; |
| 1295 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1296 | func = PCI_FUNC(pdev->devfn); |
| 1297 | slot = PCI_SLOT(pdev->devfn); |
| 1298 | if (slot == 3) { |
| 1299 | if (unlikely(func > MAX_MCR_FUNC)) |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1300 | goto error; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1301 | pvt->pci_mcr[func] = pdev; |
| 1302 | } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) { |
| 1303 | if (unlikely(func > MAX_CHAN_FUNC)) |
| 1304 | goto error; |
| 1305 | pvt->pci_ch[slot - 4][func] = pdev; |
| 1306 | } else if (!slot && !func) |
| 1307 | pvt->pci_noncore = pdev; |
| 1308 | else |
| 1309 | goto error; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1310 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1311 | debugf0("Associated fn %d.%d, dev = %p, socket %d\n", |
| 1312 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
| 1313 | pdev, i7core_dev->socket); |
Mauro Carvalho Chehab | 14d2c08 | 2009-09-02 23:52:36 -0300 | [diff] [blame] | 1314 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1315 | if (PCI_SLOT(pdev->devfn) == 3 && |
| 1316 | PCI_FUNC(pdev->devfn) == 2) |
| 1317 | pvt->is_registered = 1; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1318 | } |
Mauro Carvalho Chehab | e9bd2e7 | 2009-07-09 22:14:35 -0300 | [diff] [blame] | 1319 | |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1320 | return 0; |
| 1321 | |
| 1322 | error: |
| 1323 | i7core_printk(KERN_ERR, "Device %d, function %d " |
| 1324 | "is out of the expected range\n", |
| 1325 | slot, func); |
| 1326 | return -EINVAL; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1327 | } |
| 1328 | |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1329 | /**************************************************************************** |
| 1330 | Error check routines |
| 1331 | ****************************************************************************/ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1332 | static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci, |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1333 | int chan, int dimm, int add) |
| 1334 | { |
| 1335 | char *msg; |
| 1336 | struct i7core_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1337 | int row = pvt->csrow_map[chan][dimm], i; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1338 | |
| 1339 | for (i = 0; i < add; i++) { |
| 1340 | msg = kasprintf(GFP_KERNEL, "Corrected error " |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1341 | "(Socket=%d channel=%d dimm=%d)", |
| 1342 | pvt->i7core_dev->socket, chan, dimm); |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1343 | |
| 1344 | edac_mc_handle_fbd_ce(mci, row, 0, msg); |
| 1345 | kfree (msg); |
| 1346 | } |
| 1347 | } |
| 1348 | |
| 1349 | static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci, |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1350 | int chan, int new0, int new1, int new2) |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1351 | { |
| 1352 | struct i7core_pvt *pvt = mci->pvt_info; |
| 1353 | int add0 = 0, add1 = 0, add2 = 0; |
| 1354 | /* Updates CE counters if it is not the first time here */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1355 | if (pvt->ce_count_available) { |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1356 | /* Updates CE counters */ |
| 1357 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1358 | add2 = new2 - pvt->rdimm_last_ce_count[chan][2]; |
| 1359 | add1 = new1 - pvt->rdimm_last_ce_count[chan][1]; |
| 1360 | add0 = new0 - pvt->rdimm_last_ce_count[chan][0]; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1361 | |
| 1362 | if (add2 < 0) |
| 1363 | add2 += 0x7fff; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1364 | pvt->rdimm_ce_count[chan][2] += add2; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1365 | |
| 1366 | if (add1 < 0) |
| 1367 | add1 += 0x7fff; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1368 | pvt->rdimm_ce_count[chan][1] += add1; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1369 | |
| 1370 | if (add0 < 0) |
| 1371 | add0 += 0x7fff; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1372 | pvt->rdimm_ce_count[chan][0] += add0; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1373 | } else |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1374 | pvt->ce_count_available = 1; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1375 | |
| 1376 | /* Store the new values */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1377 | pvt->rdimm_last_ce_count[chan][2] = new2; |
| 1378 | pvt->rdimm_last_ce_count[chan][1] = new1; |
| 1379 | pvt->rdimm_last_ce_count[chan][0] = new0; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1380 | |
| 1381 | /*updated the edac core */ |
| 1382 | if (add0 != 0) |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1383 | i7core_rdimm_update_csrow(mci, chan, 0, add0); |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1384 | if (add1 != 0) |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1385 | i7core_rdimm_update_csrow(mci, chan, 1, add1); |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1386 | if (add2 != 0) |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1387 | i7core_rdimm_update_csrow(mci, chan, 2, add2); |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1388 | |
| 1389 | } |
| 1390 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1391 | static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci) |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1392 | { |
| 1393 | struct i7core_pvt *pvt = mci->pvt_info; |
| 1394 | u32 rcv[3][2]; |
| 1395 | int i, new0, new1, new2; |
| 1396 | |
| 1397 | /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1398 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0, |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1399 | &rcv[0][0]); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1400 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1, |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1401 | &rcv[0][1]); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1402 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2, |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1403 | &rcv[1][0]); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1404 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3, |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1405 | &rcv[1][1]); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1406 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4, |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1407 | &rcv[2][0]); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1408 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5, |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1409 | &rcv[2][1]); |
| 1410 | for (i = 0 ; i < 3; i++) { |
| 1411 | debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n", |
| 1412 | (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]); |
| 1413 | /*if the channel has 3 dimms*/ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1414 | if (pvt->channel[i].dimms > 2) { |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1415 | new0 = DIMM_BOT_COR_ERR(rcv[i][0]); |
| 1416 | new1 = DIMM_TOP_COR_ERR(rcv[i][0]); |
| 1417 | new2 = DIMM_BOT_COR_ERR(rcv[i][1]); |
| 1418 | } else { |
| 1419 | new0 = DIMM_TOP_COR_ERR(rcv[i][0]) + |
| 1420 | DIMM_BOT_COR_ERR(rcv[i][0]); |
| 1421 | new1 = DIMM_TOP_COR_ERR(rcv[i][1]) + |
| 1422 | DIMM_BOT_COR_ERR(rcv[i][1]); |
| 1423 | new2 = 0; |
| 1424 | } |
| 1425 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1426 | i7core_rdimm_update_ce_count(mci, i, new0, new1, new2); |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1427 | } |
| 1428 | } |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1429 | |
| 1430 | /* This function is based on the device 3 function 4 registers as described on: |
| 1431 | * Intel Xeon Processor 5500 Series Datasheet Volume 2 |
| 1432 | * http://www.intel.com/Assets/PDF/datasheet/321322.pdf |
| 1433 | * also available at: |
| 1434 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf |
| 1435 | */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1436 | static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci) |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1437 | { |
| 1438 | struct i7core_pvt *pvt = mci->pvt_info; |
| 1439 | u32 rcv1, rcv0; |
| 1440 | int new0, new1, new2; |
| 1441 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1442 | if (!pvt->pci_mcr[4]) { |
Mauro Carvalho Chehab | b990538 | 2009-08-05 21:36:35 -0300 | [diff] [blame] | 1443 | debugf0("%s MCR registers not found\n", __func__); |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1444 | return; |
| 1445 | } |
| 1446 | |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1447 | /* Corrected test errors */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1448 | pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1); |
| 1449 | pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0); |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1450 | |
| 1451 | /* Store the new values */ |
| 1452 | new2 = DIMM2_COR_ERR(rcv1); |
| 1453 | new1 = DIMM1_COR_ERR(rcv0); |
| 1454 | new0 = DIMM0_COR_ERR(rcv0); |
| 1455 | |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1456 | /* Updates CE counters if it is not the first time here */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1457 | if (pvt->ce_count_available) { |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1458 | /* Updates CE counters */ |
| 1459 | int add0, add1, add2; |
| 1460 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1461 | add2 = new2 - pvt->udimm_last_ce_count[2]; |
| 1462 | add1 = new1 - pvt->udimm_last_ce_count[1]; |
| 1463 | add0 = new0 - pvt->udimm_last_ce_count[0]; |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1464 | |
| 1465 | if (add2 < 0) |
| 1466 | add2 += 0x7fff; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1467 | pvt->udimm_ce_count[2] += add2; |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1468 | |
| 1469 | if (add1 < 0) |
| 1470 | add1 += 0x7fff; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1471 | pvt->udimm_ce_count[1] += add1; |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1472 | |
| 1473 | if (add0 < 0) |
| 1474 | add0 += 0x7fff; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1475 | pvt->udimm_ce_count[0] += add0; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1476 | |
| 1477 | if (add0 | add1 | add2) |
| 1478 | i7core_printk(KERN_ERR, "New Corrected error(s): " |
| 1479 | "dimm0: +%d, dimm1: +%d, dimm2 +%d\n", |
| 1480 | add0, add1, add2); |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1481 | } else |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1482 | pvt->ce_count_available = 1; |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1483 | |
| 1484 | /* Store the new values */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1485 | pvt->udimm_last_ce_count[2] = new2; |
| 1486 | pvt->udimm_last_ce_count[1] = new1; |
| 1487 | pvt->udimm_last_ce_count[0] = new0; |
Mauro Carvalho Chehab | 442305b | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1488 | } |
| 1489 | |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1490 | /* |
| 1491 | * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32 |
| 1492 | * Architectures Software Developer’s Manual Volume 3B. |
Mauro Carvalho Chehab | f237fcf | 2009-07-15 19:53:24 -0300 | [diff] [blame] | 1493 | * Nehalem are defined as family 0x06, model 0x1a |
| 1494 | * |
| 1495 | * The MCA registers used here are the following ones: |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1496 | * struct mce field MCA Register |
Mauro Carvalho Chehab | f237fcf | 2009-07-15 19:53:24 -0300 | [diff] [blame] | 1497 | * m->status MSR_IA32_MC8_STATUS |
| 1498 | * m->addr MSR_IA32_MC8_ADDR |
| 1499 | * m->misc MSR_IA32_MC8_MISC |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1500 | * In the case of Nehalem, the error information is masked at .status and .misc |
| 1501 | * fields |
| 1502 | */ |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1503 | static void i7core_mce_output_error(struct mem_ctl_info *mci, |
| 1504 | struct mce *m) |
| 1505 | { |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1506 | struct i7core_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | a639539 | 2009-07-17 10:54:23 -0300 | [diff] [blame] | 1507 | char *type, *optype, *err, *msg; |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1508 | unsigned long error = m->status & 0x1ff0000l; |
Mauro Carvalho Chehab | a639539 | 2009-07-17 10:54:23 -0300 | [diff] [blame] | 1509 | u32 optypenum = (m->status >> 4) & 0x07; |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1510 | u32 core_err_cnt = (m->status >> 38) && 0x7fff; |
| 1511 | u32 dimm = (m->misc >> 16) & 0x3; |
| 1512 | u32 channel = (m->misc >> 18) & 0x3; |
| 1513 | u32 syndrome = m->misc >> 32; |
| 1514 | u32 errnum = find_first_bit(&error, 32); |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1515 | int csrow; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1516 | |
Mauro Carvalho Chehab | c5d3452 | 2009-07-17 10:28:15 -0300 | [diff] [blame] | 1517 | if (m->mcgstatus & 1) |
| 1518 | type = "FATAL"; |
| 1519 | else |
| 1520 | type = "NON_FATAL"; |
| 1521 | |
Mauro Carvalho Chehab | a639539 | 2009-07-17 10:54:23 -0300 | [diff] [blame] | 1522 | switch (optypenum) { |
Mauro Carvalho Chehab | b990538 | 2009-08-05 21:36:35 -0300 | [diff] [blame] | 1523 | case 0: |
| 1524 | optype = "generic undef request"; |
| 1525 | break; |
| 1526 | case 1: |
| 1527 | optype = "read error"; |
| 1528 | break; |
| 1529 | case 2: |
| 1530 | optype = "write error"; |
| 1531 | break; |
| 1532 | case 3: |
| 1533 | optype = "addr/cmd error"; |
| 1534 | break; |
| 1535 | case 4: |
| 1536 | optype = "scrubbing error"; |
| 1537 | break; |
| 1538 | default: |
| 1539 | optype = "reserved"; |
| 1540 | break; |
Mauro Carvalho Chehab | a639539 | 2009-07-17 10:54:23 -0300 | [diff] [blame] | 1541 | } |
| 1542 | |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1543 | switch (errnum) { |
| 1544 | case 16: |
| 1545 | err = "read ECC error"; |
| 1546 | break; |
| 1547 | case 17: |
| 1548 | err = "RAS ECC error"; |
| 1549 | break; |
| 1550 | case 18: |
| 1551 | err = "write parity error"; |
| 1552 | break; |
| 1553 | case 19: |
| 1554 | err = "redundacy loss"; |
| 1555 | break; |
| 1556 | case 20: |
| 1557 | err = "reserved"; |
| 1558 | break; |
| 1559 | case 21: |
| 1560 | err = "memory range error"; |
| 1561 | break; |
| 1562 | case 22: |
| 1563 | err = "RTID out of range"; |
| 1564 | break; |
| 1565 | case 23: |
| 1566 | err = "address parity error"; |
| 1567 | break; |
| 1568 | case 24: |
| 1569 | err = "byte enable parity error"; |
| 1570 | break; |
| 1571 | default: |
| 1572 | err = "unknown"; |
| 1573 | } |
| 1574 | |
Mauro Carvalho Chehab | f237fcf | 2009-07-15 19:53:24 -0300 | [diff] [blame] | 1575 | /* FIXME: should convert addr into bank and rank information */ |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1576 | msg = kasprintf(GFP_ATOMIC, |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1577 | "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, " |
Mauro Carvalho Chehab | a639539 | 2009-07-17 10:54:23 -0300 | [diff] [blame] | 1578 | "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n", |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1579 | type, (long long) m->addr, m->cpu, dimm, channel, |
Mauro Carvalho Chehab | a639539 | 2009-07-17 10:54:23 -0300 | [diff] [blame] | 1580 | syndrome, core_err_cnt, (long long)m->status, |
| 1581 | (long long)m->misc, optype, err); |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1582 | |
| 1583 | debugf0("%s", msg); |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1584 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1585 | csrow = pvt->csrow_map[channel][dimm]; |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1586 | |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1587 | /* Call the helper to output message */ |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1588 | if (m->mcgstatus & 1) |
| 1589 | edac_mc_handle_fbd_ue(mci, csrow, 0, |
| 1590 | 0 /* FIXME: should be channel here */, msg); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1591 | else if (!pvt->is_registered) |
Mauro Carvalho Chehab | b4e8f0b | 2009-09-02 23:49:59 -0300 | [diff] [blame] | 1592 | edac_mc_handle_fbd_ce(mci, csrow, |
| 1593 | 0 /* FIXME: should be channel here */, msg); |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1594 | |
| 1595 | kfree(msg); |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1596 | } |
| 1597 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1598 | /* |
Mauro Carvalho Chehab | 87d1d27 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1599 | * i7core_check_error Retrieve and process errors reported by the |
| 1600 | * hardware. Called by the Core module. |
| 1601 | */ |
| 1602 | static void i7core_check_error(struct mem_ctl_info *mci) |
| 1603 | { |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1604 | struct i7core_pvt *pvt = mci->pvt_info; |
| 1605 | int i; |
| 1606 | unsigned count = 0; |
| 1607 | struct mce *m = NULL; |
| 1608 | unsigned long flags; |
| 1609 | |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1610 | /* Copy all mce errors into a temporary buffer */ |
| 1611 | spin_lock_irqsave(&pvt->mce_lock, flags); |
| 1612 | if (pvt->mce_count) { |
| 1613 | m = kmalloc(sizeof(*m) * pvt->mce_count, GFP_ATOMIC); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1614 | |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1615 | if (m) { |
| 1616 | count = pvt->mce_count; |
| 1617 | memcpy(m, &pvt->mce_entry, sizeof(*m) * count); |
| 1618 | } |
| 1619 | pvt->mce_count = 0; |
| 1620 | } |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1621 | |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1622 | spin_unlock_irqrestore(&pvt->mce_lock, flags); |
| 1623 | |
| 1624 | /* proccess mcelog errors */ |
| 1625 | for (i = 0; i < count; i++) |
| 1626 | i7core_mce_output_error(mci, &m[i]); |
| 1627 | |
| 1628 | kfree(m); |
| 1629 | |
| 1630 | /* check memory count errors */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1631 | if (!pvt->is_registered) |
| 1632 | i7core_udimm_check_mc_ecc_err(mci); |
| 1633 | else |
| 1634 | i7core_rdimm_check_mc_ecc_err(mci); |
Mauro Carvalho Chehab | 87d1d27 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1635 | } |
| 1636 | |
| 1637 | /* |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1638 | * i7core_mce_check_error Replicates mcelog routine to get errors |
| 1639 | * This routine simply queues mcelog errors, and |
| 1640 | * return. The error itself should be handled later |
| 1641 | * by i7core_check_error. |
| 1642 | */ |
| 1643 | static int i7core_mce_check_error(void *priv, struct mce *mce) |
| 1644 | { |
Mauro Carvalho Chehab | c5d3452 | 2009-07-17 10:28:15 -0300 | [diff] [blame] | 1645 | struct mem_ctl_info *mci = priv; |
| 1646 | struct i7core_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1647 | unsigned long flags; |
| 1648 | |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1649 | /* |
| 1650 | * Just let mcelog handle it if the error is |
| 1651 | * outside the memory controller |
| 1652 | */ |
| 1653 | if (((mce->status & 0xffff) >> 7) != 1) |
| 1654 | return 0; |
| 1655 | |
Mauro Carvalho Chehab | f237fcf | 2009-07-15 19:53:24 -0300 | [diff] [blame] | 1656 | /* Bank 8 registers are the only ones that we know how to handle */ |
| 1657 | if (mce->bank != 8) |
| 1658 | return 0; |
| 1659 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1660 | /* Only handle if it is the right mc controller */ |
Mauro Carvalho Chehab | 6c6aa3a | 2009-09-05 03:27:04 -0300 | [diff] [blame] | 1661 | if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket) { |
| 1662 | debugf0("mc%d: ignoring mce log for socket %d. " |
| 1663 | "Another mc should get it.\n", |
| 1664 | pvt->i7core_dev->socket, |
| 1665 | cpu_data(mce->cpu).phys_proc_id); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1666 | return 0; |
Mauro Carvalho Chehab | 6c6aa3a | 2009-09-05 03:27:04 -0300 | [diff] [blame] | 1667 | } |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1668 | |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1669 | spin_lock_irqsave(&pvt->mce_lock, flags); |
| 1670 | if (pvt->mce_count < MCE_LOG_LEN) { |
| 1671 | memcpy(&pvt->mce_entry[pvt->mce_count], mce, sizeof(*mce)); |
| 1672 | pvt->mce_count++; |
| 1673 | } |
| 1674 | spin_unlock_irqrestore(&pvt->mce_lock, flags); |
| 1675 | |
Mauro Carvalho Chehab | c5d3452 | 2009-07-17 10:28:15 -0300 | [diff] [blame] | 1676 | /* Handle fatal errors immediately */ |
| 1677 | if (mce->mcgstatus & 1) |
| 1678 | i7core_check_error(mci); |
| 1679 | |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1680 | /* Advice mcelog that the error were handled */ |
Mauro Carvalho Chehab | 8a2f118 | 2009-07-15 19:01:08 -0300 | [diff] [blame] | 1681 | return 1; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1682 | } |
| 1683 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1684 | static int i7core_register_mci(struct i7core_dev *i7core_dev, |
| 1685 | int num_channels, int num_csrows) |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1686 | { |
| 1687 | struct mem_ctl_info *mci; |
| 1688 | struct i7core_pvt *pvt; |
Mauro Carvalho Chehab | ba6c5c6 | 2009-07-15 09:02:32 -0300 | [diff] [blame] | 1689 | int csrow = 0; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1690 | int rc; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1691 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1692 | /* allocate a new MC control structure */ |
Mauro Carvalho Chehab | d4c2779 | 2009-09-05 04:12:02 -0300 | [diff] [blame] | 1693 | mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, |
| 1694 | i7core_dev->socket); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1695 | if (unlikely(!mci)) |
| 1696 | return -ENOMEM; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1697 | |
| 1698 | debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci); |
| 1699 | |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1700 | /* record ptr to the generic device */ |
| 1701 | mci->dev = &i7core_dev->pdev[0]->dev; |
| 1702 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1703 | pvt = mci->pvt_info; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1704 | memset(pvt, 0, sizeof(*pvt)); |
Mauro Carvalho Chehab | 67166af | 2009-07-15 06:56:23 -0300 | [diff] [blame] | 1705 | |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 1706 | /* |
| 1707 | * FIXME: how to handle RDDR3 at MCI level? It is possible to have |
| 1708 | * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different |
| 1709 | * memory channels |
| 1710 | */ |
| 1711 | mci->mtype_cap = MEM_FLAG_DDR3; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1712 | mci->edac_ctl_cap = EDAC_FLAG_NONE; |
| 1713 | mci->edac_cap = EDAC_FLAG_NONE; |
| 1714 | mci->mod_name = "i7core_edac.c"; |
| 1715 | mci->mod_ver = I7CORE_REVISION; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1716 | mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d", |
| 1717 | i7core_dev->socket); |
| 1718 | mci->dev_name = pci_name(i7core_dev->pdev[0]); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1719 | mci->ctl_page_to_phys = NULL; |
Mauro Carvalho Chehab | a5538e5 | 2009-09-23 18:56:47 -0300 | [diff] [blame^] | 1720 | mci->mc_driver_sysfs_attributes = i7core_sysfs_attrs; |
Mauro Carvalho Chehab | 87d1d27 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1721 | /* Set the function pointer to an actual operation function */ |
| 1722 | mci->edac_check = i7core_check_error; |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1723 | |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1724 | /* Store pci devices at mci for faster access */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1725 | rc = mci_bind_devs(mci, i7core_dev); |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 1726 | if (unlikely(rc < 0)) |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1727 | goto fail; |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1728 | |
| 1729 | /* Get dimm basic config */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1730 | get_dimm_config(mci, &csrow); |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1731 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1732 | /* add this new MC control structure to EDAC's list of MCs */ |
Mauro Carvalho Chehab | b7c7615 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1733 | if (unlikely(edac_mc_add_mc(mci))) { |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1734 | debugf0("MC: " __FILE__ |
| 1735 | ": %s(): failed edac_mc_add_mc()\n", __func__); |
| 1736 | /* FIXME: perhaps some code should go here that disables error |
| 1737 | * reporting if we just enabled it |
| 1738 | */ |
Mauro Carvalho Chehab | b7c7615 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1739 | |
| 1740 | rc = -EINVAL; |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1741 | goto fail; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1742 | } |
| 1743 | |
| 1744 | /* allocating generic PCI control info */ |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1745 | i7core_pci = edac_pci_create_generic_ctl(&i7core_dev->pdev[0]->dev, |
| 1746 | EDAC_MOD_STR); |
Mauro Carvalho Chehab | 41fcb7f | 2009-06-22 22:48:31 -0300 | [diff] [blame] | 1747 | if (unlikely(!i7core_pci)) { |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1748 | printk(KERN_WARNING |
| 1749 | "%s(): Unable to create PCI control\n", |
| 1750 | __func__); |
| 1751 | printk(KERN_WARNING |
| 1752 | "%s(): PCI error report via EDAC not setup\n", |
| 1753 | __func__); |
| 1754 | } |
| 1755 | |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1756 | /* Default error mask is any memory */ |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1757 | pvt->inject.channel = 0; |
Mauro Carvalho Chehab | 194a40f | 2009-06-22 22:48:28 -0300 | [diff] [blame] | 1758 | pvt->inject.dimm = -1; |
| 1759 | pvt->inject.rank = -1; |
| 1760 | pvt->inject.bank = -1; |
| 1761 | pvt->inject.page = -1; |
| 1762 | pvt->inject.col = -1; |
| 1763 | |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1764 | /* Registers on edac_mce in order to receive memory errors */ |
Mauro Carvalho Chehab | c5d3452 | 2009-07-17 10:28:15 -0300 | [diff] [blame] | 1765 | pvt->edac_mce.priv = mci; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1766 | pvt->edac_mce.check_error = i7core_mce_check_error; |
| 1767 | spin_lock_init(&pvt->mce_lock); |
| 1768 | |
| 1769 | rc = edac_mce_register(&pvt->edac_mce); |
Mauro Carvalho Chehab | b990538 | 2009-08-05 21:36:35 -0300 | [diff] [blame] | 1770 | if (unlikely(rc < 0)) { |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1771 | debugf0("MC: " __FILE__ |
| 1772 | ": %s(): failed edac_mce_register()\n", __func__); |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1773 | } |
| 1774 | |
| 1775 | fail: |
| 1776 | edac_mc_free(mci); |
| 1777 | return rc; |
| 1778 | } |
| 1779 | |
| 1780 | /* |
| 1781 | * i7core_probe Probe for ONE instance of device to see if it is |
| 1782 | * present. |
| 1783 | * return: |
| 1784 | * 0 for FOUND a device |
| 1785 | * < 0 for error code |
| 1786 | */ |
| 1787 | static int __devinit i7core_probe(struct pci_dev *pdev, |
| 1788 | const struct pci_device_id *id) |
| 1789 | { |
| 1790 | int dev_idx = id->driver_data; |
| 1791 | int rc; |
| 1792 | struct i7core_dev *i7core_dev; |
| 1793 | |
| 1794 | /* |
Mauro Carvalho Chehab | d4c2779 | 2009-09-05 04:12:02 -0300 | [diff] [blame] | 1795 | * All memory controllers are allocated at the first pass. |
Mauro Carvalho Chehab | f474294 | 2009-09-05 02:35:08 -0300 | [diff] [blame] | 1796 | */ |
| 1797 | if (unlikely(dev_idx >= 1)) |
| 1798 | return -EINVAL; |
| 1799 | |
| 1800 | /* get the pci devices we want to reserve for our use */ |
| 1801 | mutex_lock(&i7core_edac_lock); |
| 1802 | rc = i7core_get_devices(); |
| 1803 | if (unlikely(rc < 0)) |
| 1804 | goto fail0; |
| 1805 | |
| 1806 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) { |
| 1807 | int channels; |
| 1808 | int csrows; |
| 1809 | |
| 1810 | /* Check the number of active and not disabled channels */ |
| 1811 | rc = i7core_get_active_channels(i7core_dev->socket, |
| 1812 | &channels, &csrows); |
| 1813 | if (unlikely(rc < 0)) |
| 1814 | goto fail1; |
| 1815 | |
Mauro Carvalho Chehab | d4c2779 | 2009-09-05 04:12:02 -0300 | [diff] [blame] | 1816 | rc = i7core_register_mci(i7core_dev, channels, csrows); |
| 1817 | if (unlikely(rc < 0)) |
| 1818 | goto fail1; |
Mauro Carvalho Chehab | d538164 | 2009-07-09 22:06:41 -0300 | [diff] [blame] | 1819 | } |
| 1820 | |
Mauro Carvalho Chehab | ef708b5 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1821 | i7core_printk(KERN_INFO, "Driver loaded.\n"); |
Mauro Carvalho Chehab | 8f33190 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1822 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1823 | mutex_unlock(&i7core_edac_lock); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1824 | return 0; |
| 1825 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1826 | fail1: |
Mauro Carvalho Chehab | 13d6e9b | 2009-09-05 12:15:20 -0300 | [diff] [blame] | 1827 | i7core_put_all_devices(); |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1828 | fail0: |
| 1829 | mutex_unlock(&i7core_edac_lock); |
Mauro Carvalho Chehab | b7c7615 | 2009-06-22 22:48:30 -0300 | [diff] [blame] | 1830 | return rc; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1831 | } |
| 1832 | |
| 1833 | /* |
| 1834 | * i7core_remove destructor for one instance of device |
| 1835 | * |
| 1836 | */ |
| 1837 | static void __devexit i7core_remove(struct pci_dev *pdev) |
| 1838 | { |
| 1839 | struct mem_ctl_info *mci; |
Mauro Carvalho Chehab | 22e6bcb | 2009-09-05 23:06:50 -0300 | [diff] [blame] | 1840 | struct i7core_dev *i7core_dev, *tmp; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1841 | |
| 1842 | debugf0(__FILE__ ": %s()\n", __func__); |
| 1843 | |
| 1844 | if (i7core_pci) |
| 1845 | edac_pci_release_generic_ctl(i7core_pci); |
| 1846 | |
Mauro Carvalho Chehab | 22e6bcb | 2009-09-05 23:06:50 -0300 | [diff] [blame] | 1847 | /* |
| 1848 | * we have a trouble here: pdev value for removal will be wrong, since |
| 1849 | * it will point to the X58 register used to detect that the machine |
| 1850 | * is a Nehalem or upper design. However, due to the way several PCI |
| 1851 | * devices are grouped together to provide MC functionality, we need |
| 1852 | * to use a different method for releasing the devices |
| 1853 | */ |
Mauro Carvalho Chehab | 87d1d27 | 2009-06-22 22:48:29 -0300 | [diff] [blame] | 1854 | |
Mauro Carvalho Chehab | 6660770 | 2009-09-05 00:52:11 -0300 | [diff] [blame] | 1855 | mutex_lock(&i7core_edac_lock); |
Mauro Carvalho Chehab | 22e6bcb | 2009-09-05 23:06:50 -0300 | [diff] [blame] | 1856 | list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) { |
| 1857 | mci = edac_mc_del_mc(&i7core_dev->pdev[0]->dev); |
| 1858 | if (mci) { |
| 1859 | struct i7core_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1860 | |
Mauro Carvalho Chehab | 22e6bcb | 2009-09-05 23:06:50 -0300 | [diff] [blame] | 1861 | i7core_dev = pvt->i7core_dev; |
| 1862 | edac_mce_unregister(&pvt->edac_mce); |
| 1863 | kfree(mci->ctl_name); |
| 1864 | edac_mc_free(mci); |
| 1865 | i7core_put_devices(i7core_dev); |
| 1866 | } else { |
| 1867 | i7core_printk(KERN_ERR, |
| 1868 | "Couldn't find mci for socket %d\n", |
| 1869 | i7core_dev->socket); |
| 1870 | } |
| 1871 | } |
| 1872 | mutex_unlock(&i7core_edac_lock); |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1873 | } |
| 1874 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1875 | MODULE_DEVICE_TABLE(pci, i7core_pci_tbl); |
| 1876 | |
| 1877 | /* |
| 1878 | * i7core_driver pci_driver structure for this module |
| 1879 | * |
| 1880 | */ |
| 1881 | static struct pci_driver i7core_driver = { |
| 1882 | .name = "i7core_edac", |
| 1883 | .probe = i7core_probe, |
| 1884 | .remove = __devexit_p(i7core_remove), |
| 1885 | .id_table = i7core_pci_tbl, |
| 1886 | }; |
| 1887 | |
| 1888 | /* |
| 1889 | * i7core_init Module entry function |
| 1890 | * Try to initialize this module for its devices |
| 1891 | */ |
| 1892 | static int __init i7core_init(void) |
| 1893 | { |
| 1894 | int pci_rc; |
| 1895 | |
| 1896 | debugf2("MC: " __FILE__ ": %s()\n", __func__); |
| 1897 | |
| 1898 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
| 1899 | opstate_init(); |
| 1900 | |
Keith Mannthey | bc2d724 | 2009-09-03 00:05:05 -0300 | [diff] [blame] | 1901 | i7core_xeon_pci_fixup(); |
| 1902 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1903 | pci_rc = pci_register_driver(&i7core_driver); |
| 1904 | |
Mauro Carvalho Chehab | 3ef288a | 2009-09-02 23:43:33 -0300 | [diff] [blame] | 1905 | if (pci_rc >= 0) |
| 1906 | return 0; |
| 1907 | |
| 1908 | i7core_printk(KERN_ERR, "Failed to register device with error %d.\n", |
| 1909 | pci_rc); |
| 1910 | |
| 1911 | return pci_rc; |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 1912 | } |
| 1913 | |
| 1914 | /* |
| 1915 | * i7core_exit() Module exit function |
| 1916 | * Unregister the driver |
| 1917 | */ |
| 1918 | static void __exit i7core_exit(void) |
| 1919 | { |
| 1920 | debugf2("MC: " __FILE__ ": %s()\n", __func__); |
| 1921 | pci_unregister_driver(&i7core_driver); |
| 1922 | } |
| 1923 | |
| 1924 | module_init(i7core_init); |
| 1925 | module_exit(i7core_exit); |
| 1926 | |
| 1927 | MODULE_LICENSE("GPL"); |
| 1928 | MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); |
| 1929 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); |
| 1930 | MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - " |
| 1931 | I7CORE_REVISION); |
| 1932 | |
| 1933 | module_param(edac_op_state, int, 0444); |
| 1934 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |