blob: 1aba2c74160eb5c51ce49dd679de2dd0090fe2dd [file] [log] [blame]
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +00001/*
2 * Copyright (C) 2011 Google, Inc.
3 * Copyright (C) 2012 Intel, Inc.
4 * Copyright (C) 2013 Intel, Inc.
Christoffer Dall2f3be882016-01-06 14:05:15 +00005 * Copyright (C) 2014 Linaro Limited
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +00006 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18/* This source file contains the implementation of a special device driver
19 * that intends to provide a *very* fast communication channel between the
20 * guest system and the QEMU emulator.
21 *
22 * Usage from the guest is simply the following (error handling simplified):
23 *
24 * int fd = open("/dev/qemu_pipe",O_RDWR);
25 * .... write() or read() through the pipe.
26 *
27 * This driver doesn't deal with the exact protocol used during the session.
28 * It is intended to be as simple as something like:
29 *
30 * // do this _just_ after opening the fd to connect to a specific
31 * // emulator service.
32 * const char* msg = "<pipename>";
33 * if (write(fd, msg, strlen(msg)+1) < 0) {
34 * ... could not connect to <pipename> service
35 * close(fd);
36 * }
37 *
38 * // after this, simply read() and write() to communicate with the
39 * // service. Exact protocol details left as an exercise to the reader.
40 *
41 * This driver is very fast because it doesn't copy any data through
42 * intermediate buffers, since the emulator is capable of translating
43 * guest user addresses into host ones.
44 *
45 * Note that we must however ensure that each user page involved in the
46 * exchange is properly mapped during a transfer.
47 */
48
49#include <linux/module.h>
50#include <linux/interrupt.h>
51#include <linux/kernel.h>
52#include <linux/spinlock.h>
53#include <linux/miscdevice.h>
54#include <linux/platform_device.h>
55#include <linux/poll.h>
56#include <linux/sched.h>
57#include <linux/bitops.h>
58#include <linux/slab.h>
59#include <linux/io.h>
Alana99698f2014-05-12 16:57:22 +010060#include <linux/goldfish.h>
Shraddha Barke1d427da2016-02-12 16:11:54 +053061#include <linux/dma-mapping.h>
Christoffer Dall2f3be882016-01-06 14:05:15 +000062#include <linux/mm.h>
Jason Hud62f3242016-01-06 14:06:55 +000063#include <linux/acpi.h>
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +000064
65/*
66 * IMPORTANT: The following constants must match the ones used and defined
67 * in external/qemu/hw/goldfish_pipe.c in the Android source tree.
68 */
69
70/* pipe device registers */
71#define PIPE_REG_COMMAND 0x00 /* write: value = command */
72#define PIPE_REG_STATUS 0x04 /* read */
73#define PIPE_REG_CHANNEL 0x08 /* read/write: channel id */
Jun Tian49a75c42014-05-12 16:54:46 +010074#define PIPE_REG_CHANNEL_HIGH 0x30 /* read/write: channel id */
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +000075#define PIPE_REG_SIZE 0x0c /* read/write: buffer size */
76#define PIPE_REG_ADDRESS 0x10 /* write: physical address */
Jun Tian49a75c42014-05-12 16:54:46 +010077#define PIPE_REG_ADDRESS_HIGH 0x34 /* write: physical address */
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +000078#define PIPE_REG_WAKES 0x14 /* read: wake flags */
79#define PIPE_REG_PARAMS_ADDR_LOW 0x18 /* read/write: batch data address */
80#define PIPE_REG_PARAMS_ADDR_HIGH 0x1c /* read/write: batch data address */
81#define PIPE_REG_ACCESS_PARAMS 0x20 /* write: batch access */
Yu Ning4f420712016-01-06 14:06:40 +000082#define PIPE_REG_VERSION 0x24 /* read: device version */
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +000083
84/* list of commands for PIPE_REG_COMMAND */
85#define CMD_OPEN 1 /* open new channel */
86#define CMD_CLOSE 2 /* close channel (from guest) */
87#define CMD_POLL 3 /* poll read/write status */
88
89/* List of bitflags returned in status of CMD_POLL command */
90#define PIPE_POLL_IN (1 << 0)
91#define PIPE_POLL_OUT (1 << 1)
92#define PIPE_POLL_HUP (1 << 2)
93
94/* The following commands are related to write operations */
95#define CMD_WRITE_BUFFER 4 /* send a user buffer to the emulator */
96#define CMD_WAKE_ON_WRITE 5 /* tell the emulator to wake us when writing
97 is possible */
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +000098#define CMD_READ_BUFFER 6 /* receive a user buffer from the emulator */
99#define CMD_WAKE_ON_READ 7 /* tell the emulator to wake us when reading
100 * is possible */
101
102/* Possible status values used to signal errors - see goldfish_pipe_error_convert */
103#define PIPE_ERROR_INVAL -1
104#define PIPE_ERROR_AGAIN -2
105#define PIPE_ERROR_NOMEM -3
106#define PIPE_ERROR_IO -4
107
108/* Bit-flags used to signal events from the emulator */
109#define PIPE_WAKE_CLOSED (1 << 0) /* emulator closed pipe */
110#define PIPE_WAKE_READ (1 << 1) /* pipe can now be read from */
111#define PIPE_WAKE_WRITE (1 << 2) /* pipe can now be written to */
112
113struct access_params {
Jun Tian49a75c42014-05-12 16:54:46 +0100114 unsigned long channel;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000115 u32 size;
Jun Tian49a75c42014-05-12 16:54:46 +0100116 unsigned long address;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000117 u32 cmd;
118 u32 result;
119 /* reserved for future extension */
120 u32 flags;
121};
122
123/* The global driver data. Holds a reference to the i/o page used to
124 * communicate with the emulator, and a wake queue for blocked tasks
125 * waiting to be awoken.
126 */
127struct goldfish_pipe_dev {
128 spinlock_t lock;
129 unsigned char __iomem *base;
130 struct access_params *aps;
131 int irq;
Yu Ning4f420712016-01-06 14:06:40 +0000132 u32 version;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000133};
134
135static struct goldfish_pipe_dev pipe_dev[1];
136
137/* This data type models a given pipe instance */
138struct goldfish_pipe {
139 struct goldfish_pipe_dev *dev;
140 struct mutex lock;
141 unsigned long flags;
142 wait_queue_head_t wake_queue;
143};
144
145
146/* Bit flags for the 'flags' field */
147enum {
148 BIT_CLOSED_ON_HOST = 0, /* pipe closed by host */
149 BIT_WAKE_ON_WRITE = 1, /* want to be woken on writes */
150 BIT_WAKE_ON_READ = 2, /* want to be woken on reads */
151};
152
153
154static u32 goldfish_cmd_status(struct goldfish_pipe *pipe, u32 cmd)
Alana99698f2014-05-12 16:57:22 +0100155{
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000156 unsigned long flags;
157 u32 status;
158 struct goldfish_pipe_dev *dev = pipe->dev;
159
160 spin_lock_irqsave(&dev->lock, flags);
Peter Senna Tschudin07d783f2015-05-19 11:44:46 +0200161 gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL,
162 dev->base + PIPE_REG_CHANNEL_HIGH);
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000163 writel(cmd, dev->base + PIPE_REG_COMMAND);
164 status = readl(dev->base + PIPE_REG_STATUS);
165 spin_unlock_irqrestore(&dev->lock, flags);
166 return status;
167}
168
169static void goldfish_cmd(struct goldfish_pipe *pipe, u32 cmd)
Alana99698f2014-05-12 16:57:22 +0100170{
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000171 unsigned long flags;
172 struct goldfish_pipe_dev *dev = pipe->dev;
173
174 spin_lock_irqsave(&dev->lock, flags);
Peter Senna Tschudin07d783f2015-05-19 11:44:46 +0200175 gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL,
176 dev->base + PIPE_REG_CHANNEL_HIGH);
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000177 writel(cmd, dev->base + PIPE_REG_COMMAND);
178 spin_unlock_irqrestore(&dev->lock, flags);
179}
180
181/* This function converts an error code returned by the emulator through
182 * the PIPE_REG_STATUS i/o register into a valid negative errno value.
183 */
184static int goldfish_pipe_error_convert(int status)
185{
186 switch (status) {
187 case PIPE_ERROR_AGAIN:
188 return -EAGAIN;
189 case PIPE_ERROR_NOMEM:
190 return -ENOMEM;
191 case PIPE_ERROR_IO:
192 return -EIO;
193 default:
194 return -EINVAL;
195 }
196}
197
198/*
199 * Notice: QEMU will return 0 for un-known register access, indicating
200 * param_acess is supported or not
201 */
202static int valid_batchbuffer_addr(struct goldfish_pipe_dev *dev,
203 struct access_params *aps)
204{
205 u32 aph, apl;
206 u64 paddr;
207 aph = readl(dev->base + PIPE_REG_PARAMS_ADDR_HIGH);
208 apl = readl(dev->base + PIPE_REG_PARAMS_ADDR_LOW);
209
210 paddr = ((u64)aph << 32) | apl;
211 if (paddr != (__pa(aps)))
212 return 0;
213 return 1;
214}
215
216/* 0 on success */
217static int setup_access_params_addr(struct platform_device *pdev,
218 struct goldfish_pipe_dev *dev)
219{
Shraddha Barke1d427da2016-02-12 16:11:54 +0530220 dma_addr_t dma_handle;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000221 struct access_params *aps;
222
Shraddha Barke1d427da2016-02-12 16:11:54 +0530223 aps = dmam_alloc_coherent(&pdev->dev, sizeof(struct access_params),
224 &dma_handle, GFP_KERNEL);
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000225 if (!aps)
Shraddha Barke1d427da2016-02-12 16:11:54 +0530226 return -ENOMEM;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000227
Shraddha Barke1d427da2016-02-12 16:11:54 +0530228 writel(upper_32_bits(dma_handle), dev->base + PIPE_REG_PARAMS_ADDR_HIGH);
229 writel(lower_32_bits(dma_handle), dev->base + PIPE_REG_PARAMS_ADDR_LOW);
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000230
231 if (valid_batchbuffer_addr(dev, aps)) {
232 dev->aps = aps;
233 return 0;
234 } else
235 return -1;
236}
237
238/* A value that will not be set by qemu emulator */
239#define INITIAL_BATCH_RESULT (0xdeadbeaf)
240static int access_with_param(struct goldfish_pipe_dev *dev, const int cmd,
241 unsigned long address, unsigned long avail,
242 struct goldfish_pipe *pipe, int *status)
243{
244 struct access_params *aps = dev->aps;
245
246 if (aps == NULL)
247 return -1;
248
249 aps->result = INITIAL_BATCH_RESULT;
250 aps->channel = (unsigned long)pipe;
251 aps->size = avail;
252 aps->address = address;
253 aps->cmd = cmd;
254 writel(cmd, dev->base + PIPE_REG_ACCESS_PARAMS);
255 /*
256 * If the aps->result has not changed, that means
257 * that the batch command failed
258 */
259 if (aps->result == INITIAL_BATCH_RESULT)
260 return -1;
261 *status = aps->result;
262 return 0;
263}
264
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000265static ssize_t goldfish_pipe_read_write(struct file *filp, char __user *buffer,
Christoffer Dall2f3be882016-01-06 14:05:15 +0000266 size_t bufflen, int is_write)
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000267{
268 unsigned long irq_flags;
269 struct goldfish_pipe *pipe = filp->private_data;
270 struct goldfish_pipe_dev *dev = pipe->dev;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000271 unsigned long address, address_end;
Christoffer Dall2f3be882016-01-06 14:05:15 +0000272 int count = 0, ret = -EINVAL;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000273
274 /* If the emulator already closed the pipe, no need to go further */
275 if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags))
276 return -EIO;
277
278 /* Null reads or writes succeeds */
Joe Perches3411d032015-04-10 16:47:35 -0700279 if (unlikely(bufflen == 0))
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000280 return 0;
281
282 /* Check the buffer range for access */
283 if (!access_ok(is_write ? VERIFY_WRITE : VERIFY_READ,
284 buffer, bufflen))
285 return -EFAULT;
286
287 /* Serialize access to the pipe */
288 if (mutex_lock_interruptible(&pipe->lock))
289 return -ERESTARTSYS;
290
291 address = (unsigned long)(void *)buffer;
292 address_end = address + bufflen;
293
294 while (address < address_end) {
Christoffer Dall2f3be882016-01-06 14:05:15 +0000295 unsigned long page_end = (address & PAGE_MASK) + PAGE_SIZE;
296 unsigned long next = page_end < address_end ? page_end
297 : address_end;
298 unsigned long avail = next - address;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000299 int status, wakeBit;
Christoffer Dall2f3be882016-01-06 14:05:15 +0000300 struct page *page;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000301
Yu Ning4f420712016-01-06 14:06:40 +0000302 /* Either vaddr or paddr depending on the device version */
303 unsigned long xaddr;
304
Christoffer Dall2f3be882016-01-06 14:05:15 +0000305 /*
306 * We grab the pages on a page-by-page basis in case user
307 * space gives us a potentially huge buffer but the read only
308 * returns a small amount, then there's no need to pin that
309 * much memory to the process.
310 */
Yu Ning4f420712016-01-06 14:06:40 +0000311 down_read(&current->mm->mmap_sem);
Lorenzo Stoakes768ae302016-10-13 01:20:16 +0100312 ret = get_user_pages(address, 1, is_write ? 0 : FOLL_WRITE,
313 &page, NULL);
Yu Ning4f420712016-01-06 14:06:40 +0000314 up_read(&current->mm->mmap_sem);
Christoffer Dall2f3be882016-01-06 14:05:15 +0000315 if (ret < 0)
Dan Carpenter5fae0542016-02-02 12:48:09 +0300316 break;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000317
Yu Ning4f420712016-01-06 14:06:40 +0000318 if (dev->version) {
319 /* Device version 1 or newer (qemu-android) expects the
320 * physical address.
321 */
322 xaddr = page_to_phys(page) | (address & ~PAGE_MASK);
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000323 } else {
Yu Ning4f420712016-01-06 14:06:40 +0000324 /* Device version 0 (classic emulator) expects the
325 * virtual address.
326 */
327 xaddr = address;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000328 }
329
330 /* Now, try to transfer the bytes in the current page */
331 spin_lock_irqsave(&dev->lock, irq_flags);
Alex Bennée23c5ee22016-01-06 14:04:31 +0000332 if (access_with_param(dev,
333 is_write ? CMD_WRITE_BUFFER : CMD_READ_BUFFER,
Yu Ning4f420712016-01-06 14:06:40 +0000334 xaddr, avail, pipe, &status)) {
Peter Senna Tschudin07d783f2015-05-19 11:44:46 +0200335 gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL,
336 dev->base + PIPE_REG_CHANNEL_HIGH);
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000337 writel(avail, dev->base + PIPE_REG_SIZE);
Yu Ning4f420712016-01-06 14:06:40 +0000338 gf_write_ptr((void *)xaddr,
Peter Senna Tschudin07d783f2015-05-19 11:44:46 +0200339 dev->base + PIPE_REG_ADDRESS,
340 dev->base + PIPE_REG_ADDRESS_HIGH);
Alex Bennée23c5ee22016-01-06 14:04:31 +0000341 writel(is_write ? CMD_WRITE_BUFFER : CMD_READ_BUFFER,
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000342 dev->base + PIPE_REG_COMMAND);
343 status = readl(dev->base + PIPE_REG_STATUS);
344 }
345 spin_unlock_irqrestore(&dev->lock, irq_flags);
346
Christoffer Dall2f3be882016-01-06 14:05:15 +0000347 if (status > 0 && !is_write)
348 set_page_dirty(page);
349 put_page(page);
350
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000351 if (status > 0) { /* Correct transfer */
Christoffer Dall2f3be882016-01-06 14:05:15 +0000352 count += status;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000353 address += status;
354 continue;
Christoffer Dall2f3be882016-01-06 14:05:15 +0000355 } else if (status == 0) { /* EOF */
356 ret = 0;
357 break;
358 } else if (status < 0 && count > 0) {
359 /*
360 * An error occurred and we already transferred
361 * something on one of the previous pages.
362 * Just return what we already copied and log this
363 * err.
364 *
365 * Note: This seems like an incorrect approach but
366 * cannot change it until we check if any user space
367 * ABI relies on this behavior.
368 */
Greg Hackmann25dd0f42016-01-06 14:05:55 +0000369 if (status != PIPE_ERROR_AGAIN)
370 pr_info_ratelimited("goldfish_pipe: backend returned error %d on %s\n",
Christoffer Dall2f3be882016-01-06 14:05:15 +0000371 status, is_write ? "write" : "read");
372 ret = 0;
373 break;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000374 }
375
Christoffer Dall2f3be882016-01-06 14:05:15 +0000376 /*
377 * If the error is not PIPE_ERROR_AGAIN, or if we are not in
378 * non-blocking mode, just return the error code.
379 */
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000380 if (status != PIPE_ERROR_AGAIN ||
381 (filp->f_flags & O_NONBLOCK) != 0) {
382 ret = goldfish_pipe_error_convert(status);
383 break;
384 }
385
Christoffer Dall2f3be882016-01-06 14:05:15 +0000386 /*
387 * The backend blocked the read/write, wait until the backend
388 * tells us it's ready to process more data.
389 */
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000390 wakeBit = is_write ? BIT_WAKE_ON_WRITE : BIT_WAKE_ON_READ;
391 set_bit(wakeBit, &pipe->flags);
392
393 /* Tell the emulator we're going to wait for a wake event */
Alex Bennée23c5ee22016-01-06 14:04:31 +0000394 goldfish_cmd(pipe,
395 is_write ? CMD_WAKE_ON_WRITE : CMD_WAKE_ON_READ);
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000396
397 /* Unlock the pipe, then wait for the wake signal */
398 mutex_unlock(&pipe->lock);
399
400 while (test_bit(wakeBit, &pipe->flags)) {
401 if (wait_event_interruptible(
402 pipe->wake_queue,
403 !test_bit(wakeBit, &pipe->flags)))
404 return -ERESTARTSYS;
405
406 if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags))
407 return -EIO;
408 }
409
410 /* Try to re-acquire the lock */
411 if (mutex_lock_interruptible(&pipe->lock))
412 return -ERESTARTSYS;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000413 }
414 mutex_unlock(&pipe->lock);
Christoffer Dall2f3be882016-01-06 14:05:15 +0000415
416 if (ret < 0)
417 return ret;
418 else
419 return count;
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000420}
421
422static ssize_t goldfish_pipe_read(struct file *filp, char __user *buffer,
423 size_t bufflen, loff_t *ppos)
424{
425 return goldfish_pipe_read_write(filp, buffer, bufflen, 0);
426}
427
428static ssize_t goldfish_pipe_write(struct file *filp,
429 const char __user *buffer, size_t bufflen,
430 loff_t *ppos)
431{
432 return goldfish_pipe_read_write(filp, (char __user *)buffer,
433 bufflen, 1);
434}
435
436
437static unsigned int goldfish_pipe_poll(struct file *filp, poll_table *wait)
438{
439 struct goldfish_pipe *pipe = filp->private_data;
440 unsigned int mask = 0;
441 int status;
442
443 mutex_lock(&pipe->lock);
444
445 poll_wait(filp, &pipe->wake_queue, wait);
446
447 status = goldfish_cmd_status(pipe, CMD_POLL);
448
449 mutex_unlock(&pipe->lock);
450
451 if (status & PIPE_POLL_IN)
452 mask |= POLLIN | POLLRDNORM;
453
454 if (status & PIPE_POLL_OUT)
455 mask |= POLLOUT | POLLWRNORM;
456
457 if (status & PIPE_POLL_HUP)
458 mask |= POLLHUP;
459
460 if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags))
461 mask |= POLLERR;
462
463 return mask;
464}
465
466static irqreturn_t goldfish_pipe_interrupt(int irq, void *dev_id)
467{
468 struct goldfish_pipe_dev *dev = dev_id;
469 unsigned long irq_flags;
470 int count = 0;
471
Christoffer Dall2f3be882016-01-06 14:05:15 +0000472 /*
473 * We're going to read from the emulator a list of (channel,flags)
474 * pairs corresponding to the wake events that occurred on each
475 * blocked pipe (i.e. channel).
476 */
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000477 spin_lock_irqsave(&dev->lock, irq_flags);
478 for (;;) {
479 /* First read the channel, 0 means the end of the list */
480 struct goldfish_pipe *pipe;
481 unsigned long wakes;
Jun Tian49a75c42014-05-12 16:54:46 +0100482 unsigned long channel = 0;
483
484#ifdef CONFIG_64BIT
485 channel = (u64)readl(dev->base + PIPE_REG_CHANNEL_HIGH) << 32;
Jun Tian25c72c72014-05-12 16:54:57 +0100486
487 if (channel == 0)
488 break;
Jun Tian49a75c42014-05-12 16:54:46 +0100489#endif
490 channel |= readl(dev->base + PIPE_REG_CHANNEL);
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000491
492 if (channel == 0)
493 break;
494
495 /* Convert channel to struct pipe pointer + read wake flags */
496 wakes = readl(dev->base + PIPE_REG_WAKES);
497 pipe = (struct goldfish_pipe *)(ptrdiff_t)channel;
498
499 /* Did the emulator just closed a pipe? */
500 if (wakes & PIPE_WAKE_CLOSED) {
501 set_bit(BIT_CLOSED_ON_HOST, &pipe->flags);
502 wakes |= PIPE_WAKE_READ | PIPE_WAKE_WRITE;
503 }
504 if (wakes & PIPE_WAKE_READ)
505 clear_bit(BIT_WAKE_ON_READ, &pipe->flags);
506 if (wakes & PIPE_WAKE_WRITE)
507 clear_bit(BIT_WAKE_ON_WRITE, &pipe->flags);
508
509 wake_up_interruptible(&pipe->wake_queue);
510 count++;
511 }
512 spin_unlock_irqrestore(&dev->lock, irq_flags);
513
514 return (count == 0) ? IRQ_NONE : IRQ_HANDLED;
515}
516
517/**
518 * goldfish_pipe_open - open a channel to the AVD
519 * @inode: inode of device
520 * @file: file struct of opener
521 *
522 * Create a new pipe link between the emulator and the use application.
523 * Each new request produces a new pipe.
524 *
525 * Note: we use the pipe ID as a mux. All goldfish emulations are 32bit
526 * right now so this is fine. A move to 64bit will need this addressing
527 */
528static int goldfish_pipe_open(struct inode *inode, struct file *file)
529{
530 struct goldfish_pipe *pipe;
531 struct goldfish_pipe_dev *dev = pipe_dev;
532 int32_t status;
533
534 /* Allocate new pipe kernel object */
535 pipe = kzalloc(sizeof(*pipe), GFP_KERNEL);
536 if (pipe == NULL)
537 return -ENOMEM;
538
539 pipe->dev = dev;
540 mutex_init(&pipe->lock);
541 init_waitqueue_head(&pipe->wake_queue);
542
543 /*
544 * Now, tell the emulator we're opening a new pipe. We use the
545 * pipe object's address as the channel identifier for simplicity.
546 */
547
548 status = goldfish_cmd_status(pipe, CMD_OPEN);
549 if (status < 0) {
550 kfree(pipe);
551 return status;
552 }
553
554 /* All is done, save the pipe into the file's private data field */
555 file->private_data = pipe;
556 return 0;
557}
558
559static int goldfish_pipe_release(struct inode *inode, struct file *filp)
560{
561 struct goldfish_pipe *pipe = filp->private_data;
562
563 /* The guest is closing the channel, so tell the emulator right now */
564 goldfish_cmd(pipe, CMD_CLOSE);
565 kfree(pipe);
566 filp->private_data = NULL;
567 return 0;
568}
569
570static const struct file_operations goldfish_pipe_fops = {
571 .owner = THIS_MODULE,
572 .read = goldfish_pipe_read,
573 .write = goldfish_pipe_write,
574 .poll = goldfish_pipe_poll,
575 .open = goldfish_pipe_open,
576 .release = goldfish_pipe_release,
577};
578
579static struct miscdevice goldfish_pipe_device = {
580 .minor = MISC_DYNAMIC_MINOR,
581 .name = "goldfish_pipe",
582 .fops = &goldfish_pipe_fops,
583};
584
585static int goldfish_pipe_probe(struct platform_device *pdev)
586{
587 int err;
588 struct resource *r;
589 struct goldfish_pipe_dev *dev = pipe_dev;
590
591 /* not thread safe, but this should not happen */
592 WARN_ON(dev->base != NULL);
593
594 spin_lock_init(&dev->lock);
595
596 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
597 if (r == NULL || resource_size(r) < PAGE_SIZE) {
598 dev_err(&pdev->dev, "can't allocate i/o page\n");
599 return -EINVAL;
600 }
601 dev->base = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
602 if (dev->base == NULL) {
603 dev_err(&pdev->dev, "ioremap failed\n");
604 return -EINVAL;
605 }
606
607 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
608 if (r == NULL) {
609 err = -EINVAL;
610 goto error;
611 }
612 dev->irq = r->start;
613
614 err = devm_request_irq(&pdev->dev, dev->irq, goldfish_pipe_interrupt,
615 IRQF_SHARED, "goldfish_pipe", dev);
616 if (err) {
617 dev_err(&pdev->dev, "unable to allocate IRQ\n");
618 goto error;
619 }
620
621 err = misc_register(&goldfish_pipe_device);
622 if (err) {
623 dev_err(&pdev->dev, "unable to register device\n");
624 goto error;
625 }
626 setup_access_params_addr(pdev, dev);
Yu Ning4f420712016-01-06 14:06:40 +0000627
628 /* Although the pipe device in the classic Android emulator does not
629 * recognize the 'version' register, it won't treat this as an error
630 * either and will simply return 0, which is fine.
631 */
632 dev->version = readl(dev->base + PIPE_REG_VERSION);
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000633 return 0;
634
635error:
636 dev->base = NULL;
637 return err;
638}
639
640static int goldfish_pipe_remove(struct platform_device *pdev)
641{
642 struct goldfish_pipe_dev *dev = pipe_dev;
643 misc_deregister(&goldfish_pipe_device);
644 dev->base = NULL;
645 return 0;
646}
647
Jason Hud62f3242016-01-06 14:06:55 +0000648static const struct acpi_device_id goldfish_pipe_acpi_match[] = {
649 { "GFSH0003", 0 },
650 { },
651};
652MODULE_DEVICE_TABLE(acpi, goldfish_pipe_acpi_match);
653
Greg Hackmann91a18a42016-01-06 14:05:36 +0000654static const struct of_device_id goldfish_pipe_of_match[] = {
655 { .compatible = "google,android-pipe", },
656 {},
657};
658MODULE_DEVICE_TABLE(of, goldfish_pipe_of_match);
659
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000660static struct platform_driver goldfish_pipe = {
661 .probe = goldfish_pipe_probe,
662 .remove = goldfish_pipe_remove,
663 .driver = {
Greg Hackmann91a18a42016-01-06 14:05:36 +0000664 .name = "goldfish_pipe",
665 .owner = THIS_MODULE,
666 .of_match_table = goldfish_pipe_of_match,
Jason Hud62f3242016-01-06 14:06:55 +0000667 .acpi_match_table = ACPI_PTR(goldfish_pipe_acpi_match),
David 'Digit' Turnerc89f2752013-01-21 23:48:21 +0000668 }
669};
670
671module_platform_driver(goldfish_pipe);
672MODULE_AUTHOR("David Turner <digit@google.com>");
673MODULE_LICENSE("GPL");