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Russell Kinga09e64f2008-08-05 16:14:15 +01001/*
2 * arch/arm/mach-at91/include/mach/debug-macro.S
3 *
4 * Copyright (C) 2003-2005 SAN People
5 *
6 * Debugging macro include header
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <mach/hardware.h>
15#include <mach/at91_dbgu.h>
16
Jeremy Kerr0ea12932010-07-06 18:30:06 +080017 .macro addruart, rp, rv
Jean-Christophe PLAGNIOL-VILLARD1ff5b1b2011-05-03 01:11:25 +080018 ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address)
19 ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address)
Russell Kinga09e64f2008-08-05 16:14:15 +010020 .endm
21
22 .macro senduart,rd,rx
Jean-Christophe PLAGNIOL-VILLARD1ff5b1b2011-05-03 01:11:25 +080023 strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
Russell Kinga09e64f2008-08-05 16:14:15 +010024 .endm
25
26 .macro waituart,rd,rx
Jean-Christophe PLAGNIOL-VILLARD1ff5b1b2011-05-03 01:11:25 +0800271001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
28 tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
Russell Kinga09e64f2008-08-05 16:14:15 +010029 beq 1001b
30 .endm
31
32 .macro busyuart,rd,rx
Jean-Christophe PLAGNIOL-VILLARD1ff5b1b2011-05-03 01:11:25 +0800331001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
34 tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
Russell Kinga09e64f2008-08-05 16:14:15 +010035 beq 1001b
36 .endm
37