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gerrit-public.fairphone.software / kernel / msm-4.9 / a6d1be0e5825246da6df42cdaa21f3ce66698ff2 / . / arch / arm / boot / dts / phy3250.dts
blob: 1dbfea8b7bdfb9ac6628e1b14ff8a7b8629a7780 [file] [log] [blame]
Roland Stiggee04920d2012-04-22 12:01:19 +0200[diff] [blame]1/*
2 * PHYTEC phyCORE-LPC3250 board
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "lpc32xx.dtsi"
16
17/ {
18 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
19 compatible = "phytec,phy3250", "nxp,lpc3250";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 device_type = "memory";
25 reg = <0 0x4000000>;
26 };
27
28 ahb {
29 mac: ethernet@31060000 {
30 phy-mode = "rmii";
31 use-iram;
32 };
33
34 /* Here, choose exactly one from: ohci, usbd */
35 ohci@31020000 {
36 transceiver = <&isp1301>;
37 status = "okay";
38 };
39
40/*
41 usbd@31020000 {
42 transceiver = <&isp1301>;
43 status = "okay";
44 };
45*/
46
47 clcd@31040000 {
48 status = "okay";
49 };
50
51 /* 64MB Flash via SLC NAND controller */
52 slc: flash@20020000 {
53 status = "okay";
54 #address-cells = <1>;
55 #size-cells = <1>;
56
Roland Stigge15ab2182012-06-14 16:16:16 +0200[diff] [blame]57 nxp,wdr-clks = <14>;
58 nxp,wwidth = <40000000>;
59 nxp,whold = <100000000>;
60 nxp,wsetup = <100000000>;
61 nxp,rdr-clks = <14>;
62 nxp,rwidth = <40000000>;
63 nxp,rhold = <66666666>;
64 nxp,rsetup = <100000000>;
65 nand-on-flash-bbt;
66 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
67
Roland Stiggee04920d2012-04-22 12:01:19 +0200[diff] [blame]68 mtd0@00000000 {
69 label = "phy3250-boot";
70 reg = <0x00000000 0x00064000>;
71 read-only;
72 };
73
74 mtd1@00064000 {
75 label = "phy3250-uboot";
76 reg = <0x00064000 0x00190000>;
77 read-only;
78 };
79
80 mtd2@001f4000 {
81 label = "phy3250-ubt-prms";
82 reg = <0x001f4000 0x00010000>;
83 };
84
85 mtd3@00204000 {
86 label = "phy3250-kernel";
87 reg = <0x00204000 0x00400000>;
88 };
89
90 mtd4@00604000 {
91 label = "phy3250-rootfs";
92 reg = <0x00604000 0x039fc000>;
93 };
94 };
95
96 apb {
97 i2c1: i2c@400A0000 {
98 clock-frequency = <100000>;
99
100 pcf8563: rtc@51 {
101 compatible = "nxp,pcf8563";
102 reg = <0x51>;
103 };
104
105 uda1380: uda1380@18 {
106 compatible = "nxp,uda1380";
107 reg = <0x18>;
108 power-gpio = <&gpio 0x59 0>;
109 reset-gpio = <&gpio 0x51 0>;
110 dac-clk = "wspll";
111 };
112 };
113
114 i2c2: i2c@400A8000 {
115 clock-frequency = <100000>;
116 };
117
118 i2cusb: i2c@31020300 {
119 clock-frequency = <100000>;
120
121 isp1301: usb-transceiver@2c {
122 compatible = "nxp,isp1301";
123 reg = <0x2c>;
124 };
125 };
126
127 ssp0: ssp@20084000 {
128 eeprom: at25@0 {
129 compatible = "atmel,at25";
130 };
131 };
132 };
133
134 fab {
135 tsc@40048000 {
136 status = "okay";
137 };
Roland Stiggea6d1be02012-06-14 16:16:17 +0200[diff] [blame^]138
139 key@40050000 {
140 status = "okay";
141 keypad,num-rows = <1>;
142 keypad,num-columns = <1>;
143 nxp,debounce-delay-ms = <3>;
144 nxp,scan-delay-ms = <34>;
145 linux,keymap = <0x00000002>;
146 };
Roland Stiggee04920d2012-04-22 12:01:19 +0200[diff] [blame]147 };
148 };
149
150 leds {
151 compatible = "gpio-leds";
152
153 led0 {
Roland Stiggea0352542012-05-19 12:28:53 +0200[diff] [blame]154 gpios = <&gpio 5 1 1>; /* GPO_P3 1, GPIO 80, active low */
Roland Stiggee04920d2012-04-22 12:01:19 +0200[diff] [blame]155 linux,default-trigger = "heartbeat";
156 default-state = "off";
157 };
158
159 led1 {
Roland Stiggea0352542012-05-19 12:28:53 +0200[diff] [blame]160 gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
Roland Stiggee04920d2012-04-22 12:01:19 +0200[diff] [blame]161 linux,default-trigger = "timer";
162 default-state = "off";
163 };
164 };
165};