Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / a6e2f029ae34f41adb6ae3812c32c5d326e1abd2 / . / arch / mips / include / asm / asmmacro.h
blob: 76317a70200d18048404438bd85b69fb8bf8ec3e [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Ralf Baechle
7 */
8#ifndef _ASM_ASMMACRO_H
9#define _ASM_ASMMACRO_H
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700[diff] [blame]10
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]11#include <asm/hazards.h>
Jim Quinlan71ca7582013-11-27 15:34:50 -0500[diff] [blame]12#include <asm/asm-offsets.h>
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]13#include <asm/msa.h>
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700[diff] [blame]14
Ralf Baechle875d43e2005-09-03 15:56:16 -0700[diff] [blame]15#ifdef CONFIG_32BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]16#include <asm/asmmacro-32.h>
17#endif
Ralf Baechle875d43e2005-09-03 15:56:16 -0700[diff] [blame]18#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]19#include <asm/asmmacro-64.h>
20#endif
21
Leonid Yegoshin226da552014-11-05 12:56:40 +0000[diff] [blame]22#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
David Daneyb6354db2008-12-10 08:37:25 -0800[diff] [blame]23 .macro local_irq_enable reg=t0
24 ei
25 irq_enable_hazard
26 .endm
27
28 .macro local_irq_disable reg=t0
29 di
30 irq_disable_hazard
31 .endm
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]32#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]33 .macro local_irq_enable reg=t0
34 mfc0 \reg, CP0_STATUS
35 ori \reg, \reg, 1
36 mtc0 \reg, CP0_STATUS
37 irq_enable_hazard
38 .endm
39
40 .macro local_irq_disable reg=t0
Jim Quinlan71ca7582013-11-27 15:34:50 -0500[diff] [blame]41#ifdef CONFIG_PREEMPT
42 lw \reg, TI_PRE_COUNT($28)
43 addi \reg, \reg, 1
44 sw \reg, TI_PRE_COUNT($28)
45#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]46 mfc0 \reg, CP0_STATUS
47 ori \reg, \reg, 1
48 xori \reg, \reg, 1
49 mtc0 \reg, CP0_STATUS
50 irq_disable_hazard
Jim Quinlan71ca7582013-11-27 15:34:50 -0500[diff] [blame]51#ifdef CONFIG_PREEMPT
52 lw \reg, TI_PRE_COUNT($28)
53 addi \reg, \reg, -1
54 sw \reg, TI_PRE_COUNT($28)
55#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]56 .endm
Ralf Baechleb633648c52014-05-23 16:29:44 +0200[diff] [blame]57#endif /* CONFIG_CPU_MIPSR2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]58
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]59 .macro fpu_save_16even thread tmp=t0
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]60 .set push
61 SET_HARDFLOAT
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]62 cfc1 \tmp, fcr31
James Hogan466aec52015-01-30 12:09:38 +0000[diff] [blame]63 sdc1 $f0, THREAD_FPR0(\thread)
64 sdc1 $f2, THREAD_FPR2(\thread)
65 sdc1 $f4, THREAD_FPR4(\thread)
66 sdc1 $f6, THREAD_FPR6(\thread)
67 sdc1 $f8, THREAD_FPR8(\thread)
68 sdc1 $f10, THREAD_FPR10(\thread)
69 sdc1 $f12, THREAD_FPR12(\thread)
70 sdc1 $f14, THREAD_FPR14(\thread)
71 sdc1 $f16, THREAD_FPR16(\thread)
72 sdc1 $f18, THREAD_FPR18(\thread)
73 sdc1 $f20, THREAD_FPR20(\thread)
74 sdc1 $f22, THREAD_FPR22(\thread)
75 sdc1 $f24, THREAD_FPR24(\thread)
76 sdc1 $f26, THREAD_FPR26(\thread)
77 sdc1 $f28, THREAD_FPR28(\thread)
78 sdc1 $f30, THREAD_FPR30(\thread)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]79 sw \tmp, THREAD_FCR31(\thread)
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]80 .set pop
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]81 .endm
82
83 .macro fpu_save_16odd thread
84 .set push
85 .set mips64r2
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]86 SET_HARDFLOAT
James Hogan466aec52015-01-30 12:09:38 +0000[diff] [blame]87 sdc1 $f1, THREAD_FPR1(\thread)
88 sdc1 $f3, THREAD_FPR3(\thread)
89 sdc1 $f5, THREAD_FPR5(\thread)
90 sdc1 $f7, THREAD_FPR7(\thread)
91 sdc1 $f9, THREAD_FPR9(\thread)
92 sdc1 $f11, THREAD_FPR11(\thread)
93 sdc1 $f13, THREAD_FPR13(\thread)
94 sdc1 $f15, THREAD_FPR15(\thread)
95 sdc1 $f17, THREAD_FPR17(\thread)
96 sdc1 $f19, THREAD_FPR19(\thread)
97 sdc1 $f21, THREAD_FPR21(\thread)
98 sdc1 $f23, THREAD_FPR23(\thread)
99 sdc1 $f25, THREAD_FPR25(\thread)
100 sdc1 $f27, THREAD_FPR27(\thread)
101 sdc1 $f29, THREAD_FPR29(\thread)
102 sdc1 $f31, THREAD_FPR31(\thread)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]103 .set pop
104 .endm
105
106 .macro fpu_save_double thread status tmp
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]107#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
108 defined(CONFIG_CPU_MIPS32_R6)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]109 sll \tmp, \status, 5
110 bgez \tmp, 10f
111 fpu_save_16odd \thread
11210:
113#endif
114 fpu_save_16even \thread \tmp
115 .endm
116
117 .macro fpu_restore_16even thread tmp=t0
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]118 .set push
119 SET_HARDFLOAT
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]120 lw \tmp, THREAD_FCR31(\thread)
James Hogan466aec52015-01-30 12:09:38 +0000[diff] [blame]121 ldc1 $f0, THREAD_FPR0(\thread)
122 ldc1 $f2, THREAD_FPR2(\thread)
123 ldc1 $f4, THREAD_FPR4(\thread)
124 ldc1 $f6, THREAD_FPR6(\thread)
125 ldc1 $f8, THREAD_FPR8(\thread)
126 ldc1 $f10, THREAD_FPR10(\thread)
127 ldc1 $f12, THREAD_FPR12(\thread)
128 ldc1 $f14, THREAD_FPR14(\thread)
129 ldc1 $f16, THREAD_FPR16(\thread)
130 ldc1 $f18, THREAD_FPR18(\thread)
131 ldc1 $f20, THREAD_FPR20(\thread)
132 ldc1 $f22, THREAD_FPR22(\thread)
133 ldc1 $f24, THREAD_FPR24(\thread)
134 ldc1 $f26, THREAD_FPR26(\thread)
135 ldc1 $f28, THREAD_FPR28(\thread)
136 ldc1 $f30, THREAD_FPR30(\thread)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]137 ctc1 \tmp, fcr31
138 .endm
139
140 .macro fpu_restore_16odd thread
141 .set push
142 .set mips64r2
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]143 SET_HARDFLOAT
James Hogan466aec52015-01-30 12:09:38 +0000[diff] [blame]144 ldc1 $f1, THREAD_FPR1(\thread)
145 ldc1 $f3, THREAD_FPR3(\thread)
146 ldc1 $f5, THREAD_FPR5(\thread)
147 ldc1 $f7, THREAD_FPR7(\thread)
148 ldc1 $f9, THREAD_FPR9(\thread)
149 ldc1 $f11, THREAD_FPR11(\thread)
150 ldc1 $f13, THREAD_FPR13(\thread)
151 ldc1 $f15, THREAD_FPR15(\thread)
152 ldc1 $f17, THREAD_FPR17(\thread)
153 ldc1 $f19, THREAD_FPR19(\thread)
154 ldc1 $f21, THREAD_FPR21(\thread)
155 ldc1 $f23, THREAD_FPR23(\thread)
156 ldc1 $f25, THREAD_FPR25(\thread)
157 ldc1 $f27, THREAD_FPR27(\thread)
158 ldc1 $f29, THREAD_FPR29(\thread)
159 ldc1 $f31, THREAD_FPR31(\thread)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]160 .set pop
161 .endm
162
163 .macro fpu_restore_double thread status tmp
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]164#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
165 defined(CONFIG_CPU_MIPS32_R6)
Paul Burton597ce172013-11-22 13:12:07 +0000[diff] [blame]166 sll \tmp, \status, 5
167 bgez \tmp, 10f # 16 register mode?
168
169 fpu_restore_16odd \thread
17010:
171#endif
172 fpu_restore_16even \thread \tmp
173 .endm
174
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]175#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
Paul Burton1d688082014-01-15 10:31:49 +0000[diff] [blame]176 .macro _EXT rd, rs, p, s
177 ext \rd, \rs, \p, \s
178 .endm
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]179#else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
Paul Burton1d688082014-01-15 10:31:49 +0000[diff] [blame]180 .macro _EXT rd, rs, p, s
181 srl \rd, \rs, \p
182 andi \rd, \rd, (1 << \s) - 1
183 .endm
Leonid Yegoshin207083b2014-11-24 11:54:19 +0000[diff] [blame]184#endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
Paul Burton1d688082014-01-15 10:31:49 +0000[diff] [blame]185
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]186/*
187 * Temporary until all gas have MT ASE support
188 */
189 .macro DMT reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]190 .word 0x41600bc1 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]191 .endm
192
193 .macro EMT reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]194 .word 0x41600be1 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]195 .endm
196
197 .macro DVPE reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]198 .word 0x41600001 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]199 .endm
200
201 .macro EVPE reg=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]202 .word 0x41600021 | (\reg << 16)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]203 .endm
204
205 .macro MFTR rt=0, rd=0, u=0, sel=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]206 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]207 .endm
208
209 .macro MTTR rt=0, rd=0, u=0, sel=0
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100[diff] [blame]210 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
Ralf Baechle41c594a2006-04-05 09:45:45 +0100[diff] [blame]211 .endm
212
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]213#ifdef TOOLCHAIN_SUPPORTS_MSA
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]214/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
215#undef fp
216
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]217 .macro _cfcmsa rd, cs
218 .set push
219 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]220 .set fp=64
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]221 .set msa
222 cfcmsa \rd, $\cs
223 .set pop
224 .endm
225
226 .macro _ctcmsa cd, rs
227 .set push
228 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]229 .set fp=64
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]230 .set msa
231 ctcmsa $\cd, \rs
232 .set pop
233 .endm
234
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]235 .macro ld_d wd, off, base
236 .set push
237 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]238 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]239 .set msa
240 ld.d $w\wd, \off(\base)
241 .set pop
242 .endm
243
244 .macro st_d wd, off, base
245 .set push
246 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]247 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]248 .set msa
249 st.d $w\wd, \off(\base)
250 .set pop
251 .endm
252
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]253 .macro copy_u_w ws, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]254 .set push
255 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]256 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]257 .set msa
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]258 copy_u.w $1, $w\ws[\n]
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]259 .set pop
260 .endm
261
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]262 .macro copy_u_d ws, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]263 .set push
264 .set mips64r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]265 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]266 .set msa
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]267 copy_u.d $1, $w\ws[\n]
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]268 .set pop
269 .endm
270
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]271 .macro insert_w wd, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]272 .set push
273 .set mips32r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]274 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]275 .set msa
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]276 insert.w $w\wd[\n], $1
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]277 .set pop
278 .endm
279
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]280 .macro insert_d wd, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]281 .set push
282 .set mips64r2
Markos Chandras2bd7bc22015-04-16 11:05:59 +0100[diff] [blame]283 .set fp=64
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]284 .set msa
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]285 insert.d $w\wd[\n], $1
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]286 .set pop
287 .endm
288#else
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]289
290#ifdef CONFIG_CPU_MICROMIPS
291#define CFC_MSA_INSN 0x587e0056
292#define CTC_MSA_INSN 0x583e0816
293#define LDD_MSA_INSN 0x58000837
294#define STD_MSA_INSN 0x5800083f
295#define COPY_UW_MSA_INSN 0x58f00056
296#define COPY_UD_MSA_INSN 0x58f80056
297#define INSERT_W_MSA_INSN 0x59300816
298#define INSERT_D_MSA_INSN 0x59380816
299#else
300#define CFC_MSA_INSN 0x787e0059
301#define CTC_MSA_INSN 0x783e0819
302#define LDD_MSA_INSN 0x78000823
303#define STD_MSA_INSN 0x78000827
304#define COPY_UW_MSA_INSN 0x78f00059
305#define COPY_UD_MSA_INSN 0x78f80059
306#define INSERT_W_MSA_INSN 0x79300819
307#define INSERT_D_MSA_INSN 0x79380819
308#endif
309
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]310 /*
311 * Temporary until all toolchains in use include MSA support.
312 */
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]313 .macro _cfcmsa rd, cs
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]314 .set push
315 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]316 SET_HARDFLOAT
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]317 .insn
318 .word CFC_MSA_INSN | (\cs << 11)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]319 move \rd, $1
320 .set pop
321 .endm
322
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]323 .macro _ctcmsa cd, rs
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]324 .set push
325 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]326 SET_HARDFLOAT
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]327 move $1, \rs
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]328 .word CTC_MSA_INSN | (\cd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]329 .set pop
330 .endm
331
332 .macro ld_d wd, off, base
333 .set push
334 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]335 SET_HARDFLOAT
Markos Chandras98a833c12014-11-05 14:17:52 +0000[diff] [blame]336 addu $1, \base, \off
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]337 .word LDD_MSA_INSN | (\wd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]338 .set pop
339 .endm
340
341 .macro st_d wd, off, base
342 .set push
343 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]344 SET_HARDFLOAT
Markos Chandras98a833c12014-11-05 14:17:52 +0000[diff] [blame]345 addu $1, \base, \off
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]346 .word STD_MSA_INSN | (\wd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]347 .set pop
348 .endm
349
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]350 .macro copy_u_w ws, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]351 .set push
352 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]353 SET_HARDFLOAT
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]354 .insn
355 .word COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]356 .set pop
357 .endm
358
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]359 .macro copy_u_d ws, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]360 .set push
361 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]362 SET_HARDFLOAT
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]363 .insn
364 .word COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]365 .set pop
366 .endm
367
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]368 .macro insert_w wd, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]369 .set push
370 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]371 SET_HARDFLOAT
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]372 .word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]373 .set pop
374 .endm
375
Paul Burtonf23ce382015-01-30 12:09:31 +0000[diff] [blame]376 .macro insert_d wd, n
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]377 .set push
378 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]379 SET_HARDFLOAT
Steven J. Hilld96cc3d2014-04-15 16:06:49 -0500[diff] [blame]380 .word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
Paul Burton7f65afb2014-01-27 15:23:09 +0000[diff] [blame]381 .set pop
382 .endm
383#endif
384
Paul Burton1db1af82014-01-27 15:23:11 +0000[diff] [blame]385 .macro msa_save_all thread
386 st_d 0, THREAD_FPR0, \thread
387 st_d 1, THREAD_FPR1, \thread
388 st_d 2, THREAD_FPR2, \thread
389 st_d 3, THREAD_FPR3, \thread
390 st_d 4, THREAD_FPR4, \thread
391 st_d 5, THREAD_FPR5, \thread
392 st_d 6, THREAD_FPR6, \thread
393 st_d 7, THREAD_FPR7, \thread
394 st_d 8, THREAD_FPR8, \thread
395 st_d 9, THREAD_FPR9, \thread
396 st_d 10, THREAD_FPR10, \thread
397 st_d 11, THREAD_FPR11, \thread
398 st_d 12, THREAD_FPR12, \thread
399 st_d 13, THREAD_FPR13, \thread
400 st_d 14, THREAD_FPR14, \thread
401 st_d 15, THREAD_FPR15, \thread
402 st_d 16, THREAD_FPR16, \thread
403 st_d 17, THREAD_FPR17, \thread
404 st_d 18, THREAD_FPR18, \thread
405 st_d 19, THREAD_FPR19, \thread
406 st_d 20, THREAD_FPR20, \thread
407 st_d 21, THREAD_FPR21, \thread
408 st_d 22, THREAD_FPR22, \thread
409 st_d 23, THREAD_FPR23, \thread
410 st_d 24, THREAD_FPR24, \thread
411 st_d 25, THREAD_FPR25, \thread
412 st_d 26, THREAD_FPR26, \thread
413 st_d 27, THREAD_FPR27, \thread
414 st_d 28, THREAD_FPR28, \thread
415 st_d 29, THREAD_FPR29, \thread
416 st_d 30, THREAD_FPR30, \thread
417 st_d 31, THREAD_FPR31, \thread
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]418 .set push
419 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]420 SET_HARDFLOAT
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]421 _cfcmsa $1, MSA_CSR
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]422 sw $1, THREAD_MSA_CSR(\thread)
423 .set pop
Paul Burton1db1af82014-01-27 15:23:11 +0000[diff] [blame]424 .endm
425
426 .macro msa_restore_all thread
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]427 .set push
428 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]429 SET_HARDFLOAT
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]430 lw $1, THREAD_MSA_CSR(\thread)
Paul Burtone1bebba2015-01-30 12:09:33 +0000[diff] [blame]431 _ctcmsa MSA_CSR, $1
Paul Burtonf7a46fa2014-07-11 16:44:28 +0100[diff] [blame]432 .set pop
Paul Burton1db1af82014-01-27 15:23:11 +0000[diff] [blame]433 ld_d 0, THREAD_FPR0, \thread
434 ld_d 1, THREAD_FPR1, \thread
435 ld_d 2, THREAD_FPR2, \thread
436 ld_d 3, THREAD_FPR3, \thread
437 ld_d 4, THREAD_FPR4, \thread
438 ld_d 5, THREAD_FPR5, \thread
439 ld_d 6, THREAD_FPR6, \thread
440 ld_d 7, THREAD_FPR7, \thread
441 ld_d 8, THREAD_FPR8, \thread
442 ld_d 9, THREAD_FPR9, \thread
443 ld_d 10, THREAD_FPR10, \thread
444 ld_d 11, THREAD_FPR11, \thread
445 ld_d 12, THREAD_FPR12, \thread
446 ld_d 13, THREAD_FPR13, \thread
447 ld_d 14, THREAD_FPR14, \thread
448 ld_d 15, THREAD_FPR15, \thread
449 ld_d 16, THREAD_FPR16, \thread
450 ld_d 17, THREAD_FPR17, \thread
451 ld_d 18, THREAD_FPR18, \thread
452 ld_d 19, THREAD_FPR19, \thread
453 ld_d 20, THREAD_FPR20, \thread
454 ld_d 21, THREAD_FPR21, \thread
455 ld_d 22, THREAD_FPR22, \thread
456 ld_d 23, THREAD_FPR23, \thread
457 ld_d 24, THREAD_FPR24, \thread
458 ld_d 25, THREAD_FPR25, \thread
459 ld_d 26, THREAD_FPR26, \thread
460 ld_d 27, THREAD_FPR27, \thread
461 ld_d 28, THREAD_FPR28, \thread
462 ld_d 29, THREAD_FPR29, \thread
463 ld_d 30, THREAD_FPR30, \thread
464 ld_d 31, THREAD_FPR31, \thread
465 .endm
466
Paul Burtonc9017752014-07-30 08:53:20 +0100[diff] [blame]467 .macro msa_init_upper wd
468#ifdef CONFIG_64BIT
469 insert_d \wd, 1
470#else
471 insert_w \wd, 2
472 insert_w \wd, 3
473#endif
Paul Burtonc9017752014-07-30 08:53:20 +0100[diff] [blame]474 .endm
475
476 .macro msa_init_all_upper
477 .set push
478 .set noat
Manuel Lauss842dfc12014-11-07 14:13:54 +0100[diff] [blame]479 SET_HARDFLOAT
Paul Burtonc9017752014-07-30 08:53:20 +0100[diff] [blame]480 not $1, zero
481 msa_init_upper 0
Paul Burtona3a498102015-01-30 12:09:32 +0000[diff] [blame]482 msa_init_upper 1
483 msa_init_upper 2
484 msa_init_upper 3
485 msa_init_upper 4
486 msa_init_upper 5
487 msa_init_upper 6
488 msa_init_upper 7
489 msa_init_upper 8
490 msa_init_upper 9
491 msa_init_upper 10
492 msa_init_upper 11
493 msa_init_upper 12
494 msa_init_upper 13
495 msa_init_upper 14
496 msa_init_upper 15
497 msa_init_upper 16
498 msa_init_upper 17
499 msa_init_upper 18
500 msa_init_upper 19
501 msa_init_upper 20
502 msa_init_upper 21
503 msa_init_upper 22
504 msa_init_upper 23
505 msa_init_upper 24
506 msa_init_upper 25
507 msa_init_upper 26
508 msa_init_upper 27
509 msa_init_upper 28
510 msa_init_upper 29
511 msa_init_upper 30
512 msa_init_upper 31
Paul Burtonc9017752014-07-30 08:53:20 +0100[diff] [blame]513 .set pop
514 .endm
515
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]516#endif /* _ASM_ASMMACRO_H */