Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 1 | /* sound/soc/rockchip/rockchip_i2s.c |
| 2 | * |
| 3 | * ALSA SoC Audio Layer - Rockchip I2S Controller driver |
| 4 | * |
| 5 | * Copyright (c) 2014 Rockchip Electronics Co. Ltd. |
| 6 | * Author: Jianqun <jay.xu@rock-chips.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
xujianqun | 1b21572 | 2014-07-11 19:40:05 +0800 | [diff] [blame] | 13 | #include <linux/module.h> |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 14 | #include <linux/delay.h> |
| 15 | #include <linux/of_gpio.h> |
| 16 | #include <linux/clk.h> |
| 17 | #include <linux/pm_runtime.h> |
| 18 | #include <linux/regmap.h> |
| 19 | #include <sound/pcm_params.h> |
| 20 | #include <sound/dmaengine_pcm.h> |
| 21 | |
| 22 | #include "rockchip_i2s.h" |
| 23 | |
| 24 | #define DRV_NAME "rockchip-i2s" |
| 25 | |
| 26 | struct rk_i2s_dev { |
| 27 | struct device *dev; |
| 28 | |
| 29 | struct clk *hclk; |
| 30 | struct clk *mclk; |
| 31 | |
| 32 | struct snd_dmaengine_dai_dma_data capture_dma_data; |
| 33 | struct snd_dmaengine_dai_dma_data playback_dma_data; |
| 34 | |
| 35 | struct regmap *regmap; |
| 36 | |
John Keeping | a6e806c | 2016-05-04 17:21:56 +0100 | [diff] [blame^] | 37 | /* |
| 38 | * Used to indicate the tx/rx status. |
| 39 | * I2S controller hopes to start the tx and rx together, |
| 40 | * also to stop them when they are both try to stop. |
| 41 | */ |
| 42 | bool tx_start; |
| 43 | bool rx_start; |
Caesar Wang | 2458c37 | 2015-11-06 19:38:14 +0800 | [diff] [blame] | 44 | bool is_master_mode; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 45 | }; |
| 46 | |
| 47 | static int i2s_runtime_suspend(struct device *dev) |
| 48 | { |
| 49 | struct rk_i2s_dev *i2s = dev_get_drvdata(dev); |
| 50 | |
| 51 | clk_disable_unprepare(i2s->mclk); |
| 52 | |
| 53 | return 0; |
| 54 | } |
| 55 | |
| 56 | static int i2s_runtime_resume(struct device *dev) |
| 57 | { |
| 58 | struct rk_i2s_dev *i2s = dev_get_drvdata(dev); |
| 59 | int ret; |
| 60 | |
| 61 | ret = clk_prepare_enable(i2s->mclk); |
| 62 | if (ret) { |
| 63 | dev_err(i2s->dev, "clock enable failed %d\n", ret); |
| 64 | return ret; |
| 65 | } |
| 66 | |
| 67 | return 0; |
| 68 | } |
| 69 | |
| 70 | static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai) |
| 71 | { |
| 72 | return snd_soc_dai_get_drvdata(dai); |
| 73 | } |
| 74 | |
| 75 | static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) |
| 76 | { |
| 77 | unsigned int val = 0; |
| 78 | int retry = 10; |
| 79 | |
| 80 | if (on) { |
| 81 | regmap_update_bits(i2s->regmap, I2S_DMACR, |
| 82 | I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE); |
| 83 | |
| 84 | regmap_update_bits(i2s->regmap, I2S_XFER, |
John Keeping | eba65d1 | 2015-12-09 10:32:26 +0000 | [diff] [blame] | 85 | I2S_XFER_TXS_START, |
| 86 | I2S_XFER_TXS_START); |
John Keeping | a6e806c | 2016-05-04 17:21:56 +0100 | [diff] [blame^] | 87 | |
| 88 | i2s->tx_start = true; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 89 | } else { |
John Keeping | a6e806c | 2016-05-04 17:21:56 +0100 | [diff] [blame^] | 90 | i2s->tx_start = false; |
| 91 | |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 92 | regmap_update_bits(i2s->regmap, I2S_DMACR, |
xujianqun | 4c5258a | 2014-07-12 09:02:13 +0800 | [diff] [blame] | 93 | I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE); |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 94 | |
John Keeping | eba65d1 | 2015-12-09 10:32:26 +0000 | [diff] [blame] | 95 | regmap_update_bits(i2s->regmap, I2S_XFER, |
| 96 | I2S_XFER_TXS_START, |
| 97 | I2S_XFER_TXS_STOP); |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 98 | |
John Keeping | eba65d1 | 2015-12-09 10:32:26 +0000 | [diff] [blame] | 99 | regmap_update_bits(i2s->regmap, I2S_CLR, |
| 100 | I2S_CLR_TXC, |
| 101 | I2S_CLR_TXC); |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 102 | |
John Keeping | eba65d1 | 2015-12-09 10:32:26 +0000 | [diff] [blame] | 103 | regmap_read(i2s->regmap, I2S_CLR, &val); |
| 104 | |
| 105 | /* Should wait for clear operation to finish */ |
| 106 | while (val & I2S_CLR_TXC) { |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 107 | regmap_read(i2s->regmap, I2S_CLR, &val); |
John Keeping | eba65d1 | 2015-12-09 10:32:26 +0000 | [diff] [blame] | 108 | retry--; |
| 109 | if (!retry) { |
| 110 | dev_warn(i2s->dev, "fail to clear\n"); |
| 111 | break; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 112 | } |
| 113 | } |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) |
| 118 | { |
| 119 | unsigned int val = 0; |
| 120 | int retry = 10; |
| 121 | |
| 122 | if (on) { |
| 123 | regmap_update_bits(i2s->regmap, I2S_DMACR, |
| 124 | I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE); |
| 125 | |
| 126 | regmap_update_bits(i2s->regmap, I2S_XFER, |
John Keeping | eba65d1 | 2015-12-09 10:32:26 +0000 | [diff] [blame] | 127 | I2S_XFER_RXS_START, |
| 128 | I2S_XFER_RXS_START); |
John Keeping | a6e806c | 2016-05-04 17:21:56 +0100 | [diff] [blame^] | 129 | |
| 130 | i2s->rx_start = true; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 131 | } else { |
John Keeping | a6e806c | 2016-05-04 17:21:56 +0100 | [diff] [blame^] | 132 | i2s->rx_start = false; |
| 133 | |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 134 | regmap_update_bits(i2s->regmap, I2S_DMACR, |
| 135 | I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE); |
| 136 | |
John Keeping | eba65d1 | 2015-12-09 10:32:26 +0000 | [diff] [blame] | 137 | regmap_update_bits(i2s->regmap, I2S_XFER, |
| 138 | I2S_XFER_RXS_START, |
| 139 | I2S_XFER_RXS_STOP); |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 140 | |
John Keeping | eba65d1 | 2015-12-09 10:32:26 +0000 | [diff] [blame] | 141 | regmap_update_bits(i2s->regmap, I2S_CLR, |
| 142 | I2S_CLR_RXC, |
| 143 | I2S_CLR_RXC); |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 144 | |
John Keeping | eba65d1 | 2015-12-09 10:32:26 +0000 | [diff] [blame] | 145 | regmap_read(i2s->regmap, I2S_CLR, &val); |
| 146 | |
| 147 | /* Should wait for clear operation to finish */ |
| 148 | while (val & I2S_CLR_RXC) { |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 149 | regmap_read(i2s->regmap, I2S_CLR, &val); |
John Keeping | eba65d1 | 2015-12-09 10:32:26 +0000 | [diff] [blame] | 150 | retry--; |
| 151 | if (!retry) { |
| 152 | dev_warn(i2s->dev, "fail to clear\n"); |
| 153 | break; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 154 | } |
| 155 | } |
| 156 | } |
| 157 | } |
| 158 | |
| 159 | static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, |
| 160 | unsigned int fmt) |
| 161 | { |
| 162 | struct rk_i2s_dev *i2s = to_info(cpu_dai); |
| 163 | unsigned int mask = 0, val = 0; |
| 164 | |
Jianqun | 07833d8 | 2014-09-13 08:41:03 +0800 | [diff] [blame] | 165 | mask = I2S_CKR_MSS_MASK; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 166 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 167 | case SND_SOC_DAIFMT_CBS_CFS: |
Jianqun | 07833d8 | 2014-09-13 08:41:03 +0800 | [diff] [blame] | 168 | /* Set source clock in Master mode */ |
| 169 | val = I2S_CKR_MSS_MASTER; |
Caesar Wang | 2458c37 | 2015-11-06 19:38:14 +0800 | [diff] [blame] | 170 | i2s->is_master_mode = true; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 171 | break; |
| 172 | case SND_SOC_DAIFMT_CBM_CFM: |
Jianqun | 07833d8 | 2014-09-13 08:41:03 +0800 | [diff] [blame] | 173 | val = I2S_CKR_MSS_SLAVE; |
Caesar Wang | 2458c37 | 2015-11-06 19:38:14 +0800 | [diff] [blame] | 174 | i2s->is_master_mode = false; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 175 | break; |
| 176 | default: |
| 177 | return -EINVAL; |
| 178 | } |
| 179 | |
| 180 | regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); |
| 181 | |
| 182 | mask = I2S_TXCR_IBM_MASK; |
| 183 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 184 | case SND_SOC_DAIFMT_RIGHT_J: |
| 185 | val = I2S_TXCR_IBM_RSJM; |
| 186 | break; |
| 187 | case SND_SOC_DAIFMT_LEFT_J: |
| 188 | val = I2S_TXCR_IBM_LSJM; |
| 189 | break; |
| 190 | case SND_SOC_DAIFMT_I2S: |
| 191 | val = I2S_TXCR_IBM_NORMAL; |
| 192 | break; |
| 193 | default: |
| 194 | return -EINVAL; |
| 195 | } |
| 196 | |
| 197 | regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val); |
| 198 | |
| 199 | mask = I2S_RXCR_IBM_MASK; |
| 200 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 201 | case SND_SOC_DAIFMT_RIGHT_J: |
| 202 | val = I2S_RXCR_IBM_RSJM; |
| 203 | break; |
| 204 | case SND_SOC_DAIFMT_LEFT_J: |
| 205 | val = I2S_RXCR_IBM_LSJM; |
| 206 | break; |
| 207 | case SND_SOC_DAIFMT_I2S: |
| 208 | val = I2S_RXCR_IBM_NORMAL; |
| 209 | break; |
| 210 | default: |
| 211 | return -EINVAL; |
| 212 | } |
| 213 | |
| 214 | regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val); |
| 215 | |
| 216 | return 0; |
| 217 | } |
| 218 | |
| 219 | static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, |
| 220 | struct snd_pcm_hw_params *params, |
| 221 | struct snd_soc_dai *dai) |
| 222 | { |
| 223 | struct rk_i2s_dev *i2s = to_info(dai); |
Sugar Zhang | b3f2dcd | 2015-10-08 20:40:09 +0800 | [diff] [blame] | 224 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 225 | unsigned int val = 0; |
Caesar Wang | 2458c37 | 2015-11-06 19:38:14 +0800 | [diff] [blame] | 226 | unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck; |
| 227 | |
| 228 | if (i2s->is_master_mode) { |
| 229 | mclk_rate = clk_get_rate(i2s->mclk); |
| 230 | bclk_rate = 2 * 32 * params_rate(params); |
| 231 | if (bclk_rate && mclk_rate % bclk_rate) |
| 232 | return -EINVAL; |
| 233 | |
| 234 | div_bclk = mclk_rate / bclk_rate; |
| 235 | div_lrck = bclk_rate / params_rate(params); |
| 236 | regmap_update_bits(i2s->regmap, I2S_CKR, |
| 237 | I2S_CKR_MDIV_MASK, |
| 238 | I2S_CKR_MDIV(div_bclk)); |
| 239 | |
| 240 | regmap_update_bits(i2s->regmap, I2S_CKR, |
| 241 | I2S_CKR_TSD_MASK | |
| 242 | I2S_CKR_RSD_MASK, |
| 243 | I2S_CKR_TSD(div_lrck) | |
| 244 | I2S_CKR_RSD(div_lrck)); |
| 245 | } |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 246 | |
| 247 | switch (params_format(params)) { |
| 248 | case SNDRV_PCM_FORMAT_S8: |
| 249 | val |= I2S_TXCR_VDW(8); |
| 250 | break; |
| 251 | case SNDRV_PCM_FORMAT_S16_LE: |
| 252 | val |= I2S_TXCR_VDW(16); |
| 253 | break; |
| 254 | case SNDRV_PCM_FORMAT_S20_3LE: |
| 255 | val |= I2S_TXCR_VDW(20); |
| 256 | break; |
| 257 | case SNDRV_PCM_FORMAT_S24_LE: |
| 258 | val |= I2S_TXCR_VDW(24); |
| 259 | break; |
Michael Trimarchi | 4ab936d | 2016-01-09 23:47:58 +0100 | [diff] [blame] | 260 | case SNDRV_PCM_FORMAT_S32_LE: |
| 261 | val |= I2S_TXCR_VDW(32); |
| 262 | break; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 263 | default: |
| 264 | return -EINVAL; |
| 265 | } |
| 266 | |
Sugar Zhang | 4c9c018 | 2015-10-08 20:40:07 +0800 | [diff] [blame] | 267 | switch (params_channels(params)) { |
| 268 | case 8: |
| 269 | val |= I2S_CHN_8; |
| 270 | break; |
| 271 | case 6: |
| 272 | val |= I2S_CHN_6; |
| 273 | break; |
| 274 | case 4: |
| 275 | val |= I2S_CHN_4; |
| 276 | break; |
| 277 | case 2: |
| 278 | val |= I2S_CHN_2; |
| 279 | break; |
| 280 | default: |
| 281 | dev_err(i2s->dev, "invalid channel: %d\n", |
| 282 | params_channels(params)); |
| 283 | return -EINVAL; |
| 284 | } |
| 285 | |
| 286 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
| 287 | regmap_update_bits(i2s->regmap, I2S_RXCR, |
| 288 | I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, |
| 289 | val); |
| 290 | else |
| 291 | regmap_update_bits(i2s->regmap, I2S_TXCR, |
| 292 | I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, |
| 293 | val); |
| 294 | |
Jianqun Xu | bba1431 | 2014-12-24 17:37:01 +0800 | [diff] [blame] | 295 | regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK, |
| 296 | I2S_DMACR_TDL(16)); |
| 297 | regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, |
| 298 | I2S_DMACR_RDL(16)); |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 299 | |
Sugar Zhang | b3f2dcd | 2015-10-08 20:40:09 +0800 | [diff] [blame] | 300 | val = I2S_CKR_TRCM_TXRX; |
| 301 | if (dai->driver->symmetric_rates || rtd->dai_link->symmetric_rates) |
| 302 | val = I2S_CKR_TRCM_TXSHARE; |
| 303 | |
| 304 | regmap_update_bits(i2s->regmap, I2S_CKR, |
| 305 | I2S_CKR_TRCM_MASK, |
| 306 | val); |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 307 | return 0; |
| 308 | } |
| 309 | |
| 310 | static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, |
| 311 | int cmd, struct snd_soc_dai *dai) |
| 312 | { |
| 313 | struct rk_i2s_dev *i2s = to_info(dai); |
| 314 | int ret = 0; |
| 315 | |
| 316 | switch (cmd) { |
| 317 | case SNDRV_PCM_TRIGGER_START: |
| 318 | case SNDRV_PCM_TRIGGER_RESUME: |
| 319 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 320 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
| 321 | rockchip_snd_rxctrl(i2s, 1); |
| 322 | else |
| 323 | rockchip_snd_txctrl(i2s, 1); |
| 324 | break; |
| 325 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 326 | case SNDRV_PCM_TRIGGER_STOP: |
| 327 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 328 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
| 329 | rockchip_snd_rxctrl(i2s, 0); |
| 330 | else |
| 331 | rockchip_snd_txctrl(i2s, 0); |
| 332 | break; |
| 333 | default: |
| 334 | ret = -EINVAL; |
| 335 | break; |
| 336 | } |
| 337 | |
| 338 | return ret; |
| 339 | } |
| 340 | |
| 341 | static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, |
| 342 | unsigned int freq, int dir) |
| 343 | { |
| 344 | struct rk_i2s_dev *i2s = to_info(cpu_dai); |
| 345 | int ret; |
| 346 | |
| 347 | ret = clk_set_rate(i2s->mclk, freq); |
| 348 | if (ret) |
| 349 | dev_err(i2s->dev, "Fail to set mclk %d\n", ret); |
| 350 | |
| 351 | return ret; |
| 352 | } |
| 353 | |
Jianqun | 3b40a80 | 2014-09-13 08:41:38 +0800 | [diff] [blame] | 354 | static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai) |
| 355 | { |
| 356 | struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); |
| 357 | |
| 358 | dai->capture_dma_data = &i2s->capture_dma_data; |
| 359 | dai->playback_dma_data = &i2s->playback_dma_data; |
| 360 | |
| 361 | return 0; |
| 362 | } |
| 363 | |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 364 | static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = { |
| 365 | .hw_params = rockchip_i2s_hw_params, |
| 366 | .set_sysclk = rockchip_i2s_set_sysclk, |
| 367 | .set_fmt = rockchip_i2s_set_fmt, |
| 368 | .trigger = rockchip_i2s_trigger, |
| 369 | }; |
| 370 | |
| 371 | static struct snd_soc_dai_driver rockchip_i2s_dai = { |
Jianqun | 3b40a80 | 2014-09-13 08:41:38 +0800 | [diff] [blame] | 372 | .probe = rockchip_i2s_dai_probe, |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 373 | .playback = { |
Jianqun | 3b40a80 | 2014-09-13 08:41:38 +0800 | [diff] [blame] | 374 | .stream_name = "Playback", |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 375 | .channels_min = 2, |
| 376 | .channels_max = 8, |
| 377 | .rates = SNDRV_PCM_RATE_8000_192000, |
| 378 | .formats = (SNDRV_PCM_FMTBIT_S8 | |
| 379 | SNDRV_PCM_FMTBIT_S16_LE | |
| 380 | SNDRV_PCM_FMTBIT_S20_3LE | |
Michael Trimarchi | 4ab936d | 2016-01-09 23:47:58 +0100 | [diff] [blame] | 381 | SNDRV_PCM_FMTBIT_S24_LE | |
| 382 | SNDRV_PCM_FMTBIT_S32_LE), |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 383 | }, |
| 384 | .capture = { |
Jianqun | 3b40a80 | 2014-09-13 08:41:38 +0800 | [diff] [blame] | 385 | .stream_name = "Capture", |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 386 | .channels_min = 2, |
| 387 | .channels_max = 2, |
| 388 | .rates = SNDRV_PCM_RATE_8000_192000, |
| 389 | .formats = (SNDRV_PCM_FMTBIT_S8 | |
| 390 | SNDRV_PCM_FMTBIT_S16_LE | |
| 391 | SNDRV_PCM_FMTBIT_S20_3LE | |
Michael Trimarchi | 4ab936d | 2016-01-09 23:47:58 +0100 | [diff] [blame] | 392 | SNDRV_PCM_FMTBIT_S24_LE | |
| 393 | SNDRV_PCM_FMTBIT_S32_LE), |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 394 | }, |
| 395 | .ops = &rockchip_i2s_dai_ops, |
Jianqun Xu | a12d159 | 2015-01-08 10:49:59 +0800 | [diff] [blame] | 396 | .symmetric_rates = 1, |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 397 | }; |
| 398 | |
| 399 | static const struct snd_soc_component_driver rockchip_i2s_component = { |
| 400 | .name = DRV_NAME, |
| 401 | }; |
| 402 | |
| 403 | static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg) |
| 404 | { |
| 405 | switch (reg) { |
| 406 | case I2S_TXCR: |
| 407 | case I2S_RXCR: |
| 408 | case I2S_CKR: |
| 409 | case I2S_DMACR: |
| 410 | case I2S_INTCR: |
| 411 | case I2S_XFER: |
| 412 | case I2S_CLR: |
| 413 | case I2S_TXDR: |
| 414 | return true; |
| 415 | default: |
| 416 | return false; |
| 417 | } |
| 418 | } |
| 419 | |
| 420 | static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg) |
| 421 | { |
| 422 | switch (reg) { |
| 423 | case I2S_TXCR: |
| 424 | case I2S_RXCR: |
| 425 | case I2S_CKR: |
| 426 | case I2S_DMACR: |
| 427 | case I2S_INTCR: |
| 428 | case I2S_XFER: |
| 429 | case I2S_CLR: |
| 430 | case I2S_RXDR: |
Jianqun | 2f1e93f | 2014-09-13 08:42:12 +0800 | [diff] [blame] | 431 | case I2S_FIFOLR: |
| 432 | case I2S_INTSR: |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 433 | return true; |
| 434 | default: |
| 435 | return false; |
| 436 | } |
| 437 | } |
| 438 | |
| 439 | static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg) |
| 440 | { |
| 441 | switch (reg) { |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 442 | case I2S_INTSR: |
Jianqun | 2f1e93f | 2014-09-13 08:42:12 +0800 | [diff] [blame] | 443 | case I2S_CLR: |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 444 | return true; |
| 445 | default: |
| 446 | return false; |
| 447 | } |
| 448 | } |
| 449 | |
| 450 | static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg) |
| 451 | { |
| 452 | switch (reg) { |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 453 | default: |
| 454 | return false; |
| 455 | } |
| 456 | } |
| 457 | |
Sugar Zhang | ea2e5b9 | 2016-02-22 15:56:54 +0800 | [diff] [blame] | 458 | static const struct reg_default rockchip_i2s_reg_defaults[] = { |
| 459 | {0x00, 0x0000000f}, |
| 460 | {0x04, 0x0000000f}, |
| 461 | {0x08, 0x00071f1f}, |
| 462 | {0x10, 0x001f0000}, |
| 463 | {0x14, 0x01f00000}, |
| 464 | }; |
| 465 | |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 466 | static const struct regmap_config rockchip_i2s_regmap_config = { |
| 467 | .reg_bits = 32, |
| 468 | .reg_stride = 4, |
| 469 | .val_bits = 32, |
| 470 | .max_register = I2S_RXDR, |
Sugar Zhang | ea2e5b9 | 2016-02-22 15:56:54 +0800 | [diff] [blame] | 471 | .reg_defaults = rockchip_i2s_reg_defaults, |
| 472 | .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults), |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 473 | .writeable_reg = rockchip_i2s_wr_reg, |
| 474 | .readable_reg = rockchip_i2s_rd_reg, |
| 475 | .volatile_reg = rockchip_i2s_volatile_reg, |
| 476 | .precious_reg = rockchip_i2s_precious_reg, |
| 477 | .cache_type = REGCACHE_FLAT, |
| 478 | }; |
| 479 | |
| 480 | static int rockchip_i2s_probe(struct platform_device *pdev) |
| 481 | { |
Sugar Zhang | 4c9c018 | 2015-10-08 20:40:07 +0800 | [diff] [blame] | 482 | struct device_node *node = pdev->dev.of_node; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 483 | struct rk_i2s_dev *i2s; |
Sugar Zhang | c4f9374 | 2015-11-10 15:32:07 +0800 | [diff] [blame] | 484 | struct snd_soc_dai_driver *soc_dai; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 485 | struct resource *res; |
| 486 | void __iomem *regs; |
| 487 | int ret; |
Sugar Zhang | 4c9c018 | 2015-10-08 20:40:07 +0800 | [diff] [blame] | 488 | int val; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 489 | |
| 490 | i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); |
| 491 | if (!i2s) { |
| 492 | dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n"); |
| 493 | return -ENOMEM; |
| 494 | } |
| 495 | |
| 496 | /* try to prepare related clocks */ |
| 497 | i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk"); |
| 498 | if (IS_ERR(i2s->hclk)) { |
| 499 | dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n"); |
| 500 | return PTR_ERR(i2s->hclk); |
| 501 | } |
Jianqun | 01605ad | 2014-09-13 08:43:13 +0800 | [diff] [blame] | 502 | ret = clk_prepare_enable(i2s->hclk); |
| 503 | if (ret) { |
| 504 | dev_err(i2s->dev, "hclock enable failed %d\n", ret); |
| 505 | return ret; |
| 506 | } |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 507 | |
| 508 | i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk"); |
| 509 | if (IS_ERR(i2s->mclk)) { |
| 510 | dev_err(&pdev->dev, "Can't retrieve i2s master clock\n"); |
| 511 | return PTR_ERR(i2s->mclk); |
| 512 | } |
| 513 | |
| 514 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 515 | regs = devm_ioremap_resource(&pdev->dev, res); |
Wei Yongjun | 55b2194 | 2014-07-28 21:21:00 +0800 | [diff] [blame] | 516 | if (IS_ERR(regs)) |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 517 | return PTR_ERR(regs); |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 518 | |
| 519 | i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, |
| 520 | &rockchip_i2s_regmap_config); |
| 521 | if (IS_ERR(i2s->regmap)) { |
| 522 | dev_err(&pdev->dev, |
| 523 | "Failed to initialise managed register map\n"); |
| 524 | return PTR_ERR(i2s->regmap); |
| 525 | } |
| 526 | |
| 527 | i2s->playback_dma_data.addr = res->start + I2S_TXDR; |
| 528 | i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
Jianqun Xu | 27fd36a | 2014-12-24 17:37:02 +0800 | [diff] [blame] | 529 | i2s->playback_dma_data.maxburst = 4; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 530 | |
| 531 | i2s->capture_dma_data.addr = res->start + I2S_RXDR; |
| 532 | i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
Jianqun Xu | 27fd36a | 2014-12-24 17:37:02 +0800 | [diff] [blame] | 533 | i2s->capture_dma_data.maxburst = 4; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 534 | |
| 535 | i2s->dev = &pdev->dev; |
| 536 | dev_set_drvdata(&pdev->dev, i2s); |
| 537 | |
| 538 | pm_runtime_enable(&pdev->dev); |
| 539 | if (!pm_runtime_enabled(&pdev->dev)) { |
| 540 | ret = i2s_runtime_resume(&pdev->dev); |
| 541 | if (ret) |
| 542 | goto err_pm_disable; |
| 543 | } |
| 544 | |
Sugar Zhang | c4f9374 | 2015-11-10 15:32:07 +0800 | [diff] [blame] | 545 | soc_dai = devm_kzalloc(&pdev->dev, |
| 546 | sizeof(*soc_dai), GFP_KERNEL); |
| 547 | if (!soc_dai) |
| 548 | return -ENOMEM; |
| 549 | |
| 550 | memcpy(soc_dai, &rockchip_i2s_dai, sizeof(*soc_dai)); |
| 551 | if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) { |
| 552 | if (val >= 2 && val <= 8) |
| 553 | soc_dai->playback.channels_max = val; |
| 554 | } |
| 555 | |
Sugar Zhang | 4c9c018 | 2015-10-08 20:40:07 +0800 | [diff] [blame] | 556 | if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) { |
| 557 | if (val >= 2 && val <= 8) |
Sugar Zhang | c4f9374 | 2015-11-10 15:32:07 +0800 | [diff] [blame] | 558 | soc_dai->capture.channels_max = val; |
Sugar Zhang | 4c9c018 | 2015-10-08 20:40:07 +0800 | [diff] [blame] | 559 | } |
| 560 | |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 561 | ret = devm_snd_soc_register_component(&pdev->dev, |
| 562 | &rockchip_i2s_component, |
Sugar Zhang | c4f9374 | 2015-11-10 15:32:07 +0800 | [diff] [blame] | 563 | soc_dai, 1); |
| 564 | |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 565 | if (ret) { |
| 566 | dev_err(&pdev->dev, "Could not register DAI\n"); |
| 567 | goto err_suspend; |
| 568 | } |
| 569 | |
Vaishali Thakkar | ebb75c0 | 2015-08-15 07:21:00 +0530 | [diff] [blame] | 570 | ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 571 | if (ret) { |
| 572 | dev_err(&pdev->dev, "Could not register PCM\n"); |
Vaishali Thakkar | ebb75c0 | 2015-08-15 07:21:00 +0530 | [diff] [blame] | 573 | return ret; |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 574 | } |
| 575 | |
| 576 | return 0; |
| 577 | |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 578 | err_suspend: |
| 579 | if (!pm_runtime_status_suspended(&pdev->dev)) |
| 580 | i2s_runtime_suspend(&pdev->dev); |
| 581 | err_pm_disable: |
| 582 | pm_runtime_disable(&pdev->dev); |
| 583 | |
| 584 | return ret; |
| 585 | } |
| 586 | |
| 587 | static int rockchip_i2s_remove(struct platform_device *pdev) |
| 588 | { |
| 589 | struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev); |
| 590 | |
| 591 | pm_runtime_disable(&pdev->dev); |
| 592 | if (!pm_runtime_status_suspended(&pdev->dev)) |
| 593 | i2s_runtime_suspend(&pdev->dev); |
| 594 | |
| 595 | clk_disable_unprepare(i2s->mclk); |
| 596 | clk_disable_unprepare(i2s->hclk); |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 597 | |
| 598 | return 0; |
| 599 | } |
| 600 | |
| 601 | static const struct of_device_id rockchip_i2s_match[] = { |
| 602 | { .compatible = "rockchip,rk3066-i2s", }, |
Jianqun Xu | 255edcd | 2016-02-22 16:32:05 +0800 | [diff] [blame] | 603 | { .compatible = "rockchip,rk3188-i2s", }, |
| 604 | { .compatible = "rockchip,rk3288-i2s", }, |
| 605 | { .compatible = "rockchip,rk3399-i2s", }, |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 606 | {}, |
| 607 | }; |
| 608 | |
| 609 | static const struct dev_pm_ops rockchip_i2s_pm_ops = { |
| 610 | SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume, |
| 611 | NULL) |
| 612 | }; |
| 613 | |
| 614 | static struct platform_driver rockchip_i2s_driver = { |
| 615 | .probe = rockchip_i2s_probe, |
| 616 | .remove = rockchip_i2s_remove, |
| 617 | .driver = { |
| 618 | .name = DRV_NAME, |
Jianqun Xu | 4495c89 | 2014-07-05 19:13:03 +0800 | [diff] [blame] | 619 | .of_match_table = of_match_ptr(rockchip_i2s_match), |
| 620 | .pm = &rockchip_i2s_pm_ops, |
| 621 | }, |
| 622 | }; |
| 623 | module_platform_driver(rockchip_i2s_driver); |
| 624 | |
| 625 | MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface"); |
| 626 | MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>"); |
| 627 | MODULE_LICENSE("GPL v2"); |
| 628 | MODULE_ALIAS("platform:" DRV_NAME); |
| 629 | MODULE_DEVICE_TABLE(of, rockchip_i2s_match); |