blob: 37ce8aca2cc69f3945368dd7f9a3b4de2521948e [file] [log] [blame]
Thierry Redinga1702852009-03-27 00:12:24 -07001/*
2 * linux/drivers/net/ethoc.c
3 *
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
12 */
13
14#include <linux/etherdevice.h>
15#include <linux/crc32.h>
16#include <linux/io.h>
17#include <linux/mii.h>
18#include <linux/phy.h>
19#include <linux/platform_device.h>
Alexey Dobriyand43c36d2009-10-07 17:09:06 +040020#include <linux/sched.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Thierry Redinga1702852009-03-27 00:12:24 -070022#include <net/ethoc.h>
23
Thomas Chou0baa0802009-10-04 23:33:20 +000024static int buffer_size = 0x8000; /* 32 KBytes */
25module_param(buffer_size, int, 0);
26MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
27
Thierry Redinga1702852009-03-27 00:12:24 -070028/* register offsets */
29#define MODER 0x00
30#define INT_SOURCE 0x04
31#define INT_MASK 0x08
32#define IPGT 0x0c
33#define IPGR1 0x10
34#define IPGR2 0x14
35#define PACKETLEN 0x18
36#define COLLCONF 0x1c
37#define TX_BD_NUM 0x20
38#define CTRLMODER 0x24
39#define MIIMODER 0x28
40#define MIICOMMAND 0x2c
41#define MIIADDRESS 0x30
42#define MIITX_DATA 0x34
43#define MIIRX_DATA 0x38
44#define MIISTATUS 0x3c
45#define MAC_ADDR0 0x40
46#define MAC_ADDR1 0x44
47#define ETH_HASH0 0x48
48#define ETH_HASH1 0x4c
49#define ETH_TXCTRL 0x50
50
51/* mode register */
52#define MODER_RXEN (1 << 0) /* receive enable */
53#define MODER_TXEN (1 << 1) /* transmit enable */
54#define MODER_NOPRE (1 << 2) /* no preamble */
55#define MODER_BRO (1 << 3) /* broadcast address */
56#define MODER_IAM (1 << 4) /* individual address mode */
57#define MODER_PRO (1 << 5) /* promiscuous mode */
58#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
59#define MODER_LOOP (1 << 7) /* loopback */
60#define MODER_NBO (1 << 8) /* no back-off */
61#define MODER_EDE (1 << 9) /* excess defer enable */
62#define MODER_FULLD (1 << 10) /* full duplex */
63#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
64#define MODER_DCRC (1 << 12) /* delayed CRC enable */
65#define MODER_CRC (1 << 13) /* CRC enable */
66#define MODER_HUGE (1 << 14) /* huge packets enable */
67#define MODER_PAD (1 << 15) /* padding enabled */
68#define MODER_RSM (1 << 16) /* receive small packets */
69
70/* interrupt source and mask registers */
71#define INT_MASK_TXF (1 << 0) /* transmit frame */
72#define INT_MASK_TXE (1 << 1) /* transmit error */
73#define INT_MASK_RXF (1 << 2) /* receive frame */
74#define INT_MASK_RXE (1 << 3) /* receive error */
75#define INT_MASK_BUSY (1 << 4)
76#define INT_MASK_TXC (1 << 5) /* transmit control frame */
77#define INT_MASK_RXC (1 << 6) /* receive control frame */
78
79#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
80#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
81
82#define INT_MASK_ALL ( \
83 INT_MASK_TXF | INT_MASK_TXE | \
84 INT_MASK_RXF | INT_MASK_RXE | \
85 INT_MASK_TXC | INT_MASK_RXC | \
86 INT_MASK_BUSY \
87 )
88
89/* packet length register */
90#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
91#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
92#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
93 PACKETLEN_MAX(max))
94
95/* transmit buffer number register */
96#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
97
98/* control module mode register */
99#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
100#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
101#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
102
103/* MII mode register */
104#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
105#define MIIMODER_NOPRE (1 << 8) /* no preamble */
106
107/* MII command register */
108#define MIICOMMAND_SCAN (1 << 0) /* scan status */
109#define MIICOMMAND_READ (1 << 1) /* read status */
110#define MIICOMMAND_WRITE (1 << 2) /* write control data */
111
112/* MII address register */
113#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
114#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
115#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
116 MIIADDRESS_RGAD(reg))
117
118/* MII transmit data register */
119#define MIITX_DATA_VAL(x) ((x) & 0xffff)
120
121/* MII receive data register */
122#define MIIRX_DATA_VAL(x) ((x) & 0xffff)
123
124/* MII status register */
125#define MIISTATUS_LINKFAIL (1 << 0)
126#define MIISTATUS_BUSY (1 << 1)
127#define MIISTATUS_INVALID (1 << 2)
128
129/* TX buffer descriptor */
130#define TX_BD_CS (1 << 0) /* carrier sense lost */
131#define TX_BD_DF (1 << 1) /* defer indication */
132#define TX_BD_LC (1 << 2) /* late collision */
133#define TX_BD_RL (1 << 3) /* retransmission limit */
134#define TX_BD_RETRY_MASK (0x00f0)
135#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
136#define TX_BD_UR (1 << 8) /* transmitter underrun */
137#define TX_BD_CRC (1 << 11) /* TX CRC enable */
138#define TX_BD_PAD (1 << 12) /* pad enable for short packets */
139#define TX_BD_WRAP (1 << 13)
140#define TX_BD_IRQ (1 << 14) /* interrupt request enable */
141#define TX_BD_READY (1 << 15) /* TX buffer ready */
142#define TX_BD_LEN(x) (((x) & 0xffff) << 16)
143#define TX_BD_LEN_MASK (0xffff << 16)
144
145#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
146 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
147
148/* RX buffer descriptor */
149#define RX_BD_LC (1 << 0) /* late collision */
150#define RX_BD_CRC (1 << 1) /* RX CRC error */
151#define RX_BD_SF (1 << 2) /* short frame */
152#define RX_BD_TL (1 << 3) /* too long */
153#define RX_BD_DN (1 << 4) /* dribble nibble */
154#define RX_BD_IS (1 << 5) /* invalid symbol */
155#define RX_BD_OR (1 << 6) /* receiver overrun */
156#define RX_BD_MISS (1 << 7)
157#define RX_BD_CF (1 << 8) /* control frame */
158#define RX_BD_WRAP (1 << 13)
159#define RX_BD_IRQ (1 << 14) /* interrupt request enable */
160#define RX_BD_EMPTY (1 << 15)
161#define RX_BD_LEN(x) (((x) & 0xffff) << 16)
162
163#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
164 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
165
166#define ETHOC_BUFSIZ 1536
167#define ETHOC_ZLEN 64
168#define ETHOC_BD_BASE 0x400
169#define ETHOC_TIMEOUT (HZ / 2)
170#define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
171
172/**
173 * struct ethoc - driver-private device structure
174 * @iobase: pointer to I/O memory region
175 * @membase: pointer to buffer memory region
Thomas Chou0baa0802009-10-04 23:33:20 +0000176 * @dma_alloc: dma allocated buffer size
Thomas Chouee02a4e2010-05-23 16:44:02 +0000177 * @io_region_size: I/O memory region size
Thierry Redinga1702852009-03-27 00:12:24 -0700178 * @num_tx: number of send buffers
179 * @cur_tx: last send buffer written
180 * @dty_tx: last buffer actually sent
181 * @num_rx: number of receive buffers
182 * @cur_rx: current receive buffer
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000183 * @vma: pointer to array of virtual memory addresses for buffers
Thierry Redinga1702852009-03-27 00:12:24 -0700184 * @netdev: pointer to network device structure
185 * @napi: NAPI structure
186 * @stats: network device statistics
187 * @msg_enable: device state flags
188 * @rx_lock: receive lock
189 * @lock: device lock
190 * @phy: attached PHY
191 * @mdio: MDIO bus for PHY access
192 * @phy_id: address of attached PHY
193 */
194struct ethoc {
195 void __iomem *iobase;
196 void __iomem *membase;
Thomas Chou0baa0802009-10-04 23:33:20 +0000197 int dma_alloc;
Thomas Chouee02a4e2010-05-23 16:44:02 +0000198 resource_size_t io_region_size;
Thierry Redinga1702852009-03-27 00:12:24 -0700199
200 unsigned int num_tx;
201 unsigned int cur_tx;
202 unsigned int dty_tx;
203
204 unsigned int num_rx;
205 unsigned int cur_rx;
206
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000207 void** vma;
208
Thierry Redinga1702852009-03-27 00:12:24 -0700209 struct net_device *netdev;
210 struct napi_struct napi;
211 struct net_device_stats stats;
212 u32 msg_enable;
213
214 spinlock_t rx_lock;
215 spinlock_t lock;
216
217 struct phy_device *phy;
218 struct mii_bus *mdio;
219 s8 phy_id;
220};
221
222/**
223 * struct ethoc_bd - buffer descriptor
224 * @stat: buffer statistics
225 * @addr: physical memory address
226 */
227struct ethoc_bd {
228 u32 stat;
229 u32 addr;
230};
231
Thomas Chou16dd18b2009-10-07 14:16:42 +0000232static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
Thierry Redinga1702852009-03-27 00:12:24 -0700233{
234 return ioread32(dev->iobase + offset);
235}
236
Thomas Chou16dd18b2009-10-07 14:16:42 +0000237static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
Thierry Redinga1702852009-03-27 00:12:24 -0700238{
239 iowrite32(data, dev->iobase + offset);
240}
241
Thomas Chou16dd18b2009-10-07 14:16:42 +0000242static inline void ethoc_read_bd(struct ethoc *dev, int index,
243 struct ethoc_bd *bd)
Thierry Redinga1702852009-03-27 00:12:24 -0700244{
245 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
246 bd->stat = ethoc_read(dev, offset + 0);
247 bd->addr = ethoc_read(dev, offset + 4);
248}
249
Thomas Chou16dd18b2009-10-07 14:16:42 +0000250static inline void ethoc_write_bd(struct ethoc *dev, int index,
Thierry Redinga1702852009-03-27 00:12:24 -0700251 const struct ethoc_bd *bd)
252{
253 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
254 ethoc_write(dev, offset + 0, bd->stat);
255 ethoc_write(dev, offset + 4, bd->addr);
256}
257
Thomas Chou16dd18b2009-10-07 14:16:42 +0000258static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
Thierry Redinga1702852009-03-27 00:12:24 -0700259{
260 u32 imask = ethoc_read(dev, INT_MASK);
261 imask |= mask;
262 ethoc_write(dev, INT_MASK, imask);
263}
264
Thomas Chou16dd18b2009-10-07 14:16:42 +0000265static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
Thierry Redinga1702852009-03-27 00:12:24 -0700266{
267 u32 imask = ethoc_read(dev, INT_MASK);
268 imask &= ~mask;
269 ethoc_write(dev, INT_MASK, imask);
270}
271
Thomas Chou16dd18b2009-10-07 14:16:42 +0000272static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
Thierry Redinga1702852009-03-27 00:12:24 -0700273{
274 ethoc_write(dev, INT_SOURCE, mask);
275}
276
Thomas Chou16dd18b2009-10-07 14:16:42 +0000277static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700278{
279 u32 mode = ethoc_read(dev, MODER);
280 mode |= MODER_RXEN | MODER_TXEN;
281 ethoc_write(dev, MODER, mode);
282}
283
Thomas Chou16dd18b2009-10-07 14:16:42 +0000284static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700285{
286 u32 mode = ethoc_read(dev, MODER);
287 mode &= ~(MODER_RXEN | MODER_TXEN);
288 ethoc_write(dev, MODER, mode);
289}
290
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000291static int ethoc_init_ring(struct ethoc *dev, void* mem_start)
Thierry Redinga1702852009-03-27 00:12:24 -0700292{
293 struct ethoc_bd bd;
294 int i;
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000295 void* vma;
Thierry Redinga1702852009-03-27 00:12:24 -0700296
297 dev->cur_tx = 0;
298 dev->dty_tx = 0;
299 dev->cur_rx = 0;
300
Jonas Bonnee4f56b2010-06-11 02:47:36 +0000301 ethoc_write(dev, TX_BD_NUM, dev->num_tx);
302
Thierry Redinga1702852009-03-27 00:12:24 -0700303 /* setup transmission buffers */
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000304 bd.addr = mem_start;
Thierry Redinga1702852009-03-27 00:12:24 -0700305 bd.stat = TX_BD_IRQ | TX_BD_CRC;
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000306 vma = dev->membase;
Thierry Redinga1702852009-03-27 00:12:24 -0700307
308 for (i = 0; i < dev->num_tx; i++) {
309 if (i == dev->num_tx - 1)
310 bd.stat |= TX_BD_WRAP;
311
312 ethoc_write_bd(dev, i, &bd);
313 bd.addr += ETHOC_BUFSIZ;
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000314
315 dev->vma[i] = vma;
316 vma += ETHOC_BUFSIZ;
Thierry Redinga1702852009-03-27 00:12:24 -0700317 }
318
Thierry Redinga1702852009-03-27 00:12:24 -0700319 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
320
321 for (i = 0; i < dev->num_rx; i++) {
322 if (i == dev->num_rx - 1)
323 bd.stat |= RX_BD_WRAP;
324
325 ethoc_write_bd(dev, dev->num_tx + i, &bd);
326 bd.addr += ETHOC_BUFSIZ;
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000327
328 dev->vma[dev->num_tx + i] = vma;
329 vma += ETHOC_BUFSIZ;
Thierry Redinga1702852009-03-27 00:12:24 -0700330 }
331
332 return 0;
333}
334
335static int ethoc_reset(struct ethoc *dev)
336{
337 u32 mode;
338
339 /* TODO: reset controller? */
340
341 ethoc_disable_rx_and_tx(dev);
342
343 /* TODO: setup registers */
344
345 /* enable FCS generation and automatic padding */
346 mode = ethoc_read(dev, MODER);
347 mode |= MODER_CRC | MODER_PAD;
348 ethoc_write(dev, MODER, mode);
349
350 /* set full-duplex mode */
351 mode = ethoc_read(dev, MODER);
352 mode |= MODER_FULLD;
353 ethoc_write(dev, MODER, mode);
354 ethoc_write(dev, IPGT, 0x15);
355
356 ethoc_ack_irq(dev, INT_MASK_ALL);
357 ethoc_enable_irq(dev, INT_MASK_ALL);
358 ethoc_enable_rx_and_tx(dev);
359 return 0;
360}
361
362static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
363 struct ethoc_bd *bd)
364{
365 struct net_device *netdev = dev->netdev;
366 unsigned int ret = 0;
367
368 if (bd->stat & RX_BD_TL) {
369 dev_err(&netdev->dev, "RX: frame too long\n");
370 dev->stats.rx_length_errors++;
371 ret++;
372 }
373
374 if (bd->stat & RX_BD_SF) {
375 dev_err(&netdev->dev, "RX: frame too short\n");
376 dev->stats.rx_length_errors++;
377 ret++;
378 }
379
380 if (bd->stat & RX_BD_DN) {
381 dev_err(&netdev->dev, "RX: dribble nibble\n");
382 dev->stats.rx_frame_errors++;
383 }
384
385 if (bd->stat & RX_BD_CRC) {
386 dev_err(&netdev->dev, "RX: wrong CRC\n");
387 dev->stats.rx_crc_errors++;
388 ret++;
389 }
390
391 if (bd->stat & RX_BD_OR) {
392 dev_err(&netdev->dev, "RX: overrun\n");
393 dev->stats.rx_over_errors++;
394 ret++;
395 }
396
397 if (bd->stat & RX_BD_MISS)
398 dev->stats.rx_missed_errors++;
399
400 if (bd->stat & RX_BD_LC) {
401 dev_err(&netdev->dev, "RX: late collision\n");
402 dev->stats.collisions++;
403 ret++;
404 }
405
406 return ret;
407}
408
409static int ethoc_rx(struct net_device *dev, int limit)
410{
411 struct ethoc *priv = netdev_priv(dev);
412 int count;
413
414 for (count = 0; count < limit; ++count) {
415 unsigned int entry;
416 struct ethoc_bd bd;
417
418 entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
419 ethoc_read_bd(priv, entry, &bd);
420 if (bd.stat & RX_BD_EMPTY)
421 break;
422
423 if (ethoc_update_rx_stats(priv, &bd) == 0) {
424 int size = bd.stat >> 16;
Eric Dumazet89d71a62009-10-13 05:34:20 +0000425 struct sk_buff *skb;
Thomas Chou050f91d2009-10-04 23:33:19 +0000426
427 size -= 4; /* strip the CRC */
Eric Dumazet89d71a62009-10-13 05:34:20 +0000428 skb = netdev_alloc_skb_ip_align(dev, size);
Thomas Chou050f91d2009-10-04 23:33:19 +0000429
Thierry Redinga1702852009-03-27 00:12:24 -0700430 if (likely(skb)) {
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000431 void *src = priv->vma[entry];
Thierry Redinga1702852009-03-27 00:12:24 -0700432 memcpy_fromio(skb_put(skb, size), src, size);
433 skb->protocol = eth_type_trans(skb, dev);
Thierry Redinga1702852009-03-27 00:12:24 -0700434 priv->stats.rx_packets++;
435 priv->stats.rx_bytes += size;
436 netif_receive_skb(skb);
437 } else {
438 if (net_ratelimit())
439 dev_warn(&dev->dev, "low on memory - "
440 "packet dropped\n");
441
442 priv->stats.rx_dropped++;
443 break;
444 }
445 }
446
447 /* clear the buffer descriptor so it can be reused */
448 bd.stat &= ~RX_BD_STATS;
449 bd.stat |= RX_BD_EMPTY;
450 ethoc_write_bd(priv, entry, &bd);
451 priv->cur_rx++;
452 }
453
454 return count;
455}
456
457static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
458{
459 struct net_device *netdev = dev->netdev;
460
461 if (bd->stat & TX_BD_LC) {
462 dev_err(&netdev->dev, "TX: late collision\n");
463 dev->stats.tx_window_errors++;
464 }
465
466 if (bd->stat & TX_BD_RL) {
467 dev_err(&netdev->dev, "TX: retransmit limit\n");
468 dev->stats.tx_aborted_errors++;
469 }
470
471 if (bd->stat & TX_BD_UR) {
472 dev_err(&netdev->dev, "TX: underrun\n");
473 dev->stats.tx_fifo_errors++;
474 }
475
476 if (bd->stat & TX_BD_CS) {
477 dev_err(&netdev->dev, "TX: carrier sense lost\n");
478 dev->stats.tx_carrier_errors++;
479 }
480
481 if (bd->stat & TX_BD_STATS)
482 dev->stats.tx_errors++;
483
484 dev->stats.collisions += (bd->stat >> 4) & 0xf;
485 dev->stats.tx_bytes += bd->stat >> 16;
486 dev->stats.tx_packets++;
487 return 0;
488}
489
490static void ethoc_tx(struct net_device *dev)
491{
492 struct ethoc *priv = netdev_priv(dev);
493
494 spin_lock(&priv->lock);
495
496 while (priv->dty_tx != priv->cur_tx) {
497 unsigned int entry = priv->dty_tx % priv->num_tx;
498 struct ethoc_bd bd;
499
500 ethoc_read_bd(priv, entry, &bd);
501 if (bd.stat & TX_BD_READY)
502 break;
503
504 entry = (++priv->dty_tx) % priv->num_tx;
505 (void)ethoc_update_tx_stats(priv, &bd);
506 }
507
508 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
509 netif_wake_queue(dev);
510
511 ethoc_ack_irq(priv, INT_MASK_TX);
512 spin_unlock(&priv->lock);
513}
514
515static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
516{
517 struct net_device *dev = (struct net_device *)dev_id;
518 struct ethoc *priv = netdev_priv(dev);
519 u32 pending;
520
521 ethoc_disable_irq(priv, INT_MASK_ALL);
522 pending = ethoc_read(priv, INT_SOURCE);
523 if (unlikely(pending == 0)) {
524 ethoc_enable_irq(priv, INT_MASK_ALL);
525 return IRQ_NONE;
526 }
527
Thomas Chou50c54a52009-10-07 14:16:43 +0000528 ethoc_ack_irq(priv, pending);
Thierry Redinga1702852009-03-27 00:12:24 -0700529
530 if (pending & INT_MASK_BUSY) {
531 dev_err(&dev->dev, "packet dropped\n");
532 priv->stats.rx_dropped++;
533 }
534
535 if (pending & INT_MASK_RX) {
536 if (napi_schedule_prep(&priv->napi))
537 __napi_schedule(&priv->napi);
538 } else {
539 ethoc_enable_irq(priv, INT_MASK_RX);
540 }
541
542 if (pending & INT_MASK_TX)
543 ethoc_tx(dev);
544
545 ethoc_enable_irq(priv, INT_MASK_ALL & ~INT_MASK_RX);
546 return IRQ_HANDLED;
547}
548
549static int ethoc_get_mac_address(struct net_device *dev, void *addr)
550{
551 struct ethoc *priv = netdev_priv(dev);
552 u8 *mac = (u8 *)addr;
553 u32 reg;
554
555 reg = ethoc_read(priv, MAC_ADDR0);
556 mac[2] = (reg >> 24) & 0xff;
557 mac[3] = (reg >> 16) & 0xff;
558 mac[4] = (reg >> 8) & 0xff;
559 mac[5] = (reg >> 0) & 0xff;
560
561 reg = ethoc_read(priv, MAC_ADDR1);
562 mac[0] = (reg >> 8) & 0xff;
563 mac[1] = (reg >> 0) & 0xff;
564
565 return 0;
566}
567
568static int ethoc_poll(struct napi_struct *napi, int budget)
569{
570 struct ethoc *priv = container_of(napi, struct ethoc, napi);
571 int work_done = 0;
572
573 work_done = ethoc_rx(priv->netdev, budget);
574 if (work_done < budget) {
575 ethoc_enable_irq(priv, INT_MASK_RX);
576 napi_complete(napi);
577 }
578
579 return work_done;
580}
581
582static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
583{
584 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
585 struct ethoc *priv = bus->priv;
586
587 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
588 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
589
590 while (time_before(jiffies, timeout)) {
591 u32 status = ethoc_read(priv, MIISTATUS);
592 if (!(status & MIISTATUS_BUSY)) {
593 u32 data = ethoc_read(priv, MIIRX_DATA);
594 /* reset MII command register */
595 ethoc_write(priv, MIICOMMAND, 0);
596 return data;
597 }
598
599 schedule();
600 }
601
602 return -EBUSY;
603}
604
605static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
606{
607 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
608 struct ethoc *priv = bus->priv;
609
610 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
611 ethoc_write(priv, MIITX_DATA, val);
612 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
613
614 while (time_before(jiffies, timeout)) {
615 u32 stat = ethoc_read(priv, MIISTATUS);
Jonas Bonnb46773d2010-06-11 02:47:39 +0000616 if (!(stat & MIISTATUS_BUSY)) {
617 /* reset MII command register */
618 ethoc_write(priv, MIICOMMAND, 0);
Thierry Redinga1702852009-03-27 00:12:24 -0700619 return 0;
Jonas Bonnb46773d2010-06-11 02:47:39 +0000620 }
Thierry Redinga1702852009-03-27 00:12:24 -0700621
622 schedule();
623 }
624
625 return -EBUSY;
626}
627
628static int ethoc_mdio_reset(struct mii_bus *bus)
629{
630 return 0;
631}
632
633static void ethoc_mdio_poll(struct net_device *dev)
634{
635}
636
637static int ethoc_mdio_probe(struct net_device *dev)
638{
639 struct ethoc *priv = netdev_priv(dev);
640 struct phy_device *phy;
Jonas Bonn637f33b82010-06-11 02:47:37 +0000641 int err;
Thierry Redinga1702852009-03-27 00:12:24 -0700642
Jonas Bonn637f33b82010-06-11 02:47:37 +0000643 if (priv->phy_id != -1) {
644 phy = priv->mdio->phy_map[priv->phy_id];
645 } else {
646 phy = phy_find_first(priv->mdio);
Thierry Redinga1702852009-03-27 00:12:24 -0700647 }
648
649 if (!phy) {
650 dev_err(&dev->dev, "no PHY found\n");
651 return -ENXIO;
652 }
653
Jonas Bonn637f33b82010-06-11 02:47:37 +0000654 err = phy_connect_direct(dev, phy, ethoc_mdio_poll, 0,
Thierry Redinga1702852009-03-27 00:12:24 -0700655 PHY_INTERFACE_MODE_GMII);
Jonas Bonn637f33b82010-06-11 02:47:37 +0000656 if (err) {
Thierry Redinga1702852009-03-27 00:12:24 -0700657 dev_err(&dev->dev, "could not attach to PHY\n");
Jonas Bonn637f33b82010-06-11 02:47:37 +0000658 return err;
Thierry Redinga1702852009-03-27 00:12:24 -0700659 }
660
661 priv->phy = phy;
662 return 0;
663}
664
665static int ethoc_open(struct net_device *dev)
666{
667 struct ethoc *priv = netdev_priv(dev);
Thierry Redinga1702852009-03-27 00:12:24 -0700668 int ret;
669
670 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
671 dev->name, dev);
672 if (ret)
673 return ret;
674
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000675 ethoc_init_ring(priv, (void*)dev->mem_start);
Thierry Redinga1702852009-03-27 00:12:24 -0700676 ethoc_reset(priv);
677
678 if (netif_queue_stopped(dev)) {
679 dev_dbg(&dev->dev, " resuming queue\n");
680 netif_wake_queue(dev);
681 } else {
682 dev_dbg(&dev->dev, " starting queue\n");
683 netif_start_queue(dev);
684 }
685
686 phy_start(priv->phy);
687 napi_enable(&priv->napi);
688
689 if (netif_msg_ifup(priv)) {
690 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
691 dev->base_addr, dev->mem_start, dev->mem_end);
692 }
693
694 return 0;
695}
696
697static int ethoc_stop(struct net_device *dev)
698{
699 struct ethoc *priv = netdev_priv(dev);
700
701 napi_disable(&priv->napi);
702
703 if (priv->phy)
704 phy_stop(priv->phy);
705
706 ethoc_disable_rx_and_tx(priv);
707 free_irq(dev->irq, dev);
708
709 if (!netif_queue_stopped(dev))
710 netif_stop_queue(dev);
711
712 return 0;
713}
714
715static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
716{
717 struct ethoc *priv = netdev_priv(dev);
718 struct mii_ioctl_data *mdio = if_mii(ifr);
719 struct phy_device *phy = NULL;
720
721 if (!netif_running(dev))
722 return -EINVAL;
723
724 if (cmd != SIOCGMIIPHY) {
725 if (mdio->phy_id >= PHY_MAX_ADDR)
726 return -ERANGE;
727
728 phy = priv->mdio->phy_map[mdio->phy_id];
729 if (!phy)
730 return -ENODEV;
731 } else {
732 phy = priv->phy;
733 }
734
735 return phy_mii_ioctl(phy, mdio, cmd);
736}
737
738static int ethoc_config(struct net_device *dev, struct ifmap *map)
739{
740 return -ENOSYS;
741}
742
743static int ethoc_set_mac_address(struct net_device *dev, void *addr)
744{
745 struct ethoc *priv = netdev_priv(dev);
746 u8 *mac = (u8 *)addr;
747
748 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
749 (mac[4] << 8) | (mac[5] << 0));
750 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
751
752 return 0;
753}
754
755static void ethoc_set_multicast_list(struct net_device *dev)
756{
757 struct ethoc *priv = netdev_priv(dev);
758 u32 mode = ethoc_read(priv, MODER);
Jiri Pirko22bedad32010-04-01 21:22:57 +0000759 struct netdev_hw_addr *ha;
Thierry Redinga1702852009-03-27 00:12:24 -0700760 u32 hash[2] = { 0, 0 };
761
762 /* set loopback mode if requested */
763 if (dev->flags & IFF_LOOPBACK)
764 mode |= MODER_LOOP;
765 else
766 mode &= ~MODER_LOOP;
767
768 /* receive broadcast frames if requested */
769 if (dev->flags & IFF_BROADCAST)
770 mode &= ~MODER_BRO;
771 else
772 mode |= MODER_BRO;
773
774 /* enable promiscuous mode if requested */
775 if (dev->flags & IFF_PROMISC)
776 mode |= MODER_PRO;
777 else
778 mode &= ~MODER_PRO;
779
780 ethoc_write(priv, MODER, mode);
781
782 /* receive multicast frames */
783 if (dev->flags & IFF_ALLMULTI) {
784 hash[0] = 0xffffffff;
785 hash[1] = 0xffffffff;
786 } else {
Jiri Pirko22bedad32010-04-01 21:22:57 +0000787 netdev_for_each_mc_addr(ha, dev) {
788 u32 crc = ether_crc(ETH_ALEN, ha->addr);
Thierry Redinga1702852009-03-27 00:12:24 -0700789 int bit = (crc >> 26) & 0x3f;
790 hash[bit >> 5] |= 1 << (bit & 0x1f);
791 }
792 }
793
794 ethoc_write(priv, ETH_HASH0, hash[0]);
795 ethoc_write(priv, ETH_HASH1, hash[1]);
796}
797
798static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
799{
800 return -ENOSYS;
801}
802
803static void ethoc_tx_timeout(struct net_device *dev)
804{
805 struct ethoc *priv = netdev_priv(dev);
806 u32 pending = ethoc_read(priv, INT_SOURCE);
807 if (likely(pending))
808 ethoc_interrupt(dev->irq, dev);
809}
810
811static struct net_device_stats *ethoc_stats(struct net_device *dev)
812{
813 struct ethoc *priv = netdev_priv(dev);
814 return &priv->stats;
815}
816
Stephen Hemminger613573252009-08-31 19:50:58 +0000817static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700818{
819 struct ethoc *priv = netdev_priv(dev);
820 struct ethoc_bd bd;
821 unsigned int entry;
822 void *dest;
823
824 if (unlikely(skb->len > ETHOC_BUFSIZ)) {
825 priv->stats.tx_errors++;
Patrick McHardy3790c8c2009-06-12 03:00:35 +0000826 goto out;
Thierry Redinga1702852009-03-27 00:12:24 -0700827 }
828
829 entry = priv->cur_tx % priv->num_tx;
830 spin_lock_irq(&priv->lock);
831 priv->cur_tx++;
832
833 ethoc_read_bd(priv, entry, &bd);
834 if (unlikely(skb->len < ETHOC_ZLEN))
835 bd.stat |= TX_BD_PAD;
836 else
837 bd.stat &= ~TX_BD_PAD;
838
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000839 dest = priv->vma[entry];
Thierry Redinga1702852009-03-27 00:12:24 -0700840 memcpy_toio(dest, skb->data, skb->len);
841
842 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
843 bd.stat |= TX_BD_LEN(skb->len);
844 ethoc_write_bd(priv, entry, &bd);
845
846 bd.stat |= TX_BD_READY;
847 ethoc_write_bd(priv, entry, &bd);
848
849 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
850 dev_dbg(&dev->dev, "stopping queue\n");
851 netif_stop_queue(dev);
852 }
853
Thierry Redinga1702852009-03-27 00:12:24 -0700854 spin_unlock_irq(&priv->lock);
Patrick McHardy3790c8c2009-06-12 03:00:35 +0000855out:
856 dev_kfree_skb(skb);
Thierry Redinga1702852009-03-27 00:12:24 -0700857 return NETDEV_TX_OK;
858}
859
860static const struct net_device_ops ethoc_netdev_ops = {
861 .ndo_open = ethoc_open,
862 .ndo_stop = ethoc_stop,
863 .ndo_do_ioctl = ethoc_ioctl,
864 .ndo_set_config = ethoc_config,
865 .ndo_set_mac_address = ethoc_set_mac_address,
866 .ndo_set_multicast_list = ethoc_set_multicast_list,
867 .ndo_change_mtu = ethoc_change_mtu,
868 .ndo_tx_timeout = ethoc_tx_timeout,
869 .ndo_get_stats = ethoc_stats,
870 .ndo_start_xmit = ethoc_start_xmit,
871};
872
873/**
874 * ethoc_probe() - initialize OpenCores ethernet MAC
875 * pdev: platform device
876 */
877static int ethoc_probe(struct platform_device *pdev)
878{
879 struct net_device *netdev = NULL;
880 struct resource *res = NULL;
881 struct resource *mmio = NULL;
882 struct resource *mem = NULL;
883 struct ethoc *priv = NULL;
884 unsigned int phy;
Jonas Bonnc527f812010-06-11 02:47:34 +0000885 int num_bd;
Thierry Redinga1702852009-03-27 00:12:24 -0700886 int ret = 0;
887
888 /* allocate networking device */
889 netdev = alloc_etherdev(sizeof(struct ethoc));
890 if (!netdev) {
891 dev_err(&pdev->dev, "cannot allocate network device\n");
892 ret = -ENOMEM;
893 goto out;
894 }
895
896 SET_NETDEV_DEV(netdev, &pdev->dev);
897 platform_set_drvdata(pdev, netdev);
898
899 /* obtain I/O memory space */
900 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
901 if (!res) {
902 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
903 ret = -ENXIO;
904 goto free;
905 }
906
907 mmio = devm_request_mem_region(&pdev->dev, res->start,
Tobias Klauserd8645842010-01-15 01:48:22 -0800908 resource_size(res), res->name);
Julia Lawall463889e2009-07-27 06:13:30 +0000909 if (!mmio) {
Thierry Redinga1702852009-03-27 00:12:24 -0700910 dev_err(&pdev->dev, "cannot request I/O memory space\n");
911 ret = -ENXIO;
912 goto free;
913 }
914
915 netdev->base_addr = mmio->start;
916
917 /* obtain buffer memory space */
918 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
Thomas Chou0baa0802009-10-04 23:33:20 +0000919 if (res) {
920 mem = devm_request_mem_region(&pdev->dev, res->start,
Tobias Klauserd8645842010-01-15 01:48:22 -0800921 resource_size(res), res->name);
Thomas Chou0baa0802009-10-04 23:33:20 +0000922 if (!mem) {
923 dev_err(&pdev->dev, "cannot request memory space\n");
924 ret = -ENXIO;
925 goto free;
926 }
927
928 netdev->mem_start = mem->start;
929 netdev->mem_end = mem->end;
Thierry Redinga1702852009-03-27 00:12:24 -0700930 }
931
Thierry Redinga1702852009-03-27 00:12:24 -0700932
933 /* obtain device IRQ number */
934 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
935 if (!res) {
936 dev_err(&pdev->dev, "cannot obtain IRQ\n");
937 ret = -ENXIO;
938 goto free;
939 }
940
941 netdev->irq = res->start;
942
943 /* setup driver-private data */
944 priv = netdev_priv(netdev);
945 priv->netdev = netdev;
Thomas Chou0baa0802009-10-04 23:33:20 +0000946 priv->dma_alloc = 0;
Thomas Chouee02a4e2010-05-23 16:44:02 +0000947 priv->io_region_size = mmio->end - mmio->start + 1;
Thierry Redinga1702852009-03-27 00:12:24 -0700948
949 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
Tobias Klauserd8645842010-01-15 01:48:22 -0800950 resource_size(mmio));
Thierry Redinga1702852009-03-27 00:12:24 -0700951 if (!priv->iobase) {
952 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
953 ret = -ENXIO;
954 goto error;
955 }
956
Thomas Chou0baa0802009-10-04 23:33:20 +0000957 if (netdev->mem_end) {
958 priv->membase = devm_ioremap_nocache(&pdev->dev,
Tobias Klauserd8645842010-01-15 01:48:22 -0800959 netdev->mem_start, resource_size(mem));
Thomas Chou0baa0802009-10-04 23:33:20 +0000960 if (!priv->membase) {
961 dev_err(&pdev->dev, "cannot remap memory space\n");
962 ret = -ENXIO;
963 goto error;
964 }
965 } else {
966 /* Allocate buffer memory */
Jonas Bonna71fba92010-06-11 02:47:40 +0000967 priv->membase = dmam_alloc_coherent(&pdev->dev,
Thomas Chou0baa0802009-10-04 23:33:20 +0000968 buffer_size, (void *)&netdev->mem_start,
969 GFP_KERNEL);
970 if (!priv->membase) {
971 dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
972 buffer_size);
973 ret = -ENOMEM;
974 goto error;
975 }
976 netdev->mem_end = netdev->mem_start + buffer_size;
977 priv->dma_alloc = buffer_size;
Thierry Redinga1702852009-03-27 00:12:24 -0700978 }
979
Jonas Bonnc527f812010-06-11 02:47:34 +0000980 /* calculate the number of TX/RX buffers, maximum 128 supported */
981 num_bd = min_t(unsigned int,
982 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
983 priv->num_tx = max(2, num_bd / 4);
984 priv->num_rx = num_bd - priv->num_tx;
985
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000986 priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void*), GFP_KERNEL);
987 if (!priv->vma) {
988 ret = -ENOMEM;
989 goto error;
990 }
991
Thierry Redinga1702852009-03-27 00:12:24 -0700992 /* Allow the platform setup code to pass in a MAC address. */
993 if (pdev->dev.platform_data) {
994 struct ethoc_platform_data *pdata =
995 (struct ethoc_platform_data *)pdev->dev.platform_data;
996 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
997 priv->phy_id = pdata->phy_id;
998 }
999
1000 /* Check that the given MAC address is valid. If it isn't, read the
1001 * current MAC from the controller. */
1002 if (!is_valid_ether_addr(netdev->dev_addr))
1003 ethoc_get_mac_address(netdev, netdev->dev_addr);
1004
1005 /* Check the MAC again for validity, if it still isn't choose and
1006 * program a random one. */
1007 if (!is_valid_ether_addr(netdev->dev_addr))
1008 random_ether_addr(netdev->dev_addr);
1009
1010 ethoc_set_mac_address(netdev, netdev->dev_addr);
1011
1012 /* register MII bus */
1013 priv->mdio = mdiobus_alloc();
1014 if (!priv->mdio) {
1015 ret = -ENOMEM;
1016 goto free;
1017 }
1018
1019 priv->mdio->name = "ethoc-mdio";
1020 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1021 priv->mdio->name, pdev->id);
1022 priv->mdio->read = ethoc_mdio_read;
1023 priv->mdio->write = ethoc_mdio_write;
1024 priv->mdio->reset = ethoc_mdio_reset;
1025 priv->mdio->priv = priv;
1026
1027 priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1028 if (!priv->mdio->irq) {
1029 ret = -ENOMEM;
1030 goto free_mdio;
1031 }
1032
1033 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
1034 priv->mdio->irq[phy] = PHY_POLL;
1035
1036 ret = mdiobus_register(priv->mdio);
1037 if (ret) {
1038 dev_err(&netdev->dev, "failed to register MDIO bus\n");
1039 goto free_mdio;
1040 }
1041
1042 ret = ethoc_mdio_probe(netdev);
1043 if (ret) {
1044 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1045 goto error;
1046 }
1047
1048 ether_setup(netdev);
1049
1050 /* setup the net_device structure */
1051 netdev->netdev_ops = &ethoc_netdev_ops;
1052 netdev->watchdog_timeo = ETHOC_TIMEOUT;
1053 netdev->features |= 0;
1054
1055 /* setup NAPI */
Thierry Redinga1702852009-03-27 00:12:24 -07001056 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1057
1058 spin_lock_init(&priv->rx_lock);
1059 spin_lock_init(&priv->lock);
1060
1061 ret = register_netdev(netdev);
1062 if (ret < 0) {
1063 dev_err(&netdev->dev, "failed to register interface\n");
Thomas Chouee02a4e2010-05-23 16:44:02 +00001064 goto error2;
Thierry Redinga1702852009-03-27 00:12:24 -07001065 }
1066
1067 goto out;
1068
Thomas Chouee02a4e2010-05-23 16:44:02 +00001069error2:
1070 netif_napi_del(&priv->napi);
Thierry Redinga1702852009-03-27 00:12:24 -07001071error:
1072 mdiobus_unregister(priv->mdio);
1073free_mdio:
1074 kfree(priv->mdio->irq);
1075 mdiobus_free(priv->mdio);
1076free:
1077 free_netdev(netdev);
1078out:
1079 return ret;
1080}
1081
1082/**
1083 * ethoc_remove() - shutdown OpenCores ethernet MAC
1084 * @pdev: platform device
1085 */
1086static int ethoc_remove(struct platform_device *pdev)
1087{
1088 struct net_device *netdev = platform_get_drvdata(pdev);
1089 struct ethoc *priv = netdev_priv(netdev);
1090
1091 platform_set_drvdata(pdev, NULL);
1092
1093 if (netdev) {
Thomas Chouee02a4e2010-05-23 16:44:02 +00001094 netif_napi_del(&priv->napi);
Thierry Redinga1702852009-03-27 00:12:24 -07001095 phy_disconnect(priv->phy);
1096 priv->phy = NULL;
1097
1098 if (priv->mdio) {
1099 mdiobus_unregister(priv->mdio);
1100 kfree(priv->mdio->irq);
1101 mdiobus_free(priv->mdio);
1102 }
Thierry Redinga1702852009-03-27 00:12:24 -07001103 unregister_netdev(netdev);
1104 free_netdev(netdev);
1105 }
1106
1107 return 0;
1108}
1109
1110#ifdef CONFIG_PM
1111static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1112{
1113 return -ENOSYS;
1114}
1115
1116static int ethoc_resume(struct platform_device *pdev)
1117{
1118 return -ENOSYS;
1119}
1120#else
1121# define ethoc_suspend NULL
1122# define ethoc_resume NULL
1123#endif
1124
1125static struct platform_driver ethoc_driver = {
1126 .probe = ethoc_probe,
1127 .remove = ethoc_remove,
1128 .suspend = ethoc_suspend,
1129 .resume = ethoc_resume,
1130 .driver = {
1131 .name = "ethoc",
1132 },
1133};
1134
1135static int __init ethoc_init(void)
1136{
1137 return platform_driver_register(&ethoc_driver);
1138}
1139
1140static void __exit ethoc_exit(void)
1141{
1142 platform_driver_unregister(&ethoc_driver);
1143}
1144
1145module_init(ethoc_init);
1146module_exit(ethoc_exit);
1147
1148MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1149MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1150MODULE_LICENSE("GPL v2");
1151