Raviteja Tamatam | e97849a | 2017-09-12 20:25:50 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include "dsi-panel-sim-video.dtsi" |
| 14 | #include "dsi-panel-sim-cmd.dtsi" |
| 15 | #include "dsi-panel-sim-dsc375-cmd.dtsi" |
| 16 | #include "dsi-panel-sim-dualmipi-video.dtsi" |
| 17 | #include "dsi-panel-sim-dualmipi-cmd.dtsi" |
| 18 | #include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" |
| 19 | #include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" |
| 20 | #include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" |
| 21 | #include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi" |
| 22 | #include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi" |
| 23 | #include <dt-bindings/clock/mdss-10nm-pll-clk.h> |
| 24 | |
| 25 | &soc { |
| 26 | dsi_panel_pwr_supply: dsi_panel_pwr_supply { |
| 27 | #address-cells = <1>; |
| 28 | #size-cells = <0>; |
| 29 | |
| 30 | qcom,panel-supply-entry@0 { |
| 31 | reg = <0>; |
| 32 | qcom,supply-name = "vddio"; |
| 33 | qcom,supply-min-voltage = <1800000>; |
| 34 | qcom,supply-max-voltage = <1800000>; |
| 35 | qcom,supply-enable-load = <62000>; |
| 36 | qcom,supply-disable-load = <80>; |
| 37 | qcom,supply-post-on-sleep = <20>; |
| 38 | }; |
| 39 | |
| 40 | qcom,panel-supply-entry@1 { |
| 41 | reg = <1>; |
| 42 | qcom,supply-name = "lab"; |
| 43 | qcom,supply-min-voltage = <4600000>; |
| 44 | qcom,supply-max-voltage = <6000000>; |
| 45 | qcom,supply-enable-load = <100000>; |
| 46 | qcom,supply-disable-load = <100>; |
| 47 | }; |
| 48 | |
| 49 | qcom,panel-supply-entry@2 { |
| 50 | reg = <2>; |
| 51 | qcom,supply-name = "ibb"; |
| 52 | qcom,supply-min-voltage = <4600000>; |
| 53 | qcom,supply-max-voltage = <6000000>; |
| 54 | qcom,supply-enable-load = <100000>; |
| 55 | qcom,supply-disable-load = <100>; |
| 56 | qcom,supply-post-on-sleep = <20>; |
| 57 | }; |
| 58 | }; |
| 59 | |
| 60 | dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { |
| 61 | #address-cells = <1>; |
| 62 | #size-cells = <0>; |
| 63 | |
| 64 | qcom,panel-supply-entry@0 { |
| 65 | reg = <0>; |
| 66 | qcom,supply-name = "vddio"; |
| 67 | qcom,supply-min-voltage = <1800000>; |
| 68 | qcom,supply-max-voltage = <1800000>; |
| 69 | qcom,supply-enable-load = <62000>; |
| 70 | qcom,supply-disable-load = <80>; |
| 71 | qcom,supply-post-on-sleep = <20>; |
| 72 | }; |
| 73 | }; |
| 74 | |
| 75 | dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb { |
| 76 | #address-cells = <1>; |
| 77 | #size-cells = <0>; |
| 78 | |
| 79 | qcom,panel-supply-entry@0 { |
| 80 | reg = <0>; |
| 81 | qcom,supply-name = "vddio"; |
| 82 | qcom,supply-min-voltage = <1800000>; |
| 83 | qcom,supply-max-voltage = <1800000>; |
| 84 | qcom,supply-enable-load = <62000>; |
| 85 | qcom,supply-disable-load = <80>; |
| 86 | qcom,supply-post-on-sleep = <20>; |
| 87 | }; |
| 88 | |
| 89 | qcom,panel-supply-entry@1 { |
| 90 | reg = <1>; |
| 91 | qcom,supply-name = "vdd"; |
| 92 | qcom,supply-min-voltage = <3000000>; |
| 93 | qcom,supply-max-voltage = <3000000>; |
| 94 | qcom,supply-enable-load = <857000>; |
| 95 | qcom,supply-disable-load = <0>; |
| 96 | qcom,supply-post-on-sleep = <0>; |
| 97 | }; |
| 98 | }; |
| 99 | |
| 100 | dsi_dual_nt35597_truly_video_display: qcom,dsi-display@0 { |
| 101 | compatible = "qcom,dsi-display"; |
| 102 | label = "dsi_dual_nt35597_truly_video_display"; |
| 103 | qcom,display-type = "primary"; |
| 104 | |
| 105 | qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| 106 | qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| 107 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 108 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 109 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 110 | |
| 111 | pinctrl-names = "panel_active", "panel_suspend"; |
| 112 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 113 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 114 | qcom,platform-reset-gpio = <&tlmm 75 0>; |
| 115 | qcom,panel-mode-gpio = <&tlmm 76 0>; |
| 116 | |
| 117 | qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>; |
| 118 | vddio-supply = <&pm660_l11>; |
| 119 | lab-supply = <&lcdb_ldo_vreg>; |
| 120 | ibb-supply = <&lcdb_ncp_vreg>; |
| 121 | }; |
| 122 | |
| 123 | dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@1 { |
| 124 | compatible = "qcom,dsi-display"; |
| 125 | label = "dsi_dual_nt35597_truly_cmd_display"; |
| 126 | qcom,display-type = "primary"; |
| 127 | |
| 128 | qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| 129 | qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| 130 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 131 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 132 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 133 | |
| 134 | pinctrl-names = "panel_active", "panel_suspend"; |
| 135 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 136 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 137 | qcom,platform-te-gpio = <&tlmm 10 0>; |
| 138 | qcom,platform-reset-gpio = <&tlmm 75 0>; |
| 139 | qcom,panel-mode-gpio = <&tlmm 76 0>; |
| 140 | |
| 141 | qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>; |
| 142 | vddio-supply = <&pm660_l11>; |
| 143 | lab-supply = <&lcdb_ldo_vreg>; |
| 144 | ibb-supply = <&lcdb_ncp_vreg>; |
| 145 | }; |
| 146 | |
| 147 | dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@2 { |
| 148 | compatible = "qcom,dsi-display"; |
| 149 | label = "dsi_nt35597_truly_dsc_cmd_display"; |
| 150 | qcom,display-type = "primary"; |
| 151 | |
| 152 | qcom,dsi-ctrl = <&mdss_dsi1>; |
| 153 | qcom,dsi-phy = <&mdss_dsi_phy1>; |
| 154 | clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, |
| 155 | <&mdss_dsi1_pll PCLK_MUX_1_CLK>; |
| 156 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 157 | |
| 158 | pinctrl-names = "panel_active", "panel_suspend"; |
| 159 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 160 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 161 | qcom,platform-te-gpio = <&tlmm 10 0>; |
| 162 | qcom,platform-reset-gpio = <&tlmm 75 0>; |
| 163 | qcom,panel-mode-gpio = <&tlmm 76 0>; |
| 164 | |
| 165 | qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>; |
| 166 | vddio-supply = <&pm660_l11>; |
| 167 | lab-supply = <&lcdb_ldo_vreg>; |
| 168 | ibb-supply = <&lcdb_ncp_vreg>; |
| 169 | }; |
| 170 | |
| 171 | dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@3 { |
| 172 | compatible = "qcom,dsi-display"; |
| 173 | label = "dsi_nt35597_truly_dsc_video_display"; |
| 174 | qcom,display-type = "primary"; |
| 175 | |
| 176 | qcom,dsi-ctrl = <&mdss_dsi1>; |
| 177 | qcom,dsi-phy = <&mdss_dsi_phy1>; |
| 178 | clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, |
| 179 | <&mdss_dsi1_pll PCLK_MUX_1_CLK>; |
| 180 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 181 | |
| 182 | pinctrl-names = "panel_active", "panel_suspend"; |
| 183 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 184 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 185 | qcom,platform-te-gpio = <&tlmm 10 0>; |
| 186 | qcom,platform-reset-gpio = <&tlmm 75 0>; |
| 187 | qcom,panel-mode-gpio = <&tlmm 76 0>; |
| 188 | |
| 189 | qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>; |
| 190 | vddio-supply = <&pm660_l11>; |
| 191 | lab-supply = <&lcdb_ldo_vreg>; |
| 192 | ibb-supply = <&lcdb_ncp_vreg>; |
| 193 | }; |
| 194 | |
| 195 | dsi_sim_vid_display: qcom,dsi-display@4 { |
| 196 | compatible = "qcom,dsi-display"; |
| 197 | label = "dsi_sim_vid_display"; |
| 198 | qcom,display-type = "primary"; |
| 199 | |
| 200 | qcom,dsi-ctrl = <&mdss_dsi0>; |
| 201 | qcom,dsi-phy = <&mdss_dsi_phy0>; |
| 202 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 203 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 204 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 205 | |
| 206 | pinctrl-names = "panel_active", "panel_suspend"; |
| 207 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 208 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 209 | |
| 210 | qcom,dsi-panel = <&dsi_sim_vid>; |
| 211 | }; |
| 212 | |
| 213 | dsi_dual_sim_vid_display: qcom,dsi-display@5 { |
| 214 | compatible = "qcom,dsi-display"; |
| 215 | label = "dsi_dual_sim_vid_display"; |
| 216 | qcom,display-type = "primary"; |
| 217 | |
| 218 | qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| 219 | qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| 220 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 221 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 222 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 223 | |
| 224 | pinctrl-names = "panel_active", "panel_suspend"; |
| 225 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 226 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 227 | |
| 228 | qcom,dsi-panel = <&dsi_dual_sim_vid>; |
| 229 | }; |
| 230 | |
| 231 | dsi_sim_cmd_display: qcom,dsi-display@6 { |
| 232 | compatible = "qcom,dsi-display"; |
| 233 | label = "dsi_sim_cmd_display"; |
| 234 | qcom,display-type = "primary"; |
| 235 | |
| 236 | qcom,dsi-ctrl = <&mdss_dsi0>; |
| 237 | qcom,dsi-phy = <&mdss_dsi_phy0>; |
| 238 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 239 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 240 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 241 | |
| 242 | pinctrl-names = "panel_active", "panel_suspend"; |
| 243 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 244 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 245 | |
| 246 | qcom,dsi-panel = <&dsi_sim_cmd>; |
| 247 | }; |
| 248 | |
| 249 | dsi_dual_sim_cmd_display: qcom,dsi-display@7 { |
| 250 | compatible = "qcom,dsi-display"; |
| 251 | label = "dsi_dual_sim_cmd_display"; |
| 252 | qcom,display-type = "primary"; |
| 253 | |
| 254 | qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| 255 | qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| 256 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 257 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 258 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 259 | |
| 260 | pinctrl-names = "panel_active", "panel_suspend"; |
| 261 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 262 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 263 | |
| 264 | qcom,dsi-panel = <&dsi_dual_sim_cmd>; |
| 265 | }; |
| 266 | |
| 267 | dsi_sim_dsc_375_cmd_display: qcom,dsi-display@8 { |
| 268 | compatible = "qcom,dsi-display"; |
| 269 | label = "dsi_sim_dsc_375_cmd_display"; |
| 270 | qcom,display-type = "primary"; |
| 271 | |
| 272 | qcom,dsi-ctrl = <&mdss_dsi0>; |
| 273 | qcom,dsi-phy = <&mdss_dsi_phy0>; |
| 274 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 275 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 276 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 277 | |
| 278 | pinctrl-names = "panel_active", "panel_suspend"; |
| 279 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 280 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 281 | |
| 282 | qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>; |
| 283 | }; |
| 284 | |
| 285 | dsi_dual_sim_dsc_375_cmd_display: qcom,dsi-display@9 { |
| 286 | compatible = "qcom,dsi-display"; |
| 287 | label = "dsi_dual_sim_dsc_375_cmd_display"; |
| 288 | qcom,display-type = "primary"; |
| 289 | |
| 290 | qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| 291 | qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| 292 | clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| 293 | <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| 294 | clock-names = "src_byte_clk", "src_pixel_clk"; |
| 295 | |
| 296 | pinctrl-names = "panel_active", "panel_suspend"; |
| 297 | pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| 298 | pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| 299 | |
| 300 | qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>; |
| 301 | }; |
| 302 | |
| 303 | sde_wb: qcom,wb-display@0 { |
| 304 | compatible = "qcom,wb-display"; |
| 305 | cell-index = <0>; |
| 306 | label = "wb_display"; |
| 307 | }; |
| 308 | |
| 309 | ext_disp: qcom,msm-ext-disp { |
| 310 | compatible = "qcom,msm-ext-disp"; |
| 311 | status = "disabled"; |
| 312 | |
| 313 | ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { |
| 314 | compatible = "qcom,msm-ext-disp-audio-codec-rx"; |
| 315 | }; |
| 316 | }; |
| 317 | |
| 318 | sde_dp: qcom,dp_display@0{ |
| 319 | cell-index = <0>; |
| 320 | compatible = "qcom,dp-display"; |
| 321 | status = "disabled"; |
| 322 | |
| 323 | gdsc-supply = <&mdss_core_gdsc>; |
| 324 | vdda-1p2-supply = <&pm660_l1>; |
| 325 | vdda-0p9-supply = <&pm660l_l1>; |
| 326 | |
| 327 | reg = <0xae90000 0xa84>, |
| 328 | <0x88eaa00 0x200>, |
| 329 | <0x88ea200 0x200>, |
| 330 | <0x88ea600 0x200>, |
| 331 | <0xaf02000 0x1a0>, |
| 332 | <0x780000 0x621c>, |
| 333 | <0x88ea030 0x10>, |
| 334 | <0x0aee1000 0x034>; |
| 335 | reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", |
| 336 | "dp_mmss_cc", "qfprom_physical", "dp_pll", |
| 337 | "hdcp_physical"; |
| 338 | |
| 339 | interrupt-parent = <&mdss_mdp>; |
| 340 | interrupts = <12 0>; |
| 341 | |
| 342 | clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, |
| 343 | <&clock_rpmh RPMH_CXO_CLK>, |
| 344 | <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, |
| 345 | <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
| 346 | <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, |
| 347 | <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, |
| 348 | <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, |
| 349 | <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, |
| 350 | <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, |
| 351 | <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, |
| 352 | <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>; |
| 353 | clock-names = "core_aux_clk", "core_usb_ref_clk_src", |
| 354 | "core_usb_ref_clk", "core_usb_cfg_ahb_clk", |
| 355 | "core_usb_pipe_clk", "ctrl_link_clk", |
| 356 | "ctrl_link_iface_clk", "ctrl_pixel_clk", |
| 357 | "crypto_clk", "pixel_clk_rcg", "pixel_parent"; |
| 358 | |
| 359 | qcom,dp-usbpd-detection = <&pm660_pdphy>; |
| 360 | qcom,ext-disp = <&ext_disp>; |
| 361 | |
| 362 | qcom,aux-cfg0-settings = [20 00]; |
| 363 | qcom,aux-cfg1-settings = [24 13 23 1d]; |
| 364 | qcom,aux-cfg2-settings = [28 24]; |
| 365 | qcom,aux-cfg3-settings = [2c 00]; |
| 366 | qcom,aux-cfg4-settings = [30 0a]; |
| 367 | qcom,aux-cfg5-settings = [34 26]; |
| 368 | qcom,aux-cfg6-settings = [38 0a]; |
| 369 | qcom,aux-cfg7-settings = [3c 03]; |
| 370 | qcom,aux-cfg8-settings = [40 bb]; |
| 371 | qcom,aux-cfg9-settings = [44 03]; |
| 372 | |
| 373 | qcom,max-pclk-frequency-khz = <675000>; |
| 374 | |
| 375 | qcom,core-supply-entries { |
| 376 | #address-cells = <1>; |
| 377 | #size-cells = <0>; |
| 378 | |
| 379 | qcom,core-supply-entry@0 { |
| 380 | reg = <0>; |
| 381 | qcom,supply-name = "gdsc"; |
| 382 | qcom,supply-min-voltage = <0>; |
| 383 | qcom,supply-max-voltage = <0>; |
| 384 | qcom,supply-enable-load = <0>; |
| 385 | qcom,supply-disable-load = <0>; |
| 386 | }; |
| 387 | }; |
| 388 | |
| 389 | qcom,ctrl-supply-entries { |
| 390 | #address-cells = <1>; |
| 391 | #size-cells = <0>; |
| 392 | |
| 393 | qcom,ctrl-supply-entry@0 { |
| 394 | reg = <0>; |
| 395 | qcom,supply-name = "vdda-1p2"; |
| 396 | qcom,supply-min-voltage = <1200000>; |
| 397 | qcom,supply-max-voltage = <1200000>; |
| 398 | qcom,supply-enable-load = <21800>; |
| 399 | qcom,supply-disable-load = <4>; |
| 400 | }; |
| 401 | }; |
| 402 | |
| 403 | qcom,phy-supply-entries { |
| 404 | #address-cells = <1>; |
| 405 | #size-cells = <0>; |
| 406 | |
| 407 | qcom,phy-supply-entry@0 { |
| 408 | reg = <0>; |
| 409 | qcom,supply-name = "vdda-0p9"; |
| 410 | qcom,supply-min-voltage = <880000>; |
| 411 | qcom,supply-max-voltage = <880000>; |
| 412 | qcom,supply-enable-load = <36000>; |
| 413 | qcom,supply-disable-load = <32>; |
| 414 | }; |
| 415 | }; |
| 416 | }; |
| 417 | }; |
| 418 | |
| 419 | &sde_dp { |
| 420 | status = "disabled"; |
| 421 | pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; |
| 422 | pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>; |
| 423 | pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>; |
| 424 | qcom,aux-en-gpio = <&tlmm 50 0>; |
| 425 | qcom,aux-sel-gpio = <&tlmm 40 0>; |
| 426 | qcom,usbplug-cc-gpio = <&tlmm 38 0>; |
| 427 | }; |
| 428 | |
| 429 | &mdss_mdp { |
| 430 | connectors = <&sde_rscc &sde_wb>; |
| 431 | }; |
| 432 | |
| 433 | &dsi_dual_nt35597_truly_video { |
| 434 | qcom,mdss-dsi-t-clk-post = <0x0D>; |
| 435 | qcom,mdss-dsi-t-clk-pre = <0x2D>; |
| 436 | qcom,mdss-dsi-display-timings { |
| 437 | timing@0{ |
| 438 | qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 439 | 07 05 03 04 00]; |
| 440 | qcom,display-topology = <2 0 2>, |
| 441 | <1 0 2>; |
| 442 | qcom,default-topology-index = <0>; |
| 443 | }; |
| 444 | }; |
| 445 | }; |
| 446 | |
| 447 | &dsi_dual_nt35597_truly_cmd { |
| 448 | qcom,mdss-dsi-t-clk-post = <0x0D>; |
| 449 | qcom,mdss-dsi-t-clk-pre = <0x2D>; |
| 450 | qcom,mdss-dsi-display-timings { |
| 451 | timing@0{ |
| 452 | qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 453 | 07 05 03 04 00]; |
| 454 | qcom,display-topology = <2 0 2>, |
| 455 | <1 0 2>; |
| 456 | qcom,default-topology-index = <0>; |
| 457 | }; |
| 458 | }; |
| 459 | }; |
| 460 | |
| 461 | &dsi_nt35597_truly_dsc_cmd { |
| 462 | qcom,mdss-dsi-t-clk-post = <0x0b>; |
| 463 | qcom,mdss-dsi-t-clk-pre = <0x23>; |
| 464 | qcom,mdss-dsi-display-timings { |
| 465 | timing@0{ |
| 466 | qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 |
| 467 | 05 03 03 04 00]; |
| 468 | qcom,display-topology = <1 1 1>, |
| 469 | <2 2 1>, /* dsc merge */ |
| 470 | <2 1 1>; /* 3d mux */ |
| 471 | qcom,default-topology-index = <1>; |
| 472 | }; |
| 473 | }; |
| 474 | }; |
| 475 | |
| 476 | &dsi_nt35597_truly_dsc_video { |
| 477 | qcom,mdss-dsi-t-clk-post = <0x0b>; |
| 478 | qcom,mdss-dsi-t-clk-pre = <0x23>; |
| 479 | qcom,mdss-dsi-display-timings { |
| 480 | timing@0{ |
| 481 | qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 |
| 482 | 04 03 03 04 00]; |
| 483 | qcom,display-topology = <1 1 1>, |
| 484 | <2 2 1>, /* dsc merge */ |
| 485 | <2 1 1>; /* 3d mux */ |
| 486 | qcom,default-topology-index = <1>; |
| 487 | }; |
| 488 | }; |
| 489 | }; |
| 490 | |
| 491 | &dsi_sim_vid { |
| 492 | qcom,mdss-dsi-t-clk-post = <0x0d>; |
| 493 | qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| 494 | qcom,mdss-dsi-display-timings { |
| 495 | timing@0{ |
| 496 | qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 497 | 07 05 03 04 00]; |
| 498 | qcom,display-topology = <1 0 1>, |
| 499 | <2 0 1>; |
| 500 | qcom,default-topology-index = <0>; |
| 501 | }; |
| 502 | }; |
| 503 | }; |
| 504 | |
| 505 | &dsi_dual_sim_vid { |
| 506 | qcom,mdss-dsi-t-clk-post = <0x0d>; |
| 507 | qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| 508 | qcom,mdss-dsi-display-timings { |
| 509 | timing@0{ |
| 510 | qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 511 | 07 05 03 04 00]; |
| 512 | qcom,display-topology = <2 0 2>, |
| 513 | <1 0 2>; |
| 514 | qcom,default-topology-index = <0>; |
| 515 | }; |
| 516 | }; |
| 517 | }; |
| 518 | |
| 519 | &dsi_sim_cmd { |
| 520 | qcom,mdss-dsi-t-clk-post = <0x0d>; |
| 521 | qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| 522 | qcom,mdss-dsi-display-timings { |
| 523 | timing@0{ |
| 524 | qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 525 | 07 05 03 04 00]; |
| 526 | qcom,display-topology = <1 0 1>, |
| 527 | <2 0 1>; |
| 528 | qcom,default-topology-index = <0>; |
| 529 | }; |
| 530 | }; |
| 531 | }; |
| 532 | |
| 533 | &dsi_dual_sim_cmd { |
| 534 | qcom,mdss-dsi-t-clk-post = <0x0d>; |
| 535 | qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| 536 | qcom,mdss-dsi-display-timings { |
| 537 | timing@0{ |
| 538 | qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 |
| 539 | 09 06 03 04 00]; |
| 540 | qcom,display-topology = <2 0 2>; |
| 541 | qcom,default-topology-index = <0>; |
| 542 | }; |
| 543 | timing@1{ |
| 544 | qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 545 | 07 05 03 04 00]; |
| 546 | qcom,display-topology = <2 0 2>, |
| 547 | <1 0 2>; |
| 548 | qcom,default-topology-index = <0>; |
| 549 | }; |
| 550 | timing@2{ |
| 551 | qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 |
| 552 | 06 04 03 04 00]; |
| 553 | qcom,display-topology = <2 0 2>; |
| 554 | qcom,default-topology-index = <0>; |
| 555 | }; |
| 556 | }; |
| 557 | }; |
| 558 | |
| 559 | &dsi_sim_dsc_375_cmd { |
| 560 | qcom,mdss-dsi-t-clk-post = <0x0d>; |
| 561 | qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| 562 | qcom,mdss-dsi-display-timings { |
| 563 | timing@0 { /* 1080p */ |
| 564 | qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 |
| 565 | 07 04 03 04 00]; |
| 566 | qcom,display-topology = <1 1 1>; |
| 567 | qcom,default-topology-index = <0>; |
| 568 | }; |
| 569 | timing@1 { /* qhd */ |
| 570 | qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 |
| 571 | 05 03 03 04 00]; |
| 572 | qcom,display-topology = <1 1 1>, |
| 573 | <2 2 1>, /* dsc merge */ |
| 574 | <2 1 1>; /* 3d mux */ |
| 575 | qcom,default-topology-index = <0>; |
| 576 | }; |
| 577 | }; |
| 578 | }; |
| 579 | |
| 580 | &dsi_dual_sim_dsc_375_cmd { |
| 581 | qcom,mdss-dsi-t-clk-post = <0x0d>; |
| 582 | qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| 583 | qcom,mdss-dsi-display-timings { |
| 584 | timing@0 { /* qhd */ |
| 585 | qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 586 | 07 05 03 04 00]; |
| 587 | qcom,display-topology = <2 2 2>; |
| 588 | qcom,default-topology-index = <0>; |
| 589 | }; |
| 590 | timing@1 { /* 4k */ |
| 591 | qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 |
| 592 | 06 04 03 04 00]; |
| 593 | qcom,display-topology = <2 2 2>; |
| 594 | qcom,default-topology-index = <0>; |
| 595 | }; |
| 596 | }; |
| 597 | }; |