blob: d17d8f245c1aead596e19a2335e6db480129b694 [file] [log] [blame]
Dave Airlie22f579c2005-06-28 22:48:56 +10001/* via_dma.c -- DMA support for the VIA Unichrome/Pro
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002 *
Dave Airlie22f579c2005-06-28 22:48:56 +10003 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
7 * All Rights Reserved.
Dave Airlieb5e89ed2005-09-25 14:28:13 +10008 *
Dave Airlie22f579c2005-06-28 22:48:56 +10009 * Copyright 2004 The Unichrome project.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sub license,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the
20 * next paragraph) shall be included in all copies or substantial portions
21 * of the Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
Dave Airlieb5e89ed2005-09-25 14:28:13 +100026 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
27 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
28 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
Dave Airlie22f579c2005-06-28 22:48:56 +100029 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 *
Dave Airlieb5e89ed2005-09-25 14:28:13 +100031 * Authors:
32 * Tungsten Graphics,
33 * Erdi Chen,
Dave Airlie22f579c2005-06-28 22:48:56 +100034 * Thomas Hellstrom.
35 */
36
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/drmP.h>
38#include <drm/via_drm.h>
Dave Airlie22f579c2005-06-28 22:48:56 +100039#include "via_drv.h"
40#include "via_3d_reg.h"
41
42#define CMDBUF_ALIGNMENT_SIZE (0x100)
43#define CMDBUF_ALIGNMENT_MASK (0x0ff)
44
45/* defines for VIA 3D registers */
46#define VIA_REG_STATUS 0x400
47#define VIA_REG_TRANSET 0x43C
48#define VIA_REG_TRANSPACE 0x440
49
50/* VIA_REG_STATUS(0x400): Engine Status */
51#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */
52#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */
53#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */
54#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */
55
56#define SetReg2DAGP(nReg, nData) { \
57 *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \
58 *((uint32_t *)(vb) + 1) = (nData); \
59 vb = ((uint32_t *)vb) + 2; \
Nicolas Kaiser58c1e852010-07-11 15:32:42 +020060 dev_priv->dma_low += 8; \
Dave Airlie22f579c2005-06-28 22:48:56 +100061}
62
Daniel Vetter85b23312013-12-11 11:34:45 +010063#define via_flush_write_combine() mb()
Dave Airlie22f579c2005-06-28 22:48:56 +100064
Nicolas Kaiser58c1e852010-07-11 15:32:42 +020065#define VIA_OUT_RING_QW(w1, w2) do { \
Dave Airlie22f579c2005-06-28 22:48:56 +100066 *vb++ = (w1); \
67 *vb++ = (w2); \
Nicolas Kaiser58c1e852010-07-11 15:32:42 +020068 dev_priv->dma_low += 8; \
69} while (0)
Dave Airlie22f579c2005-06-28 22:48:56 +100070
Nicolas Kaiser58c1e852010-07-11 15:32:42 +020071static void via_cmdbuf_start(drm_via_private_t *dev_priv);
72static void via_cmdbuf_pause(drm_via_private_t *dev_priv);
73static void via_cmdbuf_reset(drm_via_private_t *dev_priv);
74static void via_cmdbuf_rewind(drm_via_private_t *dev_priv);
75static int via_wait_idle(drm_via_private_t *dev_priv);
76static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);
Dave Airlie22f579c2005-06-28 22:48:56 +100077
78/*
79 * Free space in command buffer.
80 */
81
Nicolas Kaiser58c1e852010-07-11 15:32:42 +020082static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +100083{
Dave Airlieb5e89ed2005-09-25 14:28:13 +100084 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
Dave Airlie22f579c2005-06-28 22:48:56 +100085 uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
Dave Airlieb5e89ed2005-09-25 14:28:13 +100086
87 return ((hw_addr <= dev_priv->dma_low) ?
88 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
Dave Airlie22f579c2005-06-28 22:48:56 +100089 (hw_addr - dev_priv->dma_low));
90}
91
92/*
93 * How much does the command regulator lag behind?
94 */
95
Nicolas Kaiser58c1e852010-07-11 15:32:42 +020096static uint32_t via_cmdbuf_lag(drm_via_private_t *dev_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +100097{
Dave Airlieb5e89ed2005-09-25 14:28:13 +100098 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
Dave Airlie22f579c2005-06-28 22:48:56 +100099 uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000100
101 return ((hw_addr <= dev_priv->dma_low) ?
102 (dev_priv->dma_low - hw_addr) :
Dave Airlie22f579c2005-06-28 22:48:56 +1000103 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
104}
105
106/*
107 * Check that the given size fits in the buffer, otherwise wait.
108 */
109
110static inline int
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200111via_cmdbuf_wait(drm_via_private_t *dev_priv, unsigned int size)
Dave Airlie22f579c2005-06-28 22:48:56 +1000112{
113 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
114 uint32_t cur_addr, hw_addr, next_addr;
115 volatile uint32_t *hw_addr_ptr;
116 uint32_t count;
117 hw_addr_ptr = dev_priv->hw_addr_ptr;
118 cur_addr = dev_priv->dma_low;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000119 next_addr = cur_addr + size + 512 * 1024;
Dave Airlie22f579c2005-06-28 22:48:56 +1000120 count = 1000000;
121 do {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000122 hw_addr = *hw_addr_ptr - agp_base;
Dave Airlie22f579c2005-06-28 22:48:56 +1000123 if (count-- == 0) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000124 DRM_ERROR
125 ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
126 hw_addr, cur_addr, next_addr);
Dave Airlie22f579c2005-06-28 22:48:56 +1000127 return -1;
128 }
Thomas Hellstromf0fb6d772008-03-17 10:07:20 +1000129 if ((cur_addr < hw_addr) && (next_addr >= hw_addr))
130 msleep(1);
Dave Airlie22f579c2005-06-28 22:48:56 +1000131 } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
132 return 0;
133}
134
Dave Airlie22f579c2005-06-28 22:48:56 +1000135/*
136 * Checks whether buffer head has reach the end. Rewind the ring buffer
137 * when necessary.
138 *
139 * Returns virtual pointer to ring buffer.
140 */
141
142static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
143 unsigned int size)
144{
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000145 if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >
146 dev_priv->dma_high) {
Dave Airlie22f579c2005-06-28 22:48:56 +1000147 via_cmdbuf_rewind(dev_priv);
148 }
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200149 if (via_cmdbuf_wait(dev_priv, size) != 0)
Dave Airlie22f579c2005-06-28 22:48:56 +1000150 return NULL;
Dave Airlie22f579c2005-06-28 22:48:56 +1000151
152 return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
153}
154
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200155int via_dma_cleanup(struct drm_device *dev)
Dave Airlie22f579c2005-06-28 22:48:56 +1000156{
157 if (dev->dev_private) {
158 drm_via_private_t *dev_priv =
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000159 (drm_via_private_t *) dev->dev_private;
Dave Airlie22f579c2005-06-28 22:48:56 +1000160
161 if (dev_priv->ring.virtual_start) {
162 via_cmdbuf_reset(dev_priv);
163
Daniel Vetter86c1fbd2014-09-10 12:43:56 +0200164 drm_legacy_ioremapfree(&dev_priv->ring.map, dev);
Dave Airlie22f579c2005-06-28 22:48:56 +1000165 dev_priv->ring.virtual_start = NULL;
166 }
167
168 }
169
170 return 0;
171}
172
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200173static int via_initialize(struct drm_device *dev,
174 drm_via_private_t *dev_priv,
175 drm_via_dma_init_t *init)
Dave Airlie22f579c2005-06-28 22:48:56 +1000176{
177 if (!dev_priv || !dev_priv->mmio) {
178 DRM_ERROR("via_dma_init called before via_map_init\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000179 return -EFAULT;
Dave Airlie22f579c2005-06-28 22:48:56 +1000180 }
181
182 if (dev_priv->ring.virtual_start != NULL) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000183 DRM_ERROR("called again without calling cleanup\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000184 return -EFAULT;
Dave Airlie22f579c2005-06-28 22:48:56 +1000185 }
186
187 if (!dev->agp || !dev->agp->base) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000188 DRM_ERROR("called with no agp memory available\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000189 return -EFAULT;
Dave Airlie22f579c2005-06-28 22:48:56 +1000190 }
191
Thomas Hellstrom756db732007-02-08 12:57:40 +1100192 if (dev_priv->chipset == VIA_DX9_0) {
193 DRM_ERROR("AGP DMA is not supported on this chip\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000194 return -EINVAL;
Thomas Hellstrom756db732007-02-08 12:57:40 +1100195 }
196
Dave Airlie22f579c2005-06-28 22:48:56 +1000197 dev_priv->ring.map.offset = dev->agp->base + init->offset;
198 dev_priv->ring.map.size = init->size;
199 dev_priv->ring.map.type = 0;
200 dev_priv->ring.map.flags = 0;
201 dev_priv->ring.map.mtrr = 0;
202
Daniel Vetter86c1fbd2014-09-10 12:43:56 +0200203 drm_legacy_ioremap(&dev_priv->ring.map, dev);
Dave Airlie22f579c2005-06-28 22:48:56 +1000204
205 if (dev_priv->ring.map.handle == NULL) {
206 via_dma_cleanup(dev);
207 DRM_ERROR("can not ioremap virtual address for"
208 " ring buffer\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000209 return -ENOMEM;
Dave Airlie22f579c2005-06-28 22:48:56 +1000210 }
211
212 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
213
214 dev_priv->dma_ptr = dev_priv->ring.virtual_start;
215 dev_priv->dma_low = 0;
216 dev_priv->dma_high = init->size;
217 dev_priv->dma_wrap = init->size;
218 dev_priv->dma_offset = init->offset;
219 dev_priv->last_pause_ptr = NULL;
Dave Airlie92514242005-11-12 21:52:46 +1100220 dev_priv->hw_addr_ptr =
221 (volatile uint32_t *)((char *)dev_priv->mmio->handle +
222 init->reg_pause_addr);
Dave Airlie22f579c2005-06-28 22:48:56 +1000223
224 via_cmdbuf_start(dev_priv);
225
226 return 0;
227}
228
Eric Anholtc153f452007-09-03 12:06:45 +1000229static int via_dma_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +1000230{
Dave Airlie22f579c2005-06-28 22:48:56 +1000231 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +1000232 drm_via_dma_init_t *init = data;
Dave Airlie22f579c2005-06-28 22:48:56 +1000233 int retcode = 0;
234
Eric Anholtc153f452007-09-03 12:06:45 +1000235 switch (init->func) {
Dave Airlie22f579c2005-06-28 22:48:56 +1000236 case VIA_INIT_DMA:
Daniel Vetter4cda8782013-12-11 11:34:46 +0100237 if (!capable(CAP_SYS_ADMIN))
Eric Anholt20caafa2007-08-25 19:22:43 +1000238 retcode = -EPERM;
Dave Airlie22f579c2005-06-28 22:48:56 +1000239 else
Eric Anholtc153f452007-09-03 12:06:45 +1000240 retcode = via_initialize(dev, dev_priv, init);
Dave Airlie22f579c2005-06-28 22:48:56 +1000241 break;
242 case VIA_CLEANUP_DMA:
Daniel Vetter4cda8782013-12-11 11:34:46 +0100243 if (!capable(CAP_SYS_ADMIN))
Eric Anholt20caafa2007-08-25 19:22:43 +1000244 retcode = -EPERM;
Dave Airlie22f579c2005-06-28 22:48:56 +1000245 else
246 retcode = via_dma_cleanup(dev);
247 break;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000248 case VIA_DMA_INITIALIZED:
249 retcode = (dev_priv->ring.virtual_start != NULL) ?
Eric Anholt20caafa2007-08-25 19:22:43 +1000250 0 : -EFAULT;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000251 break;
Dave Airlie22f579c2005-06-28 22:48:56 +1000252 default:
Eric Anholt20caafa2007-08-25 19:22:43 +1000253 retcode = -EINVAL;
Dave Airlie22f579c2005-06-28 22:48:56 +1000254 break;
255 }
256
257 return retcode;
258}
259
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200260static int via_dispatch_cmdbuffer(struct drm_device *dev, drm_via_cmdbuffer_t *cmd)
Dave Airlie22f579c2005-06-28 22:48:56 +1000261{
262 drm_via_private_t *dev_priv;
263 uint32_t *vb;
264 int ret;
265
266 dev_priv = (drm_via_private_t *) dev->dev_private;
267
268 if (dev_priv->ring.virtual_start == NULL) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000269 DRM_ERROR("called without initializing AGP ring buffer.\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000270 return -EFAULT;
Dave Airlie22f579c2005-06-28 22:48:56 +1000271 }
272
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200273 if (cmd->size > VIA_PCI_BUF_SIZE)
Eric Anholt20caafa2007-08-25 19:22:43 +1000274 return -ENOMEM;
Dave Airlie22f579c2005-06-28 22:48:56 +1000275
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100276 if (copy_from_user(dev_priv->pci_buf, cmd->buf, cmd->size))
Eric Anholt20caafa2007-08-25 19:22:43 +1000277 return -EFAULT;
Dave Airlie22f579c2005-06-28 22:48:56 +1000278
279 /*
280 * Running this function on AGP memory is dead slow. Therefore
281 * we run it on a temporary cacheable system memory buffer and
282 * copy it to AGP memory when ready.
283 */
284
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000285 if ((ret =
286 via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
287 cmd->size, dev, 1))) {
Dave Airlie22f579c2005-06-28 22:48:56 +1000288 return ret;
289 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000290
Dave Airlie22f579c2005-06-28 22:48:56 +1000291 vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200292 if (vb == NULL)
Eric Anholt20caafa2007-08-25 19:22:43 +1000293 return -EAGAIN;
Dave Airlie22f579c2005-06-28 22:48:56 +1000294
295 memcpy(vb, dev_priv->pci_buf, cmd->size);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000296
Dave Airlie22f579c2005-06-28 22:48:56 +1000297 dev_priv->dma_low += cmd->size;
298
299 /*
300 * Small submissions somehow stalls the CPU. (AGP cache effects?)
301 * pad to greater size.
302 */
303
304 if (cmd->size < 0x100)
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000305 via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);
Dave Airlie22f579c2005-06-28 22:48:56 +1000306 via_cmdbuf_pause(dev_priv);
307
308 return 0;
309}
310
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200311int via_driver_dma_quiescent(struct drm_device *dev)
Dave Airlie22f579c2005-06-28 22:48:56 +1000312{
313 drm_via_private_t *dev_priv = dev->dev_private;
314
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200315 if (!via_wait_idle(dev_priv))
Eric Anholt20caafa2007-08-25 19:22:43 +1000316 return -EBUSY;
Dave Airlie22f579c2005-06-28 22:48:56 +1000317 return 0;
318}
319
Eric Anholtc153f452007-09-03 12:06:45 +1000320static int via_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +1000321{
Dave Airlie22f579c2005-06-28 22:48:56 +1000322
Eric Anholt6c340ea2007-08-25 20:23:09 +1000323 LOCK_TEST_WITH_RETURN(dev, file_priv);
Dave Airlie22f579c2005-06-28 22:48:56 +1000324
325 return via_driver_dma_quiescent(dev);
326}
327
Eric Anholtc153f452007-09-03 12:06:45 +1000328static int via_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +1000329{
Eric Anholtc153f452007-09-03 12:06:45 +1000330 drm_via_cmdbuffer_t *cmdbuf = data;
Dave Airlie22f579c2005-06-28 22:48:56 +1000331 int ret;
332
Eric Anholt6c340ea2007-08-25 20:23:09 +1000333 LOCK_TEST_WITH_RETURN(dev, file_priv);
Dave Airlie22f579c2005-06-28 22:48:56 +1000334
Márton Németh3e684ea2008-01-24 15:58:57 +1000335 DRM_DEBUG("buf %p size %lu\n", cmdbuf->buf, cmdbuf->size);
Dave Airlie22f579c2005-06-28 22:48:56 +1000336
Eric Anholtc153f452007-09-03 12:06:45 +1000337 ret = via_dispatch_cmdbuffer(dev, cmdbuf);
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200338 return ret;
Dave Airlie22f579c2005-06-28 22:48:56 +1000339}
340
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200341static int via_dispatch_pci_cmdbuffer(struct drm_device *dev,
342 drm_via_cmdbuffer_t *cmd)
Dave Airlie22f579c2005-06-28 22:48:56 +1000343{
344 drm_via_private_t *dev_priv = dev->dev_private;
345 int ret;
346
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200347 if (cmd->size > VIA_PCI_BUF_SIZE)
Eric Anholt20caafa2007-08-25 19:22:43 +1000348 return -ENOMEM;
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100349 if (copy_from_user(dev_priv->pci_buf, cmd->buf, cmd->size))
Eric Anholt20caafa2007-08-25 19:22:43 +1000350 return -EFAULT;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000351
352 if ((ret =
353 via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
354 cmd->size, dev, 0))) {
Dave Airlie22f579c2005-06-28 22:48:56 +1000355 return ret;
356 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000357
358 ret =
359 via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,
360 cmd->size);
Dave Airlie22f579c2005-06-28 22:48:56 +1000361 return ret;
362}
363
Eric Anholtc153f452007-09-03 12:06:45 +1000364static int via_pci_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +1000365{
Eric Anholtc153f452007-09-03 12:06:45 +1000366 drm_via_cmdbuffer_t *cmdbuf = data;
Dave Airlie22f579c2005-06-28 22:48:56 +1000367 int ret;
368
Eric Anholt6c340ea2007-08-25 20:23:09 +1000369 LOCK_TEST_WITH_RETURN(dev, file_priv);
Dave Airlie22f579c2005-06-28 22:48:56 +1000370
Márton Németh3e684ea2008-01-24 15:58:57 +1000371 DRM_DEBUG("buf %p size %lu\n", cmdbuf->buf, cmdbuf->size);
Dave Airlie22f579c2005-06-28 22:48:56 +1000372
Eric Anholtc153f452007-09-03 12:06:45 +1000373 ret = via_dispatch_pci_cmdbuffer(dev, cmdbuf);
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200374 return ret;
Dave Airlie22f579c2005-06-28 22:48:56 +1000375}
376
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200377static inline uint32_t *via_align_buffer(drm_via_private_t *dev_priv,
Dave Airlie22f579c2005-06-28 22:48:56 +1000378 uint32_t * vb, int qw_count)
379{
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200380 for (; qw_count > 0; --qw_count)
Dave Airlie22f579c2005-06-28 22:48:56 +1000381 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);
Dave Airlie22f579c2005-06-28 22:48:56 +1000382 return vb;
383}
384
Dave Airlie22f579c2005-06-28 22:48:56 +1000385/*
Joe Perches8dfba4d2008-02-03 17:11:42 +0200386 * This function is used internally by ring buffer management code.
Dave Airlie22f579c2005-06-28 22:48:56 +1000387 *
388 * Returns virtual pointer to ring buffer.
389 */
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200390static inline uint32_t *via_get_dma(drm_via_private_t *dev_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +1000391{
392 return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
393}
394
395/*
396 * Hooks a segment of data into the tail of the ring-buffer by
397 * modifying the pause address stored in the buffer itself. If
398 * the regulator has already paused, restart it.
399 */
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200400static int via_hook_segment(drm_via_private_t *dev_priv,
Dave Airlie22f579c2005-06-28 22:48:56 +1000401 uint32_t pause_addr_hi, uint32_t pause_addr_lo,
402 int no_pci_fire)
403{
404 int paused, count;
405 volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200406 uint32_t reader, ptr;
Thomas Hellstromf0fb6d772008-03-17 10:07:20 +1000407 uint32_t diff;
Dave Airlie22f579c2005-06-28 22:48:56 +1000408
409 paused = 0;
Thomas Hellstroma0a6dd02007-05-08 15:47:41 +1000410 via_flush_write_combine();
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200411 (void) *(volatile uint32_t *)(via_get_dma(dev_priv) - 1);
Thomas Hellstromf0fb6d772008-03-17 10:07:20 +1000412
Thomas Hellstromef68d292007-05-08 15:48:39 +1000413 *paused_at = pause_addr_lo;
Thomas Hellstroma0a6dd02007-05-08 15:47:41 +1000414 via_flush_write_combine();
Thomas Hellstromef68d292007-05-08 15:48:39 +1000415 (void) *paused_at;
Thomas Hellstromf0fb6d772008-03-17 10:07:20 +1000416
Thomas Hellstroma0a6dd02007-05-08 15:47:41 +1000417 reader = *(dev_priv->hw_addr_ptr);
418 ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
419 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
Thomas Hellstromf0fb6d772008-03-17 10:07:20 +1000420
Thomas Hellstroma0a6dd02007-05-08 15:47:41 +1000421 dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
Dave Airlie22f579c2005-06-28 22:48:56 +1000422
Thomas Hellstromf0fb6d772008-03-17 10:07:20 +1000423 /*
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200424 * If there is a possibility that the command reader will
Thomas Hellstromf0fb6d772008-03-17 10:07:20 +1000425 * miss the new pause address and pause on the old one,
426 * In that case we need to program the new start address
427 * using PCI.
428 */
429
430 diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;
431 count = 10000000;
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200432 while (diff == 0 && count--) {
Thomas Hellstromf0fb6d772008-03-17 10:07:20 +1000433 paused = (VIA_READ(0x41c) & 0x80000000);
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200434 if (paused)
Thomas Hellstromf0fb6d772008-03-17 10:07:20 +1000435 break;
436 reader = *(dev_priv->hw_addr_ptr);
437 diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;
Dave Airlie22f579c2005-06-28 22:48:56 +1000438 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000439
Thomas Hellstromf0fb6d772008-03-17 10:07:20 +1000440 paused = VIA_READ(0x41c) & 0x80000000;
441
Dave Airlie22f579c2005-06-28 22:48:56 +1000442 if (paused && !no_pci_fire) {
Thomas Hellstroma0a6dd02007-05-08 15:47:41 +1000443 reader = *(dev_priv->hw_addr_ptr);
Thomas Hellstromf0fb6d772008-03-17 10:07:20 +1000444 diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;
445 diff &= (dev_priv->dma_high - 1);
446 if (diff != 0 && diff < (dev_priv->dma_high >> 1)) {
447 DRM_ERROR("Paused at incorrect address. "
448 "0x%08x, 0x%08x 0x%08x\n",
449 ptr, reader, dev_priv->dma_diff);
450 } else if (diff == 0) {
Thomas Hellstroma0a6dd02007-05-08 15:47:41 +1000451 /*
452 * There is a concern that these writes may stall the PCI bus
453 * if the GPU is not idle. However, idling the GPU first
454 * doesn't make a difference.
455 */
Dave Airlie22f579c2005-06-28 22:48:56 +1000456
Dave Airlie22f579c2005-06-28 22:48:56 +1000457 VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
458 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
459 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
Thomas Hellstrom76f62552007-01-08 21:03:23 +1100460 VIA_READ(VIA_REG_TRANSPACE);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000461 }
Dave Airlie22f579c2005-06-28 22:48:56 +1000462 }
463 return paused;
464}
465
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200466static int via_wait_idle(drm_via_private_t *dev_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +1000467{
468 int count = 10000000;
Thomas Hellstroma0a6dd02007-05-08 15:47:41 +1000469
Roel Kluind9c6f542009-04-16 22:57:46 +0200470 while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && --count)
471 ;
Thomas Hellstroma0a6dd02007-05-08 15:47:41 +1000472
Roel Kluind9c6f542009-04-16 22:57:46 +0200473 while (count && (VIA_READ(VIA_REG_STATUS) &
Dave Airlie22f579c2005-06-28 22:48:56 +1000474 (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
Roel Kluind9c6f542009-04-16 22:57:46 +0200475 VIA_3D_ENG_BUSY)))
476 --count;
Dave Airlie22f579c2005-06-28 22:48:56 +1000477 return count;
478}
479
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200480static uint32_t *via_align_cmd(drm_via_private_t *dev_priv, uint32_t cmd_type,
481 uint32_t addr, uint32_t *cmd_addr_hi,
482 uint32_t *cmd_addr_lo, int skip_wait)
Dave Airlie22f579c2005-06-28 22:48:56 +1000483{
484 uint32_t agp_base;
485 uint32_t cmd_addr, addr_lo, addr_hi;
486 uint32_t *vb;
487 uint32_t qw_pad_count;
488
489 if (!skip_wait)
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000490 via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
Dave Airlie22f579c2005-06-28 22:48:56 +1000491
492 vb = via_get_dma(dev_priv);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000493 VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
494 (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
Dave Airlie22f579c2005-06-28 22:48:56 +1000495 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
496 qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000497 ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
Dave Airlie22f579c2005-06-28 22:48:56 +1000498
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000499 cmd_addr = (addr) ? addr :
500 agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
Dave Airlie22f579c2005-06-28 22:48:56 +1000501 addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
502 (cmd_addr & HC_HAGPBpL_MASK));
503 addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));
504
505 vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000506 VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);
Dave Airlie22f579c2005-06-28 22:48:56 +1000507 return vb;
508}
509
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200510static void via_cmdbuf_start(drm_via_private_t *dev_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +1000511{
512 uint32_t pause_addr_lo, pause_addr_hi;
513 uint32_t start_addr, start_addr_lo;
514 uint32_t end_addr, end_addr_lo;
515 uint32_t command;
516 uint32_t agp_base;
Thomas Hellstroma0a6dd02007-05-08 15:47:41 +1000517 uint32_t ptr;
518 uint32_t reader;
519 int count;
Dave Airlie22f579c2005-06-28 22:48:56 +1000520
Dave Airlie22f579c2005-06-28 22:48:56 +1000521 dev_priv->dma_low = 0;
522
523 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
524 start_addr = agp_base;
525 end_addr = agp_base + dev_priv->dma_high;
526
527 start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
528 end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
529 command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
530 ((end_addr & 0xff000000) >> 16));
531
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000532 dev_priv->last_pause_ptr =
533 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
534 &pause_addr_hi, &pause_addr_lo, 1) - 1;
Dave Airlie22f579c2005-06-28 22:48:56 +1000535
536 via_flush_write_combine();
Thomas Hellstromef68d292007-05-08 15:48:39 +1000537 (void) *(volatile uint32_t *)dev_priv->last_pause_ptr;
Dave Airlie22f579c2005-06-28 22:48:56 +1000538
539 VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
540 VIA_WRITE(VIA_REG_TRANSPACE, command);
541 VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
542 VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
543
544 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
545 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
Daniel Vetter85b23312013-12-11 11:34:45 +0100546 wmb();
Dave Airlie22f579c2005-06-28 22:48:56 +1000547 VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
Thomas Hellstrom76f62552007-01-08 21:03:23 +1100548 VIA_READ(VIA_REG_TRANSPACE);
Thomas Hellstroma0a6dd02007-05-08 15:47:41 +1000549
550 dev_priv->dma_diff = 0;
551
552 count = 10000000;
553 while (!(VIA_READ(0x41c) & 0x80000000) && count--);
554
555 reader = *(dev_priv->hw_addr_ptr);
556 ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
557 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
558
559 /*
560 * This is the difference between where we tell the
561 * command reader to pause and where it actually pauses.
562 * This differs between hw implementation so we need to
563 * detect it.
564 */
565
566 dev_priv->dma_diff = ptr - reader;
Dave Airlie22f579c2005-06-28 22:48:56 +1000567}
568
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200569static void via_pad_cache(drm_via_private_t *dev_priv, int qwords)
Dave Airlie22f579c2005-06-28 22:48:56 +1000570{
571 uint32_t *vb;
572
573 via_cmdbuf_wait(dev_priv, qwords + 2);
574 vb = via_get_dma(dev_priv);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000575 VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16);
576 via_align_buffer(dev_priv, vb, qwords);
Dave Airlie22f579c2005-06-28 22:48:56 +1000577}
578
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200579static inline void via_dummy_bitblt(drm_via_private_t *dev_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +1000580{
581 uint32_t *vb = via_get_dma(dev_priv);
582 SetReg2DAGP(0x0C, (0 | (0 << 16)));
583 SetReg2DAGP(0x10, 0 | (0 << 16));
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000584 SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
Dave Airlie22f579c2005-06-28 22:48:56 +1000585}
586
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200587static void via_cmdbuf_jump(drm_via_private_t *dev_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +1000588{
589 uint32_t agp_base;
590 uint32_t pause_addr_lo, pause_addr_hi;
591 uint32_t jump_addr_lo, jump_addr_hi;
592 volatile uint32_t *last_pause_ptr;
Thomas Hellstromf0fb6d772008-03-17 10:07:20 +1000593 uint32_t dma_low_save1, dma_low_save2;
Dave Airlie22f579c2005-06-28 22:48:56 +1000594
595 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000596 via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
Dave Airlie22f579c2005-06-28 22:48:56 +1000597 &jump_addr_lo, 0);
Dave Airlie22f579c2005-06-28 22:48:56 +1000598
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000599 dev_priv->dma_wrap = dev_priv->dma_low;
Dave Airlie22f579c2005-06-28 22:48:56 +1000600
601 /*
602 * Wrap command buffer to the beginning.
603 */
604
605 dev_priv->dma_low = 0;
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200606 if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0)
Dave Airlie22f579c2005-06-28 22:48:56 +1000607 DRM_ERROR("via_cmdbuf_jump failed\n");
Dave Airlie22f579c2005-06-28 22:48:56 +1000608
609 via_dummy_bitblt(dev_priv);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000610 via_dummy_bitblt(dev_priv);
Dave Airlie22f579c2005-06-28 22:48:56 +1000611
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000612 last_pause_ptr =
613 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
614 &pause_addr_lo, 0) - 1;
615 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
Dave Airlie22f579c2005-06-28 22:48:56 +1000616 &pause_addr_lo, 0);
617
618 *last_pause_ptr = pause_addr_lo;
Thomas Hellstromf0fb6d772008-03-17 10:07:20 +1000619 dma_low_save1 = dev_priv->dma_low;
Dave Airlie22f579c2005-06-28 22:48:56 +1000620
Thomas Hellstromf0fb6d772008-03-17 10:07:20 +1000621 /*
622 * Now, set a trap that will pause the regulator if it tries to rerun the old
623 * command buffer. (Which may happen if via_hook_segment detecs a command regulator pause
624 * and reissues the jump command over PCI, while the regulator has already taken the jump
625 * and actually paused at the current buffer end).
626 * There appears to be no other way to detect this condition, since the hw_addr_pointer
627 * does not seem to get updated immediately when a jump occurs.
628 */
629
630 last_pause_ptr =
631 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
632 &pause_addr_lo, 0) - 1;
633 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
634 &pause_addr_lo, 0);
635 *last_pause_ptr = pause_addr_lo;
636
637 dma_low_save2 = dev_priv->dma_low;
638 dev_priv->dma_low = dma_low_save1;
639 via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0);
640 dev_priv->dma_low = dma_low_save2;
641 via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
Dave Airlie22f579c2005-06-28 22:48:56 +1000642}
643
Thomas Hellstroma0a6dd02007-05-08 15:47:41 +1000644
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200645static void via_cmdbuf_rewind(drm_via_private_t *dev_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +1000646{
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000647 via_cmdbuf_jump(dev_priv);
Dave Airlie22f579c2005-06-28 22:48:56 +1000648}
649
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200650static void via_cmdbuf_flush(drm_via_private_t *dev_priv, uint32_t cmd_type)
Dave Airlie22f579c2005-06-28 22:48:56 +1000651{
652 uint32_t pause_addr_lo, pause_addr_hi;
653
654 via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000655 via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
Dave Airlie22f579c2005-06-28 22:48:56 +1000656}
657
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200658static void via_cmdbuf_pause(drm_via_private_t *dev_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +1000659{
660 via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
661}
662
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200663static void via_cmdbuf_reset(drm_via_private_t *dev_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +1000664{
665 via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
666 via_wait_idle(dev_priv);
667}
668
669/*
670 * User interface to the space and lag functions.
671 */
672
Eric Anholtc153f452007-09-03 12:06:45 +1000673static int via_cmdbuf_size(struct drm_device *dev, void *data, struct drm_file *file_priv)
Dave Airlie22f579c2005-06-28 22:48:56 +1000674{
Eric Anholtc153f452007-09-03 12:06:45 +1000675 drm_via_cmdbuf_size_t *d_siz = data;
Dave Airlie22f579c2005-06-28 22:48:56 +1000676 int ret = 0;
677 uint32_t tmp_size, count;
678 drm_via_private_t *dev_priv;
679
Márton Németh3e684ea2008-01-24 15:58:57 +1000680 DRM_DEBUG("\n");
Eric Anholt6c340ea2007-08-25 20:23:09 +1000681 LOCK_TEST_WITH_RETURN(dev, file_priv);
Dave Airlie22f579c2005-06-28 22:48:56 +1000682
683 dev_priv = (drm_via_private_t *) dev->dev_private;
684
685 if (dev_priv->ring.virtual_start == NULL) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000686 DRM_ERROR("called without initializing AGP ring buffer.\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000687 return -EFAULT;
Dave Airlie22f579c2005-06-28 22:48:56 +1000688 }
689
Dave Airlie22f579c2005-06-28 22:48:56 +1000690 count = 1000000;
Eric Anholtc153f452007-09-03 12:06:45 +1000691 tmp_size = d_siz->size;
692 switch (d_siz->func) {
Dave Airlie22f579c2005-06-28 22:48:56 +1000693 case VIA_CMDBUF_SPACE:
Eric Anholtc153f452007-09-03 12:06:45 +1000694 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz->size)
Roel Kluind9c6f542009-04-16 22:57:46 +0200695 && --count) {
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200696 if (!d_siz->wait)
Dave Airlie22f579c2005-06-28 22:48:56 +1000697 break;
Dave Airlie22f579c2005-06-28 22:48:56 +1000698 }
699 if (!count) {
700 DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000701 ret = -EAGAIN;
Dave Airlie22f579c2005-06-28 22:48:56 +1000702 }
703 break;
704 case VIA_CMDBUF_LAG:
Eric Anholtc153f452007-09-03 12:06:45 +1000705 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz->size)
Roel Kluind9c6f542009-04-16 22:57:46 +0200706 && --count) {
Nicolas Kaiser58c1e852010-07-11 15:32:42 +0200707 if (!d_siz->wait)
Dave Airlie22f579c2005-06-28 22:48:56 +1000708 break;
Dave Airlie22f579c2005-06-28 22:48:56 +1000709 }
710 if (!count) {
711 DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000712 ret = -EAGAIN;
Dave Airlie22f579c2005-06-28 22:48:56 +1000713 }
714 break;
715 default:
Eric Anholt20caafa2007-08-25 19:22:43 +1000716 ret = -EFAULT;
Dave Airlie22f579c2005-06-28 22:48:56 +1000717 }
Eric Anholtc153f452007-09-03 12:06:45 +1000718 d_siz->size = tmp_size;
Dave Airlie22f579c2005-06-28 22:48:56 +1000719
Dave Airlie22f579c2005-06-28 22:48:56 +1000720 return ret;
721}
Dave Airlie92514242005-11-12 21:52:46 +1100722
Rob Clarkbaa70942013-08-02 13:27:49 -0400723const struct drm_ioctl_desc via_ioctls[] = {
Dave Airlie1b2f1482010-08-14 20:20:34 +1000724 DRM_IOCTL_DEF_DRV(VIA_ALLOCMEM, via_mem_alloc, DRM_AUTH),
725 DRM_IOCTL_DEF_DRV(VIA_FREEMEM, via_mem_free, DRM_AUTH),
726 DRM_IOCTL_DEF_DRV(VIA_AGP_INIT, via_agp_init, DRM_AUTH|DRM_MASTER),
727 DRM_IOCTL_DEF_DRV(VIA_FB_INIT, via_fb_init, DRM_AUTH|DRM_MASTER),
728 DRM_IOCTL_DEF_DRV(VIA_MAP_INIT, via_map_init, DRM_AUTH|DRM_MASTER),
729 DRM_IOCTL_DEF_DRV(VIA_DEC_FUTEX, via_decoder_futex, DRM_AUTH),
730 DRM_IOCTL_DEF_DRV(VIA_DMA_INIT, via_dma_init, DRM_AUTH),
731 DRM_IOCTL_DEF_DRV(VIA_CMDBUFFER, via_cmdbuffer, DRM_AUTH),
732 DRM_IOCTL_DEF_DRV(VIA_FLUSH, via_flush_ioctl, DRM_AUTH),
733 DRM_IOCTL_DEF_DRV(VIA_PCICMD, via_pci_cmdbuffer, DRM_AUTH),
734 DRM_IOCTL_DEF_DRV(VIA_CMDBUF_SIZE, via_cmdbuf_size, DRM_AUTH),
735 DRM_IOCTL_DEF_DRV(VIA_WAIT_IRQ, via_wait_irq, DRM_AUTH),
736 DRM_IOCTL_DEF_DRV(VIA_DMA_BLIT, via_dma_blit, DRM_AUTH),
737 DRM_IOCTL_DEF_DRV(VIA_BLIT_SYNC, via_dma_blit_sync, DRM_AUTH)
Dave Airlie92514242005-11-12 21:52:46 +1100738};
739
Damien Lespiauf95aeb12014-06-09 14:39:49 +0100740int via_max_ioctl = ARRAY_SIZE(via_ioctls);