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gerrit-public.fairphone.software / kernel / msm-4.9 / a7d19057e7160a566bad9b2ba070a391fb78df96 / . / drivers / clk / samsung / clk-exynos3250.c
blob: 6e6cca3920829b5a7dc0685a071389a2d201d780 [file] [log] [blame]
Tomasz Figa2ce16c52014-05-13 22:05:06 +0900[diff] [blame]1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Common Clock Framework support for Exynos3250 SoC.
9 */
10
11#include <linux/clk.h>
12#include <linux/clkdev.h>
13#include <linux/clk-provider.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/platform_device.h>
17#include <linux/syscore_ops.h>
18
19#include <dt-bindings/clock/exynos3250.h>
20
21#include "clk.h"
22#include "clk-pll.h"
23
24#define SRC_LEFTBUS 0x4200
25#define DIV_LEFTBUS 0x4500
26#define GATE_IP_LEFTBUS 0x4800
27#define SRC_RIGHTBUS 0x8200
28#define DIV_RIGHTBUS 0x8500
29#define GATE_IP_RIGHTBUS 0x8800
30#define GATE_IP_PERIR 0x8960
31#define MPLL_LOCK 0xc010
32#define MPLL_CON0 0xc110
33#define VPLL_LOCK 0xc020
34#define VPLL_CON0 0xc120
35#define UPLL_LOCK 0xc030
36#define UPLL_CON0 0xc130
37#define SRC_TOP0 0xc210
38#define SRC_TOP1 0xc214
39#define SRC_CAM 0xc220
40#define SRC_MFC 0xc228
41#define SRC_G3D 0xc22c
42#define SRC_LCD 0xc234
43#define SRC_ISP 0xc238
44#define SRC_FSYS 0xc240
45#define SRC_PERIL0 0xc250
46#define SRC_PERIL1 0xc254
47#define SRC_MASK_TOP 0xc310
48#define SRC_MASK_CAM 0xc320
49#define SRC_MASK_LCD 0xc334
50#define SRC_MASK_ISP 0xc338
51#define SRC_MASK_FSYS 0xc340
52#define SRC_MASK_PERIL0 0xc350
53#define SRC_MASK_PERIL1 0xc354
54#define DIV_TOP 0xc510
55#define DIV_CAM 0xc520
56#define DIV_MFC 0xc528
57#define DIV_G3D 0xc52c
58#define DIV_LCD 0xc534
59#define DIV_ISP 0xc538
60#define DIV_FSYS0 0xc540
61#define DIV_FSYS1 0xc544
62#define DIV_FSYS2 0xc548
63#define DIV_PERIL0 0xc550
64#define DIV_PERIL1 0xc554
65#define DIV_PERIL3 0xc55c
66#define DIV_PERIL4 0xc560
67#define DIV_PERIL5 0xc564
68#define DIV_CAM1 0xc568
69#define CLKDIV2_RATIO 0xc580
70#define GATE_SCLK_CAM 0xc820
71#define GATE_SCLK_MFC 0xc828
72#define GATE_SCLK_G3D 0xc82c
73#define GATE_SCLK_LCD 0xc834
74#define GATE_SCLK_ISP_TOP 0xc838
75#define GATE_SCLK_FSYS 0xc840
76#define GATE_SCLK_PERIL 0xc850
77#define GATE_IP_CAM 0xc920
78#define GATE_IP_MFC 0xc928
79#define GATE_IP_G3D 0xc92c
80#define GATE_IP_LCD 0xc934
81#define GATE_IP_ISP 0xc938
82#define GATE_IP_FSYS 0xc940
83#define GATE_IP_PERIL 0xc950
84#define GATE_BLOCK 0xc970
85#define APLL_LOCK 0x14000
86#define APLL_CON0 0x14100
87#define SRC_CPU 0x14200
88#define DIV_CPU0 0x14500
89#define DIV_CPU1 0x14504
Krzysztof Kozlowski45c5b0a2014-07-18 16:36:33 +0200[diff] [blame]90#define PWR_CTRL1 0x15020
91#define PWR_CTRL2 0x15024
92
93/* Below definitions are used for PWR_CTRL settings */
94#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
95#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
96#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
97#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
98#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
99#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
100#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
101#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
102#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
103#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
104#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
105#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
Tomasz Figa2ce16c52014-05-13 22:05:06 +0900[diff] [blame]106
107/* list of PLLs to be registered */
108enum exynos3250_plls {
109 apll, mpll, vpll, upll,
110 nr_plls
111};
112
Krzysztof Kozlowskie3c3f192014-09-02 15:21:15 +0200[diff] [blame]113/* list of PLLs in DMC block to be registered */
114enum exynos3250_dmc_plls {
115 bpll, epll,
116 nr_dmc_plls
117};
118
Tomasz Figa2ce16c52014-05-13 22:05:06 +0900[diff] [blame]119static void __iomem *reg_base;
Krzysztof Kozlowskie3c3f192014-09-02 15:21:15 +0200[diff] [blame]120static void __iomem *dmc_reg_base;
Tomasz Figa2ce16c52014-05-13 22:05:06 +0900[diff] [blame]121
122/*
123 * Support for CMU save/restore across system suspends
124 */
125#ifdef CONFIG_PM_SLEEP
126static struct samsung_clk_reg_dump *exynos3250_clk_regs;
127
128static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
129 SRC_LEFTBUS,
130 DIV_LEFTBUS,
131 GATE_IP_LEFTBUS,
132 SRC_RIGHTBUS,
133 DIV_RIGHTBUS,
134 GATE_IP_RIGHTBUS,
135 GATE_IP_PERIR,
136 MPLL_LOCK,
137 MPLL_CON0,
138 VPLL_LOCK,
139 VPLL_CON0,
140 UPLL_LOCK,
141 UPLL_CON0,
142 SRC_TOP0,
143 SRC_TOP1,
144 SRC_CAM,
145 SRC_MFC,
146 SRC_G3D,
147 SRC_LCD,
148 SRC_ISP,
149 SRC_FSYS,
150 SRC_PERIL0,
151 SRC_PERIL1,
152 SRC_MASK_TOP,
153 SRC_MASK_CAM,
154 SRC_MASK_LCD,
155 SRC_MASK_ISP,
156 SRC_MASK_FSYS,
157 SRC_MASK_PERIL0,
158 SRC_MASK_PERIL1,
159 DIV_TOP,
160 DIV_CAM,
161 DIV_MFC,
162 DIV_G3D,
163 DIV_LCD,
164 DIV_ISP,
165 DIV_FSYS0,
166 DIV_FSYS1,
167 DIV_FSYS2,
168 DIV_PERIL0,
169 DIV_PERIL1,
170 DIV_PERIL3,
171 DIV_PERIL4,
172 DIV_PERIL5,
173 DIV_CAM1,
174 CLKDIV2_RATIO,
175 GATE_SCLK_CAM,
176 GATE_SCLK_MFC,
177 GATE_SCLK_G3D,
178 GATE_SCLK_LCD,
179 GATE_SCLK_ISP_TOP,
180 GATE_SCLK_FSYS,
181 GATE_SCLK_PERIL,
182 GATE_IP_CAM,
183 GATE_IP_MFC,
184 GATE_IP_G3D,
185 GATE_IP_LCD,
186 GATE_IP_ISP,
187 GATE_IP_FSYS,
188 GATE_IP_PERIL,
189 GATE_BLOCK,
190 APLL_LOCK,
191 SRC_CPU,
192 DIV_CPU0,
193 DIV_CPU1,
Krzysztof Kozlowski45c5b0a2014-07-18 16:36:33 +0200[diff] [blame]194 PWR_CTRL1,
195 PWR_CTRL2,
Tomasz Figa2ce16c52014-05-13 22:05:06 +0900[diff] [blame]196};
197
198static int exynos3250_clk_suspend(void)
199{
200 samsung_clk_save(reg_base, exynos3250_clk_regs,
201 ARRAY_SIZE(exynos3250_cmu_clk_regs));
202 return 0;
203}
204
205static void exynos3250_clk_resume(void)
206{
207 samsung_clk_restore(reg_base, exynos3250_clk_regs,
208 ARRAY_SIZE(exynos3250_cmu_clk_regs));
209}
210
211static struct syscore_ops exynos3250_clk_syscore_ops = {
212 .suspend = exynos3250_clk_suspend,
213 .resume = exynos3250_clk_resume,
214};
215
216static void exynos3250_clk_sleep_init(void)
217{
218 exynos3250_clk_regs =
219 samsung_clk_alloc_reg_dump(exynos3250_cmu_clk_regs,
220 ARRAY_SIZE(exynos3250_cmu_clk_regs));
221 if (!exynos3250_clk_regs) {
222 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
223 goto err;
224 }
225
226 register_syscore_ops(&exynos3250_clk_syscore_ops);
227 return;
228err:
229 kfree(exynos3250_clk_regs);
230}
231#else
232static inline void exynos3250_clk_sleep_init(void) { }
233#endif
234
235/* list of all parent clock list */
236PNAME(mout_vpllsrc_p) = { "fin_pll", };
237
238PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
239PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
240PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
241PNAME(mout_upll_p) = { "fin_pll", "fout_upll", };
242
243PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
244PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", };
245PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
246PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
247
248PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
249PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_vpll", };
250
251PNAME(mout_gdl_p) = { "mout_mpll_user_l", };
252PNAME(mout_gdr_p) = { "mout_mpll_user_r", };
253
254PNAME(mout_aclk_400_mcuisp_sub_p)
255 = { "fin_pll", "div_aclk_400_mcuisp", };
256PNAME(mout_aclk_266_0_p) = { "div_mpll_pre", "mout_vpll", };
257PNAME(mout_aclk_266_1_p) = { "mout_epll_user", };
258PNAME(mout_aclk_266_p) = { "mout_aclk_266_0", "mout_aclk_266_1", };
259PNAME(mout_aclk_266_sub_p) = { "fin_pll", "div_aclk_266", };
260
261PNAME(group_div_mpll_pre_p) = { "div_mpll_pre", };
262PNAME(group_epll_vpll_p) = { "mout_epll_user", "mout_vpll" };
263PNAME(group_sclk_p) = { "xxti", "xusbxti",
264 "none", "none",
265 "none", "none", "div_mpll_pre",
266 "mout_epll_user", "mout_vpll", };
267PNAME(group_sclk_audio_p) = { "audiocdclk", "none",
268 "none", "none",
269 "xxti", "xusbxti",
270 "div_mpll_pre", "mout_epll_user",
271 "mout_vpll", };
272PNAME(group_sclk_cam_blk_p) = { "xxti", "xusbxti",
273 "none", "none", "none",
274 "none", "div_mpll_pre",
275 "mout_epll_user", "mout_vpll",
Pankaj Dubey5ce37f22014-09-06 18:33:33 +0530[diff] [blame]276 "none", "none", "none",
Tomasz Figa2ce16c52014-05-13 22:05:06 +0900[diff] [blame]277 "div_cam_blk_320", };
278PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti",
279 "m_bitclkhsdiv4_2l", "none",
280 "none", "none", "div_mpll_pre",
281 "mout_epll_user", "mout_vpll",
282 "none", "none", "none",
283 "div_lcd_blk_145", };
284
285PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" };
286PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" };
287
288static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = {
289 FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
290 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
291 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
292 FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
293 FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
294
295 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
296 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
297};
298
299static struct samsung_mux_clock mux_clks[] __initdata = {
300 /*
301 * NOTE: Following table is sorted by register address in ascending
302 * order and then bitfield shift in descending order, as it is done
303 * in the User's Manual. When adding new entries, please make sure
304 * that the order is preserved, to avoid merge conflicts and make
305 * further work with defined data easier.
306 */
307
308 /* SRC_LEFTBUS */
309 MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
310 SRC_LEFTBUS, 4, 1),
311 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
312
313 /* SRC_RIGHTBUS */
314 MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
315 SRC_RIGHTBUS, 4, 1),
316 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
317
318 /* SRC_TOP0 */
319 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
320 MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
321 MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
322 MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
323 MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
324 MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
325 MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
326 MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
327 MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
328 MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
329
330 /* SRC_TOP1 */
331 MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
332 MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,
333 SRC_TOP1, 24, 1),
334 MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
335 MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
336 MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
337 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
338
339 /* SRC_CAM */
340 MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
341 MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
342
343 /* SRC_MFC */
344 MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
345 MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
346 MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
347
348 /* SRC_G3D */
349 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
350 MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
351 MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
352
353 /* SRC_LCD */
354 MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
355 MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
356
357 /* SRC_ISP */
358 MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),
359 MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
360 MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),
361
362 /* SRC_FSYS */
363 MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
Pankaj Dubeye82ba572014-09-05 17:24:41 +0530[diff] [blame]364 MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
365 MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
Tomasz Figa2ce16c52014-05-13 22:05:06 +0900[diff] [blame]366
367 /* SRC_PERIL0 */
368 MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
369 MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
370
371 /* SRC_PERIL1 */
372 MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
373 MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
374 MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),
375
376 /* SRC_CPU */
377 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
378 SRC_CPU, 24, 1),
379 MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
380 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1),
381 MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
382};
383
384static struct samsung_div_clock div_clks[] __initdata = {
385 /*
386 * NOTE: Following table is sorted by register address in ascending
387 * order and then bitfield shift in descending order, as it is done
388 * in the User's Manual. When adding new entries, please make sure
389 * that the order is preserved, to avoid merge conflicts and make
390 * further work with defined data easier.
391 */
392
393 /* DIV_LEFTBUS */
394 DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
395 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
396
397 /* DIV_RIGHTBUS */
398 DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
399 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
400
401 /* DIV_TOP */
402 DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
403 DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
404 "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
405 DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
406 DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
407 DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
408 DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
409 DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
410
411 /* DIV_CAM */
412 DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
413 DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),
414
415 /* DIV_MFC */
416 DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
417
418 /* DIV_G3D */
419 DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
420
421 /* DIV_LCD */
422 DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
423 CLK_SET_RATE_PARENT, 0),
424 DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
425 DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
426
427 /* DIV_ISP */
428 DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
429 DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
430 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
431 DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
432 DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
433 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
Pankaj Dubey59037b92014-09-09 17:24:57 +0530[diff] [blame]434 DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
Tomasz Figa2ce16c52014-05-13 22:05:06 +0900[diff] [blame]435
436 /* DIV_FSYS0 */
437 DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
438 CLK_SET_RATE_PARENT, 0),
439 DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
440
441 /* DIV_FSYS1 */
442 DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
443 CLK_SET_RATE_PARENT, 0),
444 DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
445 DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
446 CLK_SET_RATE_PARENT, 0),
447 DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
448
449 /* DIV_PERIL0 */
450 DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
451 DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
452
453 /* DIV_PERIL1 */
454 DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
455 CLK_SET_RATE_PARENT, 0),
456 DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
457 DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
458 CLK_SET_RATE_PARENT, 0),
459 DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
460
461 /* DIV_PERIL4 */
462 DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),
463 DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),
464
465 /* DIV_PERIL5 */
466 DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),
467
468 /* DIV_CPU0 */
469 DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
470 DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
471 DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
472 DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
473 DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
474 DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
475
476 /* DIV_CPU1 */
477 DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
478 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
479};
480
481static struct samsung_gate_clock gate_clks[] __initdata = {
482 /*
483 * NOTE: Following table is sorted by register address in ascending
484 * order and then bitfield shift in descending order, as it is done
485 * in the User's Manual. When adding new entries, please make sure
486 * that the order is preserved, to avoid merge conflicts and make
487 * further work with defined data easier.
488 */
489
490 /* GATE_IP_LEFTBUS */
491 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
492 CLK_IGNORE_UNUSED, 0),
493 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
494 CLK_IGNORE_UNUSED, 0),
495 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
496 CLK_IGNORE_UNUSED, 0),
497 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
498 CLK_IGNORE_UNUSED, 0),
499
500 /* GATE_IP_RIGHTBUS */
501 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
502 GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
503 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
504 GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
505 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
506 GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
507 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
508 CLK_IGNORE_UNUSED, 0),
509 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
510 CLK_IGNORE_UNUSED, 0),
511 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
512 CLK_IGNORE_UNUSED, 0),
513
514 /* GATE_IP_PERIR */
515 GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
516 CLK_IGNORE_UNUSED, 0),
517 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
518 CLK_IGNORE_UNUSED, 0),
519 GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
520 GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
521 GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
522 GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
523 GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
524 CLK_IGNORE_UNUSED, 0),
525 GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
526 GATE_IP_PERIR, 17, 0, 0),
527 GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
528 GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
529 GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
530 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
531 GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
532 CLK_IGNORE_UNUSED, 0),
533 GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
534 CLK_IGNORE_UNUSED, 0),
535 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
536 CLK_IGNORE_UNUSED, 0),
537 GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
538 CLK_IGNORE_UNUSED, 0),
539 GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
540 CLK_IGNORE_UNUSED, 0),
541 GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
542 CLK_IGNORE_UNUSED, 0),
543 GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
544 CLK_IGNORE_UNUSED, 0),
545 GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
546 CLK_IGNORE_UNUSED, 0),
547 GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
548 CLK_IGNORE_UNUSED, 0),
549 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
550 CLK_IGNORE_UNUSED, 0),
551 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
552 CLK_IGNORE_UNUSED, 0),
553 GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
554 CLK_IGNORE_UNUSED, 0),
555
556 /* GATE_SCLK_CAM */
557 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
558 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
559 GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
560 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
561 GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
562 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
563 GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
564 GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
565
566 /* GATE_SCLK_MFC */
567 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
568 GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
569
570 /* GATE_SCLK_G3D */
571 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
572 GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
573
574 /* GATE_SCLK_LCD */
575 GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
576 GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
577 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
578 GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
579 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
580 GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
581
582 /* GATE_SCLK_ISP_TOP */
583 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
584 GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
585 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
586 GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
587 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
588 GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
589 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
590 GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
591
592 /* GATE_SCLK_FSYS */
593 GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
594 GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
595 GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
596 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
597 GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
598 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
599 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
600 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
601 GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
602
603 /* GATE_SCLK_PERIL */
604 GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
605 GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
606 GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
607 GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
608 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
609 GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
610 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
611 GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
612 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
613 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
614 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
615 GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
616
617 /* GATE_IP_CAM */
618 GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
619 CLK_IGNORE_UNUSED, 0),
620 GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
621 GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),
622 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
623 GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),
624 GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
625 GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),
626 GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
627 GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),
628 GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
629 GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),
630 GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
631 GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),
632 GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
633 GATE_IP_CAM, 11, 0, 0),
634 GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
635 GATE_IP_CAM, 9, 0, 0),
636 GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
637 GATE_IP_CAM, 8, 0, 0),
638 GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
639 GATE_IP_CAM, 7, 0, 0),
640 GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
641 GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
642 GATE_IP_CAM, 2, 0, 0),
643 GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
644 GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
645
646 /* GATE_IP_MFC */
647 GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
648 CLK_IGNORE_UNUSED, 0),
649 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
650 CLK_IGNORE_UNUSED, 0),
651 GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
652 GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
653
654 /* GATE_IP_G3D */
655 GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
656 GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
657 CLK_IGNORE_UNUSED, 0),
658 GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
659 CLK_IGNORE_UNUSED, 0),
660 GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
661
662 /* GATE_IP_LCD */
663 GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
664 CLK_IGNORE_UNUSED, 0),
665 GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
666 CLK_IGNORE_UNUSED, 0),
667 GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
668 CLK_IGNORE_UNUSED, 0),
669 GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
670 GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
671 GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
672 GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
673
674 /* GATE_IP_ISP */
675 GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
676 GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
677 GATE_IP_ISP, 3, 0, 0),
678 GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
679 GATE_IP_ISP, 2, 0, 0),
680 GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
681 GATE_IP_ISP, 1, 0, 0),
682
683 /* GATE_IP_FSYS */
684 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
685 GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
686 CLK_IGNORE_UNUSED, 0),
687 GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
688 GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
689 GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
690 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
691 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
692 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
693 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
694
695 /* GATE_IP_PERIL */
696 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
697 GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
698 GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
699 GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
700 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
701 GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
702 GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
703 GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
704 GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
705 GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
706 GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
707 GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
708 GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
709 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
710 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
711};
712
713/* APLL & MPLL & BPLL & UPLL */
714static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
715 PLL_35XX_RATE(1200000000, 400, 4, 1),
716 PLL_35XX_RATE(1100000000, 275, 3, 1),
717 PLL_35XX_RATE(1066000000, 533, 6, 1),
718 PLL_35XX_RATE(1000000000, 250, 3, 1),
719 PLL_35XX_RATE( 960000000, 320, 4, 1),
720 PLL_35XX_RATE( 900000000, 300, 4, 1),
721 PLL_35XX_RATE( 850000000, 425, 6, 1),
722 PLL_35XX_RATE( 800000000, 200, 3, 1),
723 PLL_35XX_RATE( 700000000, 175, 3, 1),
724 PLL_35XX_RATE( 667000000, 667, 12, 1),
725 PLL_35XX_RATE( 600000000, 400, 4, 2),
726 PLL_35XX_RATE( 533000000, 533, 6, 2),
727 PLL_35XX_RATE( 520000000, 260, 3, 2),
728 PLL_35XX_RATE( 500000000, 250, 3, 2),
729 PLL_35XX_RATE( 400000000, 200, 3, 2),
730 PLL_35XX_RATE( 200000000, 200, 3, 3),
731 PLL_35XX_RATE( 100000000, 200, 3, 4),
732 { /* sentinel */ }
733};
734
Krzysztof Kozlowskie3c3f192014-09-02 15:21:15 +0200[diff] [blame]735/* EPLL */
736static struct samsung_pll_rate_table exynos3250_epll_rates[] = {
737 PLL_36XX_RATE(800000000, 200, 3, 1, 0),
738 PLL_36XX_RATE(288000000, 96, 2, 2, 0),
739 PLL_36XX_RATE(192000000, 128, 2, 3, 0),
740 PLL_36XX_RATE(144000000, 96, 2, 3, 0),
741 PLL_36XX_RATE( 96000000, 128, 2, 4, 0),
742 PLL_36XX_RATE( 84000000, 112, 2, 4, 0),
743 PLL_36XX_RATE( 80000004, 106, 2, 4, 43691),
744 PLL_36XX_RATE( 73728000, 98, 2, 4, 19923),
745 PLL_36XX_RATE( 67737598, 270, 3, 5, 62285),
746 PLL_36XX_RATE( 65535999, 174, 2, 5, 49982),
747 PLL_36XX_RATE( 50000000, 200, 3, 5, 0),
748 PLL_36XX_RATE( 49152002, 131, 2, 5, 4719),
749 PLL_36XX_RATE( 48000000, 128, 2, 5, 0),
750 PLL_36XX_RATE( 45158401, 180, 3, 5, 41524),
751 { /* sentinel */ }
752};
753
Tomasz Figa2ce16c52014-05-13 22:05:06 +0900[diff] [blame]754/* VPLL */
755static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
756 PLL_36XX_RATE(600000000, 100, 2, 1, 0),
757 PLL_36XX_RATE(533000000, 266, 3, 2, 32768),
758 PLL_36XX_RATE(519230987, 173, 2, 2, 5046),
759 PLL_36XX_RATE(500000000, 250, 3, 2, 0),
760 PLL_36XX_RATE(445500000, 148, 2, 2, 32768),
761 PLL_36XX_RATE(445055007, 148, 2, 2, 23047),
762 PLL_36XX_RATE(400000000, 200, 3, 2, 0),
763 PLL_36XX_RATE(371250000, 123, 2, 2, 49152),
764 PLL_36XX_RATE(370878997, 185, 3, 2, 28803),
765 PLL_36XX_RATE(340000000, 170, 3, 2, 0),
766 PLL_36XX_RATE(335000015, 111, 2, 2, 43691),
767 PLL_36XX_RATE(333000000, 111, 2, 2, 0),
768 PLL_36XX_RATE(330000000, 110, 2, 2, 0),
769 PLL_36XX_RATE(320000015, 106, 2, 2, 43691),
770 PLL_36XX_RATE(300000000, 100, 2, 2, 0),
771 PLL_36XX_RATE(275000000, 275, 3, 3, 0),
772 PLL_36XX_RATE(222750000, 148, 2, 3, 32768),
773 PLL_36XX_RATE(222528007, 148, 2, 3, 23069),
774 PLL_36XX_RATE(160000000, 160, 3, 3, 0),
775 PLL_36XX_RATE(148500000, 99, 2, 3, 0),
776 PLL_36XX_RATE(148352005, 98, 2, 3, 59070),
777 PLL_36XX_RATE(108000000, 144, 2, 4, 0),
778 PLL_36XX_RATE( 74250000, 99, 2, 4, 0),
779 PLL_36XX_RATE( 74176002, 98, 3, 4, 59070),
780 PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
781 PLL_36XX_RATE( 54000000, 144, 2, 5, 0),
782 { /* sentinel */ }
783};
784
785static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = {
786 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
787 APLL_LOCK, APLL_CON0, NULL),
788 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
789 MPLL_LOCK, MPLL_CON0, NULL),
790 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
791 VPLL_LOCK, VPLL_CON0, NULL),
792 [upll] = PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
793 UPLL_LOCK, UPLL_CON0, NULL),
794};
795
Krzysztof Kozlowski45c5b0a2014-07-18 16:36:33 +0200[diff] [blame]796static void __init exynos3_core_down_clock(void)
797{
798 unsigned int tmp;
799
800 /*
801 * Enable arm clock down (in idle) and set arm divider
802 * ratios in WFI/WFE state.
803 */
804 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
805 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
806 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
807 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
808 __raw_writel(tmp, reg_base + PWR_CTRL1);
809
810 /*
811 * Disable the clock up feature on Exynos4x12, in case it was
812 * enabled by bootloader.
813 */
814 __raw_writel(0x0, reg_base + PWR_CTRL2);
815}
816
Tomasz Figa2ce16c52014-05-13 22:05:06 +0900[diff] [blame]817static void __init exynos3250_cmu_init(struct device_node *np)
818{
819 struct samsung_clk_provider *ctx;
820
821 reg_base = of_iomap(np, 0);
822 if (!reg_base)
823 panic("%s: failed to map registers\n", __func__);
824
825 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
826 if (!ctx)
827 panic("%s: unable to allocate context.\n", __func__);
828
829 samsung_clk_register_fixed_factor(ctx, fixed_factor_clks,
830 ARRAY_SIZE(fixed_factor_clks));
831
832 exynos3250_plls[apll].rate_table = exynos3250_pll_rates;
833 exynos3250_plls[mpll].rate_table = exynos3250_pll_rates;
834 exynos3250_plls[vpll].rate_table = exynos3250_vpll_rates;
835 exynos3250_plls[upll].rate_table = exynos3250_pll_rates;
836
837 samsung_clk_register_pll(ctx, exynos3250_plls,
838 ARRAY_SIZE(exynos3250_plls), reg_base);
839
840 samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
841 samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
842 samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
843
Krzysztof Kozlowski45c5b0a2014-07-18 16:36:33 +0200[diff] [blame]844 exynos3_core_down_clock();
845
Tomasz Figa2ce16c52014-05-13 22:05:06 +0900[diff] [blame]846 exynos3250_clk_sleep_init();
Sylwester Nawrockid5e136a2014-06-18 17:46:52 +0200[diff] [blame]847
848 samsung_clk_of_add_provider(np, ctx);
Tomasz Figa2ce16c52014-05-13 22:05:06 +0900[diff] [blame]849}
850CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
Krzysztof Kozlowskie3c3f192014-09-02 15:21:15 +0200[diff] [blame]851
852/*
853 * CMU DMC
854 */
855
856#define BPLL_LOCK 0x0118
857#define BPLL_CON0 0x0218
858#define BPLL_CON1 0x021c
859#define BPLL_CON2 0x0220
860#define SRC_DMC 0x0300
861#define DIV_DMC1 0x0504
862#define GATE_BUS_DMC0 0x0700
863#define GATE_BUS_DMC1 0x0704
864#define GATE_BUS_DMC2 0x0708
865#define GATE_BUS_DMC3 0x070c
866#define GATE_SCLK_DMC 0x0800
867#define GATE_IP_DMC0 0x0900
868#define GATE_IP_DMC1 0x0904
869#define EPLL_LOCK 0x1110
870#define EPLL_CON0 0x1114
871#define EPLL_CON1 0x1118
872#define EPLL_CON2 0x111c
873#define SRC_EPLL 0x1120
874
875/*
876 * Support for CMU save/restore across system suspends
877 */
878#ifdef CONFIG_PM_SLEEP
879static struct samsung_clk_reg_dump *exynos3250_dmc_clk_regs;
880
881static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = {
882 BPLL_LOCK,
883 BPLL_CON0,
884 BPLL_CON1,
885 BPLL_CON2,
886 SRC_DMC,
887 DIV_DMC1,
888 GATE_BUS_DMC0,
889 GATE_BUS_DMC1,
890 GATE_BUS_DMC2,
891 GATE_BUS_DMC3,
892 GATE_SCLK_DMC,
893 GATE_IP_DMC0,
894 GATE_IP_DMC1,
895 EPLL_LOCK,
896 EPLL_CON0,
897 EPLL_CON1,
898 EPLL_CON2,
899 SRC_EPLL,
900};
901
902static int exynos3250_dmc_clk_suspend(void)
903{
904 samsung_clk_save(dmc_reg_base, exynos3250_dmc_clk_regs,
905 ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
906 return 0;
907}
908
909static void exynos3250_dmc_clk_resume(void)
910{
911 samsung_clk_restore(dmc_reg_base, exynos3250_dmc_clk_regs,
912 ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
913}
914
915static struct syscore_ops exynos3250_dmc_clk_syscore_ops = {
916 .suspend = exynos3250_dmc_clk_suspend,
917 .resume = exynos3250_dmc_clk_resume,
918};
919
920static void exynos3250_dmc_clk_sleep_init(void)
921{
922 exynos3250_dmc_clk_regs =
923 samsung_clk_alloc_reg_dump(exynos3250_cmu_dmc_clk_regs,
924 ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
925 if (!exynos3250_dmc_clk_regs) {
926 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
927 goto err;
928 }
929
930 register_syscore_ops(&exynos3250_dmc_clk_syscore_ops);
931 return;
932err:
933 kfree(exynos3250_dmc_clk_regs);
934}
935#else
936static inline void exynos3250_dmc_clk_sleep_init(void) { }
937#endif
938
939PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
940PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
941PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", };
942PNAME(mout_dphy_p) = { "mout_mpll_mif", "mout_bpll", };
943
944static struct samsung_mux_clock dmc_mux_clks[] __initdata = {
945 /*
946 * NOTE: Following table is sorted by register address in ascending
947 * order and then bitfield shift in descending order, as it is done
948 * in the User's Manual. When adding new entries, please make sure
949 * that the order is preserved, to avoid merge conflicts and make
950 * further work with defined data easier.
951 */
952
953 /* SRC_DMC */
954 MUX(CLK_MOUT_MPLL_MIF, "mout_mpll_mif", mout_mpll_mif_p, SRC_DMC, 12, 1),
955 MUX(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
956 MUX(CLK_MOUT_DPHY, "mout_dphy", mout_dphy_p, SRC_DMC, 8, 1),
957 MUX(CLK_MOUT_DMC_BUS, "mout_dmc_bus", mout_dphy_p, SRC_DMC, 4, 1),
958
959 /* SRC_EPLL */
960 MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1),
961};
962
963static struct samsung_div_clock dmc_div_clks[] __initdata = {
964 /*
965 * NOTE: Following table is sorted by register address in ascending
966 * order and then bitfield shift in descending order, as it is done
967 * in the User's Manual. When adding new entries, please make sure
968 * that the order is preserved, to avoid merge conflicts and make
969 * further work with defined data easier.
970 */
971
972 /* DIV_DMC1 */
973 DIV(CLK_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
974 DIV(CLK_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
975 DIV(CLK_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus", DIV_DMC1, 19, 2),
976 DIV(CLK_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
977 DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
978};
979
980static struct samsung_pll_clock exynos3250_dmc_plls[nr_dmc_plls] __initdata = {
981 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
982 BPLL_LOCK, BPLL_CON0, NULL),
983 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
984 EPLL_LOCK, EPLL_CON0, NULL),
985};
986
987static void __init exynos3250_cmu_dmc_init(struct device_node *np)
988{
989 struct samsung_clk_provider *ctx;
990
991 dmc_reg_base = of_iomap(np, 0);
992 if (!dmc_reg_base)
993 panic("%s: failed to map registers\n", __func__);
994
995 ctx = samsung_clk_init(np, dmc_reg_base, NR_CLKS_DMC);
996 if (!ctx)
997 panic("%s: unable to allocate context.\n", __func__);
998
999 exynos3250_dmc_plls[bpll].rate_table = exynos3250_pll_rates;
1000 exynos3250_dmc_plls[epll].rate_table = exynos3250_epll_rates;
1001
1002 pr_err("CLK registering epll bpll: %d, %d, %d, %d\n",
1003 exynos3250_dmc_plls[bpll].rate_table[0].rate,
1004 exynos3250_dmc_plls[bpll].rate_table[0].mdiv,
1005 exynos3250_dmc_plls[bpll].rate_table[0].pdiv,
1006 exynos3250_dmc_plls[bpll].rate_table[0].sdiv
1007 );
1008 samsung_clk_register_pll(ctx, exynos3250_dmc_plls,
1009 ARRAY_SIZE(exynos3250_dmc_plls), dmc_reg_base);
1010
1011 samsung_clk_register_mux(ctx, dmc_mux_clks, ARRAY_SIZE(dmc_mux_clks));
1012 samsung_clk_register_div(ctx, dmc_div_clks, ARRAY_SIZE(dmc_div_clks));
1013
1014 exynos3250_dmc_clk_sleep_init();
1015
1016 samsung_clk_of_add_provider(np, ctx);
1017}
1018CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
1019 exynos3250_cmu_dmc_init);