Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1 | /* |
| 2 | * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling |
| 3 | * |
| 4 | * Copyright (C) 2004-2013 Synopsys, Inc. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions, and the following disclaimer, |
| 11 | * without modification. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. The names of the above-listed copyright holders may not be used |
| 16 | * to endorse or promote products derived from this software without |
| 17 | * specific prior written permission. |
| 18 | * |
| 19 | * ALTERNATIVELY, this software may be distributed under the terms of the |
| 20 | * GNU General Public License ("GPL") as published by the Free Software |
| 21 | * Foundation; either version 2 of the License, or (at your option) any |
| 22 | * later version. |
| 23 | * |
| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS |
| 25 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
| 26 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 27 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 28 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 29 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 30 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 31 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| 32 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 33 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 34 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 35 | */ |
| 36 | |
| 37 | /* |
| 38 | * This file contains the interrupt handlers for Host mode |
| 39 | */ |
| 40 | #include <linux/kernel.h> |
| 41 | #include <linux/module.h> |
| 42 | #include <linux/spinlock.h> |
| 43 | #include <linux/interrupt.h> |
| 44 | #include <linux/dma-mapping.h> |
| 45 | #include <linux/io.h> |
| 46 | #include <linux/slab.h> |
| 47 | #include <linux/usb.h> |
| 48 | |
| 49 | #include <linux/usb/hcd.h> |
| 50 | #include <linux/usb/ch11.h> |
| 51 | |
| 52 | #include "core.h" |
| 53 | #include "hcd.h" |
| 54 | |
| 55 | /* This function is for debug only */ |
| 56 | static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg) |
| 57 | { |
| 58 | #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 59 | u16 curr_frame_number = hsotg->frame_number; |
| 60 | |
| 61 | if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) { |
| 62 | if (((hsotg->last_frame_num + 1) & HFNUM_MAX_FRNUM) != |
| 63 | curr_frame_number) { |
| 64 | hsotg->frame_num_array[hsotg->frame_num_idx] = |
| 65 | curr_frame_number; |
| 66 | hsotg->last_frame_num_array[hsotg->frame_num_idx] = |
| 67 | hsotg->last_frame_num; |
| 68 | hsotg->frame_num_idx++; |
| 69 | } |
| 70 | } else if (!hsotg->dumped_frame_num_array) { |
| 71 | int i; |
| 72 | |
| 73 | dev_info(hsotg->dev, "Frame Last Frame\n"); |
| 74 | dev_info(hsotg->dev, "----- ----------\n"); |
| 75 | for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) { |
| 76 | dev_info(hsotg->dev, "0x%04x 0x%04x\n", |
| 77 | hsotg->frame_num_array[i], |
| 78 | hsotg->last_frame_num_array[i]); |
| 79 | } |
| 80 | hsotg->dumped_frame_num_array = 1; |
| 81 | } |
| 82 | hsotg->last_frame_num = curr_frame_number; |
| 83 | #endif |
| 84 | } |
| 85 | |
| 86 | static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg, |
| 87 | struct dwc2_host_chan *chan, |
| 88 | struct dwc2_qtd *qtd) |
| 89 | { |
| 90 | struct urb *usb_urb; |
| 91 | |
Paul Zimmerman | 399fdf9 | 2013-07-13 14:53:50 -0700 | [diff] [blame] | 92 | if (!chan->qh) |
| 93 | return; |
| 94 | |
| 95 | if (chan->qh->dev_speed == USB_SPEED_HIGH) |
| 96 | return; |
| 97 | |
| 98 | if (!qtd->urb) |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 99 | return; |
| 100 | |
| 101 | usb_urb = qtd->urb->priv; |
Paul Zimmerman | 399fdf9 | 2013-07-13 14:53:50 -0700 | [diff] [blame] | 102 | if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt) |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 103 | return; |
| 104 | |
Paul Zimmerman | 399fdf9 | 2013-07-13 14:53:50 -0700 | [diff] [blame] | 105 | if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) { |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 106 | chan->qh->tt_buffer_dirty = 1; |
| 107 | if (usb_hub_clear_tt_buffer(usb_urb)) |
| 108 | /* Clear failed; let's hope things work anyway */ |
| 109 | chan->qh->tt_buffer_dirty = 0; |
| 110 | } |
| 111 | } |
| 112 | |
| 113 | /* |
| 114 | * Handles the start-of-frame interrupt in host mode. Non-periodic |
| 115 | * transactions may be queued to the DWC_otg controller for the current |
| 116 | * (micro)frame. Periodic transactions may be queued to the controller |
| 117 | * for the next (micro)frame. |
| 118 | */ |
| 119 | static void dwc2_sof_intr(struct dwc2_hsotg *hsotg) |
| 120 | { |
| 121 | struct list_head *qh_entry; |
| 122 | struct dwc2_qh *qh; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 123 | enum dwc2_transaction_type tr_type; |
| 124 | |
| 125 | #ifdef DEBUG_SOF |
| 126 | dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n"); |
| 127 | #endif |
| 128 | |
Matthijs Kooijman | 37e1dcc | 2013-04-29 19:40:23 +0000 | [diff] [blame] | 129 | hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 130 | |
| 131 | dwc2_track_missed_sofs(hsotg); |
| 132 | |
| 133 | /* Determine whether any periodic QHs should be executed */ |
| 134 | qh_entry = hsotg->periodic_sched_inactive.next; |
| 135 | while (qh_entry != &hsotg->periodic_sched_inactive) { |
| 136 | qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry); |
| 137 | qh_entry = qh_entry->next; |
| 138 | if (dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number)) |
| 139 | /* |
| 140 | * Move QH to the ready list to be executed next |
| 141 | * (micro)frame |
| 142 | */ |
| 143 | list_move(&qh->qh_list_entry, |
| 144 | &hsotg->periodic_sched_ready); |
| 145 | } |
| 146 | tr_type = dwc2_hcd_select_transactions(hsotg); |
| 147 | if (tr_type != DWC2_TRANSACTION_NONE) |
| 148 | dwc2_hcd_queue_transactions(hsotg, tr_type); |
| 149 | |
| 150 | /* Clear interrupt */ |
| 151 | writel(GINTSTS_SOF, hsotg->regs + GINTSTS); |
| 152 | } |
| 153 | |
| 154 | /* |
| 155 | * Handles the Rx FIFO Level Interrupt, which indicates that there is |
| 156 | * at least one packet in the Rx FIFO. The packets are moved from the FIFO to |
| 157 | * memory if the DWC_otg controller is operating in Slave mode. |
| 158 | */ |
| 159 | static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg) |
| 160 | { |
| 161 | u32 grxsts, chnum, bcnt, dpid, pktsts; |
| 162 | struct dwc2_host_chan *chan; |
| 163 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 164 | if (dbg_perio()) |
| 165 | dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n"); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 166 | |
| 167 | grxsts = readl(hsotg->regs + GRXSTSP); |
Matthijs Kooijman | d6ec53e | 2013-08-30 18:45:15 +0200 | [diff] [blame] | 168 | chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 169 | chan = hsotg->hc_ptr_array[chnum]; |
| 170 | if (!chan) { |
| 171 | dev_err(hsotg->dev, "Unable to get corresponding channel\n"); |
| 172 | return; |
| 173 | } |
| 174 | |
Matthijs Kooijman | d6ec53e | 2013-08-30 18:45:15 +0200 | [diff] [blame] | 175 | bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT; |
| 176 | dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT; |
Matthijs Kooijman | f923463 | 2013-08-30 18:45:13 +0200 | [diff] [blame] | 177 | pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 178 | |
| 179 | /* Packet Status */ |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 180 | if (dbg_perio()) { |
| 181 | dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum); |
| 182 | dev_vdbg(hsotg->dev, " Count = %d\n", bcnt); |
| 183 | dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid, |
| 184 | chan->data_pid_start); |
Matthijs Kooijman | f923463 | 2013-08-30 18:45:13 +0200 | [diff] [blame] | 185 | dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 186 | } |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 187 | |
| 188 | switch (pktsts) { |
| 189 | case GRXSTS_PKTSTS_HCHIN: |
| 190 | /* Read the data into the host buffer */ |
| 191 | if (bcnt > 0) { |
| 192 | dwc2_read_packet(hsotg, chan->xfer_buf, bcnt); |
| 193 | |
| 194 | /* Update the HC fields for the next packet received */ |
| 195 | chan->xfer_count += bcnt; |
| 196 | chan->xfer_buf += bcnt; |
| 197 | } |
| 198 | break; |
| 199 | case GRXSTS_PKTSTS_HCHIN_XFER_COMP: |
| 200 | case GRXSTS_PKTSTS_DATATOGGLEERR: |
| 201 | case GRXSTS_PKTSTS_HCHHALTED: |
| 202 | /* Handled in interrupt, just ignore data */ |
| 203 | break; |
| 204 | default: |
| 205 | dev_err(hsotg->dev, |
| 206 | "RxFIFO Level Interrupt: Unknown status %d\n", pktsts); |
| 207 | break; |
| 208 | } |
| 209 | } |
| 210 | |
| 211 | /* |
| 212 | * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More |
| 213 | * data packets may be written to the FIFO for OUT transfers. More requests |
| 214 | * may be written to the non-periodic request queue for IN transfers. This |
| 215 | * interrupt is enabled only in Slave mode. |
| 216 | */ |
| 217 | static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg) |
| 218 | { |
| 219 | dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n"); |
| 220 | dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC); |
| 221 | } |
| 222 | |
| 223 | /* |
| 224 | * This interrupt occurs when the periodic Tx FIFO is half-empty. More data |
| 225 | * packets may be written to the FIFO for OUT transfers. More requests may be |
| 226 | * written to the periodic request queue for IN transfers. This interrupt is |
| 227 | * enabled only in Slave mode. |
| 228 | */ |
| 229 | static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg) |
| 230 | { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 231 | if (dbg_perio()) |
| 232 | dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n"); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 233 | dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC); |
| 234 | } |
| 235 | |
| 236 | static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, |
| 237 | u32 *hprt0_modify) |
| 238 | { |
| 239 | struct dwc2_core_params *params = hsotg->core_params; |
| 240 | int do_reset = 0; |
| 241 | u32 usbcfg; |
| 242 | u32 prtspd; |
| 243 | u32 hcfg; |
Matthijs Kooijman | bcc5def | 2013-04-29 19:42:00 +0000 | [diff] [blame] | 244 | u32 fslspclksel; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 245 | u32 hfir; |
| 246 | |
| 247 | dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); |
| 248 | |
| 249 | /* Every time when port enables calculate HFIR.FrInterval */ |
| 250 | hfir = readl(hsotg->regs + HFIR); |
| 251 | hfir &= ~HFIR_FRINT_MASK; |
| 252 | hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT & |
| 253 | HFIR_FRINT_MASK; |
| 254 | writel(hfir, hsotg->regs + HFIR); |
| 255 | |
| 256 | /* Check if we need to adjust the PHY clock speed for low power */ |
| 257 | if (!params->host_support_fs_ls_low_power) { |
| 258 | /* Port has been enabled, set the reset change flag */ |
| 259 | hsotg->flags.b.port_reset_change = 1; |
| 260 | return; |
| 261 | } |
| 262 | |
| 263 | usbcfg = readl(hsotg->regs + GUSBCFG); |
Matthijs Kooijman | f923463 | 2013-08-30 18:45:13 +0200 | [diff] [blame] | 264 | prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 265 | |
| 266 | if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) { |
| 267 | /* Low power */ |
| 268 | if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) { |
| 269 | /* Set PHY low power clock select for FS/LS devices */ |
| 270 | usbcfg |= GUSBCFG_PHY_LP_CLK_SEL; |
| 271 | writel(usbcfg, hsotg->regs + GUSBCFG); |
| 272 | do_reset = 1; |
| 273 | } |
| 274 | |
| 275 | hcfg = readl(hsotg->regs + HCFG); |
Matthijs Kooijman | f923463 | 2013-08-30 18:45:13 +0200 | [diff] [blame] | 276 | fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >> |
| 277 | HCFG_FSLSPCLKSEL_SHIFT; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 278 | |
| 279 | if (prtspd == HPRT0_SPD_LOW_SPEED && |
| 280 | params->host_ls_low_power_phy_clk == |
| 281 | DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) { |
| 282 | /* 6 MHZ */ |
| 283 | dev_vdbg(hsotg->dev, |
| 284 | "FS_PHY programming HCFG to 6 MHz\n"); |
Matthijs Kooijman | bcc5def | 2013-04-29 19:42:00 +0000 | [diff] [blame] | 285 | if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) { |
Matthijs Kooijman | f923463 | 2013-08-30 18:45:13 +0200 | [diff] [blame] | 286 | fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 287 | hcfg &= ~HCFG_FSLSPCLKSEL_MASK; |
Matthijs Kooijman | f923463 | 2013-08-30 18:45:13 +0200 | [diff] [blame] | 288 | hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 289 | writel(hcfg, hsotg->regs + HCFG); |
| 290 | do_reset = 1; |
| 291 | } |
| 292 | } else { |
| 293 | /* 48 MHZ */ |
| 294 | dev_vdbg(hsotg->dev, |
| 295 | "FS_PHY programming HCFG to 48 MHz\n"); |
Matthijs Kooijman | bcc5def | 2013-04-29 19:42:00 +0000 | [diff] [blame] | 296 | if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) { |
Matthijs Kooijman | f923463 | 2013-08-30 18:45:13 +0200 | [diff] [blame] | 297 | fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 298 | hcfg &= ~HCFG_FSLSPCLKSEL_MASK; |
Matthijs Kooijman | f923463 | 2013-08-30 18:45:13 +0200 | [diff] [blame] | 299 | hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 300 | writel(hcfg, hsotg->regs + HCFG); |
| 301 | do_reset = 1; |
| 302 | } |
| 303 | } |
| 304 | } else { |
| 305 | /* Not low power */ |
| 306 | if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) { |
| 307 | usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL; |
| 308 | writel(usbcfg, hsotg->regs + GUSBCFG); |
| 309 | do_reset = 1; |
| 310 | } |
| 311 | } |
| 312 | |
| 313 | if (do_reset) { |
| 314 | *hprt0_modify |= HPRT0_RST; |
| 315 | queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work, |
| 316 | msecs_to_jiffies(60)); |
| 317 | } else { |
| 318 | /* Port has been enabled, set the reset change flag */ |
| 319 | hsotg->flags.b.port_reset_change = 1; |
| 320 | } |
| 321 | } |
| 322 | |
| 323 | /* |
| 324 | * There are multiple conditions that can cause a port interrupt. This function |
| 325 | * determines which interrupt conditions have occurred and handles them |
| 326 | * appropriately. |
| 327 | */ |
| 328 | static void dwc2_port_intr(struct dwc2_hsotg *hsotg) |
| 329 | { |
| 330 | u32 hprt0; |
| 331 | u32 hprt0_modify; |
| 332 | |
| 333 | dev_vdbg(hsotg->dev, "--Port Interrupt--\n"); |
| 334 | |
| 335 | hprt0 = readl(hsotg->regs + HPRT0); |
| 336 | hprt0_modify = hprt0; |
| 337 | |
| 338 | /* |
| 339 | * Clear appropriate bits in HPRT0 to clear the interrupt bit in |
| 340 | * GINTSTS |
| 341 | */ |
| 342 | hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | |
| 343 | HPRT0_OVRCURRCHG); |
| 344 | |
| 345 | /* |
| 346 | * Port Connect Detected |
| 347 | * Set flag and clear if detected |
| 348 | */ |
| 349 | if (hprt0 & HPRT0_CONNDET) { |
| 350 | dev_vdbg(hsotg->dev, |
| 351 | "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n", |
| 352 | hprt0); |
| 353 | hsotg->flags.b.port_connect_status_change = 1; |
| 354 | hsotg->flags.b.port_connect_status = 1; |
| 355 | hprt0_modify |= HPRT0_CONNDET; |
| 356 | |
| 357 | /* |
| 358 | * The Hub driver asserts a reset when it sees port connect |
| 359 | * status change flag |
| 360 | */ |
| 361 | } |
| 362 | |
| 363 | /* |
| 364 | * Port Enable Changed |
| 365 | * Clear if detected - Set internal flag if disabled |
| 366 | */ |
| 367 | if (hprt0 & HPRT0_ENACHG) { |
| 368 | dev_vdbg(hsotg->dev, |
| 369 | " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n", |
| 370 | hprt0, !!(hprt0 & HPRT0_ENA)); |
| 371 | hprt0_modify |= HPRT0_ENACHG; |
| 372 | if (hprt0 & HPRT0_ENA) |
| 373 | dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify); |
| 374 | else |
| 375 | hsotg->flags.b.port_enable_change = 1; |
| 376 | } |
| 377 | |
| 378 | /* Overcurrent Change Interrupt */ |
| 379 | if (hprt0 & HPRT0_OVRCURRCHG) { |
| 380 | dev_vdbg(hsotg->dev, |
| 381 | " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n", |
| 382 | hprt0); |
| 383 | hsotg->flags.b.port_over_current_change = 1; |
| 384 | hprt0_modify |= HPRT0_OVRCURRCHG; |
| 385 | } |
| 386 | |
| 387 | /* Clear Port Interrupts */ |
| 388 | writel(hprt0_modify, hsotg->regs + HPRT0); |
| 389 | } |
| 390 | |
| 391 | /* |
| 392 | * Gets the actual length of a transfer after the transfer halts. halt_status |
| 393 | * holds the reason for the halt. |
| 394 | * |
| 395 | * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read |
| 396 | * is set to 1 upon return if less than the requested number of bytes were |
| 397 | * transferred. short_read may also be NULL on entry, in which case it remains |
| 398 | * unchanged. |
| 399 | */ |
| 400 | static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg, |
| 401 | struct dwc2_host_chan *chan, int chnum, |
| 402 | struct dwc2_qtd *qtd, |
| 403 | enum dwc2_halt_status halt_status, |
| 404 | int *short_read) |
| 405 | { |
| 406 | u32 hctsiz, count, length; |
| 407 | |
| 408 | hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); |
| 409 | |
| 410 | if (halt_status == DWC2_HC_XFER_COMPLETE) { |
| 411 | if (chan->ep_is_in) { |
Matthijs Kooijman | d6ec53e | 2013-08-30 18:45:15 +0200 | [diff] [blame] | 412 | count = (hctsiz & TSIZ_XFERSIZE_MASK) >> |
| 413 | TSIZ_XFERSIZE_SHIFT; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 414 | length = chan->xfer_len - count; |
| 415 | if (short_read != NULL) |
| 416 | *short_read = (count != 0); |
| 417 | } else if (chan->qh->do_split) { |
| 418 | length = qtd->ssplit_out_xfer_count; |
| 419 | } else { |
| 420 | length = chan->xfer_len; |
| 421 | } |
| 422 | } else { |
| 423 | /* |
| 424 | * Must use the hctsiz.pktcnt field to determine how much data |
| 425 | * has been transferred. This field reflects the number of |
| 426 | * packets that have been transferred via the USB. This is |
| 427 | * always an integral number of packets if the transfer was |
| 428 | * halted before its normal completion. (Can't use the |
| 429 | * hctsiz.xfersize field because that reflects the number of |
| 430 | * bytes transferred via the AHB, not the USB). |
| 431 | */ |
Matthijs Kooijman | d6ec53e | 2013-08-30 18:45:15 +0200 | [diff] [blame] | 432 | count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 433 | length = (chan->start_pkt_count - count) * chan->max_packet; |
| 434 | } |
| 435 | |
| 436 | return length; |
| 437 | } |
| 438 | |
| 439 | /** |
| 440 | * dwc2_update_urb_state() - Updates the state of the URB after a Transfer |
| 441 | * Complete interrupt on the host channel. Updates the actual_length field |
| 442 | * of the URB based on the number of bytes transferred via the host channel. |
| 443 | * Sets the URB status if the data transfer is finished. |
| 444 | * |
| 445 | * Return: 1 if the data transfer specified by the URB is completely finished, |
| 446 | * 0 otherwise |
| 447 | */ |
| 448 | static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg, |
| 449 | struct dwc2_host_chan *chan, int chnum, |
| 450 | struct dwc2_hcd_urb *urb, |
| 451 | struct dwc2_qtd *qtd) |
| 452 | { |
| 453 | u32 hctsiz; |
| 454 | int xfer_done = 0; |
| 455 | int short_read = 0; |
| 456 | int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd, |
| 457 | DWC2_HC_XFER_COMPLETE, |
| 458 | &short_read); |
| 459 | |
| 460 | if (urb->actual_length + xfer_length > urb->length) { |
| 461 | dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__); |
| 462 | xfer_length = urb->length - urb->actual_length; |
| 463 | } |
| 464 | |
| 465 | /* Non DWORD-aligned buffer case handling */ |
| 466 | if (chan->align_buf && xfer_length && chan->ep_is_in) { |
Paul Zimmerman | 0cf31f8 | 2013-07-13 14:53:52 -0700 | [diff] [blame] | 467 | dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 468 | memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf, |
| 469 | xfer_length); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 470 | } |
| 471 | |
| 472 | dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n", |
| 473 | urb->actual_length, xfer_length); |
| 474 | urb->actual_length += xfer_length; |
| 475 | |
| 476 | if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK && |
| 477 | (urb->flags & URB_SEND_ZERO_PACKET) && |
| 478 | urb->actual_length >= urb->length && |
| 479 | !(urb->length % chan->max_packet)) { |
| 480 | xfer_done = 0; |
| 481 | } else if (short_read || urb->actual_length >= urb->length) { |
| 482 | xfer_done = 1; |
| 483 | urb->status = 0; |
| 484 | } |
| 485 | |
| 486 | hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); |
| 487 | dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", |
| 488 | __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); |
| 489 | dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len); |
| 490 | dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n", |
Matthijs Kooijman | d6ec53e | 2013-08-30 18:45:15 +0200 | [diff] [blame] | 491 | (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 492 | dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length); |
| 493 | dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length); |
| 494 | dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read, |
| 495 | xfer_done); |
| 496 | |
| 497 | return xfer_done; |
| 498 | } |
| 499 | |
| 500 | /* |
| 501 | * Save the starting data toggle for the next transfer. The data toggle is |
| 502 | * saved in the QH for non-control transfers and it's saved in the QTD for |
| 503 | * control transfers. |
| 504 | */ |
| 505 | void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, |
| 506 | struct dwc2_host_chan *chan, int chnum, |
| 507 | struct dwc2_qtd *qtd) |
| 508 | { |
| 509 | u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); |
Matthijs Kooijman | f923463 | 2013-08-30 18:45:13 +0200 | [diff] [blame] | 510 | u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 511 | |
| 512 | if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) { |
| 513 | if (pid == TSIZ_SC_MC_PID_DATA0) |
| 514 | chan->qh->data_toggle = DWC2_HC_PID_DATA0; |
| 515 | else |
| 516 | chan->qh->data_toggle = DWC2_HC_PID_DATA1; |
| 517 | } else { |
| 518 | if (pid == TSIZ_SC_MC_PID_DATA0) |
| 519 | qtd->data_toggle = DWC2_HC_PID_DATA0; |
| 520 | else |
| 521 | qtd->data_toggle = DWC2_HC_PID_DATA1; |
| 522 | } |
| 523 | } |
| 524 | |
| 525 | /** |
| 526 | * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when |
| 527 | * the transfer is stopped for any reason. The fields of the current entry in |
| 528 | * the frame descriptor array are set based on the transfer state and the input |
| 529 | * halt_status. Completes the Isochronous URB if all the URB frames have been |
| 530 | * completed. |
| 531 | * |
| 532 | * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be |
| 533 | * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE. |
| 534 | */ |
| 535 | static enum dwc2_halt_status dwc2_update_isoc_urb_state( |
| 536 | struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, |
| 537 | int chnum, struct dwc2_qtd *qtd, |
| 538 | enum dwc2_halt_status halt_status) |
| 539 | { |
| 540 | struct dwc2_hcd_iso_packet_desc *frame_desc; |
| 541 | struct dwc2_hcd_urb *urb = qtd->urb; |
| 542 | |
| 543 | if (!urb) |
| 544 | return DWC2_HC_XFER_NO_HALT_STATUS; |
| 545 | |
| 546 | frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; |
| 547 | |
| 548 | switch (halt_status) { |
| 549 | case DWC2_HC_XFER_COMPLETE: |
| 550 | frame_desc->status = 0; |
| 551 | frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg, |
| 552 | chan, chnum, qtd, halt_status, NULL); |
| 553 | |
| 554 | /* Non DWORD-aligned buffer case handling */ |
| 555 | if (chan->align_buf && frame_desc->actual_length && |
| 556 | chan->ep_is_in) { |
Paul Zimmerman | 0cf31f8 | 2013-07-13 14:53:52 -0700 | [diff] [blame] | 557 | dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", |
| 558 | __func__); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 559 | memcpy(urb->buf + frame_desc->offset + |
| 560 | qtd->isoc_split_offset, chan->qh->dw_align_buf, |
| 561 | frame_desc->actual_length); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 562 | } |
| 563 | break; |
| 564 | case DWC2_HC_XFER_FRAME_OVERRUN: |
| 565 | urb->error_count++; |
| 566 | if (chan->ep_is_in) |
| 567 | frame_desc->status = -ENOSR; |
| 568 | else |
| 569 | frame_desc->status = -ECOMM; |
| 570 | frame_desc->actual_length = 0; |
| 571 | break; |
| 572 | case DWC2_HC_XFER_BABBLE_ERR: |
| 573 | urb->error_count++; |
| 574 | frame_desc->status = -EOVERFLOW; |
| 575 | /* Don't need to update actual_length in this case */ |
| 576 | break; |
| 577 | case DWC2_HC_XFER_XACT_ERR: |
| 578 | urb->error_count++; |
| 579 | frame_desc->status = -EPROTO; |
| 580 | frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg, |
| 581 | chan, chnum, qtd, halt_status, NULL); |
| 582 | |
| 583 | /* Non DWORD-aligned buffer case handling */ |
| 584 | if (chan->align_buf && frame_desc->actual_length && |
| 585 | chan->ep_is_in) { |
Paul Zimmerman | 0cf31f8 | 2013-07-13 14:53:52 -0700 | [diff] [blame] | 586 | dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", |
| 587 | __func__); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 588 | memcpy(urb->buf + frame_desc->offset + |
| 589 | qtd->isoc_split_offset, chan->qh->dw_align_buf, |
| 590 | frame_desc->actual_length); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 591 | } |
| 592 | |
| 593 | /* Skip whole frame */ |
| 594 | if (chan->qh->do_split && |
| 595 | chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in && |
| 596 | hsotg->core_params->dma_enable > 0) { |
| 597 | qtd->complete_split = 0; |
| 598 | qtd->isoc_split_offset = 0; |
| 599 | } |
| 600 | |
| 601 | break; |
| 602 | default: |
| 603 | dev_err(hsotg->dev, "Unhandled halt_status (%d)\n", |
| 604 | halt_status); |
| 605 | break; |
| 606 | } |
| 607 | |
| 608 | if (++qtd->isoc_frame_index == urb->packet_count) { |
| 609 | /* |
| 610 | * urb->status is not used for isoc transfers. The individual |
| 611 | * frame_desc statuses are used instead. |
| 612 | */ |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 613 | dwc2_host_complete(hsotg, qtd, 0); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 614 | halt_status = DWC2_HC_XFER_URB_COMPLETE; |
| 615 | } else { |
| 616 | halt_status = DWC2_HC_XFER_COMPLETE; |
| 617 | } |
| 618 | |
| 619 | return halt_status; |
| 620 | } |
| 621 | |
| 622 | /* |
| 623 | * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic |
| 624 | * QHs, removes the QH from the active non-periodic schedule. If any QTDs are |
| 625 | * still linked to the QH, the QH is added to the end of the inactive |
| 626 | * non-periodic schedule. For periodic QHs, removes the QH from the periodic |
| 627 | * schedule if no more QTDs are linked to the QH. |
| 628 | */ |
| 629 | static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, |
| 630 | int free_qtd) |
| 631 | { |
| 632 | int continue_split = 0; |
| 633 | struct dwc2_qtd *qtd; |
| 634 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 635 | if (dbg_qh(qh)) |
| 636 | dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__, |
| 637 | hsotg, qh, free_qtd); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 638 | |
| 639 | if (list_empty(&qh->qtd_list)) { |
| 640 | dev_dbg(hsotg->dev, "## QTD list empty ##\n"); |
| 641 | goto no_qtd; |
| 642 | } |
| 643 | |
| 644 | qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); |
| 645 | |
| 646 | if (qtd->complete_split) |
| 647 | continue_split = 1; |
| 648 | else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID || |
| 649 | qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END) |
| 650 | continue_split = 1; |
| 651 | |
| 652 | if (free_qtd) { |
| 653 | dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); |
| 654 | continue_split = 0; |
| 655 | } |
| 656 | |
| 657 | no_qtd: |
| 658 | if (qh->channel) |
| 659 | qh->channel->align_buf = 0; |
| 660 | qh->channel = NULL; |
| 661 | dwc2_hcd_qh_deactivate(hsotg, qh, continue_split); |
| 662 | } |
| 663 | |
| 664 | /** |
| 665 | * dwc2_release_channel() - Releases a host channel for use by other transfers |
| 666 | * |
| 667 | * @hsotg: The HCD state structure |
| 668 | * @chan: The host channel to release |
| 669 | * @qtd: The QTD associated with the host channel. This QTD may be |
| 670 | * freed if the transfer is complete or an error has occurred. |
| 671 | * @halt_status: Reason the channel is being released. This status |
| 672 | * determines the actions taken by this function. |
| 673 | * |
| 674 | * Also attempts to select and queue more transactions since at least one host |
| 675 | * channel is available. |
| 676 | */ |
| 677 | static void dwc2_release_channel(struct dwc2_hsotg *hsotg, |
| 678 | struct dwc2_host_chan *chan, |
| 679 | struct dwc2_qtd *qtd, |
| 680 | enum dwc2_halt_status halt_status) |
| 681 | { |
| 682 | enum dwc2_transaction_type tr_type; |
| 683 | u32 haintmsk; |
| 684 | int free_qtd = 0; |
| 685 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 686 | if (dbg_hc(chan)) |
| 687 | dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n", |
| 688 | __func__, chan->hc_num, halt_status); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 689 | |
| 690 | switch (halt_status) { |
| 691 | case DWC2_HC_XFER_URB_COMPLETE: |
| 692 | free_qtd = 1; |
| 693 | break; |
| 694 | case DWC2_HC_XFER_AHB_ERR: |
| 695 | case DWC2_HC_XFER_STALL: |
| 696 | case DWC2_HC_XFER_BABBLE_ERR: |
| 697 | free_qtd = 1; |
| 698 | break; |
| 699 | case DWC2_HC_XFER_XACT_ERR: |
Matthijs Kooijman | 8509f2f | 2013-03-25 12:00:25 -0700 | [diff] [blame] | 700 | if (qtd && qtd->error_count >= 3) { |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 701 | dev_vdbg(hsotg->dev, |
| 702 | " Complete URB with transaction error\n"); |
| 703 | free_qtd = 1; |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 704 | dwc2_host_complete(hsotg, qtd, -EPROTO); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 705 | } |
| 706 | break; |
| 707 | case DWC2_HC_XFER_URB_DEQUEUE: |
| 708 | /* |
| 709 | * The QTD has already been removed and the QH has been |
| 710 | * deactivated. Don't want to do anything except release the |
| 711 | * host channel and try to queue more transfers. |
| 712 | */ |
| 713 | goto cleanup; |
| 714 | case DWC2_HC_XFER_PERIODIC_INCOMPLETE: |
| 715 | dev_vdbg(hsotg->dev, " Complete URB with I/O error\n"); |
| 716 | free_qtd = 1; |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 717 | dwc2_host_complete(hsotg, qtd, -EIO); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 718 | break; |
| 719 | case DWC2_HC_XFER_NO_HALT_STATUS: |
| 720 | default: |
| 721 | break; |
| 722 | } |
| 723 | |
| 724 | dwc2_deactivate_qh(hsotg, chan->qh, free_qtd); |
| 725 | |
| 726 | cleanup: |
| 727 | /* |
| 728 | * Release the host channel for use by other transfers. The cleanup |
| 729 | * function clears the channel interrupt enables and conditions, so |
| 730 | * there's no need to clear the Channel Halted interrupt separately. |
| 731 | */ |
| 732 | if (!list_empty(&chan->hc_list_entry)) |
| 733 | list_del(&chan->hc_list_entry); |
| 734 | dwc2_hc_cleanup(hsotg, chan); |
| 735 | list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); |
| 736 | |
Dom Cobley | 20f2eb9 | 2013-09-23 14:23:34 -0700 | [diff] [blame] | 737 | if (hsotg->core_params->uframe_sched > 0) { |
| 738 | hsotg->available_host_channels++; |
| 739 | } else { |
| 740 | switch (chan->ep_type) { |
| 741 | case USB_ENDPOINT_XFER_CONTROL: |
| 742 | case USB_ENDPOINT_XFER_BULK: |
| 743 | hsotg->non_periodic_channels--; |
| 744 | break; |
| 745 | default: |
| 746 | /* |
| 747 | * Don't release reservations for periodic channels |
| 748 | * here. That's done when a periodic transfer is |
| 749 | * descheduled (i.e. when the QH is removed from the |
| 750 | * periodic schedule). |
| 751 | */ |
| 752 | break; |
| 753 | } |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 754 | } |
| 755 | |
| 756 | haintmsk = readl(hsotg->regs + HAINTMSK); |
| 757 | haintmsk &= ~(1 << chan->hc_num); |
| 758 | writel(haintmsk, hsotg->regs + HAINTMSK); |
| 759 | |
| 760 | /* Try to queue more transfers now that there's a free channel */ |
| 761 | tr_type = dwc2_hcd_select_transactions(hsotg); |
| 762 | if (tr_type != DWC2_TRANSACTION_NONE) |
| 763 | dwc2_hcd_queue_transactions(hsotg, tr_type); |
| 764 | } |
| 765 | |
| 766 | /* |
| 767 | * Halts a host channel. If the channel cannot be halted immediately because |
| 768 | * the request queue is full, this function ensures that the FIFO empty |
| 769 | * interrupt for the appropriate queue is enabled so that the halt request can |
| 770 | * be queued when there is space in the request queue. |
| 771 | * |
| 772 | * This function may also be called in DMA mode. In that case, the channel is |
| 773 | * simply released since the core always halts the channel automatically in |
| 774 | * DMA mode. |
| 775 | */ |
| 776 | static void dwc2_halt_channel(struct dwc2_hsotg *hsotg, |
| 777 | struct dwc2_host_chan *chan, struct dwc2_qtd *qtd, |
| 778 | enum dwc2_halt_status halt_status) |
| 779 | { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 780 | if (dbg_hc(chan)) |
| 781 | dev_vdbg(hsotg->dev, "%s()\n", __func__); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 782 | |
| 783 | if (hsotg->core_params->dma_enable > 0) { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 784 | if (dbg_hc(chan)) |
| 785 | dev_vdbg(hsotg->dev, "DMA enabled\n"); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 786 | dwc2_release_channel(hsotg, chan, qtd, halt_status); |
| 787 | return; |
| 788 | } |
| 789 | |
| 790 | /* Slave mode processing */ |
| 791 | dwc2_hc_halt(hsotg, chan, halt_status); |
| 792 | |
| 793 | if (chan->halt_on_queue) { |
| 794 | u32 gintmsk; |
| 795 | |
| 796 | dev_vdbg(hsotg->dev, "Halt on queue\n"); |
| 797 | if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || |
| 798 | chan->ep_type == USB_ENDPOINT_XFER_BULK) { |
| 799 | dev_vdbg(hsotg->dev, "control/bulk\n"); |
| 800 | /* |
| 801 | * Make sure the Non-periodic Tx FIFO empty interrupt |
| 802 | * is enabled so that the non-periodic schedule will |
| 803 | * be processed |
| 804 | */ |
| 805 | gintmsk = readl(hsotg->regs + GINTMSK); |
| 806 | gintmsk |= GINTSTS_NPTXFEMP; |
| 807 | writel(gintmsk, hsotg->regs + GINTMSK); |
| 808 | } else { |
| 809 | dev_vdbg(hsotg->dev, "isoc/intr\n"); |
| 810 | /* |
| 811 | * Move the QH from the periodic queued schedule to |
| 812 | * the periodic assigned schedule. This allows the |
| 813 | * halt to be queued when the periodic schedule is |
| 814 | * processed. |
| 815 | */ |
| 816 | list_move(&chan->qh->qh_list_entry, |
| 817 | &hsotg->periodic_sched_assigned); |
| 818 | |
| 819 | /* |
| 820 | * Make sure the Periodic Tx FIFO Empty interrupt is |
| 821 | * enabled so that the periodic schedule will be |
| 822 | * processed |
| 823 | */ |
| 824 | gintmsk = readl(hsotg->regs + GINTMSK); |
| 825 | gintmsk |= GINTSTS_PTXFEMP; |
| 826 | writel(gintmsk, hsotg->regs + GINTMSK); |
| 827 | } |
| 828 | } |
| 829 | } |
| 830 | |
| 831 | /* |
| 832 | * Performs common cleanup for non-periodic transfers after a Transfer |
| 833 | * Complete interrupt. This function should be called after any endpoint type |
| 834 | * specific handling is finished to release the host channel. |
| 835 | */ |
| 836 | static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg, |
| 837 | struct dwc2_host_chan *chan, |
| 838 | int chnum, struct dwc2_qtd *qtd, |
| 839 | enum dwc2_halt_status halt_status) |
| 840 | { |
| 841 | dev_vdbg(hsotg->dev, "%s()\n", __func__); |
| 842 | |
| 843 | qtd->error_count = 0; |
| 844 | |
| 845 | if (chan->hcint & HCINTMSK_NYET) { |
| 846 | /* |
| 847 | * Got a NYET on the last transaction of the transfer. This |
| 848 | * means that the endpoint should be in the PING state at the |
| 849 | * beginning of the next transfer. |
| 850 | */ |
| 851 | dev_vdbg(hsotg->dev, "got NYET\n"); |
| 852 | chan->qh->ping_state = 1; |
| 853 | } |
| 854 | |
| 855 | /* |
| 856 | * Always halt and release the host channel to make it available for |
| 857 | * more transfers. There may still be more phases for a control |
| 858 | * transfer or more data packets for a bulk transfer at this point, |
| 859 | * but the host channel is still halted. A channel will be reassigned |
| 860 | * to the transfer when the non-periodic schedule is processed after |
| 861 | * the channel is released. This allows transactions to be queued |
| 862 | * properly via dwc2_hcd_queue_transactions, which also enables the |
| 863 | * Tx FIFO Empty interrupt if necessary. |
| 864 | */ |
| 865 | if (chan->ep_is_in) { |
| 866 | /* |
| 867 | * IN transfers in Slave mode require an explicit disable to |
| 868 | * halt the channel. (In DMA mode, this call simply releases |
| 869 | * the channel.) |
| 870 | */ |
| 871 | dwc2_halt_channel(hsotg, chan, qtd, halt_status); |
| 872 | } else { |
| 873 | /* |
| 874 | * The channel is automatically disabled by the core for OUT |
| 875 | * transfers in Slave mode |
| 876 | */ |
| 877 | dwc2_release_channel(hsotg, chan, qtd, halt_status); |
| 878 | } |
| 879 | } |
| 880 | |
| 881 | /* |
| 882 | * Performs common cleanup for periodic transfers after a Transfer Complete |
| 883 | * interrupt. This function should be called after any endpoint type specific |
| 884 | * handling is finished to release the host channel. |
| 885 | */ |
| 886 | static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg, |
| 887 | struct dwc2_host_chan *chan, int chnum, |
| 888 | struct dwc2_qtd *qtd, |
| 889 | enum dwc2_halt_status halt_status) |
| 890 | { |
| 891 | u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); |
| 892 | |
| 893 | qtd->error_count = 0; |
| 894 | |
| 895 | if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0) |
| 896 | /* Core halts channel in these cases */ |
| 897 | dwc2_release_channel(hsotg, chan, qtd, halt_status); |
| 898 | else |
| 899 | /* Flush any outstanding requests from the Tx queue */ |
| 900 | dwc2_halt_channel(hsotg, chan, qtd, halt_status); |
| 901 | } |
| 902 | |
| 903 | static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg, |
| 904 | struct dwc2_host_chan *chan, int chnum, |
| 905 | struct dwc2_qtd *qtd) |
| 906 | { |
| 907 | struct dwc2_hcd_iso_packet_desc *frame_desc; |
| 908 | u32 len; |
| 909 | |
| 910 | if (!qtd->urb) |
| 911 | return 0; |
| 912 | |
| 913 | frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; |
| 914 | len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd, |
| 915 | DWC2_HC_XFER_COMPLETE, NULL); |
| 916 | if (!len) { |
| 917 | qtd->complete_split = 0; |
| 918 | qtd->isoc_split_offset = 0; |
| 919 | return 0; |
| 920 | } |
| 921 | |
| 922 | frame_desc->actual_length += len; |
| 923 | |
Paul Zimmerman | e7e59e1 | 2013-11-25 13:42:46 -0800 | [diff] [blame] | 924 | if (chan->align_buf) { |
Paul Zimmerman | 0cf31f8 | 2013-07-13 14:53:52 -0700 | [diff] [blame] | 925 | dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 926 | memcpy(qtd->urb->buf + frame_desc->offset + |
| 927 | qtd->isoc_split_offset, chan->qh->dw_align_buf, len); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 928 | } |
| 929 | |
| 930 | qtd->isoc_split_offset += len; |
| 931 | |
| 932 | if (frame_desc->actual_length >= frame_desc->length) { |
| 933 | frame_desc->status = 0; |
| 934 | qtd->isoc_frame_index++; |
| 935 | qtd->complete_split = 0; |
| 936 | qtd->isoc_split_offset = 0; |
| 937 | } |
| 938 | |
| 939 | if (qtd->isoc_frame_index == qtd->urb->packet_count) { |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 940 | dwc2_host_complete(hsotg, qtd, 0); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 941 | dwc2_release_channel(hsotg, chan, qtd, |
| 942 | DWC2_HC_XFER_URB_COMPLETE); |
| 943 | } else { |
| 944 | dwc2_release_channel(hsotg, chan, qtd, |
| 945 | DWC2_HC_XFER_NO_HALT_STATUS); |
| 946 | } |
| 947 | |
| 948 | return 1; /* Indicates that channel released */ |
| 949 | } |
| 950 | |
| 951 | /* |
| 952 | * Handles a host channel Transfer Complete interrupt. This handler may be |
| 953 | * called in either DMA mode or Slave mode. |
| 954 | */ |
| 955 | static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg, |
| 956 | struct dwc2_host_chan *chan, int chnum, |
| 957 | struct dwc2_qtd *qtd) |
| 958 | { |
| 959 | struct dwc2_hcd_urb *urb = qtd->urb; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 960 | enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE; |
Paul Zimmerman | 2b54fa6 | 2014-02-12 17:44:35 -0800 | [diff] [blame] | 961 | int pipe_type; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 962 | int urb_xfer_done; |
| 963 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 964 | if (dbg_hc(chan)) |
| 965 | dev_vdbg(hsotg->dev, |
| 966 | "--Host Channel %d Interrupt: Transfer Complete--\n", |
| 967 | chnum); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 968 | |
Paul Zimmerman | 2b54fa6 | 2014-02-12 17:44:35 -0800 | [diff] [blame] | 969 | if (!urb) |
| 970 | goto handle_xfercomp_done; |
| 971 | |
| 972 | pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); |
| 973 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 974 | if (hsotg->core_params->dma_desc_enable > 0) { |
| 975 | dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status); |
| 976 | if (pipe_type == USB_ENDPOINT_XFER_ISOC) |
| 977 | /* Do not disable the interrupt, just clear it */ |
| 978 | return; |
| 979 | goto handle_xfercomp_done; |
| 980 | } |
| 981 | |
| 982 | /* Handle xfer complete on CSPLIT */ |
| 983 | if (chan->qh->do_split) { |
| 984 | if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in && |
| 985 | hsotg->core_params->dma_enable > 0) { |
| 986 | if (qtd->complete_split && |
| 987 | dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum, |
| 988 | qtd)) |
| 989 | goto handle_xfercomp_done; |
| 990 | } else { |
| 991 | qtd->complete_split = 0; |
| 992 | } |
| 993 | } |
| 994 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 995 | /* Update the QTD and URB states */ |
| 996 | switch (pipe_type) { |
| 997 | case USB_ENDPOINT_XFER_CONTROL: |
| 998 | switch (qtd->control_phase) { |
| 999 | case DWC2_CONTROL_SETUP: |
| 1000 | if (urb->length > 0) |
| 1001 | qtd->control_phase = DWC2_CONTROL_DATA; |
| 1002 | else |
| 1003 | qtd->control_phase = DWC2_CONTROL_STATUS; |
| 1004 | dev_vdbg(hsotg->dev, |
| 1005 | " Control setup transaction done\n"); |
| 1006 | halt_status = DWC2_HC_XFER_COMPLETE; |
| 1007 | break; |
| 1008 | case DWC2_CONTROL_DATA: |
| 1009 | urb_xfer_done = dwc2_update_urb_state(hsotg, chan, |
| 1010 | chnum, urb, qtd); |
| 1011 | if (urb_xfer_done) { |
| 1012 | qtd->control_phase = DWC2_CONTROL_STATUS; |
| 1013 | dev_vdbg(hsotg->dev, |
| 1014 | " Control data transfer done\n"); |
| 1015 | } else { |
| 1016 | dwc2_hcd_save_data_toggle(hsotg, chan, chnum, |
| 1017 | qtd); |
| 1018 | } |
| 1019 | halt_status = DWC2_HC_XFER_COMPLETE; |
| 1020 | break; |
| 1021 | case DWC2_CONTROL_STATUS: |
| 1022 | dev_vdbg(hsotg->dev, " Control transfer complete\n"); |
| 1023 | if (urb->status == -EINPROGRESS) |
| 1024 | urb->status = 0; |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1025 | dwc2_host_complete(hsotg, qtd, urb->status); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1026 | halt_status = DWC2_HC_XFER_URB_COMPLETE; |
| 1027 | break; |
| 1028 | } |
| 1029 | |
| 1030 | dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd, |
| 1031 | halt_status); |
| 1032 | break; |
| 1033 | case USB_ENDPOINT_XFER_BULK: |
| 1034 | dev_vdbg(hsotg->dev, " Bulk transfer complete\n"); |
| 1035 | urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb, |
| 1036 | qtd); |
| 1037 | if (urb_xfer_done) { |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1038 | dwc2_host_complete(hsotg, qtd, urb->status); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1039 | halt_status = DWC2_HC_XFER_URB_COMPLETE; |
| 1040 | } else { |
| 1041 | halt_status = DWC2_HC_XFER_COMPLETE; |
| 1042 | } |
| 1043 | |
| 1044 | dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); |
| 1045 | dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd, |
| 1046 | halt_status); |
| 1047 | break; |
| 1048 | case USB_ENDPOINT_XFER_INT: |
| 1049 | dev_vdbg(hsotg->dev, " Interrupt transfer complete\n"); |
| 1050 | urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb, |
| 1051 | qtd); |
| 1052 | |
| 1053 | /* |
| 1054 | * Interrupt URB is done on the first transfer complete |
| 1055 | * interrupt |
| 1056 | */ |
| 1057 | if (urb_xfer_done) { |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1058 | dwc2_host_complete(hsotg, qtd, urb->status); |
| 1059 | halt_status = DWC2_HC_XFER_URB_COMPLETE; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1060 | } else { |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1061 | halt_status = DWC2_HC_XFER_COMPLETE; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1062 | } |
| 1063 | |
| 1064 | dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); |
| 1065 | dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd, |
| 1066 | halt_status); |
| 1067 | break; |
| 1068 | case USB_ENDPOINT_XFER_ISOC: |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1069 | if (dbg_perio()) |
| 1070 | dev_vdbg(hsotg->dev, " Isochronous transfer complete\n"); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1071 | if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL) |
| 1072 | halt_status = dwc2_update_isoc_urb_state(hsotg, chan, |
| 1073 | chnum, qtd, DWC2_HC_XFER_COMPLETE); |
| 1074 | dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd, |
| 1075 | halt_status); |
| 1076 | break; |
| 1077 | } |
| 1078 | |
| 1079 | handle_xfercomp_done: |
| 1080 | disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL); |
| 1081 | } |
| 1082 | |
| 1083 | /* |
| 1084 | * Handles a host channel STALL interrupt. This handler may be called in |
| 1085 | * either DMA mode or Slave mode. |
| 1086 | */ |
| 1087 | static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg, |
| 1088 | struct dwc2_host_chan *chan, int chnum, |
| 1089 | struct dwc2_qtd *qtd) |
| 1090 | { |
| 1091 | struct dwc2_hcd_urb *urb = qtd->urb; |
Paul Zimmerman | 2b54fa6 | 2014-02-12 17:44:35 -0800 | [diff] [blame] | 1092 | int pipe_type; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1093 | |
| 1094 | dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n", |
| 1095 | chnum); |
| 1096 | |
| 1097 | if (hsotg->core_params->dma_desc_enable > 0) { |
| 1098 | dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, |
| 1099 | DWC2_HC_XFER_STALL); |
| 1100 | goto handle_stall_done; |
| 1101 | } |
| 1102 | |
| 1103 | if (!urb) |
| 1104 | goto handle_stall_halt; |
| 1105 | |
Paul Zimmerman | 2b54fa6 | 2014-02-12 17:44:35 -0800 | [diff] [blame] | 1106 | pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); |
| 1107 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1108 | if (pipe_type == USB_ENDPOINT_XFER_CONTROL) |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1109 | dwc2_host_complete(hsotg, qtd, -EPIPE); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1110 | |
| 1111 | if (pipe_type == USB_ENDPOINT_XFER_BULK || |
| 1112 | pipe_type == USB_ENDPOINT_XFER_INT) { |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1113 | dwc2_host_complete(hsotg, qtd, -EPIPE); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1114 | /* |
| 1115 | * USB protocol requires resetting the data toggle for bulk |
| 1116 | * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) |
| 1117 | * setup command is issued to the endpoint. Anticipate the |
| 1118 | * CLEAR_FEATURE command since a STALL has occurred and reset |
| 1119 | * the data toggle now. |
| 1120 | */ |
| 1121 | chan->qh->data_toggle = 0; |
| 1122 | } |
| 1123 | |
| 1124 | handle_stall_halt: |
| 1125 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL); |
| 1126 | |
| 1127 | handle_stall_done: |
| 1128 | disable_hc_int(hsotg, chnum, HCINTMSK_STALL); |
| 1129 | } |
| 1130 | |
| 1131 | /* |
| 1132 | * Updates the state of the URB when a transfer has been stopped due to an |
| 1133 | * abnormal condition before the transfer completes. Modifies the |
| 1134 | * actual_length field of the URB to reflect the number of bytes that have |
| 1135 | * actually been transferred via the host channel. |
| 1136 | */ |
| 1137 | static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg, |
| 1138 | struct dwc2_host_chan *chan, int chnum, |
| 1139 | struct dwc2_hcd_urb *urb, |
| 1140 | struct dwc2_qtd *qtd, |
| 1141 | enum dwc2_halt_status halt_status) |
| 1142 | { |
| 1143 | u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, |
| 1144 | qtd, halt_status, NULL); |
| 1145 | u32 hctsiz; |
| 1146 | |
| 1147 | if (urb->actual_length + xfer_length > urb->length) { |
| 1148 | dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__); |
| 1149 | xfer_length = urb->length - urb->actual_length; |
| 1150 | } |
| 1151 | |
| 1152 | /* Non DWORD-aligned buffer case handling */ |
| 1153 | if (chan->align_buf && xfer_length && chan->ep_is_in) { |
Paul Zimmerman | 0cf31f8 | 2013-07-13 14:53:52 -0700 | [diff] [blame] | 1154 | dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1155 | memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf, |
| 1156 | xfer_length); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1157 | } |
| 1158 | |
| 1159 | urb->actual_length += xfer_length; |
| 1160 | |
| 1161 | hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); |
| 1162 | dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", |
| 1163 | __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); |
| 1164 | dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n", |
| 1165 | chan->start_pkt_count); |
| 1166 | dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n", |
Matthijs Kooijman | d6ec53e | 2013-08-30 18:45:15 +0200 | [diff] [blame] | 1167 | (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1168 | dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet); |
| 1169 | dev_vdbg(hsotg->dev, " bytes_transferred %d\n", |
| 1170 | xfer_length); |
| 1171 | dev_vdbg(hsotg->dev, " urb->actual_length %d\n", |
| 1172 | urb->actual_length); |
| 1173 | dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", |
| 1174 | urb->length); |
| 1175 | } |
| 1176 | |
| 1177 | /* |
| 1178 | * Handles a host channel NAK interrupt. This handler may be called in either |
| 1179 | * DMA mode or Slave mode. |
| 1180 | */ |
| 1181 | static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg, |
| 1182 | struct dwc2_host_chan *chan, int chnum, |
| 1183 | struct dwc2_qtd *qtd) |
| 1184 | { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1185 | if (dbg_hc(chan)) |
| 1186 | dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n", |
| 1187 | chnum); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1188 | |
| 1189 | /* |
| 1190 | * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and |
| 1191 | * interrupt. Re-start the SSPLIT transfer. |
| 1192 | */ |
| 1193 | if (chan->do_split) { |
| 1194 | if (chan->complete_split) |
| 1195 | qtd->error_count = 0; |
| 1196 | qtd->complete_split = 0; |
| 1197 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); |
| 1198 | goto handle_nak_done; |
| 1199 | } |
| 1200 | |
| 1201 | switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { |
| 1202 | case USB_ENDPOINT_XFER_CONTROL: |
| 1203 | case USB_ENDPOINT_XFER_BULK: |
| 1204 | if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) { |
| 1205 | /* |
| 1206 | * NAK interrupts are enabled on bulk/control IN |
| 1207 | * transfers in DMA mode for the sole purpose of |
| 1208 | * resetting the error count after a transaction error |
| 1209 | * occurs. The core will continue transferring data. |
| 1210 | */ |
| 1211 | qtd->error_count = 0; |
| 1212 | break; |
| 1213 | } |
| 1214 | |
| 1215 | /* |
| 1216 | * NAK interrupts normally occur during OUT transfers in DMA |
| 1217 | * or Slave mode. For IN transfers, more requests will be |
| 1218 | * queued as request queue space is available. |
| 1219 | */ |
| 1220 | qtd->error_count = 0; |
| 1221 | |
| 1222 | if (!chan->qh->ping_state) { |
| 1223 | dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, |
| 1224 | qtd, DWC2_HC_XFER_NAK); |
| 1225 | dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); |
| 1226 | |
| 1227 | if (chan->speed == USB_SPEED_HIGH) |
| 1228 | chan->qh->ping_state = 1; |
| 1229 | } |
| 1230 | |
| 1231 | /* |
| 1232 | * Halt the channel so the transfer can be re-started from |
| 1233 | * the appropriate point or the PING protocol will |
| 1234 | * start/continue |
| 1235 | */ |
| 1236 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); |
| 1237 | break; |
| 1238 | case USB_ENDPOINT_XFER_INT: |
| 1239 | qtd->error_count = 0; |
| 1240 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK); |
| 1241 | break; |
| 1242 | case USB_ENDPOINT_XFER_ISOC: |
| 1243 | /* Should never get called for isochronous transfers */ |
| 1244 | dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n"); |
| 1245 | break; |
| 1246 | } |
| 1247 | |
| 1248 | handle_nak_done: |
| 1249 | disable_hc_int(hsotg, chnum, HCINTMSK_NAK); |
| 1250 | } |
| 1251 | |
| 1252 | /* |
| 1253 | * Handles a host channel ACK interrupt. This interrupt is enabled when |
| 1254 | * performing the PING protocol in Slave mode, when errors occur during |
| 1255 | * either Slave mode or DMA mode, and during Start Split transactions. |
| 1256 | */ |
| 1257 | static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg, |
| 1258 | struct dwc2_host_chan *chan, int chnum, |
| 1259 | struct dwc2_qtd *qtd) |
| 1260 | { |
| 1261 | struct dwc2_hcd_iso_packet_desc *frame_desc; |
| 1262 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1263 | if (dbg_hc(chan)) |
| 1264 | dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n", |
| 1265 | chnum); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1266 | |
| 1267 | if (chan->do_split) { |
| 1268 | /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */ |
| 1269 | if (!chan->ep_is_in && |
| 1270 | chan->data_pid_start != DWC2_HC_PID_SETUP) |
| 1271 | qtd->ssplit_out_xfer_count = chan->xfer_len; |
| 1272 | |
| 1273 | if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) { |
| 1274 | qtd->complete_split = 1; |
| 1275 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK); |
| 1276 | } else { |
| 1277 | /* ISOC OUT */ |
| 1278 | switch (chan->xact_pos) { |
| 1279 | case DWC2_HCSPLT_XACTPOS_ALL: |
| 1280 | break; |
| 1281 | case DWC2_HCSPLT_XACTPOS_END: |
| 1282 | qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; |
| 1283 | qtd->isoc_split_offset = 0; |
| 1284 | break; |
| 1285 | case DWC2_HCSPLT_XACTPOS_BEGIN: |
| 1286 | case DWC2_HCSPLT_XACTPOS_MID: |
| 1287 | /* |
| 1288 | * For BEGIN or MID, calculate the length for |
| 1289 | * the next microframe to determine the correct |
| 1290 | * SSPLIT token, either MID or END |
| 1291 | */ |
| 1292 | frame_desc = &qtd->urb->iso_descs[ |
| 1293 | qtd->isoc_frame_index]; |
| 1294 | qtd->isoc_split_offset += 188; |
| 1295 | |
| 1296 | if (frame_desc->length - qtd->isoc_split_offset |
| 1297 | <= 188) |
| 1298 | qtd->isoc_split_pos = |
| 1299 | DWC2_HCSPLT_XACTPOS_END; |
| 1300 | else |
| 1301 | qtd->isoc_split_pos = |
| 1302 | DWC2_HCSPLT_XACTPOS_MID; |
| 1303 | break; |
| 1304 | } |
| 1305 | } |
| 1306 | } else { |
| 1307 | qtd->error_count = 0; |
| 1308 | |
| 1309 | if (chan->qh->ping_state) { |
| 1310 | chan->qh->ping_state = 0; |
| 1311 | /* |
| 1312 | * Halt the channel so the transfer can be re-started |
| 1313 | * from the appropriate point. This only happens in |
| 1314 | * Slave mode. In DMA mode, the ping_state is cleared |
| 1315 | * when the transfer is started because the core |
| 1316 | * automatically executes the PING, then the transfer. |
| 1317 | */ |
| 1318 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK); |
| 1319 | } |
| 1320 | } |
| 1321 | |
| 1322 | /* |
| 1323 | * If the ACK occurred when _not_ in the PING state, let the channel |
| 1324 | * continue transferring data after clearing the error count |
| 1325 | */ |
| 1326 | disable_hc_int(hsotg, chnum, HCINTMSK_ACK); |
| 1327 | } |
| 1328 | |
| 1329 | /* |
| 1330 | * Handles a host channel NYET interrupt. This interrupt should only occur on |
| 1331 | * Bulk and Control OUT endpoints and for complete split transactions. If a |
| 1332 | * NYET occurs at the same time as a Transfer Complete interrupt, it is |
| 1333 | * handled in the xfercomp interrupt handler, not here. This handler may be |
| 1334 | * called in either DMA mode or Slave mode. |
| 1335 | */ |
| 1336 | static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg, |
| 1337 | struct dwc2_host_chan *chan, int chnum, |
| 1338 | struct dwc2_qtd *qtd) |
| 1339 | { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1340 | if (dbg_hc(chan)) |
| 1341 | dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n", |
| 1342 | chnum); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1343 | |
| 1344 | /* |
| 1345 | * NYET on CSPLIT |
| 1346 | * re-do the CSPLIT immediately on non-periodic |
| 1347 | */ |
| 1348 | if (chan->do_split && chan->complete_split) { |
| 1349 | if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC && |
| 1350 | hsotg->core_params->dma_enable > 0) { |
| 1351 | qtd->complete_split = 0; |
| 1352 | qtd->isoc_split_offset = 0; |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1353 | qtd->isoc_frame_index++; |
Paul Zimmerman | 7902c16 | 2013-04-22 14:00:18 -0700 | [diff] [blame] | 1354 | if (qtd->urb && |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1355 | qtd->isoc_frame_index == qtd->urb->packet_count) { |
| 1356 | dwc2_host_complete(hsotg, qtd, 0); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1357 | dwc2_release_channel(hsotg, chan, qtd, |
Paul Zimmerman | 7902c16 | 2013-04-22 14:00:18 -0700 | [diff] [blame] | 1358 | DWC2_HC_XFER_URB_COMPLETE); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1359 | } else { |
| 1360 | dwc2_release_channel(hsotg, chan, qtd, |
| 1361 | DWC2_HC_XFER_NO_HALT_STATUS); |
| 1362 | } |
| 1363 | goto handle_nyet_done; |
| 1364 | } |
| 1365 | |
| 1366 | if (chan->ep_type == USB_ENDPOINT_XFER_INT || |
| 1367 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) { |
| 1368 | int frnum = dwc2_hcd_get_frame_number(hsotg); |
| 1369 | |
| 1370 | if (dwc2_full_frame_num(frnum) != |
| 1371 | dwc2_full_frame_num(chan->qh->sched_frame)) { |
| 1372 | /* |
| 1373 | * No longer in the same full speed frame. |
| 1374 | * Treat this as a transaction error. |
| 1375 | */ |
| 1376 | #if 0 |
| 1377 | /* |
| 1378 | * Todo: Fix system performance so this can |
| 1379 | * be treated as an error. Right now complete |
| 1380 | * splits cannot be scheduled precisely enough |
| 1381 | * due to other system activity, so this error |
| 1382 | * occurs regularly in Slave mode. |
| 1383 | */ |
| 1384 | qtd->error_count++; |
| 1385 | #endif |
| 1386 | qtd->complete_split = 0; |
| 1387 | dwc2_halt_channel(hsotg, chan, qtd, |
| 1388 | DWC2_HC_XFER_XACT_ERR); |
| 1389 | /* Todo: add support for isoc release */ |
| 1390 | goto handle_nyet_done; |
| 1391 | } |
| 1392 | } |
| 1393 | |
| 1394 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET); |
| 1395 | goto handle_nyet_done; |
| 1396 | } |
| 1397 | |
| 1398 | chan->qh->ping_state = 1; |
| 1399 | qtd->error_count = 0; |
| 1400 | |
| 1401 | dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd, |
| 1402 | DWC2_HC_XFER_NYET); |
| 1403 | dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); |
| 1404 | |
| 1405 | /* |
| 1406 | * Halt the channel and re-start the transfer so the PING protocol |
| 1407 | * will start |
| 1408 | */ |
| 1409 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET); |
| 1410 | |
| 1411 | handle_nyet_done: |
| 1412 | disable_hc_int(hsotg, chnum, HCINTMSK_NYET); |
| 1413 | } |
| 1414 | |
| 1415 | /* |
| 1416 | * Handles a host channel babble interrupt. This handler may be called in |
| 1417 | * either DMA mode or Slave mode. |
| 1418 | */ |
| 1419 | static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg, |
| 1420 | struct dwc2_host_chan *chan, int chnum, |
| 1421 | struct dwc2_qtd *qtd) |
| 1422 | { |
| 1423 | dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n", |
| 1424 | chnum); |
| 1425 | |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1426 | dwc2_hc_handle_tt_clear(hsotg, chan, qtd); |
| 1427 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1428 | if (hsotg->core_params->dma_desc_enable > 0) { |
| 1429 | dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, |
| 1430 | DWC2_HC_XFER_BABBLE_ERR); |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1431 | goto disable_int; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1432 | } |
| 1433 | |
| 1434 | if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) { |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1435 | dwc2_host_complete(hsotg, qtd, -EOVERFLOW); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1436 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR); |
| 1437 | } else { |
| 1438 | enum dwc2_halt_status halt_status; |
| 1439 | |
| 1440 | halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum, |
| 1441 | qtd, DWC2_HC_XFER_BABBLE_ERR); |
| 1442 | dwc2_halt_channel(hsotg, chan, qtd, halt_status); |
| 1443 | } |
| 1444 | |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1445 | disable_int: |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1446 | disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR); |
| 1447 | } |
| 1448 | |
| 1449 | /* |
| 1450 | * Handles a host channel AHB error interrupt. This handler is only called in |
| 1451 | * DMA mode. |
| 1452 | */ |
| 1453 | static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg, |
| 1454 | struct dwc2_host_chan *chan, int chnum, |
| 1455 | struct dwc2_qtd *qtd) |
| 1456 | { |
| 1457 | struct dwc2_hcd_urb *urb = qtd->urb; |
| 1458 | char *pipetype, *speed; |
| 1459 | u32 hcchar; |
| 1460 | u32 hcsplt; |
| 1461 | u32 hctsiz; |
| 1462 | u32 hc_dma; |
| 1463 | |
| 1464 | dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n", |
| 1465 | chnum); |
| 1466 | |
| 1467 | if (!urb) |
| 1468 | goto handle_ahberr_halt; |
| 1469 | |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1470 | dwc2_hc_handle_tt_clear(hsotg, chan, qtd); |
| 1471 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1472 | hcchar = readl(hsotg->regs + HCCHAR(chnum)); |
| 1473 | hcsplt = readl(hsotg->regs + HCSPLT(chnum)); |
| 1474 | hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); |
| 1475 | hc_dma = readl(hsotg->regs + HCDMA(chnum)); |
| 1476 | |
| 1477 | dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum); |
| 1478 | dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt); |
| 1479 | dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma); |
| 1480 | dev_err(hsotg->dev, " Device address: %d\n", |
| 1481 | dwc2_hcd_get_dev_addr(&urb->pipe_info)); |
| 1482 | dev_err(hsotg->dev, " Endpoint: %d, %s\n", |
| 1483 | dwc2_hcd_get_ep_num(&urb->pipe_info), |
| 1484 | dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); |
| 1485 | |
| 1486 | switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { |
| 1487 | case USB_ENDPOINT_XFER_CONTROL: |
| 1488 | pipetype = "CONTROL"; |
| 1489 | break; |
| 1490 | case USB_ENDPOINT_XFER_BULK: |
| 1491 | pipetype = "BULK"; |
| 1492 | break; |
| 1493 | case USB_ENDPOINT_XFER_INT: |
| 1494 | pipetype = "INTERRUPT"; |
| 1495 | break; |
| 1496 | case USB_ENDPOINT_XFER_ISOC: |
| 1497 | pipetype = "ISOCHRONOUS"; |
| 1498 | break; |
| 1499 | default: |
| 1500 | pipetype = "UNKNOWN"; |
| 1501 | break; |
| 1502 | } |
| 1503 | |
| 1504 | dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype); |
| 1505 | |
| 1506 | switch (chan->speed) { |
| 1507 | case USB_SPEED_HIGH: |
| 1508 | speed = "HIGH"; |
| 1509 | break; |
| 1510 | case USB_SPEED_FULL: |
| 1511 | speed = "FULL"; |
| 1512 | break; |
| 1513 | case USB_SPEED_LOW: |
| 1514 | speed = "LOW"; |
| 1515 | break; |
| 1516 | default: |
| 1517 | speed = "UNKNOWN"; |
| 1518 | break; |
| 1519 | } |
| 1520 | |
| 1521 | dev_err(hsotg->dev, " Speed: %s\n", speed); |
| 1522 | |
| 1523 | dev_err(hsotg->dev, " Max packet size: %d\n", |
| 1524 | dwc2_hcd_get_mps(&urb->pipe_info)); |
| 1525 | dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length); |
Paul Zimmerman | 157dfaa | 2013-03-14 13:12:00 -0700 | [diff] [blame] | 1526 | dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", |
| 1527 | urb->buf, (unsigned long)urb->dma); |
| 1528 | dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", |
| 1529 | urb->setup_packet, (unsigned long)urb->setup_dma); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1530 | dev_err(hsotg->dev, " Interval: %d\n", urb->interval); |
| 1531 | |
| 1532 | /* Core halts the channel for Descriptor DMA mode */ |
| 1533 | if (hsotg->core_params->dma_desc_enable > 0) { |
| 1534 | dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, |
| 1535 | DWC2_HC_XFER_AHB_ERR); |
| 1536 | goto handle_ahberr_done; |
| 1537 | } |
| 1538 | |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1539 | dwc2_host_complete(hsotg, qtd, -EIO); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1540 | |
| 1541 | handle_ahberr_halt: |
| 1542 | /* |
| 1543 | * Force a channel halt. Don't call dwc2_halt_channel because that won't |
| 1544 | * write to the HCCHARn register in DMA mode to force the halt. |
| 1545 | */ |
| 1546 | dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR); |
| 1547 | |
| 1548 | handle_ahberr_done: |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1549 | disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR); |
| 1550 | } |
| 1551 | |
| 1552 | /* |
| 1553 | * Handles a host channel transaction error interrupt. This handler may be |
| 1554 | * called in either DMA mode or Slave mode. |
| 1555 | */ |
| 1556 | static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg, |
| 1557 | struct dwc2_host_chan *chan, int chnum, |
| 1558 | struct dwc2_qtd *qtd) |
| 1559 | { |
| 1560 | dev_dbg(hsotg->dev, |
| 1561 | "--Host Channel %d Interrupt: Transaction Error--\n", chnum); |
| 1562 | |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1563 | dwc2_hc_handle_tt_clear(hsotg, chan, qtd); |
| 1564 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1565 | if (hsotg->core_params->dma_desc_enable > 0) { |
| 1566 | dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, |
| 1567 | DWC2_HC_XFER_XACT_ERR); |
| 1568 | goto handle_xacterr_done; |
| 1569 | } |
| 1570 | |
| 1571 | switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { |
| 1572 | case USB_ENDPOINT_XFER_CONTROL: |
| 1573 | case USB_ENDPOINT_XFER_BULK: |
| 1574 | qtd->error_count++; |
| 1575 | if (!chan->qh->ping_state) { |
| 1576 | |
| 1577 | dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, |
| 1578 | qtd, DWC2_HC_XFER_XACT_ERR); |
| 1579 | dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); |
| 1580 | if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH) |
| 1581 | chan->qh->ping_state = 1; |
| 1582 | } |
| 1583 | |
| 1584 | /* |
| 1585 | * Halt the channel so the transfer can be re-started from |
| 1586 | * the appropriate point or the PING protocol will start |
| 1587 | */ |
| 1588 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR); |
| 1589 | break; |
| 1590 | case USB_ENDPOINT_XFER_INT: |
| 1591 | qtd->error_count++; |
| 1592 | if (chan->do_split && chan->complete_split) |
| 1593 | qtd->complete_split = 0; |
| 1594 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR); |
| 1595 | break; |
| 1596 | case USB_ENDPOINT_XFER_ISOC: |
| 1597 | { |
| 1598 | enum dwc2_halt_status halt_status; |
| 1599 | |
| 1600 | halt_status = dwc2_update_isoc_urb_state(hsotg, chan, |
| 1601 | chnum, qtd, DWC2_HC_XFER_XACT_ERR); |
| 1602 | dwc2_halt_channel(hsotg, chan, qtd, halt_status); |
| 1603 | } |
| 1604 | break; |
| 1605 | } |
| 1606 | |
| 1607 | handle_xacterr_done: |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1608 | disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR); |
| 1609 | } |
| 1610 | |
| 1611 | /* |
| 1612 | * Handles a host channel frame overrun interrupt. This handler may be called |
| 1613 | * in either DMA mode or Slave mode. |
| 1614 | */ |
| 1615 | static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg, |
| 1616 | struct dwc2_host_chan *chan, int chnum, |
| 1617 | struct dwc2_qtd *qtd) |
| 1618 | { |
| 1619 | enum dwc2_halt_status halt_status; |
| 1620 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1621 | if (dbg_hc(chan)) |
| 1622 | dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n", |
| 1623 | chnum); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1624 | |
Paul Zimmerman | 0d012b9 | 2013-07-13 14:53:48 -0700 | [diff] [blame] | 1625 | dwc2_hc_handle_tt_clear(hsotg, chan, qtd); |
| 1626 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1627 | switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) { |
| 1628 | case USB_ENDPOINT_XFER_CONTROL: |
| 1629 | case USB_ENDPOINT_XFER_BULK: |
| 1630 | break; |
| 1631 | case USB_ENDPOINT_XFER_INT: |
| 1632 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN); |
| 1633 | break; |
| 1634 | case USB_ENDPOINT_XFER_ISOC: |
| 1635 | halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum, |
| 1636 | qtd, DWC2_HC_XFER_FRAME_OVERRUN); |
| 1637 | dwc2_halt_channel(hsotg, chan, qtd, halt_status); |
| 1638 | break; |
| 1639 | } |
| 1640 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1641 | disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN); |
| 1642 | } |
| 1643 | |
| 1644 | /* |
| 1645 | * Handles a host channel data toggle error interrupt. This handler may be |
| 1646 | * called in either DMA mode or Slave mode. |
| 1647 | */ |
| 1648 | static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg, |
| 1649 | struct dwc2_host_chan *chan, int chnum, |
| 1650 | struct dwc2_qtd *qtd) |
| 1651 | { |
| 1652 | dev_dbg(hsotg->dev, |
| 1653 | "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum); |
| 1654 | |
| 1655 | if (chan->ep_is_in) |
| 1656 | qtd->error_count = 0; |
| 1657 | else |
| 1658 | dev_err(hsotg->dev, |
| 1659 | "Data Toggle Error on OUT transfer, channel %d\n", |
| 1660 | chnum); |
| 1661 | |
| 1662 | dwc2_hc_handle_tt_clear(hsotg, chan, qtd); |
| 1663 | disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR); |
| 1664 | } |
| 1665 | |
| 1666 | /* |
| 1667 | * For debug only. It checks that a valid halt status is set and that |
| 1668 | * HCCHARn.chdis is clear. If there's a problem, corrective action is |
| 1669 | * taken and a warning is issued. |
| 1670 | * |
| 1671 | * Return: true if halt status is ok, false otherwise |
| 1672 | */ |
| 1673 | static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg, |
| 1674 | struct dwc2_host_chan *chan, int chnum, |
| 1675 | struct dwc2_qtd *qtd) |
| 1676 | { |
| 1677 | #ifdef DEBUG |
| 1678 | u32 hcchar; |
| 1679 | u32 hctsiz; |
| 1680 | u32 hcintmsk; |
| 1681 | u32 hcsplt; |
| 1682 | |
| 1683 | if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) { |
| 1684 | /* |
| 1685 | * This code is here only as a check. This condition should |
| 1686 | * never happen. Ignore the halt if it does occur. |
| 1687 | */ |
| 1688 | hcchar = readl(hsotg->regs + HCCHAR(chnum)); |
| 1689 | hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); |
| 1690 | hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); |
| 1691 | hcsplt = readl(hsotg->regs + HCSPLT(chnum)); |
| 1692 | dev_dbg(hsotg->dev, |
| 1693 | "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n", |
| 1694 | __func__); |
| 1695 | dev_dbg(hsotg->dev, |
| 1696 | "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n", |
| 1697 | chnum, hcchar, hctsiz); |
| 1698 | dev_dbg(hsotg->dev, |
| 1699 | "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n", |
| 1700 | chan->hcint, hcintmsk, hcsplt); |
Matthijs Kooijman | 8509f2f | 2013-03-25 12:00:25 -0700 | [diff] [blame] | 1701 | if (qtd) |
| 1702 | dev_dbg(hsotg->dev, "qtd->complete_split %d\n", |
| 1703 | qtd->complete_split); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1704 | dev_warn(hsotg->dev, |
| 1705 | "%s: no halt status, channel %d, ignoring interrupt\n", |
| 1706 | __func__, chnum); |
| 1707 | return false; |
| 1708 | } |
| 1709 | |
| 1710 | /* |
| 1711 | * This code is here only as a check. hcchar.chdis should never be set |
| 1712 | * when the halt interrupt occurs. Halt the channel again if it does |
| 1713 | * occur. |
| 1714 | */ |
| 1715 | hcchar = readl(hsotg->regs + HCCHAR(chnum)); |
| 1716 | if (hcchar & HCCHAR_CHDIS) { |
| 1717 | dev_warn(hsotg->dev, |
| 1718 | "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n", |
| 1719 | __func__, hcchar); |
| 1720 | chan->halt_pending = 0; |
| 1721 | dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status); |
| 1722 | return false; |
| 1723 | } |
| 1724 | #endif |
| 1725 | |
| 1726 | return true; |
| 1727 | } |
| 1728 | |
| 1729 | /* |
| 1730 | * Handles a host Channel Halted interrupt in DMA mode. This handler |
| 1731 | * determines the reason the channel halted and proceeds accordingly. |
| 1732 | */ |
| 1733 | static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg, |
| 1734 | struct dwc2_host_chan *chan, int chnum, |
| 1735 | struct dwc2_qtd *qtd) |
| 1736 | { |
| 1737 | u32 hcintmsk; |
| 1738 | int out_nak_enh = 0; |
| 1739 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1740 | if (dbg_hc(chan)) |
| 1741 | dev_vdbg(hsotg->dev, |
| 1742 | "--Host Channel %d Interrupt: DMA Channel Halted--\n", |
| 1743 | chnum); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1744 | |
| 1745 | /* |
| 1746 | * For core with OUT NAK enhancement, the flow for high-speed |
| 1747 | * CONTROL/BULK OUT is handled a little differently |
| 1748 | */ |
Matthijs Kooijman | 9badec2 | 2013-08-30 18:45:21 +0200 | [diff] [blame] | 1749 | if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) { |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1750 | if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in && |
| 1751 | (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || |
| 1752 | chan->ep_type == USB_ENDPOINT_XFER_BULK)) { |
| 1753 | out_nak_enh = 1; |
| 1754 | } |
| 1755 | } |
| 1756 | |
| 1757 | if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE || |
| 1758 | (chan->halt_status == DWC2_HC_XFER_AHB_ERR && |
| 1759 | hsotg->core_params->dma_desc_enable <= 0)) { |
| 1760 | if (hsotg->core_params->dma_desc_enable > 0) |
| 1761 | dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, |
| 1762 | chan->halt_status); |
| 1763 | else |
| 1764 | /* |
| 1765 | * Just release the channel. A dequeue can happen on a |
| 1766 | * transfer timeout. In the case of an AHB Error, the |
| 1767 | * channel was forced to halt because there's no way to |
| 1768 | * gracefully recover. |
| 1769 | */ |
| 1770 | dwc2_release_channel(hsotg, chan, qtd, |
| 1771 | chan->halt_status); |
| 1772 | return; |
| 1773 | } |
| 1774 | |
| 1775 | hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); |
| 1776 | |
| 1777 | if (chan->hcint & HCINTMSK_XFERCOMPL) { |
| 1778 | /* |
| 1779 | * Todo: This is here because of a possible hardware bug. Spec |
| 1780 | * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT |
| 1781 | * interrupt w/ACK bit set should occur, but I only see the |
| 1782 | * XFERCOMP bit, even with it masked out. This is a workaround |
| 1783 | * for that behavior. Should fix this when hardware is fixed. |
| 1784 | */ |
| 1785 | if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in) |
| 1786 | dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); |
| 1787 | dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd); |
| 1788 | } else if (chan->hcint & HCINTMSK_STALL) { |
| 1789 | dwc2_hc_stall_intr(hsotg, chan, chnum, qtd); |
| 1790 | } else if ((chan->hcint & HCINTMSK_XACTERR) && |
| 1791 | hsotg->core_params->dma_desc_enable <= 0) { |
| 1792 | if (out_nak_enh) { |
| 1793 | if (chan->hcint & |
| 1794 | (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) { |
| 1795 | dev_vdbg(hsotg->dev, |
| 1796 | "XactErr with NYET/NAK/ACK\n"); |
| 1797 | qtd->error_count = 0; |
| 1798 | } else { |
| 1799 | dev_vdbg(hsotg->dev, |
| 1800 | "XactErr without NYET/NAK/ACK\n"); |
| 1801 | } |
| 1802 | } |
| 1803 | |
| 1804 | /* |
| 1805 | * Must handle xacterr before nak or ack. Could get a xacterr |
| 1806 | * at the same time as either of these on a BULK/CONTROL OUT |
| 1807 | * that started with a PING. The xacterr takes precedence. |
| 1808 | */ |
| 1809 | dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); |
| 1810 | } else if ((chan->hcint & HCINTMSK_XCS_XACT) && |
| 1811 | hsotg->core_params->dma_desc_enable > 0) { |
| 1812 | dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); |
| 1813 | } else if ((chan->hcint & HCINTMSK_AHBERR) && |
| 1814 | hsotg->core_params->dma_desc_enable > 0) { |
| 1815 | dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd); |
| 1816 | } else if (chan->hcint & HCINTMSK_BBLERR) { |
| 1817 | dwc2_hc_babble_intr(hsotg, chan, chnum, qtd); |
| 1818 | } else if (chan->hcint & HCINTMSK_FRMOVRUN) { |
| 1819 | dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd); |
| 1820 | } else if (!out_nak_enh) { |
| 1821 | if (chan->hcint & HCINTMSK_NYET) { |
| 1822 | /* |
| 1823 | * Must handle nyet before nak or ack. Could get a nyet |
| 1824 | * at the same time as either of those on a BULK/CONTROL |
| 1825 | * OUT that started with a PING. The nyet takes |
| 1826 | * precedence. |
| 1827 | */ |
| 1828 | dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd); |
| 1829 | } else if ((chan->hcint & HCINTMSK_NAK) && |
| 1830 | !(hcintmsk & HCINTMSK_NAK)) { |
| 1831 | /* |
| 1832 | * If nak is not masked, it's because a non-split IN |
| 1833 | * transfer is in an error state. In that case, the nak |
| 1834 | * is handled by the nak interrupt handler, not here. |
| 1835 | * Handle nak here for BULK/CONTROL OUT transfers, which |
| 1836 | * halt on a NAK to allow rewinding the buffer pointer. |
| 1837 | */ |
| 1838 | dwc2_hc_nak_intr(hsotg, chan, chnum, qtd); |
| 1839 | } else if ((chan->hcint & HCINTMSK_ACK) && |
| 1840 | !(hcintmsk & HCINTMSK_ACK)) { |
| 1841 | /* |
| 1842 | * If ack is not masked, it's because a non-split IN |
| 1843 | * transfer is in an error state. In that case, the ack |
| 1844 | * is handled by the ack interrupt handler, not here. |
| 1845 | * Handle ack here for split transfers. Start splits |
| 1846 | * halt on ACK. |
| 1847 | */ |
| 1848 | dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); |
| 1849 | } else { |
| 1850 | if (chan->ep_type == USB_ENDPOINT_XFER_INT || |
| 1851 | chan->ep_type == USB_ENDPOINT_XFER_ISOC) { |
| 1852 | /* |
| 1853 | * A periodic transfer halted with no other |
| 1854 | * channel interrupts set. Assume it was halted |
| 1855 | * by the core because it could not be completed |
| 1856 | * in its scheduled (micro)frame. |
| 1857 | */ |
| 1858 | dev_dbg(hsotg->dev, |
| 1859 | "%s: Halt channel %d (assume incomplete periodic transfer)\n", |
| 1860 | __func__, chnum); |
| 1861 | dwc2_halt_channel(hsotg, chan, qtd, |
| 1862 | DWC2_HC_XFER_PERIODIC_INCOMPLETE); |
| 1863 | } else { |
| 1864 | dev_err(hsotg->dev, |
| 1865 | "%s: Channel %d - ChHltd set, but reason is unknown\n", |
| 1866 | __func__, chnum); |
| 1867 | dev_err(hsotg->dev, |
| 1868 | "hcint 0x%08x, intsts 0x%08x\n", |
| 1869 | chan->hcint, |
| 1870 | readl(hsotg->regs + GINTSTS)); |
Nick Hudson | 151d0cb | 2014-09-11 15:22:48 -0700 | [diff] [blame] | 1871 | goto error; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1872 | } |
| 1873 | } |
| 1874 | } else { |
| 1875 | dev_info(hsotg->dev, |
| 1876 | "NYET/NAK/ACK/other in non-error case, 0x%08x\n", |
| 1877 | chan->hcint); |
Nick Hudson | 151d0cb | 2014-09-11 15:22:48 -0700 | [diff] [blame] | 1878 | error: |
| 1879 | /* Failthrough: use 3-strikes rule */ |
| 1880 | qtd->error_count++; |
| 1881 | dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, |
| 1882 | qtd, DWC2_HC_XFER_XACT_ERR); |
| 1883 | dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd); |
| 1884 | dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1885 | } |
| 1886 | } |
| 1887 | |
| 1888 | /* |
| 1889 | * Handles a host channel Channel Halted interrupt |
| 1890 | * |
| 1891 | * In slave mode, this handler is called only when the driver specifically |
| 1892 | * requests a halt. This occurs during handling other host channel interrupts |
| 1893 | * (e.g. nak, xacterr, stall, nyet, etc.). |
| 1894 | * |
| 1895 | * In DMA mode, this is the interrupt that occurs when the core has finished |
| 1896 | * processing a transfer on a channel. Other host channel interrupts (except |
| 1897 | * ahberr) are disabled in DMA mode. |
| 1898 | */ |
| 1899 | static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg, |
| 1900 | struct dwc2_host_chan *chan, int chnum, |
| 1901 | struct dwc2_qtd *qtd) |
| 1902 | { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1903 | if (dbg_hc(chan)) |
| 1904 | dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n", |
| 1905 | chnum); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1906 | |
| 1907 | if (hsotg->core_params->dma_enable > 0) { |
| 1908 | dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd); |
| 1909 | } else { |
| 1910 | if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd)) |
| 1911 | return; |
| 1912 | dwc2_release_channel(hsotg, chan, qtd, chan->halt_status); |
| 1913 | } |
| 1914 | } |
| 1915 | |
| 1916 | /* Handles interrupt for a specific Host Channel */ |
| 1917 | static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum) |
| 1918 | { |
| 1919 | struct dwc2_qtd *qtd; |
| 1920 | struct dwc2_host_chan *chan; |
| 1921 | u32 hcint, hcintmsk; |
| 1922 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 1923 | chan = hsotg->hc_ptr_array[chnum]; |
| 1924 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1925 | hcint = readl(hsotg->regs + HCINT(chnum)); |
| 1926 | hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1927 | if (!chan) { |
| 1928 | dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n"); |
| 1929 | writel(hcint, hsotg->regs + HCINT(chnum)); |
| 1930 | return; |
| 1931 | } |
| 1932 | |
Rashika Kheria | 723a231 | 2013-10-30 04:16:55 +0530 | [diff] [blame] | 1933 | if (dbg_hc(chan)) { |
| 1934 | dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n", |
| 1935 | chnum); |
| 1936 | dev_vdbg(hsotg->dev, |
| 1937 | " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", |
| 1938 | hcint, hcintmsk, hcint & hcintmsk); |
| 1939 | } |
| 1940 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1941 | writel(hcint, hsotg->regs + HCINT(chnum)); |
| 1942 | chan->hcint = hcint; |
| 1943 | hcint &= hcintmsk; |
| 1944 | |
Matthijs Kooijman | 8509f2f | 2013-03-25 12:00:25 -0700 | [diff] [blame] | 1945 | /* |
| 1946 | * If the channel was halted due to a dequeue, the qtd list might |
| 1947 | * be empty or at least the first entry will not be the active qtd. |
| 1948 | * In this case, take a shortcut and just release the channel. |
| 1949 | */ |
| 1950 | if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) { |
| 1951 | /* |
| 1952 | * If the channel was halted, this should be the only |
| 1953 | * interrupt unmasked |
| 1954 | */ |
| 1955 | WARN_ON(hcint != HCINTMSK_CHHLTD); |
| 1956 | if (hsotg->core_params->dma_desc_enable > 0) |
| 1957 | dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, |
| 1958 | chan->halt_status); |
| 1959 | else |
| 1960 | dwc2_release_channel(hsotg, chan, NULL, |
| 1961 | chan->halt_status); |
| 1962 | return; |
| 1963 | } |
| 1964 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1965 | if (list_empty(&chan->qh->qtd_list)) { |
Matthijs Kooijman | 8509f2f | 2013-03-25 12:00:25 -0700 | [diff] [blame] | 1966 | /* |
| 1967 | * TODO: Will this ever happen with the |
| 1968 | * DWC2_HC_XFER_URB_DEQUEUE handling above? |
| 1969 | */ |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 1970 | dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n", |
| 1971 | chnum); |
| 1972 | dev_dbg(hsotg->dev, |
| 1973 | " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", |
| 1974 | chan->hcint, hcintmsk, hcint); |
| 1975 | chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; |
| 1976 | disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD); |
| 1977 | chan->hcint = 0; |
| 1978 | return; |
| 1979 | } |
| 1980 | |
| 1981 | qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd, |
| 1982 | qtd_list_entry); |
| 1983 | |
| 1984 | if (hsotg->core_params->dma_enable <= 0) { |
| 1985 | if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD) |
| 1986 | hcint &= ~HCINTMSK_CHHLTD; |
| 1987 | } |
| 1988 | |
| 1989 | if (hcint & HCINTMSK_XFERCOMPL) { |
| 1990 | dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd); |
| 1991 | /* |
| 1992 | * If NYET occurred at same time as Xfer Complete, the NYET is |
| 1993 | * handled by the Xfer Complete interrupt handler. Don't want |
| 1994 | * to call the NYET interrupt handler in this case. |
| 1995 | */ |
| 1996 | hcint &= ~HCINTMSK_NYET; |
| 1997 | } |
| 1998 | if (hcint & HCINTMSK_CHHLTD) |
| 1999 | dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd); |
| 2000 | if (hcint & HCINTMSK_AHBERR) |
| 2001 | dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd); |
| 2002 | if (hcint & HCINTMSK_STALL) |
| 2003 | dwc2_hc_stall_intr(hsotg, chan, chnum, qtd); |
| 2004 | if (hcint & HCINTMSK_NAK) |
| 2005 | dwc2_hc_nak_intr(hsotg, chan, chnum, qtd); |
| 2006 | if (hcint & HCINTMSK_ACK) |
| 2007 | dwc2_hc_ack_intr(hsotg, chan, chnum, qtd); |
| 2008 | if (hcint & HCINTMSK_NYET) |
| 2009 | dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd); |
| 2010 | if (hcint & HCINTMSK_XACTERR) |
| 2011 | dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd); |
| 2012 | if (hcint & HCINTMSK_BBLERR) |
| 2013 | dwc2_hc_babble_intr(hsotg, chan, chnum, qtd); |
| 2014 | if (hcint & HCINTMSK_FRMOVRUN) |
| 2015 | dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd); |
| 2016 | if (hcint & HCINTMSK_DATATGLERR) |
| 2017 | dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd); |
| 2018 | |
| 2019 | chan->hcint = 0; |
| 2020 | } |
| 2021 | |
| 2022 | /* |
| 2023 | * This interrupt indicates that one or more host channels has a pending |
| 2024 | * interrupt. There are multiple conditions that can cause each host channel |
| 2025 | * interrupt. This function determines which conditions have occurred for each |
| 2026 | * host channel interrupt and handles them appropriately. |
| 2027 | */ |
| 2028 | static void dwc2_hc_intr(struct dwc2_hsotg *hsotg) |
| 2029 | { |
| 2030 | u32 haint; |
| 2031 | int i; |
| 2032 | |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 2033 | haint = readl(hsotg->regs + HAINT); |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 2034 | if (dbg_perio()) { |
| 2035 | dev_vdbg(hsotg->dev, "%s()\n", __func__); |
| 2036 | |
| 2037 | dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint); |
| 2038 | } |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 2039 | |
| 2040 | for (i = 0; i < hsotg->core_params->host_channels; i++) { |
| 2041 | if (haint & (1 << i)) |
| 2042 | dwc2_hc_n_intr(hsotg, i); |
| 2043 | } |
| 2044 | } |
| 2045 | |
| 2046 | /* This function handles interrupts for the HCD */ |
Matthijs Kooijman | ca18f4a | 2013-04-25 23:39:15 +0200 | [diff] [blame] | 2047 | irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg) |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 2048 | { |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 2049 | u32 gintsts, dbg_gintsts; |
Matthijs Kooijman | 6aafb00 | 2013-04-25 23:39:14 +0200 | [diff] [blame] | 2050 | irqreturn_t retval = IRQ_NONE; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 2051 | |
Paul Zimmerman | 54216ac | 2013-11-25 13:42:44 -0800 | [diff] [blame] | 2052 | if (!dwc2_is_controller_alive(hsotg)) { |
Paul Zimmerman | 057715f | 2013-11-22 16:43:51 -0800 | [diff] [blame] | 2053 | dev_warn(hsotg->dev, "Controller is dead\n"); |
Matthijs Kooijman | 6aafb00 | 2013-04-25 23:39:14 +0200 | [diff] [blame] | 2054 | return retval; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 2055 | } |
| 2056 | |
| 2057 | spin_lock(&hsotg->lock); |
| 2058 | |
| 2059 | /* Check if HOST Mode */ |
| 2060 | if (dwc2_is_host_mode(hsotg)) { |
| 2061 | gintsts = dwc2_read_core_intr(hsotg); |
| 2062 | if (!gintsts) { |
| 2063 | spin_unlock(&hsotg->lock); |
Matthijs Kooijman | 6aafb00 | 2013-04-25 23:39:14 +0200 | [diff] [blame] | 2064 | return retval; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 2065 | } |
| 2066 | |
Matthijs Kooijman | 6aafb00 | 2013-04-25 23:39:14 +0200 | [diff] [blame] | 2067 | retval = IRQ_HANDLED; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 2068 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 2069 | dbg_gintsts = gintsts; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 2070 | #ifndef DEBUG_SOF |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 2071 | dbg_gintsts &= ~GINTSTS_SOF; |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 2072 | #endif |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 2073 | if (!dbg_perio()) |
| 2074 | dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL | |
| 2075 | GINTSTS_PTXFEMP); |
| 2076 | |
| 2077 | /* Only print if there are any non-suppressed interrupts left */ |
| 2078 | if (dbg_gintsts) |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 2079 | dev_vdbg(hsotg->dev, |
| 2080 | "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", |
| 2081 | gintsts); |
| 2082 | |
| 2083 | if (gintsts & GINTSTS_SOF) |
| 2084 | dwc2_sof_intr(hsotg); |
| 2085 | if (gintsts & GINTSTS_RXFLVL) |
| 2086 | dwc2_rx_fifo_level_intr(hsotg); |
| 2087 | if (gintsts & GINTSTS_NPTXFEMP) |
| 2088 | dwc2_np_tx_fifo_empty_intr(hsotg); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 2089 | if (gintsts & GINTSTS_PRTINT) |
| 2090 | dwc2_port_intr(hsotg); |
| 2091 | if (gintsts & GINTSTS_HCHINT) |
| 2092 | dwc2_hc_intr(hsotg); |
| 2093 | if (gintsts & GINTSTS_PTXFEMP) |
| 2094 | dwc2_perio_tx_fifo_empty_intr(hsotg); |
| 2095 | |
Matthijs Kooijman | b49977a | 2013-04-10 09:55:50 +0200 | [diff] [blame] | 2096 | if (dbg_gintsts) { |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 2097 | dev_vdbg(hsotg->dev, |
| 2098 | "DWC OTG HCD Finished Servicing Interrupts\n"); |
| 2099 | dev_vdbg(hsotg->dev, |
| 2100 | "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n", |
| 2101 | readl(hsotg->regs + GINTSTS), |
| 2102 | readl(hsotg->regs + GINTMSK)); |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 2103 | } |
Paul Zimmerman | 7359d48 | 2013-03-11 17:47:59 -0700 | [diff] [blame] | 2104 | } |
| 2105 | |
| 2106 | spin_unlock(&hsotg->lock); |
| 2107 | |
| 2108 | return retval; |
| 2109 | } |