| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* arch/arm/mach-sa1100/include/mach/debug-macro.S |
| 2 | * |
| 3 | * Debugging macro include header |
| 4 | * |
| 5 | * Copyright (C) 1994-1999 Russell King |
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | */ |
| 13 | #include <mach/hardware.h> |
| 14 | |
| Nicolas Pitre | 639da5e | 2011-08-31 22:55:46 -0400 | [diff] [blame] | 15 | .macro addruart, rp, rv, tmp |
| Jeremy Kerr | 0ea1293 | 2010-07-06 18:30:06 +0800 | [diff] [blame] | 16 | mrc p15, 0, \rp, c1, c0 |
| 17 | tst \rp, #1 @ MMU enabled? |
| 18 | moveq \rp, #0x80000000 @ physical base address |
| 19 | movne \rp, #0xf8000000 @ virtual address |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 20 | |
| 21 | @ We probe for the active serial port here, coherently with |
| 22 | @ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h. |
| 23 | @ We assume r1 can be clobbered. |
| 24 | |
| 25 | @ see if Ser3 is active |
| Jeremy Kerr | 0ea1293 | 2010-07-06 18:30:06 +0800 | [diff] [blame] | 26 | add \rp, \rp, #0x00050000 |
| 27 | ldr \rv, [\rp, #UTCR3] |
| 28 | tst \rv, #UTCR3_TXE |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 29 | |
| 30 | @ if Ser3 is inactive, then try Ser1 |
| Jeremy Kerr | 0ea1293 | 2010-07-06 18:30:06 +0800 | [diff] [blame] | 31 | addeq \rp, \rp, #(0x00010000 - 0x00050000) |
| 32 | ldreq \rv, [\rp, #UTCR3] |
| 33 | tsteq \rv, #UTCR3_TXE |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 34 | |
| 35 | @ if Ser1 is inactive, then try Ser2 |
| Jeremy Kerr | 0ea1293 | 2010-07-06 18:30:06 +0800 | [diff] [blame] | 36 | addeq \rp, \rp, #(0x00030000 - 0x00010000) |
| 37 | ldreq \rv, [\rp, #UTCR3] |
| 38 | tsteq \rv, #UTCR3_TXE |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 39 | |
| Jeremy Kerr | 0ea1293 | 2010-07-06 18:30:06 +0800 | [diff] [blame] | 40 | @ clear top bits, and generate both phys and virt addresses |
| 41 | lsl \rp, \rp, #8 |
| 42 | lsr \rp, \rp, #8 |
| 43 | orr \rv, \rp, #0xf8000000 @ virtual |
| 44 | orr \rp, \rp, #0x80000000 @ physical |
| 45 | |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 46 | .endm |
| 47 | |
| 48 | .macro senduart,rd,rx |
| 49 | str \rd, [\rx, #UTDR] |
| 50 | .endm |
| 51 | |
| 52 | .macro waituart,rd,rx |
| 53 | 1001: ldr \rd, [\rx, #UTSR1] |
| 54 | tst \rd, #UTSR1_TNF |
| 55 | beq 1001b |
| 56 | .endm |
| 57 | |
| 58 | .macro busyuart,rd,rx |
| 59 | 1001: ldr \rd, [\rx, #UTSR1] |
| 60 | tst \rd, #UTSR1_TBY |
| 61 | bne 1001b |
| 62 | .endm |