Yinghai Lu | 5aeecaf | 2008-08-19 20:49:59 -0700 | [diff] [blame] | 1 | #include <linux/interrupt.h> |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 2 | #include <linux/dmar.h> |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 3 | #include <linux/spinlock.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 4 | #include <linux/slab.h> |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 5 | #include <linux/jiffies.h> |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 6 | #include <linux/hpet.h> |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 7 | #include <linux/pci.h> |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 8 | #include <linux/irq.h> |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 9 | #include <asm/io_apic.h> |
Yinghai Lu | 17483a1 | 2008-12-12 13:14:18 -0800 | [diff] [blame] | 10 | #include <asm/smp.h> |
Jaswinder Singh Rajput | 6d652ea | 2009-01-07 21:38:59 +0530 | [diff] [blame] | 11 | #include <asm/cpu.h> |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 12 | #include <linux/intel-iommu.h> |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 13 | #include "intr_remapping.h" |
Alexander Beregalov | 46f06b72 | 2009-04-06 16:45:28 +0100 | [diff] [blame] | 14 | #include <acpi/acpi.h> |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 15 | #include <asm/pci-direct.h> |
| 16 | #include "pci.h" |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 17 | |
| 18 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 19 | static struct hpet_scope ir_hpet[MAX_HPET_TBS]; |
| 20 | static int ir_ioapic_num, ir_hpet_num; |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 21 | int intr_remapping_enabled; |
| 22 | |
Weidong Han | 03ea815 | 2009-04-17 16:42:15 +0800 | [diff] [blame] | 23 | static int disable_intremap; |
Chris Wright | d1423d5 | 2010-07-20 11:06:49 -0700 | [diff] [blame] | 24 | static int disable_sourceid_checking; |
| 25 | |
Weidong Han | 03ea815 | 2009-04-17 16:42:15 +0800 | [diff] [blame] | 26 | static __init int setup_nointremap(char *str) |
| 27 | { |
| 28 | disable_intremap = 1; |
| 29 | return 0; |
| 30 | } |
| 31 | early_param("nointremap", setup_nointremap); |
| 32 | |
Chris Wright | d1423d5 | 2010-07-20 11:06:49 -0700 | [diff] [blame] | 33 | static __init int setup_intremap(char *str) |
| 34 | { |
| 35 | if (!str) |
| 36 | return -EINVAL; |
| 37 | |
| 38 | if (!strncmp(str, "on", 2)) |
| 39 | disable_intremap = 0; |
| 40 | else if (!strncmp(str, "off", 3)) |
| 41 | disable_intremap = 1; |
| 42 | else if (!strncmp(str, "nosid", 5)) |
| 43 | disable_sourceid_checking = 1; |
| 44 | |
| 45 | return 0; |
| 46 | } |
| 47 | early_param("intremap", setup_intremap); |
| 48 | |
Yinghai Lu | 5aeecaf | 2008-08-19 20:49:59 -0700 | [diff] [blame] | 49 | struct irq_2_iommu { |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 50 | struct intel_iommu *iommu; |
| 51 | u16 irte_index; |
| 52 | u16 sub_handle; |
| 53 | u8 irte_mask; |
Yinghai Lu | 5aeecaf | 2008-08-19 20:49:59 -0700 | [diff] [blame] | 54 | }; |
| 55 | |
Yinghai Lu | d7e51e6 | 2009-01-07 15:03:13 -0800 | [diff] [blame] | 56 | #ifdef CONFIG_GENERIC_HARDIRQS |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 57 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) |
| 58 | { |
Thomas Gleixner | a8ef54a | 2010-10-04 16:51:27 +0200 | [diff] [blame^] | 59 | return get_irq_iommu(irq); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 60 | } |
| 61 | |
Yinghai Lu | 70590ea | 2009-08-26 16:21:54 -0700 | [diff] [blame] | 62 | static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq) |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 63 | { |
Thomas Gleixner | a8ef54a | 2010-10-04 16:51:27 +0200 | [diff] [blame^] | 64 | struct irq_data *data = irq_get_irq_data(irq); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 65 | |
Thomas Gleixner | a8ef54a | 2010-10-04 16:51:27 +0200 | [diff] [blame^] | 66 | if (WARN_ONCE(data->irq_2_iommu, |
| 67 | KERN_DEBUG "irq_2_iommu!=NULL irq %u\n", irq)) |
| 68 | return data->irq_2_iommu; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 69 | |
Thomas Gleixner | a8ef54a | 2010-10-04 16:51:27 +0200 | [diff] [blame^] | 70 | data->irq_2_iommu = kzalloc_node(sizeof(*data->irq_2_iommu), |
| 71 | GFP_ATOMIC, data->node); |
| 72 | return data->irq_2_iommu; |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 73 | } |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 74 | |
Thomas Gleixner | 0e1e367 | 2010-10-04 16:20:16 +0200 | [diff] [blame] | 75 | static void irq_2_iommu_free(unsigned int irq) |
| 76 | { |
| 77 | struct irq_data *d = irq_get_irq_data(irq); |
| 78 | struct irq_2_iommu *p = d->irq_2_iommu; |
| 79 | |
| 80 | d->irq_2_iommu = NULL; |
| 81 | kfree(p); |
| 82 | } |
| 83 | |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 84 | #else /* !CONFIG_SPARSE_IRQ */ |
| 85 | |
| 86 | static struct irq_2_iommu irq_2_iommuX[NR_IRQS]; |
| 87 | |
| 88 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) |
| 89 | { |
| 90 | if (irq < nr_irqs) |
| 91 | return &irq_2_iommuX[irq]; |
| 92 | |
| 93 | return NULL; |
| 94 | } |
| 95 | static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq) |
| 96 | { |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 97 | return irq_2_iommu(irq); |
| 98 | } |
Thomas Gleixner | 0e1e367 | 2010-10-04 16:20:16 +0200 | [diff] [blame] | 99 | |
| 100 | static void irq_2_iommu_free(unsigned int irq) { } |
| 101 | |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 102 | #endif |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 103 | |
| 104 | static DEFINE_SPINLOCK(irq_2_ir_lock); |
| 105 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 106 | static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq) |
| 107 | { |
| 108 | struct irq_2_iommu *irq_iommu; |
| 109 | |
| 110 | irq_iommu = irq_2_iommu(irq); |
| 111 | |
| 112 | if (!irq_iommu) |
| 113 | return NULL; |
| 114 | |
| 115 | if (!irq_iommu->iommu) |
| 116 | return NULL; |
| 117 | |
| 118 | return irq_iommu; |
| 119 | } |
| 120 | |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 121 | int irq_remapped(int irq) |
| 122 | { |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 123 | return valid_irq_2_iommu(irq) != NULL; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | int get_irte(int irq, struct irte *entry) |
| 127 | { |
| 128 | int index; |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 129 | struct irq_2_iommu *irq_iommu; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 130 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 131 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 132 | if (!entry) |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 133 | return -1; |
| 134 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 135 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 136 | irq_iommu = valid_irq_2_iommu(irq); |
| 137 | if (!irq_iommu) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 138 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 139 | return -1; |
| 140 | } |
| 141 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 142 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
| 143 | *entry = *(irq_iommu->iommu->ir_table->base + index); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 144 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 145 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 146 | return 0; |
| 147 | } |
| 148 | |
| 149 | int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) |
| 150 | { |
| 151 | struct ir_table *table = iommu->ir_table; |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 152 | struct irq_2_iommu *irq_iommu; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 153 | u16 index, start_index; |
| 154 | unsigned int mask = 0; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 155 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 156 | int i; |
| 157 | |
| 158 | if (!count) |
| 159 | return -1; |
| 160 | |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 161 | #ifndef CONFIG_SPARSE_IRQ |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 162 | /* protect irq_2_iommu_alloc later */ |
| 163 | if (irq >= nr_irqs) |
| 164 | return -1; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 165 | #endif |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 166 | |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 167 | /* |
| 168 | * start the IRTE search from index 0. |
| 169 | */ |
| 170 | index = start_index = 0; |
| 171 | |
| 172 | if (count > 1) { |
| 173 | count = __roundup_pow_of_two(count); |
| 174 | mask = ilog2(count); |
| 175 | } |
| 176 | |
| 177 | if (mask > ecap_max_handle_mask(iommu->ecap)) { |
| 178 | printk(KERN_ERR |
| 179 | "Requested mask %x exceeds the max invalidation handle" |
| 180 | " mask value %Lx\n", mask, |
| 181 | ecap_max_handle_mask(iommu->ecap)); |
| 182 | return -1; |
| 183 | } |
| 184 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 185 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 186 | do { |
| 187 | for (i = index; i < index + count; i++) |
| 188 | if (table->base[i].present) |
| 189 | break; |
| 190 | /* empty index found */ |
| 191 | if (i == index + count) |
| 192 | break; |
| 193 | |
| 194 | index = (index + count) % INTR_REMAP_TABLE_ENTRIES; |
| 195 | |
| 196 | if (index == start_index) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 197 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 198 | printk(KERN_ERR "can't allocate an IRTE\n"); |
| 199 | return -1; |
| 200 | } |
| 201 | } while (1); |
| 202 | |
| 203 | for (i = index; i < index + count; i++) |
| 204 | table->base[i].present = 1; |
| 205 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 206 | irq_iommu = irq_2_iommu_alloc(irq); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 207 | if (!irq_iommu) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 208 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 209 | printk(KERN_ERR "can't allocate irq_2_iommu\n"); |
| 210 | return -1; |
| 211 | } |
| 212 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 213 | irq_iommu->iommu = iommu; |
| 214 | irq_iommu->irte_index = index; |
| 215 | irq_iommu->sub_handle = 0; |
| 216 | irq_iommu->irte_mask = mask; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 217 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 218 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 219 | |
| 220 | return index; |
| 221 | } |
| 222 | |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 223 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 224 | { |
| 225 | struct qi_desc desc; |
| 226 | |
| 227 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) |
| 228 | | QI_IEC_SELECTIVE; |
| 229 | desc.high = 0; |
| 230 | |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 231 | return qi_submit_sync(&desc, iommu); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 232 | } |
| 233 | |
| 234 | int map_irq_to_irte_handle(int irq, u16 *sub_handle) |
| 235 | { |
| 236 | int index; |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 237 | struct irq_2_iommu *irq_iommu; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 238 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 239 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 240 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 241 | irq_iommu = valid_irq_2_iommu(irq); |
| 242 | if (!irq_iommu) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 243 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 244 | return -1; |
| 245 | } |
| 246 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 247 | *sub_handle = irq_iommu->sub_handle; |
| 248 | index = irq_iommu->irte_index; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 249 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 250 | return index; |
| 251 | } |
| 252 | |
| 253 | int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) |
| 254 | { |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 255 | struct irq_2_iommu *irq_iommu; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 256 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 257 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 258 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Suresh Siddha | 7ddfb65 | 2008-08-20 17:22:51 -0700 | [diff] [blame] | 259 | |
| 260 | irq_iommu = irq_2_iommu_alloc(irq); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 261 | |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 262 | if (!irq_iommu) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 263 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 264 | printk(KERN_ERR "can't allocate irq_2_iommu\n"); |
| 265 | return -1; |
| 266 | } |
| 267 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 268 | irq_iommu->iommu = iommu; |
| 269 | irq_iommu->irte_index = index; |
| 270 | irq_iommu->sub_handle = subhandle; |
| 271 | irq_iommu->irte_mask = 0; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 272 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 273 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 274 | |
| 275 | return 0; |
| 276 | } |
| 277 | |
| 278 | int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index) |
| 279 | { |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 280 | struct irq_2_iommu *irq_iommu; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 281 | unsigned long flags; |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 282 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 283 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 284 | irq_iommu = valid_irq_2_iommu(irq); |
| 285 | if (!irq_iommu) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 286 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 287 | return -1; |
| 288 | } |
| 289 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 290 | irq_iommu->iommu = NULL; |
| 291 | irq_iommu->irte_index = 0; |
| 292 | irq_iommu->sub_handle = 0; |
| 293 | irq_2_iommu(irq)->irte_mask = 0; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 294 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 295 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 296 | |
| 297 | return 0; |
| 298 | } |
| 299 | |
| 300 | int modify_irte(int irq, struct irte *irte_modified) |
| 301 | { |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 302 | int rc; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 303 | int index; |
| 304 | struct irte *irte; |
| 305 | struct intel_iommu *iommu; |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 306 | struct irq_2_iommu *irq_iommu; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 307 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 308 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 309 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 310 | irq_iommu = valid_irq_2_iommu(irq); |
| 311 | if (!irq_iommu) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 312 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 313 | return -1; |
| 314 | } |
| 315 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 316 | iommu = irq_iommu->iommu; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 317 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 318 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 319 | irte = &iommu->ir_table->base[index]; |
| 320 | |
Linus Torvalds | c513b67 | 2010-08-06 11:02:31 -0700 | [diff] [blame] | 321 | set_64bit(&irte->low, irte_modified->low); |
| 322 | set_64bit(&irte->high, irte_modified->high); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 323 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
| 324 | |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 325 | rc = qi_flush_iec(iommu, index, 0); |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 326 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 327 | |
| 328 | return rc; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 329 | } |
| 330 | |
| 331 | int flush_irte(int irq) |
| 332 | { |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 333 | int rc; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 334 | int index; |
| 335 | struct intel_iommu *iommu; |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 336 | struct irq_2_iommu *irq_iommu; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 337 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 338 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 339 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 340 | irq_iommu = valid_irq_2_iommu(irq); |
| 341 | if (!irq_iommu) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 342 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 343 | return -1; |
| 344 | } |
| 345 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 346 | iommu = irq_iommu->iommu; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 347 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 348 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 349 | |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 350 | rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask); |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 351 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 352 | |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 353 | return rc; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 354 | } |
| 355 | |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 356 | struct intel_iommu *map_hpet_to_ir(u8 hpet_id) |
| 357 | { |
| 358 | int i; |
| 359 | |
| 360 | for (i = 0; i < MAX_HPET_TBS; i++) |
| 361 | if (ir_hpet[i].id == hpet_id) |
| 362 | return ir_hpet[i].iommu; |
| 363 | return NULL; |
| 364 | } |
| 365 | |
Suresh Siddha | 89027d3 | 2008-07-10 11:16:56 -0700 | [diff] [blame] | 366 | struct intel_iommu *map_ioapic_to_ir(int apic) |
| 367 | { |
| 368 | int i; |
| 369 | |
| 370 | for (i = 0; i < MAX_IO_APICS; i++) |
| 371 | if (ir_ioapic[i].id == apic) |
| 372 | return ir_ioapic[i].iommu; |
| 373 | return NULL; |
| 374 | } |
| 375 | |
Suresh Siddha | 75c46fa | 2008-07-10 11:16:57 -0700 | [diff] [blame] | 376 | struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
| 377 | { |
| 378 | struct dmar_drhd_unit *drhd; |
| 379 | |
| 380 | drhd = dmar_find_matched_drhd_unit(dev); |
| 381 | if (!drhd) |
| 382 | return NULL; |
| 383 | |
| 384 | return drhd->iommu; |
| 385 | } |
| 386 | |
Weidong Han | c4658b4 | 2009-05-23 00:41:14 +0800 | [diff] [blame] | 387 | static int clear_entries(struct irq_2_iommu *irq_iommu) |
| 388 | { |
| 389 | struct irte *start, *entry, *end; |
| 390 | struct intel_iommu *iommu; |
| 391 | int index; |
| 392 | |
| 393 | if (irq_iommu->sub_handle) |
| 394 | return 0; |
| 395 | |
| 396 | iommu = irq_iommu->iommu; |
| 397 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
| 398 | |
| 399 | start = iommu->ir_table->base + index; |
| 400 | end = start + (1 << irq_iommu->irte_mask); |
| 401 | |
| 402 | for (entry = start; entry < end; entry++) { |
Linus Torvalds | c513b67 | 2010-08-06 11:02:31 -0700 | [diff] [blame] | 403 | set_64bit(&entry->low, 0); |
| 404 | set_64bit(&entry->high, 0); |
Weidong Han | c4658b4 | 2009-05-23 00:41:14 +0800 | [diff] [blame] | 405 | } |
| 406 | |
| 407 | return qi_flush_iec(iommu, index, irq_iommu->irte_mask); |
| 408 | } |
| 409 | |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 410 | int free_irte(int irq) |
| 411 | { |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 412 | int rc = 0; |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 413 | struct irq_2_iommu *irq_iommu; |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 414 | unsigned long flags; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 415 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 416 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 417 | irq_iommu = valid_irq_2_iommu(irq); |
| 418 | if (!irq_iommu) { |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 419 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 420 | return -1; |
| 421 | } |
| 422 | |
Weidong Han | c4658b4 | 2009-05-23 00:41:14 +0800 | [diff] [blame] | 423 | rc = clear_entries(irq_iommu); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 424 | |
Yinghai Lu | e420dfb | 2008-08-19 20:50:21 -0700 | [diff] [blame] | 425 | irq_iommu->iommu = NULL; |
| 426 | irq_iommu->irte_index = 0; |
| 427 | irq_iommu->sub_handle = 0; |
| 428 | irq_iommu->irte_mask = 0; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 429 | |
Suresh Siddha | 4c5502b | 2009-03-16 17:04:53 -0700 | [diff] [blame] | 430 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 431 | |
Thomas Gleixner | 0e1e367 | 2010-10-04 16:20:16 +0200 | [diff] [blame] | 432 | irq_2_iommu_free(irq); |
| 433 | |
Yu Zhao | 704126a | 2009-01-04 16:28:52 +0800 | [diff] [blame] | 434 | return rc; |
Suresh Siddha | b6fcb33 | 2008-07-10 11:16:44 -0700 | [diff] [blame] | 435 | } |
| 436 | |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 437 | /* |
| 438 | * source validation type |
| 439 | */ |
| 440 | #define SVT_NO_VERIFY 0x0 /* no verification is required */ |
| 441 | #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fiels */ |
| 442 | #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ |
| 443 | |
| 444 | /* |
| 445 | * source-id qualifier |
| 446 | */ |
| 447 | #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ |
| 448 | #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore |
| 449 | * the third least significant bit |
| 450 | */ |
| 451 | #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore |
| 452 | * the second and third least significant bits |
| 453 | */ |
| 454 | #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore |
| 455 | * the least three significant bits |
| 456 | */ |
| 457 | |
| 458 | /* |
| 459 | * set SVT, SQ and SID fields of irte to verify |
| 460 | * source ids of interrupt requests |
| 461 | */ |
| 462 | static void set_irte_sid(struct irte *irte, unsigned int svt, |
| 463 | unsigned int sq, unsigned int sid) |
| 464 | { |
Chris Wright | d1423d5 | 2010-07-20 11:06:49 -0700 | [diff] [blame] | 465 | if (disable_sourceid_checking) |
| 466 | svt = SVT_NO_VERIFY; |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 467 | irte->svt = svt; |
| 468 | irte->sq = sq; |
| 469 | irte->sid = sid; |
| 470 | } |
| 471 | |
| 472 | int set_ioapic_sid(struct irte *irte, int apic) |
| 473 | { |
| 474 | int i; |
| 475 | u16 sid = 0; |
| 476 | |
| 477 | if (!irte) |
| 478 | return -1; |
| 479 | |
| 480 | for (i = 0; i < MAX_IO_APICS; i++) { |
| 481 | if (ir_ioapic[i].id == apic) { |
| 482 | sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; |
| 483 | break; |
| 484 | } |
| 485 | } |
| 486 | |
| 487 | if (sid == 0) { |
| 488 | pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic); |
| 489 | return -1; |
| 490 | } |
| 491 | |
| 492 | set_irte_sid(irte, 1, 0, sid); |
| 493 | |
| 494 | return 0; |
| 495 | } |
| 496 | |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 497 | int set_hpet_sid(struct irte *irte, u8 id) |
| 498 | { |
| 499 | int i; |
| 500 | u16 sid = 0; |
| 501 | |
| 502 | if (!irte) |
| 503 | return -1; |
| 504 | |
| 505 | for (i = 0; i < MAX_HPET_TBS; i++) { |
| 506 | if (ir_hpet[i].id == id) { |
| 507 | sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; |
| 508 | break; |
| 509 | } |
| 510 | } |
| 511 | |
| 512 | if (sid == 0) { |
| 513 | pr_warning("Failed to set source-id of HPET block (%d)\n", id); |
| 514 | return -1; |
| 515 | } |
| 516 | |
| 517 | /* |
| 518 | * Should really use SQ_ALL_16. Some platforms are broken. |
| 519 | * While we figure out the right quirks for these broken platforms, use |
| 520 | * SQ_13_IGNORE_3 for now. |
| 521 | */ |
| 522 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); |
| 523 | |
| 524 | return 0; |
| 525 | } |
| 526 | |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 527 | int set_msi_sid(struct irte *irte, struct pci_dev *dev) |
| 528 | { |
| 529 | struct pci_dev *bridge; |
| 530 | |
| 531 | if (!irte || !dev) |
| 532 | return -1; |
| 533 | |
| 534 | /* PCIe device or Root Complex integrated PCI device */ |
Kenji Kaneshige | 5f4d91a | 2009-11-11 14:36:17 +0900 | [diff] [blame] | 535 | if (pci_is_pcie(dev) || !dev->bus->parent) { |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 536 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, |
| 537 | (dev->bus->number << 8) | dev->devfn); |
| 538 | return 0; |
| 539 | } |
| 540 | |
| 541 | bridge = pci_find_upstream_pcie_bridge(dev); |
| 542 | if (bridge) { |
Stefan Assmann | 45e829e | 2009-12-03 06:49:24 -0500 | [diff] [blame] | 543 | if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */ |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 544 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, |
| 545 | (bridge->bus->number << 8) | dev->bus->number); |
| 546 | else /* this is a legacy PCI bridge */ |
| 547 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, |
| 548 | (bridge->bus->number << 8) | bridge->devfn); |
| 549 | } |
| 550 | |
| 551 | return 0; |
| 552 | } |
| 553 | |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 554 | static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) |
| 555 | { |
| 556 | u64 addr; |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 557 | u32 sts; |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 558 | unsigned long flags; |
| 559 | |
| 560 | addr = virt_to_phys((void *)iommu->ir_table->base); |
| 561 | |
| 562 | spin_lock_irqsave(&iommu->register_lock, flags); |
| 563 | |
| 564 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, |
| 565 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); |
| 566 | |
| 567 | /* Set interrupt-remapping table pointer */ |
Han, Weidong | 161fde0 | 2009-04-03 17:15:47 +0800 | [diff] [blame] | 568 | iommu->gcmd |= DMA_GCMD_SIRTP; |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 569 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 570 | |
| 571 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 572 | readl, (sts & DMA_GSTS_IRTPS), sts); |
| 573 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
| 574 | |
| 575 | /* |
| 576 | * global invalidation of interrupt entry cache before enabling |
| 577 | * interrupt-remapping. |
| 578 | */ |
| 579 | qi_global_iec(iommu); |
| 580 | |
| 581 | spin_lock_irqsave(&iommu->register_lock, flags); |
| 582 | |
| 583 | /* Enable interrupt-remapping */ |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 584 | iommu->gcmd |= DMA_GCMD_IRE; |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 585 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 586 | |
| 587 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 588 | readl, (sts & DMA_GSTS_IRES), sts); |
| 589 | |
| 590 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
| 591 | } |
| 592 | |
| 593 | |
| 594 | static int setup_intr_remapping(struct intel_iommu *iommu, int mode) |
| 595 | { |
| 596 | struct ir_table *ir_table; |
| 597 | struct page *pages; |
| 598 | |
| 599 | ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table), |
Suresh Siddha | fa4b57c | 2009-03-16 17:05:05 -0700 | [diff] [blame] | 600 | GFP_ATOMIC); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 601 | |
| 602 | if (!iommu->ir_table) |
| 603 | return -ENOMEM; |
| 604 | |
Suresh Siddha | 824cd75 | 2009-10-02 11:01:23 -0700 | [diff] [blame] | 605 | pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, |
| 606 | INTR_REMAP_PAGE_ORDER); |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 607 | |
| 608 | if (!pages) { |
| 609 | printk(KERN_ERR "failed to allocate pages of order %d\n", |
| 610 | INTR_REMAP_PAGE_ORDER); |
| 611 | kfree(iommu->ir_table); |
| 612 | return -ENOMEM; |
| 613 | } |
| 614 | |
| 615 | ir_table->base = page_address(pages); |
| 616 | |
| 617 | iommu_set_intr_remapping(iommu, mode); |
| 618 | return 0; |
| 619 | } |
| 620 | |
Suresh Siddha | eba67e5 | 2009-03-16 17:04:56 -0700 | [diff] [blame] | 621 | /* |
| 622 | * Disable Interrupt Remapping. |
| 623 | */ |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 624 | static void iommu_disable_intr_remapping(struct intel_iommu *iommu) |
Suresh Siddha | eba67e5 | 2009-03-16 17:04:56 -0700 | [diff] [blame] | 625 | { |
| 626 | unsigned long flags; |
| 627 | u32 sts; |
| 628 | |
| 629 | if (!ecap_ir_support(iommu->ecap)) |
| 630 | return; |
| 631 | |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 632 | /* |
| 633 | * global invalidation of interrupt entry cache before disabling |
| 634 | * interrupt-remapping. |
| 635 | */ |
| 636 | qi_global_iec(iommu); |
| 637 | |
Suresh Siddha | eba67e5 | 2009-03-16 17:04:56 -0700 | [diff] [blame] | 638 | spin_lock_irqsave(&iommu->register_lock, flags); |
| 639 | |
| 640 | sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); |
| 641 | if (!(sts & DMA_GSTS_IRES)) |
| 642 | goto end; |
| 643 | |
| 644 | iommu->gcmd &= ~DMA_GCMD_IRE; |
| 645 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
| 646 | |
| 647 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
| 648 | readl, !(sts & DMA_GSTS_IRES), sts); |
| 649 | |
| 650 | end: |
| 651 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
| 652 | } |
| 653 | |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 654 | int __init intr_remapping_supported(void) |
| 655 | { |
| 656 | struct dmar_drhd_unit *drhd; |
| 657 | |
Weidong Han | 03ea815 | 2009-04-17 16:42:15 +0800 | [diff] [blame] | 658 | if (disable_intremap) |
| 659 | return 0; |
| 660 | |
Youquan Song | 074835f | 2009-09-09 12:05:39 -0400 | [diff] [blame] | 661 | if (!dmar_ir_support()) |
| 662 | return 0; |
| 663 | |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 664 | for_each_drhd_unit(drhd) { |
| 665 | struct intel_iommu *iommu = drhd->iommu; |
| 666 | |
| 667 | if (!ecap_ir_support(iommu->ecap)) |
| 668 | return 0; |
| 669 | } |
| 670 | |
| 671 | return 1; |
| 672 | } |
| 673 | |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 674 | int __init enable_intr_remapping(int eim) |
| 675 | { |
| 676 | struct dmar_drhd_unit *drhd; |
| 677 | int setup = 0; |
| 678 | |
Youquan Song | e936d07 | 2009-09-07 10:58:07 -0400 | [diff] [blame] | 679 | if (parse_ioapics_under_ir() != 1) { |
| 680 | printk(KERN_INFO "Not enable interrupt remapping\n"); |
| 681 | return -1; |
| 682 | } |
| 683 | |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 684 | for_each_drhd_unit(drhd) { |
| 685 | struct intel_iommu *iommu = drhd->iommu; |
| 686 | |
| 687 | /* |
Han, Weidong | 34aaaa9 | 2009-04-04 17:21:26 +0800 | [diff] [blame] | 688 | * If the queued invalidation is already initialized, |
| 689 | * shouldn't disable it. |
| 690 | */ |
| 691 | if (iommu->qi) |
| 692 | continue; |
| 693 | |
| 694 | /* |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 695 | * Clear previous faults. |
| 696 | */ |
| 697 | dmar_fault(-1, iommu); |
| 698 | |
| 699 | /* |
| 700 | * Disable intr remapping and queued invalidation, if already |
| 701 | * enabled prior to OS handover. |
| 702 | */ |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 703 | iommu_disable_intr_remapping(iommu); |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 704 | |
| 705 | dmar_disable_qi(iommu); |
| 706 | } |
| 707 | |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 708 | /* |
| 709 | * check for the Interrupt-remapping support |
| 710 | */ |
| 711 | for_each_drhd_unit(drhd) { |
| 712 | struct intel_iommu *iommu = drhd->iommu; |
| 713 | |
| 714 | if (!ecap_ir_support(iommu->ecap)) |
| 715 | continue; |
| 716 | |
| 717 | if (eim && !ecap_eim_support(iommu->ecap)) { |
| 718 | printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, " |
| 719 | " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap); |
| 720 | return -1; |
| 721 | } |
| 722 | } |
| 723 | |
| 724 | /* |
| 725 | * Enable queued invalidation for all the DRHD's. |
| 726 | */ |
| 727 | for_each_drhd_unit(drhd) { |
| 728 | int ret; |
| 729 | struct intel_iommu *iommu = drhd->iommu; |
| 730 | ret = dmar_enable_qi(iommu); |
| 731 | |
| 732 | if (ret) { |
| 733 | printk(KERN_ERR "DRHD %Lx: failed to enable queued, " |
| 734 | " invalidation, ecap %Lx, ret %d\n", |
| 735 | drhd->reg_base_addr, iommu->ecap, ret); |
| 736 | return -1; |
| 737 | } |
| 738 | } |
| 739 | |
| 740 | /* |
| 741 | * Setup Interrupt-remapping for all the DRHD's now. |
| 742 | */ |
| 743 | for_each_drhd_unit(drhd) { |
| 744 | struct intel_iommu *iommu = drhd->iommu; |
| 745 | |
| 746 | if (!ecap_ir_support(iommu->ecap)) |
| 747 | continue; |
| 748 | |
| 749 | if (setup_intr_remapping(iommu, eim)) |
| 750 | goto error; |
| 751 | |
| 752 | setup = 1; |
| 753 | } |
| 754 | |
| 755 | if (!setup) |
| 756 | goto error; |
| 757 | |
| 758 | intr_remapping_enabled = 1; |
| 759 | |
| 760 | return 0; |
| 761 | |
| 762 | error: |
| 763 | /* |
| 764 | * handle error condition gracefully here! |
| 765 | */ |
| 766 | return -1; |
| 767 | } |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 768 | |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 769 | static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, |
| 770 | struct intel_iommu *iommu) |
| 771 | { |
| 772 | struct acpi_dmar_pci_path *path; |
| 773 | u8 bus; |
| 774 | int count; |
| 775 | |
| 776 | bus = scope->bus; |
| 777 | path = (struct acpi_dmar_pci_path *)(scope + 1); |
| 778 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) |
| 779 | / sizeof(struct acpi_dmar_pci_path); |
| 780 | |
| 781 | while (--count > 0) { |
| 782 | /* |
| 783 | * Access PCI directly due to the PCI |
| 784 | * subsystem isn't initialized yet. |
| 785 | */ |
| 786 | bus = read_pci_config_byte(bus, path->dev, path->fn, |
| 787 | PCI_SECONDARY_BUS); |
| 788 | path++; |
| 789 | } |
| 790 | ir_hpet[ir_hpet_num].bus = bus; |
| 791 | ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->dev, path->fn); |
| 792 | ir_hpet[ir_hpet_num].iommu = iommu; |
| 793 | ir_hpet[ir_hpet_num].id = scope->enumeration_id; |
| 794 | ir_hpet_num++; |
| 795 | } |
| 796 | |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 797 | static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, |
| 798 | struct intel_iommu *iommu) |
| 799 | { |
| 800 | struct acpi_dmar_pci_path *path; |
| 801 | u8 bus; |
| 802 | int count; |
| 803 | |
| 804 | bus = scope->bus; |
| 805 | path = (struct acpi_dmar_pci_path *)(scope + 1); |
| 806 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) |
| 807 | / sizeof(struct acpi_dmar_pci_path); |
| 808 | |
| 809 | while (--count > 0) { |
| 810 | /* |
| 811 | * Access PCI directly due to the PCI |
| 812 | * subsystem isn't initialized yet. |
| 813 | */ |
| 814 | bus = read_pci_config_byte(bus, path->dev, path->fn, |
| 815 | PCI_SECONDARY_BUS); |
| 816 | path++; |
| 817 | } |
| 818 | |
| 819 | ir_ioapic[ir_ioapic_num].bus = bus; |
| 820 | ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->dev, path->fn); |
| 821 | ir_ioapic[ir_ioapic_num].iommu = iommu; |
| 822 | ir_ioapic[ir_ioapic_num].id = scope->enumeration_id; |
| 823 | ir_ioapic_num++; |
| 824 | } |
| 825 | |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 826 | static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, |
| 827 | struct intel_iommu *iommu) |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 828 | { |
| 829 | struct acpi_dmar_hardware_unit *drhd; |
| 830 | struct acpi_dmar_device_scope *scope; |
| 831 | void *start, *end; |
| 832 | |
| 833 | drhd = (struct acpi_dmar_hardware_unit *)header; |
| 834 | |
| 835 | start = (void *)(drhd + 1); |
| 836 | end = ((void *)drhd) + header->length; |
| 837 | |
| 838 | while (start < end) { |
| 839 | scope = start; |
| 840 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { |
| 841 | if (ir_ioapic_num == MAX_IO_APICS) { |
| 842 | printk(KERN_WARNING "Exceeded Max IO APICS\n"); |
| 843 | return -1; |
| 844 | } |
| 845 | |
Yinghai Lu | 680a752 | 2010-04-08 19:58:23 +0100 | [diff] [blame] | 846 | printk(KERN_INFO "IOAPIC id %d under DRHD base " |
| 847 | " 0x%Lx IOMMU %d\n", scope->enumeration_id, |
| 848 | drhd->address, iommu->seq_id); |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 849 | |
Weidong Han | f007e99 | 2009-05-23 00:41:15 +0800 | [diff] [blame] | 850 | ir_parse_one_ioapic_scope(scope, iommu); |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 851 | } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) { |
| 852 | if (ir_hpet_num == MAX_HPET_TBS) { |
| 853 | printk(KERN_WARNING "Exceeded Max HPET blocks\n"); |
| 854 | return -1; |
| 855 | } |
| 856 | |
| 857 | printk(KERN_INFO "HPET id %d under DRHD base" |
| 858 | " 0x%Lx\n", scope->enumeration_id, |
| 859 | drhd->address); |
| 860 | |
| 861 | ir_parse_one_hpet_scope(scope, iommu); |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 862 | } |
| 863 | start += scope->length; |
| 864 | } |
| 865 | |
| 866 | return 0; |
| 867 | } |
| 868 | |
| 869 | /* |
| 870 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping |
| 871 | * hardware unit. |
| 872 | */ |
| 873 | int __init parse_ioapics_under_ir(void) |
| 874 | { |
| 875 | struct dmar_drhd_unit *drhd; |
| 876 | int ir_supported = 0; |
| 877 | |
| 878 | for_each_drhd_unit(drhd) { |
| 879 | struct intel_iommu *iommu = drhd->iommu; |
| 880 | |
| 881 | if (ecap_ir_support(iommu->ecap)) { |
Suresh Siddha | 20f3097 | 2009-08-04 12:07:08 -0700 | [diff] [blame] | 882 | if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu)) |
Suresh Siddha | ad3ad3f | 2008-07-10 11:16:40 -0700 | [diff] [blame] | 883 | return -1; |
| 884 | |
| 885 | ir_supported = 1; |
| 886 | } |
| 887 | } |
| 888 | |
| 889 | if (ir_supported && ir_ioapic_num != nr_ioapics) { |
| 890 | printk(KERN_WARNING |
| 891 | "Not all IO-APIC's listed under remapping hardware\n"); |
| 892 | return -1; |
| 893 | } |
| 894 | |
| 895 | return ir_supported; |
| 896 | } |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 897 | |
| 898 | void disable_intr_remapping(void) |
| 899 | { |
| 900 | struct dmar_drhd_unit *drhd; |
| 901 | struct intel_iommu *iommu = NULL; |
| 902 | |
| 903 | /* |
| 904 | * Disable Interrupt-remapping for all the DRHD's now. |
| 905 | */ |
| 906 | for_each_iommu(iommu, drhd) { |
| 907 | if (!ecap_ir_support(iommu->ecap)) |
| 908 | continue; |
| 909 | |
| 910 | iommu_disable_intr_remapping(iommu); |
| 911 | } |
| 912 | } |
| 913 | |
| 914 | int reenable_intr_remapping(int eim) |
| 915 | { |
| 916 | struct dmar_drhd_unit *drhd; |
| 917 | int setup = 0; |
| 918 | struct intel_iommu *iommu = NULL; |
| 919 | |
| 920 | for_each_iommu(iommu, drhd) |
| 921 | if (iommu->qi) |
| 922 | dmar_reenable_qi(iommu); |
| 923 | |
| 924 | /* |
| 925 | * Setup Interrupt-remapping for all the DRHD's now. |
| 926 | */ |
| 927 | for_each_iommu(iommu, drhd) { |
| 928 | if (!ecap_ir_support(iommu->ecap)) |
| 929 | continue; |
| 930 | |
| 931 | /* Set up interrupt remapping for iommu.*/ |
| 932 | iommu_set_intr_remapping(iommu, eim); |
| 933 | setup = 1; |
| 934 | } |
| 935 | |
| 936 | if (!setup) |
| 937 | goto error; |
| 938 | |
| 939 | return 0; |
| 940 | |
| 941 | error: |
| 942 | /* |
| 943 | * handle error condition gracefully here! |
| 944 | */ |
| 945 | return -1; |
| 946 | } |
| 947 | |