blob: d95a7a9cfd1ebd1935231ce3f9fb4df62acd7793 [file] [log] [blame]
Andrew Lunn82bb2da2012-11-17 17:00:45 +01001/ {
Ezequiel Garcia54397d82013-07-26 10:18:05 -03002 mbus {
Sebastian Hesselbarth7b36efd2014-04-30 14:56:29 +02003 pciec: pcie-controller {
Ezequiel Garcia54397d82013-07-26 10:18:05 -03004 compatible = "marvell,kirkwood-pcie";
5 status = "disabled";
6 device_type = "pci";
7
8 #address-cells = <3>;
9 #size-cells = <2>;
10
11 bus-range = <0x00 0xff>;
12
13 ranges =
14 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
15 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
16 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
17
Sebastian Hesselbarth7b36efd2014-04-30 14:56:29 +020018 pcie0: pcie@1,0 {
Ezequiel Garcia54397d82013-07-26 10:18:05 -030019 device_type = "pci";
20 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
21 reg = <0x0800 0 0 0 0>;
22 #address-cells = <3>;
23 #size-cells = <2>;
24 #interrupt-cells = <1>;
25 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
26 0x81000000 0 0 0x81000000 0x1 0 1 0>;
27 interrupt-map-mask = <0 0 0 0>;
28 interrupt-map = <0 0 0 0 &intc 9>;
29 marvell,pcie-port = <0>;
30 marvell,pcie-lane = <0>;
31 clocks = <&gate_clk 2>;
32 status = "disabled";
33 };
34 };
35 };
36
Andrew Lunn82bb2da2012-11-17 17:00:45 +010037 ocp@f1000000 {
Sebastian Hesselbartha9483962014-04-30 14:56:32 +020038 pinctrl: pin-controller@10000 {
Andrew Lunn82bb2da2012-11-17 17:00:45 +010039 compatible = "marvell,88f6281-pinctrl";
40 reg = <0x10000 0x20>;
41
42 pmx_nand: pmx-nand {
43 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
44 "mpp4", "mpp5", "mpp18",
45 "mpp19";
46 marvell,function = "nand";
47 };
48 pmx_sata0: pmx-sata0 {
49 marvell,pins = "mpp5", "mpp21", "mpp23";
50 marvell,function = "sata0";
51 };
52 pmx_sata1: pmx-sata1 {
53 marvell,pins = "mpp4", "mpp20", "mpp22";
54 marvell,function = "sata1";
55 };
56 pmx_spi: pmx-spi {
57 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
58 marvell,function = "spi";
59 };
60 pmx_twsi0: pmx-twsi0 {
61 marvell,pins = "mpp8", "mpp9";
62 marvell,function = "twsi0";
63 };
64 pmx_uart0: pmx-uart0 {
65 marvell,pins = "mpp10", "mpp11";
66 marvell,function = "uart0";
67 };
68 pmx_uart1: pmx-uart1 {
69 marvell,pins = "mpp13", "mpp14";
70 marvell,function = "uart1";
71 };
Stefan Peterde64ee52012-11-19 16:00:02 +010072 pmx_sdio: pmx-sdio {
73 marvell,pins = "mpp12", "mpp13", "mpp14",
74 "mpp15", "mpp16", "mpp17";
75 marvell,function = "sdio";
76 };
Andrew Lunn82bb2da2012-11-17 17:00:45 +010077 };
Thomas Petazzoni670ee032013-05-15 15:36:56 +020078
Sebastian Hesselbarth7b36efd2014-04-30 14:56:29 +020079 rtc: rtc@10300 {
Valentin Longchampdf6bf2e2013-05-27 17:40:32 +020080 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
81 reg = <0x10300 0x20>;
82 interrupts = <53>;
83 clocks = <&gate_clk 7>;
84 };
85
Sebastian Hesselbarth7b36efd2014-04-30 14:56:29 +020086 sata: sata@80000 {
Valentin Longchampdf6bf2e2013-05-27 17:40:32 +020087 compatible = "marvell,orion-sata";
88 reg = <0x80000 0x5000>;
89 interrupts = <21>;
90 clocks = <&gate_clk 14>, <&gate_clk 15>;
91 clock-names = "0", "1";
Andrew Lunn0ad82cd2013-12-17 21:21:52 +010092 phys = <&sata_phy0>, <&sata_phy1>;
93 phy-names = "port0", "port1";
Valentin Longchampdf6bf2e2013-05-27 17:40:32 +020094 status = "disabled";
95 };
96
Sebastian Hesselbarth7b36efd2014-04-30 14:56:29 +020097 sdio: mvsdio@90000 {
Valentin Longchampdf6bf2e2013-05-27 17:40:32 +020098 compatible = "marvell,orion-sdio";
99 reg = <0x90000 0x200>;
100 interrupts = <28>;
101 clocks = <&gate_clk 4>;
Sebastian Hesselbarth02423992013-11-15 15:20:24 +0100102 pinctrl-0 = <&pmx_sdio>;
103 pinctrl-names = "default";
Valentin Longchampdf6bf2e2013-05-27 17:40:32 +0200104 bus-width = <4>;
105 cap-sdio-irq;
106 cap-sd-highspeed;
107 cap-mmc-highspeed;
108 status = "disabled";
109 };
Andrew Lunn82bb2da2012-11-17 17:00:45 +0100110 };
Stefan Peterde64ee52012-11-19 16:00:02 +0100111};