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gerrit-public.fairphone.software / kernel / msm-4.9 / a94bea343c2f747c62ef66b52d2430e6aeb75434 / . / drivers / scsi / mpt3sas / mpi / mpi2.h
blob: d730c5ca14669266b8e856d7ba64ed52bd2098f5 [file] [log] [blame]
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]1/*
Sreekanth Reddya4ffce02014-09-12 15:35:29 +0530[diff] [blame]2 * Copyright (c) 2000-2014 LSI Corporation.
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]3 *
4 *
5 * Name: mpi2.h
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
10 *
Sreekanth Reddya94bea32015-06-30 12:24:51 +0530[diff] [blame^]11 * mpi2.h Version: 02.00.33
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]12 *
13 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
14 * prefix are for use only on MPI v2.5 products, and must not be used
15 * with MPI v2.0 products. Unless otherwise noted, names beginning with
16 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
17 *
18 * Version History
19 * ---------------
20 *
21 * Date Version Description
22 * -------- -------- ------------------------------------------------------
23 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
24 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
25 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
26 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
27 * Moved ReplyPostHostIndex register to offset 0x6C of the
28 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
29 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
30 * Added union of request descriptors.
31 * Added union of reply descriptors.
32 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
33 * Added define for MPI2_VERSION_02_00.
34 * Fixed the size of the FunctionDependent5 field in the
35 * MPI2_DEFAULT_REPLY structure.
36 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
37 * Removed the MPI-defined Fault Codes and extended the
38 * product specific codes up to 0xEFFF.
39 * Added a sixth key value for the WriteSequence register
40 * and changed the flush value to 0x0.
41 * Added message function codes for Diagnostic Buffer Post
42 * and Diagnsotic Release.
43 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
44 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
45 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
46 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
47 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
48 * Added #defines for marking a reply descriptor as unused.
49 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
50 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
51 * Moved LUN field defines from mpi2_init.h.
52 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
53 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
54 * In all request and reply descriptors, replaced VF_ID
55 * field with MSIxIndex field.
56 * Removed DevHandle field from
57 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
58 * bytes reserved.
59 * Added RAID Accelerator functionality.
60 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
61 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
62 * Added MSI-x index mask and shift for Reply Post Host
63 * Index register.
64 * Added function code for Host Based Discovery Action.
65 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
66 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
67 * Added defines for product-specific range of message
68 * function codes, 0xF0 to 0xFF.
69 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
70 * Added alternative defines for the SGE Direction bit.
71 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
72 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
73 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
74 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
75 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
76 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
77 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
78 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
80 * Incorporating additions for MPI v2.5.
81 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
82 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
83 * Added Hard Reset delay timings.
84 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
Sreekanth Reddy17263e72013-06-29 03:54:07 +0530[diff] [blame]85 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
86 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
87 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
88 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
Sreekanth Reddy861ff732014-09-12 15:35:25 +0530[diff] [blame]89 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
90 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
Sreekanth Reddya94bea32015-06-30 12:24:51 +0530[diff] [blame^]91 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
92 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]93 * --------------------------------------------------------------------------
94 */
95
96#ifndef MPI2_H
97#define MPI2_H
98
99/*****************************************************************************
100*
101* MPI Version Definitions
102*
103*****************************************************************************/
104
105#define MPI2_VERSION_MAJOR_MASK (0xFF00)
106#define MPI2_VERSION_MAJOR_SHIFT (8)
107#define MPI2_VERSION_MINOR_MASK (0x00FF)
108#define MPI2_VERSION_MINOR_SHIFT (0)
109
110/*major version for all MPI v2.x */
111#define MPI2_VERSION_MAJOR (0x02)
112
113/*minor version for MPI v2.0 compatible products */
114#define MPI2_VERSION_MINOR (0x00)
115#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
116 MPI2_VERSION_MINOR)
117#define MPI2_VERSION_02_00 (0x0200)
118
119/*minor version for MPI v2.5 compatible products */
120#define MPI25_VERSION_MINOR (0x05)
121#define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
122 MPI25_VERSION_MINOR)
123#define MPI2_VERSION_02_05 (0x0205)
124
125/*Unit and Dev versioning for this MPI header set */
Sreekanth Reddya94bea32015-06-30 12:24:51 +0530[diff] [blame^]126#define MPI2_HEADER_VERSION_UNIT (0x21)
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]127#define MPI2_HEADER_VERSION_DEV (0x00)
128#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
129#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
130#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
131#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
132#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
133 MPI2_HEADER_VERSION_DEV)
134
135/*****************************************************************************
136*
137* IOC State Definitions
138*
139*****************************************************************************/
140
141#define MPI2_IOC_STATE_RESET (0x00000000)
142#define MPI2_IOC_STATE_READY (0x10000000)
143#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
144#define MPI2_IOC_STATE_FAULT (0x40000000)
145
146#define MPI2_IOC_STATE_MASK (0xF0000000)
147#define MPI2_IOC_STATE_SHIFT (28)
148
149/*Fault state range for prodcut specific codes */
150#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
151#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
152
153/*****************************************************************************
154*
155* System Interface Register Definitions
156*
157*****************************************************************************/
158
159typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
160 U32 Doorbell; /*0x00 */
161 U32 WriteSequence; /*0x04 */
162 U32 HostDiagnostic; /*0x08 */
163 U32 Reserved1; /*0x0C */
164 U32 DiagRWData; /*0x10 */
165 U32 DiagRWAddressLow; /*0x14 */
166 U32 DiagRWAddressHigh; /*0x18 */
167 U32 Reserved2[5]; /*0x1C */
168 U32 HostInterruptStatus; /*0x30 */
169 U32 HostInterruptMask; /*0x34 */
170 U32 DCRData; /*0x38 */
171 U32 DCRAddress; /*0x3C */
172 U32 Reserved3[2]; /*0x40 */
173 U32 ReplyFreeHostIndex; /*0x48 */
174 U32 Reserved4[8]; /*0x4C */
175 U32 ReplyPostHostIndex; /*0x6C */
176 U32 Reserved5; /*0x70 */
177 U32 HCBSize; /*0x74 */
178 U32 HCBAddressLow; /*0x78 */
179 U32 HCBAddressHigh; /*0x7C */
180 U32 Reserved6[16]; /*0x80 */
181 U32 RequestDescriptorPostLow; /*0xC0 */
182 U32 RequestDescriptorPostHigh; /*0xC4 */
183 U32 Reserved7[14]; /*0xC8 */
184} MPI2_SYSTEM_INTERFACE_REGS,
185 *PTR_MPI2_SYSTEM_INTERFACE_REGS,
186 Mpi2SystemInterfaceRegs_t,
187 *pMpi2SystemInterfaceRegs_t;
188
189/*
190 *Defines for working with the Doorbell register.
191 */
192#define MPI2_DOORBELL_OFFSET (0x00000000)
193
194/*IOC --> System values */
195#define MPI2_DOORBELL_USED (0x08000000)
196#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
197#define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
198#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
199#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
200
201/*System --> IOC values */
202#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
203#define MPI2_DOORBELL_FUNCTION_SHIFT (24)
204#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
205#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
206
207/*
208 *Defines for the WriteSequence register
209 */
210#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
211#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
212#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
213#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
214#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
215#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
216#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
217#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
218#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
219
220/*
221 *Defines for the HostDiagnostic register
222 */
223#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
224
225#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
226#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
227#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
228
229#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
230#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
231#define MPI2_DIAG_HCB_MODE (0x00000100)
232#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
233#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
234#define MPI2_DIAG_RESET_HISTORY (0x00000020)
235#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
236#define MPI2_DIAG_RESET_ADAPTER (0x00000004)
237#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
238
239/*
240 *Offsets for DiagRWData and address
241 */
242#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
243#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
244#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
245
246/*
247 *Defines for the HostInterruptStatus register
248 */
249#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
250#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
251#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
252#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
253#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
254#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
255#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
256
257/*
258 *Defines for the HostInterruptMask register
259 */
260#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
261#define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
262#define MPI2_HIM_REPLY_INT_MASK (0x00000008)
263#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
264#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
265#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
266
267/*
268 *Offsets for DCRData and address
269 */
270#define MPI2_DCR_DATA_OFFSET (0x00000038)
271#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
272
273/*
274 *Offset for the Reply Free Queue
275 */
276#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
277
278/*
279 *Defines for the Reply Descriptor Post Queue
280 */
281#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
282#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
283#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
284#define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
Sreekanth Reddy17263e72013-06-29 03:54:07 +0530[diff] [blame]285#define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/
286
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]287
288/*
289 *Defines for the HCBSize and address
290 */
291#define MPI2_HCB_SIZE_OFFSET (0x00000074)
292#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
293#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
294
295#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
296#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
297
298/*
299 *Offsets for the Request Queue
300 */
301#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
302#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
303
304/*Hard Reset delay timings */
305#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
306#define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
307#define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
308
309/*****************************************************************************
310*
311* Message Descriptors
312*
313*****************************************************************************/
314
315/*Request Descriptors */
316
317/*Default Request Descriptor */
318typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
319 U8 RequestFlags; /*0x00 */
320 U8 MSIxIndex; /*0x01 */
321 U16 SMID; /*0x02 */
322 U16 LMID; /*0x04 */
323 U16 DescriptorTypeDependent; /*0x06 */
324} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
325 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
326 Mpi2DefaultRequestDescriptor_t,
327 *pMpi2DefaultRequestDescriptor_t;
328
329/*defines for the RequestFlags field */
330#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
331#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
332#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
333#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
334#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
335#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
336#define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
337
338#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
339
340/*High Priority Request Descriptor */
341typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
342 U8 RequestFlags; /*0x00 */
343 U8 MSIxIndex; /*0x01 */
344 U16 SMID; /*0x02 */
345 U16 LMID; /*0x04 */
346 U16 Reserved1; /*0x06 */
347} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
348 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
349 Mpi2HighPriorityRequestDescriptor_t,
350 *pMpi2HighPriorityRequestDescriptor_t;
351
352/*SCSI IO Request Descriptor */
353typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
354 U8 RequestFlags; /*0x00 */
355 U8 MSIxIndex; /*0x01 */
356 U16 SMID; /*0x02 */
357 U16 LMID; /*0x04 */
358 U16 DevHandle; /*0x06 */
359} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
360 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
361 Mpi2SCSIIORequestDescriptor_t,
362 *pMpi2SCSIIORequestDescriptor_t;
363
364/*SCSI Target Request Descriptor */
365typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
366 U8 RequestFlags; /*0x00 */
367 U8 MSIxIndex; /*0x01 */
368 U16 SMID; /*0x02 */
369 U16 LMID; /*0x04 */
370 U16 IoIndex; /*0x06 */
371} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
372 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
373 Mpi2SCSITargetRequestDescriptor_t,
374 *pMpi2SCSITargetRequestDescriptor_t;
375
376/*RAID Accelerator Request Descriptor */
377typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
378 U8 RequestFlags; /*0x00 */
379 U8 MSIxIndex; /*0x01 */
380 U16 SMID; /*0x02 */
381 U16 LMID; /*0x04 */
382 U16 Reserved; /*0x06 */
383} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
384 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
385 Mpi2RAIDAcceleratorRequestDescriptor_t,
386 *pMpi2RAIDAcceleratorRequestDescriptor_t;
387
388/*Fast Path SCSI IO Request Descriptor */
389typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
390 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
391 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
392 Mpi25FastPathSCSIIORequestDescriptor_t,
393 *pMpi25FastPathSCSIIORequestDescriptor_t;
394
395/*union of Request Descriptors */
396typedef union _MPI2_REQUEST_DESCRIPTOR_UNION {
397 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
398 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
399 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
400 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
401 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
402 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
403 U64 Words;
404} MPI2_REQUEST_DESCRIPTOR_UNION,
405 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
406 Mpi2RequestDescriptorUnion_t,
407 *pMpi2RequestDescriptorUnion_t;
408
409/*Reply Descriptors */
410
411/*Default Reply Descriptor */
412typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
413 U8 ReplyFlags; /*0x00 */
414 U8 MSIxIndex; /*0x01 */
415 U16 DescriptorTypeDependent1; /*0x02 */
416 U32 DescriptorTypeDependent2; /*0x04 */
417} MPI2_DEFAULT_REPLY_DESCRIPTOR,
418 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
419 Mpi2DefaultReplyDescriptor_t,
420 *pMpi2DefaultReplyDescriptor_t;
421
422/*defines for the ReplyFlags field */
423#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
424#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
425#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
426#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
427#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
428#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
429#define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
430#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
431
432/*values for marking a reply descriptor as unused */
433#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
434#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
435
436/*Address Reply Descriptor */
437typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
438 U8 ReplyFlags; /*0x00 */
439 U8 MSIxIndex; /*0x01 */
440 U16 SMID; /*0x02 */
441 U32 ReplyFrameAddress; /*0x04 */
442} MPI2_ADDRESS_REPLY_DESCRIPTOR,
443 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
444 Mpi2AddressReplyDescriptor_t,
445 *pMpi2AddressReplyDescriptor_t;
446
447#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
448
449/*SCSI IO Success Reply Descriptor */
450typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
451 U8 ReplyFlags; /*0x00 */
452 U8 MSIxIndex; /*0x01 */
453 U16 SMID; /*0x02 */
454 U16 TaskTag; /*0x04 */
455 U16 Reserved1; /*0x06 */
456} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
457 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
458 Mpi2SCSIIOSuccessReplyDescriptor_t,
459 *pMpi2SCSIIOSuccessReplyDescriptor_t;
460
461/*TargetAssist Success Reply Descriptor */
462typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
463 U8 ReplyFlags; /*0x00 */
464 U8 MSIxIndex; /*0x01 */
465 U16 SMID; /*0x02 */
466 U8 SequenceNumber; /*0x04 */
467 U8 Reserved1; /*0x05 */
468 U16 IoIndex; /*0x06 */
469} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
470 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
471 Mpi2TargetAssistSuccessReplyDescriptor_t,
472 *pMpi2TargetAssistSuccessReplyDescriptor_t;
473
474/*Target Command Buffer Reply Descriptor */
475typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
476 U8 ReplyFlags; /*0x00 */
477 U8 MSIxIndex; /*0x01 */
478 U8 VP_ID; /*0x02 */
479 U8 Flags; /*0x03 */
480 U16 InitiatorDevHandle; /*0x04 */
481 U16 IoIndex; /*0x06 */
482} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
483 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
484 Mpi2TargetCommandBufferReplyDescriptor_t,
485 *pMpi2TargetCommandBufferReplyDescriptor_t;
486
487/*defines for Flags field */
488#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
489
490/*RAID Accelerator Success Reply Descriptor */
491typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
492 U8 ReplyFlags; /*0x00 */
493 U8 MSIxIndex; /*0x01 */
494 U16 SMID; /*0x02 */
495 U32 Reserved; /*0x04 */
496} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
497 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
498 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
499 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
500
501/*Fast Path SCSI IO Success Reply Descriptor */
502typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
503 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
504 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
505 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
506 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
507
508/*union of Reply Descriptors */
509typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
510 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
511 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
512 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
513 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
514 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
515 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
516 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
517 U64 Words;
518} MPI2_REPLY_DESCRIPTORS_UNION,
519 *PTR_MPI2_REPLY_DESCRIPTORS_UNION,
520 Mpi2ReplyDescriptorsUnion_t,
521 *pMpi2ReplyDescriptorsUnion_t;
522
523/*****************************************************************************
524*
525* Message Functions
526*
527*****************************************************************************/
528
529#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00)
530#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
531#define MPI2_FUNCTION_IOC_INIT (0x02)
532#define MPI2_FUNCTION_IOC_FACTS (0x03)
533#define MPI2_FUNCTION_CONFIG (0x04)
534#define MPI2_FUNCTION_PORT_FACTS (0x05)
535#define MPI2_FUNCTION_PORT_ENABLE (0x06)
536#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07)
537#define MPI2_FUNCTION_EVENT_ACK (0x08)
538#define MPI2_FUNCTION_FW_DOWNLOAD (0x09)
539#define MPI2_FUNCTION_TARGET_ASSIST (0x0B)
540#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C)
541#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D)
542#define MPI2_FUNCTION_FW_UPLOAD (0x12)
543#define MPI2_FUNCTION_RAID_ACTION (0x15)
544#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16)
545#define MPI2_FUNCTION_TOOLBOX (0x17)
546#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18)
547#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A)
548#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B)
549#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C)
550#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D)
551#define MPI2_FUNCTION_DIAG_RELEASE (0x1E)
552#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24)
553#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25)
554#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C)
555#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
556#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
557#define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
558#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
559#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
560
561/*Doorbell functions */
562#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
563#define MPI2_FUNCTION_HANDSHAKE (0x42)
564
565/*****************************************************************************
566*
567* IOC Status Values
568*
569*****************************************************************************/
570
571/*mask for IOCStatus status value */
572#define MPI2_IOCSTATUS_MASK (0x7FFF)
573
574/****************************************************************************
575* Common IOCStatus values for all replies
576****************************************************************************/
577
578#define MPI2_IOCSTATUS_SUCCESS (0x0000)
579#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
580#define MPI2_IOCSTATUS_BUSY (0x0002)
581#define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
582#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
583#define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
584#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
585#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
586#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
587#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
588
589/****************************************************************************
590* Config IOCStatus values
591****************************************************************************/
592
593#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
594#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
595#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
596#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
597#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
598#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
599
600/****************************************************************************
601* SCSI IO Reply
602****************************************************************************/
603
604#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
605#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
606#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
607#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
608#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
609#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
610#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
611#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
612#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
613#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
614#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
615#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
616
617/****************************************************************************
618* For use by SCSI Initiator and SCSI Target end-to-end data protection
619****************************************************************************/
620
621#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
622#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
623#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
624
625/****************************************************************************
626* SCSI Target values
627****************************************************************************/
628
629#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
630#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
631#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
632#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
633#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
634#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
635#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
636#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
637#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
638#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
639
640/****************************************************************************
641* Serial Attached SCSI values
642****************************************************************************/
643
644#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
645#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
646
647/****************************************************************************
648* Diagnostic Buffer Post / Diagnostic Release values
649****************************************************************************/
650
651#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
652
653/****************************************************************************
654* RAID Accelerator values
655****************************************************************************/
656
657#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
658
659/****************************************************************************
660* IOCStatus flag to indicate that log info is available
661****************************************************************************/
662
663#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
664
665/****************************************************************************
666* IOCLogInfo Types
667****************************************************************************/
668
669#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
670#define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
671#define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
672#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
673#define MPI2_IOCLOGINFO_TYPE_FC (0x2)
674#define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
675#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
676#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
677
678/*****************************************************************************
679*
680* Standard Message Structures
681*
682*****************************************************************************/
683
684/****************************************************************************
685*Request Message Header for all request messages
686****************************************************************************/
687
688typedef struct _MPI2_REQUEST_HEADER {
689 U16 FunctionDependent1; /*0x00 */
690 U8 ChainOffset; /*0x02 */
691 U8 Function; /*0x03 */
692 U16 FunctionDependent2; /*0x04 */
693 U8 FunctionDependent3; /*0x06 */
694 U8 MsgFlags; /*0x07 */
695 U8 VP_ID; /*0x08 */
696 U8 VF_ID; /*0x09 */
697 U16 Reserved1; /*0x0A */
698} MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER,
699 MPI2RequestHeader_t, *pMPI2RequestHeader_t;
700
701/****************************************************************************
702* Default Reply
703****************************************************************************/
704
705typedef struct _MPI2_DEFAULT_REPLY {
706 U16 FunctionDependent1; /*0x00 */
707 U8 MsgLength; /*0x02 */
708 U8 Function; /*0x03 */
709 U16 FunctionDependent2; /*0x04 */
710 U8 FunctionDependent3; /*0x06 */
711 U8 MsgFlags; /*0x07 */
712 U8 VP_ID; /*0x08 */
713 U8 VF_ID; /*0x09 */
714 U16 Reserved1; /*0x0A */
715 U16 FunctionDependent5; /*0x0C */
716 U16 IOCStatus; /*0x0E */
717 U32 IOCLogInfo; /*0x10 */
718} MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY,
719 MPI2DefaultReply_t, *pMPI2DefaultReply_t;
720
721/*common version structure/union used in messages and configuration pages */
722
723typedef struct _MPI2_VERSION_STRUCT {
724 U8 Dev; /*0x00 */
725 U8 Unit; /*0x01 */
726 U8 Minor; /*0x02 */
727 U8 Major; /*0x03 */
728} MPI2_VERSION_STRUCT;
729
730typedef union _MPI2_VERSION_UNION {
731 MPI2_VERSION_STRUCT Struct;
732 U32 Word;
733} MPI2_VERSION_UNION;
734
735/*LUN field defines, common to many structures */
736#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
737#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
738#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
739#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
740#define MPI2_LUN_LEVEL_1_WORD (0xFF00)
741#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
742
743/*****************************************************************************
744*
745* Fusion-MPT MPI Scatter Gather Elements
746*
747*****************************************************************************/
748
749/****************************************************************************
750* MPI Simple Element structures
751****************************************************************************/
752
753typedef struct _MPI2_SGE_SIMPLE32 {
754 U32 FlagsLength;
755 U32 Address;
756} MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32,
757 Mpi2SGESimple32_t, *pMpi2SGESimple32_t;
758
759typedef struct _MPI2_SGE_SIMPLE64 {
760 U32 FlagsLength;
761 U64 Address;
762} MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64,
763 Mpi2SGESimple64_t, *pMpi2SGESimple64_t;
764
765typedef struct _MPI2_SGE_SIMPLE_UNION {
766 U32 FlagsLength;
767 union {
768 U32 Address32;
769 U64 Address64;
770 } u;
771} MPI2_SGE_SIMPLE_UNION,
772 *PTR_MPI2_SGE_SIMPLE_UNION,
773 Mpi2SGESimpleUnion_t,
774 *pMpi2SGESimpleUnion_t;
775
776/****************************************************************************
777* MPI Chain Element structures - for MPI v2.0 products only
778****************************************************************************/
779
780typedef struct _MPI2_SGE_CHAIN32 {
781 U16 Length;
782 U8 NextChainOffset;
783 U8 Flags;
784 U32 Address;
785} MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32,
786 Mpi2SGEChain32_t, *pMpi2SGEChain32_t;
787
788typedef struct _MPI2_SGE_CHAIN64 {
789 U16 Length;
790 U8 NextChainOffset;
791 U8 Flags;
792 U64 Address;
793} MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64,
794 Mpi2SGEChain64_t, *pMpi2SGEChain64_t;
795
796typedef struct _MPI2_SGE_CHAIN_UNION {
797 U16 Length;
798 U8 NextChainOffset;
799 U8 Flags;
800 union {
801 U32 Address32;
802 U64 Address64;
803 } u;
804} MPI2_SGE_CHAIN_UNION,
805 *PTR_MPI2_SGE_CHAIN_UNION,
806 Mpi2SGEChainUnion_t,
807 *pMpi2SGEChainUnion_t;
808
809/****************************************************************************
810* MPI Transaction Context Element structures - for MPI v2.0 products only
811****************************************************************************/
812
813typedef struct _MPI2_SGE_TRANSACTION32 {
814 U8 Reserved;
815 U8 ContextSize;
816 U8 DetailsLength;
817 U8 Flags;
818 U32 TransactionContext[1];
819 U32 TransactionDetails[1];
820} MPI2_SGE_TRANSACTION32,
821 *PTR_MPI2_SGE_TRANSACTION32,
822 Mpi2SGETransaction32_t,
823 *pMpi2SGETransaction32_t;
824
825typedef struct _MPI2_SGE_TRANSACTION64 {
826 U8 Reserved;
827 U8 ContextSize;
828 U8 DetailsLength;
829 U8 Flags;
830 U32 TransactionContext[2];
831 U32 TransactionDetails[1];
832} MPI2_SGE_TRANSACTION64,
833 *PTR_MPI2_SGE_TRANSACTION64,
834 Mpi2SGETransaction64_t,
835 *pMpi2SGETransaction64_t;
836
837typedef struct _MPI2_SGE_TRANSACTION96 {
838 U8 Reserved;
839 U8 ContextSize;
840 U8 DetailsLength;
841 U8 Flags;
842 U32 TransactionContext[3];
843 U32 TransactionDetails[1];
844} MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96,
845 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t;
846
847typedef struct _MPI2_SGE_TRANSACTION128 {
848 U8 Reserved;
849 U8 ContextSize;
850 U8 DetailsLength;
851 U8 Flags;
852 U32 TransactionContext[4];
853 U32 TransactionDetails[1];
854} MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128,
855 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128;
856
857typedef struct _MPI2_SGE_TRANSACTION_UNION {
858 U8 Reserved;
859 U8 ContextSize;
860 U8 DetailsLength;
861 U8 Flags;
862 union {
863 U32 TransactionContext32[1];
864 U32 TransactionContext64[2];
865 U32 TransactionContext96[3];
866 U32 TransactionContext128[4];
867 } u;
868 U32 TransactionDetails[1];
869} MPI2_SGE_TRANSACTION_UNION,
870 *PTR_MPI2_SGE_TRANSACTION_UNION,
871 Mpi2SGETransactionUnion_t,
872 *pMpi2SGETransactionUnion_t;
873
874/****************************************************************************
875* MPI SGE union for IO SGL's - for MPI v2.0 products only
876****************************************************************************/
877
878typedef struct _MPI2_MPI_SGE_IO_UNION {
879 union {
880 MPI2_SGE_SIMPLE_UNION Simple;
881 MPI2_SGE_CHAIN_UNION Chain;
882 } u;
883} MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION,
884 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t;
885
886/****************************************************************************
887* MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
888****************************************************************************/
889
890typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION {
891 union {
892 MPI2_SGE_SIMPLE_UNION Simple;
893 MPI2_SGE_TRANSACTION_UNION Transaction;
894 } u;
895} MPI2_SGE_TRANS_SIMPLE_UNION,
896 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
897 Mpi2SGETransSimpleUnion_t,
898 *pMpi2SGETransSimpleUnion_t;
899
900/****************************************************************************
901* All MPI SGE types union
902****************************************************************************/
903
904typedef struct _MPI2_MPI_SGE_UNION {
905 union {
906 MPI2_SGE_SIMPLE_UNION Simple;
907 MPI2_SGE_CHAIN_UNION Chain;
908 MPI2_SGE_TRANSACTION_UNION Transaction;
909 } u;
910} MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION,
911 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t;
912
913/****************************************************************************
914* MPI SGE field definition and masks
915****************************************************************************/
916
917/*Flags field bit definitions */
918
919#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
920#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
921#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
922#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
923#define MPI2_SGE_FLAGS_DIRECTION (0x04)
924#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
925#define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
926
927#define MPI2_SGE_FLAGS_SHIFT (24)
928
929#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
930#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
931
932/*Element Type */
933
934#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
935#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
936#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
937#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
938
939/*Address location */
940
941#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
942
943/*Direction */
944
945#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
946#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
947
948#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
949#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
950
951/*Address Size */
952
953#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
954#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
955
956/*Context Size */
957
958#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
959#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
960#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
961#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
962
963#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
964#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
965
966/****************************************************************************
967* MPI SGE operation Macros
968****************************************************************************/
969
970/*SIMPLE FlagsLength manipulations... */
971#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
972#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \
973 MPI2_SGE_FLAGS_SHIFT)
974#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
975#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
976
977#define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \
978 MPI2_SGE_LENGTH(l))
979
980#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
981#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
982#define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
983 MPI2_SGE_SET_FLAGS_LENGTH(f, l))
984
985/*CAUTION - The following are READ-MODIFY-WRITE! */
986#define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
987 MPI2_SGE_SET_FLAGS(f))
988#define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
989 MPI2_SGE_LENGTH(l))
990
991#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \
992 MPI2_SGE_CHAIN_OFFSET_SHIFT)
993
994/*****************************************************************************
995*
996* Fusion-MPT IEEE Scatter Gather Elements
997*
998*****************************************************************************/
999
1000/****************************************************************************
1001* IEEE Simple Element structures
1002****************************************************************************/
1003
1004/*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1005typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
1006 U32 Address;
1007 U32 FlagsLength;
1008} MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32,
1009 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t;
1010
1011typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
1012 U64 Address;
1013 U32 Length;
1014 U16 Reserved1;
1015 U8 Reserved2;
1016 U8 Flags;
1017} MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64,
1018 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t;
1019
1020typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
1021 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1022 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1023} MPI2_IEEE_SGE_SIMPLE_UNION,
1024 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1025 Mpi2IeeeSgeSimpleUnion_t,
1026 *pMpi2IeeeSgeSimpleUnion_t;
1027
1028/****************************************************************************
1029* IEEE Chain Element structures
1030****************************************************************************/
1031
1032/*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1033typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1034
1035/*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1036typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1037
1038typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
1039 MPI2_IEEE_SGE_CHAIN32 Chain32;
1040 MPI2_IEEE_SGE_CHAIN64 Chain64;
1041} MPI2_IEEE_SGE_CHAIN_UNION,
1042 *PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1043 Mpi2IeeeSgeChainUnion_t,
1044 *pMpi2IeeeSgeChainUnion_t;
1045
1046/*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 products only */
1047typedef struct _MPI25_IEEE_SGE_CHAIN64 {
1048 U64 Address;
1049 U32 Length;
1050 U16 Reserved1;
1051 U8 NextChainOffset;
1052 U8 Flags;
1053} MPI25_IEEE_SGE_CHAIN64,
1054 *PTR_MPI25_IEEE_SGE_CHAIN64,
1055 Mpi25IeeeSgeChain64_t,
1056 *pMpi25IeeeSgeChain64_t;
1057
1058/****************************************************************************
1059* All IEEE SGE types union
1060****************************************************************************/
1061
1062/*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1063typedef struct _MPI2_IEEE_SGE_UNION {
1064 union {
1065 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1066 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1067 } u;
1068} MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION,
1069 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t;
1070
1071/****************************************************************************
1072* IEEE SGE union for IO SGL's
1073****************************************************************************/
1074
1075typedef union _MPI25_SGE_IO_UNION {
1076 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1077 MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1078} MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION,
1079 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t;
1080
1081/****************************************************************************
1082* IEEE SGE field definitions and masks
1083****************************************************************************/
1084
1085/*Flags field bit definitions */
1086
1087#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1088#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1089
1090#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1091
1092#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1093
1094/*Element Type */
1095
1096#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1097#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1098
1099/*Data Location Address Space */
1100
1101#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1102#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1103#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1104#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1105#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1106#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1107#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1108 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR)
1109
1110/****************************************************************************
1111* IEEE SGE operation Macros
1112****************************************************************************/
1113
1114/*SIMPLE FlagsLength manipulations... */
1115#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1116#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \
1117 >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1118#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1119
1120#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\
1121 MPI2_IEEE32_SGE_LENGTH(l))
1122
1123#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \
1124 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1125#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \
1126 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1127#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1128 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l))
1129
1130/*CAUTION - The following are READ-MODIFY-WRITE! */
1131#define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1132 MPI2_IEEE32_SGE_SET_FLAGS(f))
1133#define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1134 MPI2_IEEE32_SGE_LENGTH(l))
1135
1136/*****************************************************************************
1137*
1138* Fusion-MPT MPI/IEEE Scatter Gather Unions
1139*
1140*****************************************************************************/
1141
1142typedef union _MPI2_SIMPLE_SGE_UNION {
1143 MPI2_SGE_SIMPLE_UNION MpiSimple;
1144 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1145} MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION,
1146 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t;
1147
1148typedef union _MPI2_SGE_IO_UNION {
1149 MPI2_SGE_SIMPLE_UNION MpiSimple;
1150 MPI2_SGE_CHAIN_UNION MpiChain;
1151 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1152 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1153} MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION,
1154 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t;
1155
1156/****************************************************************************
1157*
1158* Values for SGLFlags field, used in many request messages with an SGL
1159*
1160****************************************************************************/
1161
1162/*values for MPI SGL Data Location Address Space subfield */
1163#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1164#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1165#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1166#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1167#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1168/*values for SGL Type subfield */
1169#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1170#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1171#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1172#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1173
1174#endif