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Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef _ASM_M32R_M32R_H_
2#define _ASM_M32R_M32R_H_
3
4/*
5 * Renesas M32R processor
6 *
7 * Copyright (C) 2003, 2004 Renesas Technology Corp.
8 */
9
Linus Torvalds1da177e2005-04-16 15:20:36 -070010
11/* Chip type */
12#if defined(CONFIG_CHIP_XNUX_MP) || defined(CONFIG_CHIP_XNUX2_MP)
13#include <asm/m32r_mp_fpga.h>
14#elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
15 || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
Hirokazu Takata9287d952006-01-06 00:18:41 -080016 || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <asm/m32102.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#endif
19
20/* Platform type */
21#if defined(CONFIG_PLAT_M32700UT)
22#include <asm/m32700ut/m32700ut_pld.h>
23#include <asm/m32700ut/m32700ut_lan.h>
24#include <asm/m32700ut/m32700ut_lcd.h>
25#endif /* CONFIG_PLAT_M32700UT */
26
27#if defined(CONFIG_PLAT_OPSPUT)
28#include <asm/opsput/opsput_pld.h>
29#include <asm/opsput/opsput_lan.h>
30#include <asm/opsput/opsput_lcd.h>
31#endif /* CONFIG_PLAT_OPSPUT */
32
33#if defined(CONFIG_PLAT_MAPPI2)
34#include <asm/mappi2/mappi2_pld.h>
35#endif /* CONFIG_PLAT_MAPPI2 */
36
Hirokazu Takata23680862005-06-21 17:16:10 -070037#if defined(CONFIG_PLAT_MAPPI3)
38#include <asm/mappi3/mappi3_pld.h>
39#endif /* CONFIG_PLAT_MAPPI3 */
40
Linus Torvalds1da177e2005-04-16 15:20:36 -070041#if defined(CONFIG_PLAT_USRV)
42#include <asm/m32700ut/m32700ut_pld.h>
43#endif
44
Hirokazu Takata9287d952006-01-06 00:18:41 -080045#if defined(CONFIG_PLAT_M32104UT)
46#include <asm/m32104ut/m32104ut_pld.h>
47#endif /* CONFIG_PLAT_M32104 */
48
Linus Torvalds1da177e2005-04-16 15:20:36 -070049/*
50 * M32R Register
51 */
52
53/*
54 * MMU Register
55 */
56
57#define MMU_REG_BASE (0xffff0000)
58#define ITLB_BASE (0xfe000000)
59#define DTLB_BASE (0xfe000800)
60
61#define NR_TLB_ENTRIES CONFIG_TLB_ENTRIES
62
63#define MATM MMU_REG_BASE /* MMU Address Translation Mode
64 Register */
65#define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */
66#define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */
67#define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */
68#define MDEVA (0x10 + MMU_REG_BASE) /* MMU Operand Exception Virtual
69 Address Register */
70#define MDEVP (0x14 + MMU_REG_BASE) /* MMU Operand Exception Virtual Page
71 Number Register */
72#define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */
73#define MSVA (0x20 + MMU_REG_BASE) /* MMU Search Virtual Address
74 Register */
75#define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */
76#define MIDXI (0x28 + MMU_REG_BASE) /* MMU Index Register for
77 Instruciton */
78#define MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */
79
80#define MATM_offset (MATM - MMU_REG_BASE)
81#define MPSZ_offset (MPSZ - MMU_REG_BASE)
82#define MASID_offset (MASID - MMU_REG_BASE)
83#define MESTS_offset (MESTS - MMU_REG_BASE)
84#define MDEVA_offset (MDEVA - MMU_REG_BASE)
85#define MDEVP_offset (MDEVP - MMU_REG_BASE)
86#define MPTB_offset (MPTB - MMU_REG_BASE)
87#define MSVA_offset (MSVA - MMU_REG_BASE)
88#define MTOP_offset (MTOP - MMU_REG_BASE)
89#define MIDXI_offset (MIDXI - MMU_REG_BASE)
90#define MIDXD_offset (MIDXD - MMU_REG_BASE)
91
92#define MESTS_IT (1 << 0) /* Instruction TLB miss */
93#define MESTS_IA (1 << 1) /* Instruction Access Exception */
94#define MESTS_DT (1 << 4) /* Operand TLB miss */
95#define MESTS_DA (1 << 5) /* Operand Access Exception */
96#define MESTS_DRW (1 << 6) /* Operand Write Exception Flag */
97
98/*
99 * PSW (Processor Status Word)
100 */
101
102/* PSW bit */
103#define M32R_PSW_BIT_SM (7) /* Stack Mode */
104#define M32R_PSW_BIT_IE (6) /* Interrupt Enable */
105#define M32R_PSW_BIT_PM (3) /* Processor Mode [0:Supervisor,1:User] */
106#define M32R_PSW_BIT_C (0) /* Condition */
107#define M32R_PSW_BIT_BSM (7+8) /* Backup Stack Mode */
108#define M32R_PSW_BIT_BIE (6+8) /* Backup Interrupt Enable */
109#define M32R_PSW_BIT_BPM (3+8) /* Backup Processor Mode */
110#define M32R_PSW_BIT_BC (0+8) /* Backup Condition */
111
112/* PSW bit map */
113#define M32R_PSW_SM (1UL<< M32R_PSW_BIT_SM) /* Stack Mode */
114#define M32R_PSW_IE (1UL<< M32R_PSW_BIT_IE) /* Interrupt Enable */
115#define M32R_PSW_PM (1UL<< M32R_PSW_BIT_PM) /* Processor Mode */
116#define M32R_PSW_C (1UL<< M32R_PSW_BIT_C) /* Condition */
117#define M32R_PSW_BSM (1UL<< M32R_PSW_BIT_BSM) /* Backup Stack Mode */
118#define M32R_PSW_BIE (1UL<< M32R_PSW_BIT_BIE) /* Backup Interrupt Enable */
119#define M32R_PSW_BPM (1UL<< M32R_PSW_BIT_BPM) /* Backup Processor Mode */
120#define M32R_PSW_BC (1UL<< M32R_PSW_BIT_BC) /* Backup Condition */
121
122/*
123 * Direct address to SFR
124 */
125
126#include <asm/page.h>
127#ifdef CONFIG_MMU
Hirokazu Takata46ea1782006-01-06 00:18:43 -0800128#define NONCACHE_OFFSET (__PAGE_OFFSET + 0x20000000)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129#else
130#define NONCACHE_OFFSET __PAGE_OFFSET
131#endif /* CONFIG_MMU */
132
133#define M32R_ICU_ISTS_ADDR M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET
134#define M32R_ICU_IPICR_ADDR M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET
135#define M32R_ICU_IMASK_ADDR M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET
136#define M32R_FPGA_CPU_NAME_ADDR M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET
137#define M32R_FPGA_MODEL_ID_ADDR M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET
138#define M32R_FPGA_VERSION_ADDR M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET
139
140#endif /* _ASM_M32R_M32R_H_ */