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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
3 * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org>
4 * Copyright (C) 1999 SuSE GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#ifndef _PARISC_ASSEMBLY_H
22#define _PARISC_ASSEMBLY_H
23
James Bottomley618febd2005-10-21 22:53:26 -040024#define CALLEE_FLOAT_FRAME_SIZE 80
Grant Grundler61520e12005-10-21 22:56:35 -040025
26#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#define LDREG ldd
28#define STREG std
29#define LDREGX ldd,s
30#define LDREGM ldd,mb
31#define STREGM std,ma
32#define SHRREG shrd
33#define RP_OFFSET 16
34#define FRAME_SIZE 128
James Bottomley618febd2005-10-21 22:53:26 -040035#define CALLEE_REG_FRAME_SIZE 144
Grant Grundler61520e12005-10-21 22:56:35 -040036#else /* CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -070037#define LDREG ldw
38#define STREG stw
39#define LDREGX ldwx,s
40#define LDREGM ldwm
41#define STREGM stwm
42#define SHRREG shr
43#define RP_OFFSET 20
44#define FRAME_SIZE 64
James Bottomley618febd2005-10-21 22:53:26 -040045#define CALLEE_REG_FRAME_SIZE 128
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#endif
Grant Grundler61520e12005-10-21 22:56:35 -040047
James Bottomley618febd2005-10-21 22:53:26 -040048#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -070049
50#ifdef CONFIG_PA20
Kyle McMartin64f49532006-04-22 00:48:22 -060051#define LDCW ldcw,co
Linus Torvalds1da177e2005-04-16 15:20:36 -070052#define BL b,l
53# ifdef CONFIG_64BIT
54# define LEVEL 2.0w
55# else
56# define LEVEL 2.0
57# endif
58#else
Kyle McMartin64f49532006-04-22 00:48:22 -060059#define LDCW ldcw
Linus Torvalds1da177e2005-04-16 15:20:36 -070060#define BL bl
61#define LEVEL 1.1
62#endif
63
64#ifdef __ASSEMBLY__
65
66#ifdef __LP64__
67/* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so
68 * work around that for now... */
69 .level 2.0w
70#endif
71
Sam Ravnborg0013a852005-09-09 20:57:26 +020072#include <asm/asm-offsets.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070073#include <asm/page.h>
74
75#include <asm/asmregs.h>
76
77 sp = 30
78 gp = 27
79 ipsw = 22
80
81 /*
82 * We provide two versions of each macro to convert from physical
83 * to virtual and vice versa. The "_r1" versions take one argument
84 * register, but trashes r1 to do the conversion. The other
85 * version takes two arguments: a src and destination register.
86 * However, the source and destination registers can not be
87 * the same register.
88 */
89
90 .macro tophys grvirt, grphys
91 ldil L%(__PAGE_OFFSET), \grphys
92 sub \grvirt, \grphys, \grphys
93 .endm
94
95 .macro tovirt grphys, grvirt
96 ldil L%(__PAGE_OFFSET), \grvirt
97 add \grphys, \grvirt, \grvirt
98 .endm
99
100 .macro tophys_r1 gr
101 ldil L%(__PAGE_OFFSET), %r1
102 sub \gr, %r1, \gr
103 .endm
104
105 .macro tovirt_r1 gr
106 ldil L%(__PAGE_OFFSET), %r1
107 add \gr, %r1, \gr
108 .endm
109
110 .macro delay value
111 ldil L%\value, 1
112 ldo R%\value(1), 1
113 addib,UV,n -1,1,.
114 addib,NUV,n -1,1,.+8
115 nop
116 .endm
117
118 .macro debug value
119 .endm
120
121
122 /* Shift Left - note the r and t can NOT be the same! */
123 .macro shl r, sa, t
124 dep,z \r, 31-\sa, 32-\sa, \t
125 .endm
126
127 /* The PA 2.0 shift left */
128 .macro shlw r, sa, t
129 depw,z \r, 31-\sa, 32-\sa, \t
130 .endm
131
132 /* And the PA 2.0W shift left */
133 .macro shld r, sa, t
134 depd,z \r, 63-\sa, 64-\sa, \t
135 .endm
136
137 /* Shift Right - note the r and t can NOT be the same! */
138 .macro shr r, sa, t
139 extru \r, 31-\sa, 32-\sa, \t
140 .endm
141
142 /* pa20w version of shift right */
143 .macro shrd r, sa, t
144 extrd,u \r, 63-\sa, 64-\sa, \t
145 .endm
146
147 /* load 32-bit 'value' into 'reg' compensating for the ldil
148 * sign-extension when running in wide mode.
149 * WARNING!! neither 'value' nor 'reg' can be expressions
150 * containing '.'!!!! */
151 .macro load32 value, reg
152 ldil L%\value, \reg
153 ldo R%\value(\reg), \reg
154 .endm
155
156 .macro loadgp
157#ifdef __LP64__
158 ldil L%__gp, %r27
159 ldo R%__gp(%r27), %r27
160#else
161 ldil L%$global$, %r27
162 ldo R%$global$(%r27), %r27
163#endif
164 .endm
165
166#define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
167#define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
168#define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
169#define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
170
171 .macro save_general regs
172 STREG %r1, PT_GR1 (\regs)
173 STREG %r2, PT_GR2 (\regs)
174 STREG %r3, PT_GR3 (\regs)
175 STREG %r4, PT_GR4 (\regs)
176 STREG %r5, PT_GR5 (\regs)
177 STREG %r6, PT_GR6 (\regs)
178 STREG %r7, PT_GR7 (\regs)
179 STREG %r8, PT_GR8 (\regs)
180 STREG %r9, PT_GR9 (\regs)
181 STREG %r10, PT_GR10(\regs)
182 STREG %r11, PT_GR11(\regs)
183 STREG %r12, PT_GR12(\regs)
184 STREG %r13, PT_GR13(\regs)
185 STREG %r14, PT_GR14(\regs)
186 STREG %r15, PT_GR15(\regs)
187 STREG %r16, PT_GR16(\regs)
188 STREG %r17, PT_GR17(\regs)
189 STREG %r18, PT_GR18(\regs)
190 STREG %r19, PT_GR19(\regs)
191 STREG %r20, PT_GR20(\regs)
192 STREG %r21, PT_GR21(\regs)
193 STREG %r22, PT_GR22(\regs)
194 STREG %r23, PT_GR23(\regs)
195 STREG %r24, PT_GR24(\regs)
196 STREG %r25, PT_GR25(\regs)
197 /* r26 is saved in get_stack and used to preserve a value across virt_map */
198 STREG %r27, PT_GR27(\regs)
199 STREG %r28, PT_GR28(\regs)
200 /* r29 is saved in get_stack and used to point to saved registers */
201 /* r30 stack pointer saved in get_stack */
202 STREG %r31, PT_GR31(\regs)
203 .endm
204
205 .macro rest_general regs
206 /* r1 used as a temp in rest_stack and is restored there */
207 LDREG PT_GR2 (\regs), %r2
208 LDREG PT_GR3 (\regs), %r3
209 LDREG PT_GR4 (\regs), %r4
210 LDREG PT_GR5 (\regs), %r5
211 LDREG PT_GR6 (\regs), %r6
212 LDREG PT_GR7 (\regs), %r7
213 LDREG PT_GR8 (\regs), %r8
214 LDREG PT_GR9 (\regs), %r9
215 LDREG PT_GR10(\regs), %r10
216 LDREG PT_GR11(\regs), %r11
217 LDREG PT_GR12(\regs), %r12
218 LDREG PT_GR13(\regs), %r13
219 LDREG PT_GR14(\regs), %r14
220 LDREG PT_GR15(\regs), %r15
221 LDREG PT_GR16(\regs), %r16
222 LDREG PT_GR17(\regs), %r17
223 LDREG PT_GR18(\regs), %r18
224 LDREG PT_GR19(\regs), %r19
225 LDREG PT_GR20(\regs), %r20
226 LDREG PT_GR21(\regs), %r21
227 LDREG PT_GR22(\regs), %r22
228 LDREG PT_GR23(\regs), %r23
229 LDREG PT_GR24(\regs), %r24
230 LDREG PT_GR25(\regs), %r25
231 LDREG PT_GR26(\regs), %r26
232 LDREG PT_GR27(\regs), %r27
233 LDREG PT_GR28(\regs), %r28
234 /* r29 points to register save area, and is restored in rest_stack */
235 /* r30 stack pointer restored in rest_stack */
236 LDREG PT_GR31(\regs), %r31
237 .endm
238
239 .macro save_fp regs
240 fstd,ma %fr0, 8(\regs)
241 fstd,ma %fr1, 8(\regs)
242 fstd,ma %fr2, 8(\regs)
243 fstd,ma %fr3, 8(\regs)
244 fstd,ma %fr4, 8(\regs)
245 fstd,ma %fr5, 8(\regs)
246 fstd,ma %fr6, 8(\regs)
247 fstd,ma %fr7, 8(\regs)
248 fstd,ma %fr8, 8(\regs)
249 fstd,ma %fr9, 8(\regs)
250 fstd,ma %fr10, 8(\regs)
251 fstd,ma %fr11, 8(\regs)
252 fstd,ma %fr12, 8(\regs)
253 fstd,ma %fr13, 8(\regs)
254 fstd,ma %fr14, 8(\regs)
255 fstd,ma %fr15, 8(\regs)
256 fstd,ma %fr16, 8(\regs)
257 fstd,ma %fr17, 8(\regs)
258 fstd,ma %fr18, 8(\regs)
259 fstd,ma %fr19, 8(\regs)
260 fstd,ma %fr20, 8(\regs)
261 fstd,ma %fr21, 8(\regs)
262 fstd,ma %fr22, 8(\regs)
263 fstd,ma %fr23, 8(\regs)
264 fstd,ma %fr24, 8(\regs)
265 fstd,ma %fr25, 8(\regs)
266 fstd,ma %fr26, 8(\regs)
267 fstd,ma %fr27, 8(\regs)
268 fstd,ma %fr28, 8(\regs)
269 fstd,ma %fr29, 8(\regs)
270 fstd,ma %fr30, 8(\regs)
271 fstd %fr31, 0(\regs)
272 .endm
273
274 .macro rest_fp regs
275 fldd 0(\regs), %fr31
276 fldd,mb -8(\regs), %fr30
277 fldd,mb -8(\regs), %fr29
278 fldd,mb -8(\regs), %fr28
279 fldd,mb -8(\regs), %fr27
280 fldd,mb -8(\regs), %fr26
281 fldd,mb -8(\regs), %fr25
282 fldd,mb -8(\regs), %fr24
283 fldd,mb -8(\regs), %fr23
284 fldd,mb -8(\regs), %fr22
285 fldd,mb -8(\regs), %fr21
286 fldd,mb -8(\regs), %fr20
287 fldd,mb -8(\regs), %fr19
288 fldd,mb -8(\regs), %fr18
289 fldd,mb -8(\regs), %fr17
290 fldd,mb -8(\regs), %fr16
291 fldd,mb -8(\regs), %fr15
292 fldd,mb -8(\regs), %fr14
293 fldd,mb -8(\regs), %fr13
294 fldd,mb -8(\regs), %fr12
295 fldd,mb -8(\regs), %fr11
296 fldd,mb -8(\regs), %fr10
297 fldd,mb -8(\regs), %fr9
298 fldd,mb -8(\regs), %fr8
299 fldd,mb -8(\regs), %fr7
300 fldd,mb -8(\regs), %fr6
301 fldd,mb -8(\regs), %fr5
302 fldd,mb -8(\regs), %fr4
303 fldd,mb -8(\regs), %fr3
304 fldd,mb -8(\regs), %fr2
305 fldd,mb -8(\regs), %fr1
306 fldd,mb -8(\regs), %fr0
307 .endm
308
James Bottomley618febd2005-10-21 22:53:26 -0400309 .macro callee_save_float
310 fstd,ma %fr12, 8(%r30)
311 fstd,ma %fr13, 8(%r30)
312 fstd,ma %fr14, 8(%r30)
313 fstd,ma %fr15, 8(%r30)
314 fstd,ma %fr16, 8(%r30)
315 fstd,ma %fr17, 8(%r30)
316 fstd,ma %fr18, 8(%r30)
317 fstd,ma %fr19, 8(%r30)
318 fstd,ma %fr20, 8(%r30)
319 fstd,ma %fr21, 8(%r30)
320 .endm
321
322 .macro callee_rest_float
323 fldd,mb -8(%r30), %fr21
324 fldd,mb -8(%r30), %fr20
325 fldd,mb -8(%r30), %fr19
326 fldd,mb -8(%r30), %fr18
327 fldd,mb -8(%r30), %fr17
328 fldd,mb -8(%r30), %fr16
329 fldd,mb -8(%r30), %fr15
330 fldd,mb -8(%r30), %fr14
331 fldd,mb -8(%r30), %fr13
332 fldd,mb -8(%r30), %fr12
333 .endm
334
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335#ifdef __LP64__
336 .macro callee_save
James Bottomley618febd2005-10-21 22:53:26 -0400337 std,ma %r3, CALLEE_REG_FRAME_SIZE(%r30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338 mfctl %cr27, %r3
339 std %r4, -136(%r30)
340 std %r5, -128(%r30)
341 std %r6, -120(%r30)
342 std %r7, -112(%r30)
343 std %r8, -104(%r30)
344 std %r9, -96(%r30)
345 std %r10, -88(%r30)
346 std %r11, -80(%r30)
347 std %r12, -72(%r30)
348 std %r13, -64(%r30)
349 std %r14, -56(%r30)
350 std %r15, -48(%r30)
351 std %r16, -40(%r30)
352 std %r17, -32(%r30)
353 std %r18, -24(%r30)
354 std %r3, -16(%r30)
355 .endm
356
357 .macro callee_rest
358 ldd -16(%r30), %r3
359 ldd -24(%r30), %r18
360 ldd -32(%r30), %r17
361 ldd -40(%r30), %r16
362 ldd -48(%r30), %r15
363 ldd -56(%r30), %r14
364 ldd -64(%r30), %r13
365 ldd -72(%r30), %r12
366 ldd -80(%r30), %r11
367 ldd -88(%r30), %r10
368 ldd -96(%r30), %r9
369 ldd -104(%r30), %r8
370 ldd -112(%r30), %r7
371 ldd -120(%r30), %r6
372 ldd -128(%r30), %r5
373 ldd -136(%r30), %r4
374 mtctl %r3, %cr27
James Bottomley618febd2005-10-21 22:53:26 -0400375 ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376 .endm
377
378#else /* ! __LP64__ */
379
380 .macro callee_save
James Bottomley618febd2005-10-21 22:53:26 -0400381 stw,ma %r3, CALLEE_REG_FRAME_SIZE(%r30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382 mfctl %cr27, %r3
383 stw %r4, -124(%r30)
384 stw %r5, -120(%r30)
385 stw %r6, -116(%r30)
386 stw %r7, -112(%r30)
387 stw %r8, -108(%r30)
388 stw %r9, -104(%r30)
389 stw %r10, -100(%r30)
390 stw %r11, -96(%r30)
391 stw %r12, -92(%r30)
392 stw %r13, -88(%r30)
393 stw %r14, -84(%r30)
394 stw %r15, -80(%r30)
395 stw %r16, -76(%r30)
396 stw %r17, -72(%r30)
397 stw %r18, -68(%r30)
398 stw %r3, -64(%r30)
399 .endm
400
401 .macro callee_rest
402 ldw -64(%r30), %r3
403 ldw -68(%r30), %r18
404 ldw -72(%r30), %r17
405 ldw -76(%r30), %r16
406 ldw -80(%r30), %r15
407 ldw -84(%r30), %r14
408 ldw -88(%r30), %r13
409 ldw -92(%r30), %r12
410 ldw -96(%r30), %r11
411 ldw -100(%r30), %r10
412 ldw -104(%r30), %r9
413 ldw -108(%r30), %r8
414 ldw -112(%r30), %r7
415 ldw -116(%r30), %r6
416 ldw -120(%r30), %r5
417 ldw -124(%r30), %r4
418 mtctl %r3, %cr27
James Bottomley618febd2005-10-21 22:53:26 -0400419 ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420 .endm
421#endif /* ! __LP64__ */
422
423 .macro save_specials regs
424
425 SAVE_SP (%sr0, PT_SR0 (\regs))
426 SAVE_SP (%sr1, PT_SR1 (\regs))
427 SAVE_SP (%sr2, PT_SR2 (\regs))
428 SAVE_SP (%sr3, PT_SR3 (\regs))
429 SAVE_SP (%sr4, PT_SR4 (\regs))
430 SAVE_SP (%sr5, PT_SR5 (\regs))
431 SAVE_SP (%sr6, PT_SR6 (\regs))
432 SAVE_SP (%sr7, PT_SR7 (\regs))
433
434 SAVE_CR (%cr17, PT_IASQ0(\regs))
435 mtctl %r0, %cr17
436 SAVE_CR (%cr17, PT_IASQ1(\regs))
437
438 SAVE_CR (%cr18, PT_IAOQ0(\regs))
439 mtctl %r0, %cr18
440 SAVE_CR (%cr18, PT_IAOQ1(\regs))
441
442#ifdef __LP64__
443 /* cr11 (sar) is a funny one. 5 bits on PA1.1 and 6 bit on PA2.0
444 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
445 * reads 5 bits. Use mfctl,w to read all six bits. Otherwise
446 * we lose the 6th bit on a save/restore over interrupt.
447 */
448 mfctl,w %cr11, %r1
449 STREG %r1, PT_SAR (\regs)
450#else
451 SAVE_CR (%cr11, PT_SAR (\regs))
452#endif
453 SAVE_CR (%cr19, PT_IIR (\regs))
454
455 /*
456 * Code immediately following this macro (in intr_save) relies
457 * on r8 containing ipsw.
458 */
459 mfctl %cr22, %r8
460 STREG %r8, PT_PSW(\regs)
461 .endm
462
463 .macro rest_specials regs
464
465 REST_SP (%sr0, PT_SR0 (\regs))
466 REST_SP (%sr1, PT_SR1 (\regs))
467 REST_SP (%sr2, PT_SR2 (\regs))
468 REST_SP (%sr3, PT_SR3 (\regs))
469 REST_SP (%sr4, PT_SR4 (\regs))
470 REST_SP (%sr5, PT_SR5 (\regs))
471 REST_SP (%sr6, PT_SR6 (\regs))
472 REST_SP (%sr7, PT_SR7 (\regs))
473
474 REST_CR (%cr17, PT_IASQ0(\regs))
475 REST_CR (%cr17, PT_IASQ1(\regs))
476
477 REST_CR (%cr18, PT_IAOQ0(\regs))
478 REST_CR (%cr18, PT_IAOQ1(\regs))
479
480 REST_CR (%cr11, PT_SAR (\regs))
481
482 REST_CR (%cr22, PT_PSW (\regs))
483 .endm
484
Grant Grundler896a3752005-10-21 22:40:07 -0400485
486 /* First step to create a "relied upon translation"
487 * See PA 2.0 Arch. page F-4 and F-5.
488 *
489 * The ssm was originally necessary due to a "PCxT bug".
490 * But someone decided it needed to be added to the architecture
491 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
492 * It's been carried forward into PA 2.0 Arch as well. :^(
493 *
494 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
495 * rsm/ssm prevents the ifetch unit from speculatively fetching
496 * instructions past this line in the code stream.
497 * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
498 */
499 .macro pcxt_ssm_bug
500 rsm PSW_SM_I,%r0
501 nop /* 1 */
502 nop /* 2 */
503 nop /* 3 */
504 nop /* 4 */
505 nop /* 5 */
506 nop /* 6 */
507 nop /* 7 */
508 .endm
509
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510#endif /* __ASSEMBLY__ */
511#endif