Daniel Tang | d907849 | 2013-06-11 18:40:18 +1000 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/boot/nspire.dtsi |
| 3 | * |
| 4 | * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2, as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | */ |
| 11 | |
| 12 | /include/ "skeleton.dtsi" |
| 13 | |
| 14 | / { |
| 15 | interrupt-parent = <&intc>; |
| 16 | |
| 17 | cpus { |
| 18 | cpu@0 { |
| 19 | compatible = "arm,arm926ejs"; |
| 20 | }; |
| 21 | }; |
| 22 | |
| 23 | bootrom: bootrom@00000000 { |
| 24 | reg = <0x00000000 0x80000>; |
| 25 | }; |
| 26 | |
| 27 | sram: sram@A4000000 { |
| 28 | device = "memory"; |
| 29 | reg = <0xA4000000 0x20000>; |
| 30 | }; |
| 31 | |
| 32 | timer_clk: timer_clk { |
| 33 | #clock-cells = <0>; |
| 34 | compatible = "fixed-clock"; |
| 35 | clock-frequency = <32768>; |
| 36 | }; |
| 37 | |
| 38 | base_clk: base_clk { |
| 39 | #clock-cells = <0>; |
| 40 | reg = <0x900B0024 0x4>; |
| 41 | }; |
| 42 | |
| 43 | ahb_clk: ahb_clk { |
| 44 | #clock-cells = <0>; |
| 45 | reg = <0x900B0024 0x4>; |
| 46 | clocks = <&base_clk>; |
| 47 | }; |
| 48 | |
| 49 | apb_pclk: apb_pclk { |
| 50 | #clock-cells = <0>; |
| 51 | compatible = "fixed-factor-clock"; |
| 52 | clock-div = <2>; |
| 53 | clock-mult = <1>; |
| 54 | clocks = <&ahb_clk>; |
| 55 | }; |
| 56 | |
| 57 | ahb { |
| 58 | compatible = "simple-bus"; |
| 59 | #address-cells = <1>; |
| 60 | #size-cells = <1>; |
| 61 | ranges; |
| 62 | |
| 63 | spi: spi@A9000000 { |
| 64 | reg = <0xA9000000 0x1000>; |
| 65 | }; |
| 66 | |
| 67 | usb0: usb@B0000000 { |
| 68 | reg = <0xB0000000 0x1000>; |
| 69 | interrupts = <8>; |
| 70 | }; |
| 71 | |
| 72 | usb1: usb@B4000000 { |
| 73 | reg = <0xB4000000 0x1000>; |
| 74 | interrupts = <9>; |
| 75 | status = "disabled"; |
| 76 | }; |
| 77 | |
| 78 | lcd: lcd@C0000000 { |
| 79 | compatible = "arm,pl111", "arm,primecell"; |
| 80 | reg = <0xC0000000 0x1000>; |
| 81 | interrupts = <21>; |
| 82 | |
| 83 | clocks = <&apb_pclk>; |
| 84 | clock-names = "apb_pclk"; |
| 85 | }; |
| 86 | |
| 87 | adc: adc@C4000000 { |
| 88 | reg = <0xC4000000 0x1000>; |
| 89 | interrupts = <11>; |
| 90 | }; |
| 91 | |
| 92 | tdes: crypto@C8010000 { |
| 93 | reg = <0xC8010000 0x1000>; |
| 94 | }; |
| 95 | |
| 96 | sha256: crypto@CC000000 { |
| 97 | reg = <0xCC000000 0x1000>; |
| 98 | }; |
| 99 | |
| 100 | apb@90000000 { |
| 101 | compatible = "simple-bus"; |
| 102 | #address-cells = <1>; |
| 103 | #size-cells = <1>; |
| 104 | clock-ranges; |
| 105 | ranges; |
| 106 | |
| 107 | gpio: gpio@90000000 { |
| 108 | reg = <0x90000000 0x1000>; |
| 109 | interrupts = <7>; |
| 110 | }; |
| 111 | |
| 112 | fast_timer: timer@90010000 { |
| 113 | reg = <0x90010000 0x1000>; |
| 114 | interrupts = <17>; |
| 115 | }; |
| 116 | |
| 117 | uart: serial@90020000 { |
| 118 | reg = <0x90020000 0x1000>; |
| 119 | interrupts = <1>; |
| 120 | }; |
| 121 | |
| 122 | timer0: timer@900C0000 { |
| 123 | reg = <0x900C0000 0x1000>; |
| 124 | |
| 125 | clocks = <&timer_clk>; |
| 126 | }; |
| 127 | |
| 128 | timer1: timer@900D0000 { |
| 129 | reg = <0x900D0000 0x1000>; |
| 130 | interrupts = <19>; |
| 131 | |
| 132 | clocks = <&timer_clk>; |
| 133 | }; |
| 134 | |
| 135 | watchdog: watchdog@90060000 { |
| 136 | compatible = "arm,amba-primecell"; |
| 137 | reg = <0x90060000 0x1000>; |
| 138 | interrupts = <3>; |
| 139 | }; |
| 140 | |
| 141 | rtc: rtc@90090000 { |
| 142 | reg = <0x90090000 0x1000>; |
| 143 | interrupts = <4>; |
| 144 | }; |
| 145 | |
| 146 | misc: misc@900A0000 { |
| 147 | reg = <0x900A0000 0x1000>; |
| 148 | }; |
| 149 | |
| 150 | pwr: pwr@900B0000 { |
| 151 | reg = <0x900B0000 0x1000>; |
| 152 | interrupts = <15>; |
| 153 | }; |
| 154 | |
| 155 | keypad: input@900E0000 { |
| 156 | compatible = "ti,nspire-keypad"; |
| 157 | reg = <0x900E0000 0x1000>; |
| 158 | interrupts = <16>; |
| 159 | |
| 160 | scan-interval = <1000>; |
| 161 | row-delay = <200>; |
| 162 | |
| 163 | clocks = <&apb_pclk>; |
| 164 | }; |
| 165 | |
| 166 | contrast: contrast@900F0000 { |
| 167 | reg = <0x900F0000 0x1000>; |
| 168 | }; |
| 169 | |
| 170 | led: led@90110000 { |
| 171 | reg = <0x90110000 0x1000>; |
| 172 | }; |
| 173 | }; |
| 174 | }; |
| 175 | }; |