Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include "drmP.h" |
| 27 | #include "radeon_drm.h" |
| 28 | #include "radeon.h" |
| 29 | |
| 30 | #include "atom.h" |
| 31 | #include "atom-bits.h" |
| 32 | |
| 33 | /* from radeon_encoder.c */ |
| 34 | extern uint32_t |
| 35 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, |
| 36 | uint8_t dac); |
| 37 | extern void radeon_link_encoder_connector(struct drm_device *dev); |
| 38 | extern void |
| 39 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, |
| 40 | uint32_t supported_device); |
| 41 | |
| 42 | /* from radeon_connector.c */ |
| 43 | extern void |
| 44 | radeon_add_atom_connector(struct drm_device *dev, |
| 45 | uint32_t connector_id, |
| 46 | uint32_t supported_device, |
| 47 | int connector_type, |
| 48 | struct radeon_i2c_bus_rec *i2c_bus, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 49 | bool linkb, uint32_t igp_lane_info, |
| 50 | uint16_t connector_object_id); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 51 | |
| 52 | /* from radeon_legacy_encoder.c */ |
| 53 | extern void |
| 54 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, |
| 55 | uint32_t supported_device); |
| 56 | |
| 57 | union atom_supported_devices { |
| 58 | struct _ATOM_SUPPORTED_DEVICES_INFO info; |
| 59 | struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; |
| 60 | struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; |
| 61 | }; |
| 62 | |
| 63 | static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device |
| 64 | *dev, uint8_t id) |
| 65 | { |
| 66 | struct radeon_device *rdev = dev->dev_private; |
| 67 | struct atom_context *ctx = rdev->mode_info.atom_context; |
| 68 | ATOM_GPIO_I2C_ASSIGMENT gpio; |
| 69 | struct radeon_i2c_bus_rec i2c; |
| 70 | int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); |
| 71 | struct _ATOM_GPIO_I2C_INFO *i2c_info; |
| 72 | uint16_t data_offset; |
| 73 | |
| 74 | memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); |
| 75 | i2c.valid = false; |
| 76 | |
| 77 | atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset); |
| 78 | |
| 79 | i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); |
| 80 | |
| 81 | gpio = i2c_info->asGPIO_Info[id]; |
| 82 | |
| 83 | i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4; |
| 84 | i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4; |
Alex Deucher | 9b9fe72 | 2009-11-10 15:59:44 -0500 | [diff] [blame] | 85 | i2c.en_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4; |
| 86 | i2c.en_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4; |
| 87 | i2c.y_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4; |
| 88 | i2c.y_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 89 | i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4; |
| 90 | i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4; |
| 91 | i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift); |
| 92 | i2c.mask_data_mask = (1 << gpio.ucDataMaskShift); |
Alex Deucher | 9b9fe72 | 2009-11-10 15:59:44 -0500 | [diff] [blame] | 93 | i2c.en_clk_mask = (1 << gpio.ucClkEnShift); |
| 94 | i2c.en_data_mask = (1 << gpio.ucDataEnShift); |
| 95 | i2c.y_clk_mask = (1 << gpio.ucClkY_Shift); |
| 96 | i2c.y_data_mask = (1 << gpio.ucDataY_Shift); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 97 | i2c.a_clk_mask = (1 << gpio.ucClkA_Shift); |
| 98 | i2c.a_data_mask = (1 << gpio.ucDataA_Shift); |
| 99 | i2c.valid = true; |
| 100 | |
| 101 | return i2c; |
| 102 | } |
| 103 | |
| 104 | static bool radeon_atom_apply_quirks(struct drm_device *dev, |
| 105 | uint32_t supported_device, |
| 106 | int *connector_type, |
Alex Deucher | 848577e | 2009-07-08 16:15:30 -0400 | [diff] [blame] | 107 | struct radeon_i2c_bus_rec *i2c_bus, |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 108 | uint16_t *line_mux) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 109 | { |
| 110 | |
| 111 | /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ |
| 112 | if ((dev->pdev->device == 0x791e) && |
| 113 | (dev->pdev->subsystem_vendor == 0x1043) && |
| 114 | (dev->pdev->subsystem_device == 0x826d)) { |
| 115 | if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && |
| 116 | (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) |
| 117 | *connector_type = DRM_MODE_CONNECTOR_DVID; |
| 118 | } |
| 119 | |
| 120 | /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ |
| 121 | if ((dev->pdev->device == 0x7941) && |
| 122 | (dev->pdev->subsystem_vendor == 0x147b) && |
| 123 | (dev->pdev->subsystem_device == 0x2412)) { |
| 124 | if (*connector_type == DRM_MODE_CONNECTOR_DVII) |
| 125 | return false; |
| 126 | } |
| 127 | |
| 128 | /* Falcon NW laptop lists vga ddc line for LVDS */ |
| 129 | if ((dev->pdev->device == 0x5653) && |
| 130 | (dev->pdev->subsystem_vendor == 0x1462) && |
| 131 | (dev->pdev->subsystem_device == 0x0291)) { |
Alex Deucher | 848577e | 2009-07-08 16:15:30 -0400 | [diff] [blame] | 132 | if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 133 | i2c_bus->valid = false; |
Alex Deucher | 848577e | 2009-07-08 16:15:30 -0400 | [diff] [blame] | 134 | *line_mux = 53; |
| 135 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 136 | } |
| 137 | |
Alex Deucher | 4e3f9b78 | 2009-12-01 14:49:50 -0500 | [diff] [blame] | 138 | /* HIS X1300 is DVI+VGA, not DVI+DVI */ |
| 139 | if ((dev->pdev->device == 0x7146) && |
| 140 | (dev->pdev->subsystem_vendor == 0x17af) && |
| 141 | (dev->pdev->subsystem_device == 0x2058)) { |
| 142 | if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) |
| 143 | return false; |
| 144 | } |
| 145 | |
Dave Airlie | aa1a750 | 2009-12-04 11:51:34 +1000 | [diff] [blame^] | 146 | /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ |
| 147 | if ((dev->pdev->device == 0x7142) && |
| 148 | (dev->pdev->subsystem_vendor == 0x1458) && |
| 149 | (dev->pdev->subsystem_device == 0x2134)) { |
| 150 | if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) |
| 151 | return false; |
| 152 | } |
| 153 | |
| 154 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 155 | /* Funky macbooks */ |
| 156 | if ((dev->pdev->device == 0x71C5) && |
| 157 | (dev->pdev->subsystem_vendor == 0x106b) && |
| 158 | (dev->pdev->subsystem_device == 0x0080)) { |
| 159 | if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || |
| 160 | (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) |
| 161 | return false; |
| 162 | } |
| 163 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 164 | /* ASUS HD 3600 XT board lists the DVI port as HDMI */ |
| 165 | if ((dev->pdev->device == 0x9598) && |
| 166 | (dev->pdev->subsystem_vendor == 0x1043) && |
| 167 | (dev->pdev->subsystem_device == 0x01da)) { |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 168 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
Alex Deucher | d42571e | 2009-09-11 15:27:14 -0400 | [diff] [blame] | 169 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 170 | } |
| 171 | } |
| 172 | |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 173 | /* ASUS HD 3450 board lists the DVI port as HDMI */ |
| 174 | if ((dev->pdev->device == 0x95C5) && |
| 175 | (dev->pdev->subsystem_vendor == 0x1043) && |
| 176 | (dev->pdev->subsystem_device == 0x01e2)) { |
| 177 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
Alex Deucher | d42571e | 2009-09-11 15:27:14 -0400 | [diff] [blame] | 178 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 179 | } |
| 180 | } |
| 181 | |
| 182 | /* some BIOSes seem to report DAC on HDMI - usually this is a board with |
| 183 | * HDMI + VGA reporting as HDMI |
| 184 | */ |
| 185 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
| 186 | if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { |
| 187 | *connector_type = DRM_MODE_CONNECTOR_VGA; |
| 188 | *line_mux = 0; |
| 189 | } |
| 190 | } |
| 191 | |
Alex Deucher | 3e5f8ff | 2009-11-17 17:12:10 -0500 | [diff] [blame] | 192 | /* Acer laptop reports DVI-D as DVI-I */ |
| 193 | if ((dev->pdev->device == 0x95c4) && |
| 194 | (dev->pdev->subsystem_vendor == 0x1025) && |
| 195 | (dev->pdev->subsystem_device == 0x013c)) { |
| 196 | if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && |
| 197 | (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) |
| 198 | *connector_type = DRM_MODE_CONNECTOR_DVID; |
| 199 | } |
| 200 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 201 | return true; |
| 202 | } |
| 203 | |
| 204 | const int supported_devices_connector_convert[] = { |
| 205 | DRM_MODE_CONNECTOR_Unknown, |
| 206 | DRM_MODE_CONNECTOR_VGA, |
| 207 | DRM_MODE_CONNECTOR_DVII, |
| 208 | DRM_MODE_CONNECTOR_DVID, |
| 209 | DRM_MODE_CONNECTOR_DVIA, |
| 210 | DRM_MODE_CONNECTOR_SVIDEO, |
| 211 | DRM_MODE_CONNECTOR_Composite, |
| 212 | DRM_MODE_CONNECTOR_LVDS, |
| 213 | DRM_MODE_CONNECTOR_Unknown, |
| 214 | DRM_MODE_CONNECTOR_Unknown, |
| 215 | DRM_MODE_CONNECTOR_HDMIA, |
| 216 | DRM_MODE_CONNECTOR_HDMIB, |
| 217 | DRM_MODE_CONNECTOR_Unknown, |
| 218 | DRM_MODE_CONNECTOR_Unknown, |
| 219 | DRM_MODE_CONNECTOR_9PinDIN, |
| 220 | DRM_MODE_CONNECTOR_DisplayPort |
| 221 | }; |
| 222 | |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 223 | const uint16_t supported_devices_connector_object_id_convert[] = { |
| 224 | CONNECTOR_OBJECT_ID_NONE, |
| 225 | CONNECTOR_OBJECT_ID_VGA, |
| 226 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ |
| 227 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ |
| 228 | CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ |
| 229 | CONNECTOR_OBJECT_ID_COMPOSITE, |
| 230 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 231 | CONNECTOR_OBJECT_ID_LVDS, |
| 232 | CONNECTOR_OBJECT_ID_9PIN_DIN, |
| 233 | CONNECTOR_OBJECT_ID_9PIN_DIN, |
| 234 | CONNECTOR_OBJECT_ID_DISPLAYPORT, |
| 235 | CONNECTOR_OBJECT_ID_HDMI_TYPE_A, |
| 236 | CONNECTOR_OBJECT_ID_HDMI_TYPE_B, |
| 237 | CONNECTOR_OBJECT_ID_SVIDEO |
| 238 | }; |
| 239 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 240 | const int object_connector_convert[] = { |
| 241 | DRM_MODE_CONNECTOR_Unknown, |
| 242 | DRM_MODE_CONNECTOR_DVII, |
| 243 | DRM_MODE_CONNECTOR_DVII, |
| 244 | DRM_MODE_CONNECTOR_DVID, |
| 245 | DRM_MODE_CONNECTOR_DVID, |
| 246 | DRM_MODE_CONNECTOR_VGA, |
| 247 | DRM_MODE_CONNECTOR_Composite, |
| 248 | DRM_MODE_CONNECTOR_SVIDEO, |
| 249 | DRM_MODE_CONNECTOR_Unknown, |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 250 | DRM_MODE_CONNECTOR_Unknown, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 251 | DRM_MODE_CONNECTOR_9PinDIN, |
| 252 | DRM_MODE_CONNECTOR_Unknown, |
| 253 | DRM_MODE_CONNECTOR_HDMIA, |
| 254 | DRM_MODE_CONNECTOR_HDMIB, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 255 | DRM_MODE_CONNECTOR_LVDS, |
| 256 | DRM_MODE_CONNECTOR_9PinDIN, |
| 257 | DRM_MODE_CONNECTOR_Unknown, |
| 258 | DRM_MODE_CONNECTOR_Unknown, |
| 259 | DRM_MODE_CONNECTOR_Unknown, |
| 260 | DRM_MODE_CONNECTOR_DisplayPort |
| 261 | }; |
| 262 | |
| 263 | bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) |
| 264 | { |
| 265 | struct radeon_device *rdev = dev->dev_private; |
| 266 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 267 | struct atom_context *ctx = mode_info->atom_context; |
| 268 | int index = GetIndexIntoMasterTable(DATA, Object_Header); |
| 269 | uint16_t size, data_offset; |
| 270 | uint8_t frev, crev, line_mux = 0; |
| 271 | ATOM_CONNECTOR_OBJECT_TABLE *con_obj; |
| 272 | ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; |
| 273 | ATOM_OBJECT_HEADER *obj_header; |
| 274 | int i, j, path_size, device_support; |
| 275 | int connector_type; |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 276 | uint16_t igp_lane_info, conn_id, connector_object_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 277 | bool linkb; |
| 278 | struct radeon_i2c_bus_rec ddc_bus; |
| 279 | |
| 280 | atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); |
| 281 | |
| 282 | if (data_offset == 0) |
| 283 | return false; |
| 284 | |
| 285 | if (crev < 2) |
| 286 | return false; |
| 287 | |
| 288 | obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); |
| 289 | path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) |
| 290 | (ctx->bios + data_offset + |
| 291 | le16_to_cpu(obj_header->usDisplayPathTableOffset)); |
| 292 | con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) |
| 293 | (ctx->bios + data_offset + |
| 294 | le16_to_cpu(obj_header->usConnectorObjectTableOffset)); |
| 295 | device_support = le16_to_cpu(obj_header->usDeviceSupport); |
| 296 | |
| 297 | path_size = 0; |
| 298 | for (i = 0; i < path_obj->ucNumOfDispPath; i++) { |
| 299 | uint8_t *addr = (uint8_t *) path_obj->asDispPath; |
| 300 | ATOM_DISPLAY_OBJECT_PATH *path; |
| 301 | addr += path_size; |
| 302 | path = (ATOM_DISPLAY_OBJECT_PATH *) addr; |
| 303 | path_size += le16_to_cpu(path->usSize); |
| 304 | linkb = false; |
| 305 | |
| 306 | if (device_support & le16_to_cpu(path->usDeviceTag)) { |
| 307 | uint8_t con_obj_id, con_obj_num, con_obj_type; |
| 308 | |
| 309 | con_obj_id = |
| 310 | (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) |
| 311 | >> OBJECT_ID_SHIFT; |
| 312 | con_obj_num = |
| 313 | (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) |
| 314 | >> ENUM_ID_SHIFT; |
| 315 | con_obj_type = |
| 316 | (le16_to_cpu(path->usConnObjectId) & |
| 317 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; |
| 318 | |
Dave Airlie | 4bbd497 | 2009-09-25 08:56:12 +1000 | [diff] [blame] | 319 | /* TODO CV support */ |
| 320 | if (le16_to_cpu(path->usDeviceTag) == |
| 321 | ATOM_DEVICE_CV_SUPPORT) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 322 | continue; |
| 323 | |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 324 | /* IGP chips */ |
| 325 | if ((rdev->flags & RADEON_IS_IGP) && |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 326 | (con_obj_id == |
| 327 | CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { |
| 328 | uint16_t igp_offset = 0; |
| 329 | ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; |
| 330 | |
| 331 | index = |
| 332 | GetIndexIntoMasterTable(DATA, |
| 333 | IntegratedSystemInfo); |
| 334 | |
| 335 | atom_parse_data_header(ctx, index, &size, &frev, |
| 336 | &crev, &igp_offset); |
| 337 | |
| 338 | if (crev >= 2) { |
| 339 | igp_obj = |
| 340 | (ATOM_INTEGRATED_SYSTEM_INFO_V2 |
| 341 | *) (ctx->bios + igp_offset); |
| 342 | |
| 343 | if (igp_obj) { |
| 344 | uint32_t slot_config, ct; |
| 345 | |
| 346 | if (con_obj_num == 1) |
| 347 | slot_config = |
| 348 | igp_obj-> |
| 349 | ulDDISlot1Config; |
| 350 | else |
| 351 | slot_config = |
| 352 | igp_obj-> |
| 353 | ulDDISlot2Config; |
| 354 | |
| 355 | ct = (slot_config >> 16) & 0xff; |
| 356 | connector_type = |
| 357 | object_connector_convert |
| 358 | [ct]; |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 359 | connector_object_id = ct; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 360 | igp_lane_info = |
| 361 | slot_config & 0xffff; |
| 362 | } else |
| 363 | continue; |
| 364 | } else |
| 365 | continue; |
| 366 | } else { |
| 367 | igp_lane_info = 0; |
| 368 | connector_type = |
| 369 | object_connector_convert[con_obj_id]; |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 370 | connector_object_id = con_obj_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 371 | } |
| 372 | |
| 373 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
| 374 | continue; |
| 375 | |
| 376 | for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); |
| 377 | j++) { |
| 378 | uint8_t enc_obj_id, enc_obj_num, enc_obj_type; |
| 379 | |
| 380 | enc_obj_id = |
| 381 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
| 382 | OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
| 383 | enc_obj_num = |
| 384 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
| 385 | ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
| 386 | enc_obj_type = |
| 387 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
| 388 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; |
| 389 | |
| 390 | /* FIXME: add support for router objects */ |
| 391 | if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { |
| 392 | if (enc_obj_num == 2) |
| 393 | linkb = true; |
| 394 | else |
| 395 | linkb = false; |
| 396 | |
| 397 | radeon_add_atom_encoder(dev, |
| 398 | enc_obj_id, |
| 399 | le16_to_cpu |
| 400 | (path-> |
| 401 | usDeviceTag)); |
| 402 | |
| 403 | } |
| 404 | } |
| 405 | |
| 406 | /* look up gpio for ddc */ |
| 407 | if ((le16_to_cpu(path->usDeviceTag) & |
| 408 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
| 409 | == 0) { |
| 410 | for (j = 0; j < con_obj->ucNumberOfObjects; j++) { |
| 411 | if (le16_to_cpu(path->usConnObjectId) == |
| 412 | le16_to_cpu(con_obj->asObjects[j]. |
| 413 | usObjectID)) { |
| 414 | ATOM_COMMON_RECORD_HEADER |
| 415 | *record = |
| 416 | (ATOM_COMMON_RECORD_HEADER |
| 417 | *) |
| 418 | (ctx->bios + data_offset + |
| 419 | le16_to_cpu(con_obj-> |
| 420 | asObjects[j]. |
| 421 | usRecordOffset)); |
| 422 | ATOM_I2C_RECORD *i2c_record; |
| 423 | |
| 424 | while (record->ucRecordType > 0 |
| 425 | && record-> |
| 426 | ucRecordType <= |
| 427 | ATOM_MAX_OBJECT_RECORD_NUMBER) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 428 | switch (record-> |
| 429 | ucRecordType) { |
| 430 | case ATOM_I2C_RECORD_TYPE: |
| 431 | i2c_record = |
| 432 | (ATOM_I2C_RECORD |
| 433 | *) record; |
| 434 | line_mux = |
| 435 | i2c_record-> |
| 436 | sucI2cId. |
| 437 | bfI2C_LineMux; |
| 438 | break; |
| 439 | } |
| 440 | record = |
| 441 | (ATOM_COMMON_RECORD_HEADER |
| 442 | *) ((char *)record |
| 443 | + |
| 444 | record-> |
| 445 | ucRecordSize); |
| 446 | } |
| 447 | break; |
| 448 | } |
| 449 | } |
| 450 | } else |
| 451 | line_mux = 0; |
| 452 | |
| 453 | if ((le16_to_cpu(path->usDeviceTag) == |
| 454 | ATOM_DEVICE_TV1_SUPPORT) |
| 455 | || (le16_to_cpu(path->usDeviceTag) == |
| 456 | ATOM_DEVICE_TV2_SUPPORT) |
| 457 | || (le16_to_cpu(path->usDeviceTag) == |
| 458 | ATOM_DEVICE_CV_SUPPORT)) |
| 459 | ddc_bus.valid = false; |
| 460 | else |
| 461 | ddc_bus = radeon_lookup_gpio(dev, line_mux); |
| 462 | |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 463 | conn_id = le16_to_cpu(path->usConnObjectId); |
| 464 | |
| 465 | if (!radeon_atom_apply_quirks |
| 466 | (dev, le16_to_cpu(path->usDeviceTag), &connector_type, |
| 467 | &ddc_bus, &conn_id)) |
| 468 | continue; |
| 469 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 470 | radeon_add_atom_connector(dev, |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 471 | conn_id, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 472 | le16_to_cpu(path-> |
| 473 | usDeviceTag), |
| 474 | connector_type, &ddc_bus, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 475 | linkb, igp_lane_info, |
| 476 | connector_object_id); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 477 | |
| 478 | } |
| 479 | } |
| 480 | |
| 481 | radeon_link_encoder_connector(dev); |
| 482 | |
| 483 | return true; |
| 484 | } |
| 485 | |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 486 | static uint16_t atombios_get_connector_object_id(struct drm_device *dev, |
| 487 | int connector_type, |
| 488 | uint16_t devices) |
| 489 | { |
| 490 | struct radeon_device *rdev = dev->dev_private; |
| 491 | |
| 492 | if (rdev->flags & RADEON_IS_IGP) { |
| 493 | return supported_devices_connector_object_id_convert |
| 494 | [connector_type]; |
| 495 | } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || |
| 496 | (connector_type == DRM_MODE_CONNECTOR_DVID)) && |
| 497 | (devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
| 498 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 499 | struct atom_context *ctx = mode_info->atom_context; |
| 500 | int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); |
| 501 | uint16_t size, data_offset; |
| 502 | uint8_t frev, crev; |
| 503 | ATOM_XTMDS_INFO *xtmds; |
| 504 | |
| 505 | atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); |
| 506 | xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); |
| 507 | |
| 508 | if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { |
| 509 | if (connector_type == DRM_MODE_CONNECTOR_DVII) |
| 510 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; |
| 511 | else |
| 512 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; |
| 513 | } else { |
| 514 | if (connector_type == DRM_MODE_CONNECTOR_DVII) |
| 515 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
| 516 | else |
| 517 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; |
| 518 | } |
| 519 | } else { |
| 520 | return supported_devices_connector_object_id_convert |
| 521 | [connector_type]; |
| 522 | } |
| 523 | } |
| 524 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 525 | struct bios_connector { |
| 526 | bool valid; |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 527 | uint16_t line_mux; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 528 | uint16_t devices; |
| 529 | int connector_type; |
| 530 | struct radeon_i2c_bus_rec ddc_bus; |
| 531 | }; |
| 532 | |
| 533 | bool radeon_get_atom_connector_info_from_supported_devices_table(struct |
| 534 | drm_device |
| 535 | *dev) |
| 536 | { |
| 537 | struct radeon_device *rdev = dev->dev_private; |
| 538 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 539 | struct atom_context *ctx = mode_info->atom_context; |
| 540 | int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); |
| 541 | uint16_t size, data_offset; |
| 542 | uint8_t frev, crev; |
| 543 | uint16_t device_support; |
| 544 | uint8_t dac; |
| 545 | union atom_supported_devices *supported_devices; |
| 546 | int i, j; |
| 547 | struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE]; |
| 548 | |
| 549 | atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); |
| 550 | |
| 551 | supported_devices = |
| 552 | (union atom_supported_devices *)(ctx->bios + data_offset); |
| 553 | |
| 554 | device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); |
| 555 | |
| 556 | for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { |
| 557 | ATOM_CONNECTOR_INFO_I2C ci = |
| 558 | supported_devices->info.asConnInfo[i]; |
| 559 | |
| 560 | bios_connectors[i].valid = false; |
| 561 | |
| 562 | if (!(device_support & (1 << i))) { |
| 563 | continue; |
| 564 | } |
| 565 | |
| 566 | if (i == ATOM_DEVICE_CV_INDEX) { |
| 567 | DRM_DEBUG("Skipping Component Video\n"); |
| 568 | continue; |
| 569 | } |
| 570 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 571 | bios_connectors[i].connector_type = |
| 572 | supported_devices_connector_convert[ci.sucConnectorInfo. |
| 573 | sbfAccess. |
| 574 | bfConnectorType]; |
| 575 | |
| 576 | if (bios_connectors[i].connector_type == |
| 577 | DRM_MODE_CONNECTOR_Unknown) |
| 578 | continue; |
| 579 | |
| 580 | dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; |
| 581 | |
| 582 | if ((rdev->family == CHIP_RS690) || |
| 583 | (rdev->family == CHIP_RS740)) { |
| 584 | if ((i == ATOM_DEVICE_DFP2_INDEX) |
| 585 | && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2)) |
| 586 | bios_connectors[i].line_mux = |
| 587 | ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1; |
| 588 | else if ((i == ATOM_DEVICE_DFP3_INDEX) |
| 589 | && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1)) |
| 590 | bios_connectors[i].line_mux = |
| 591 | ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1; |
| 592 | else |
| 593 | bios_connectors[i].line_mux = |
| 594 | ci.sucI2cId.sbfAccess.bfI2C_LineMux; |
| 595 | } else |
| 596 | bios_connectors[i].line_mux = |
| 597 | ci.sucI2cId.sbfAccess.bfI2C_LineMux; |
| 598 | |
| 599 | /* give tv unique connector ids */ |
| 600 | if (i == ATOM_DEVICE_TV1_INDEX) { |
| 601 | bios_connectors[i].ddc_bus.valid = false; |
| 602 | bios_connectors[i].line_mux = 50; |
| 603 | } else if (i == ATOM_DEVICE_TV2_INDEX) { |
| 604 | bios_connectors[i].ddc_bus.valid = false; |
| 605 | bios_connectors[i].line_mux = 51; |
| 606 | } else if (i == ATOM_DEVICE_CV_INDEX) { |
| 607 | bios_connectors[i].ddc_bus.valid = false; |
| 608 | bios_connectors[i].line_mux = 52; |
| 609 | } else |
| 610 | bios_connectors[i].ddc_bus = |
| 611 | radeon_lookup_gpio(dev, |
| 612 | bios_connectors[i].line_mux); |
| 613 | |
| 614 | /* Always set the connector type to VGA for CRT1/CRT2. if they are |
| 615 | * shared with a DVI port, we'll pick up the DVI connector when we |
| 616 | * merge the outputs. Some bioses incorrectly list VGA ports as DVI. |
| 617 | */ |
| 618 | if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) |
| 619 | bios_connectors[i].connector_type = |
| 620 | DRM_MODE_CONNECTOR_VGA; |
| 621 | |
| 622 | if (!radeon_atom_apply_quirks |
| 623 | (dev, (1 << i), &bios_connectors[i].connector_type, |
Alex Deucher | 848577e | 2009-07-08 16:15:30 -0400 | [diff] [blame] | 624 | &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 625 | continue; |
| 626 | |
| 627 | bios_connectors[i].valid = true; |
| 628 | bios_connectors[i].devices = (1 << i); |
| 629 | |
| 630 | if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) |
| 631 | radeon_add_atom_encoder(dev, |
| 632 | radeon_get_encoder_id(dev, |
| 633 | (1 << i), |
| 634 | dac), |
| 635 | (1 << i)); |
| 636 | else |
| 637 | radeon_add_legacy_encoder(dev, |
| 638 | radeon_get_encoder_id(dev, |
| 639 | (1 << |
| 640 | i), |
| 641 | dac), |
| 642 | (1 << i)); |
| 643 | } |
| 644 | |
| 645 | /* combine shared connectors */ |
| 646 | for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { |
| 647 | if (bios_connectors[i].valid) { |
| 648 | for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) { |
| 649 | if (bios_connectors[j].valid && (i != j)) { |
| 650 | if (bios_connectors[i].line_mux == |
| 651 | bios_connectors[j].line_mux) { |
| 652 | if (((bios_connectors[i]. |
| 653 | devices & |
| 654 | (ATOM_DEVICE_DFP_SUPPORT)) |
| 655 | && (bios_connectors[j]. |
| 656 | devices & |
| 657 | (ATOM_DEVICE_CRT_SUPPORT))) |
| 658 | || |
| 659 | ((bios_connectors[j]. |
| 660 | devices & |
| 661 | (ATOM_DEVICE_DFP_SUPPORT)) |
| 662 | && (bios_connectors[i]. |
| 663 | devices & |
| 664 | (ATOM_DEVICE_CRT_SUPPORT)))) { |
| 665 | bios_connectors[i]. |
| 666 | devices |= |
| 667 | bios_connectors[j]. |
| 668 | devices; |
| 669 | bios_connectors[i]. |
| 670 | connector_type = |
| 671 | DRM_MODE_CONNECTOR_DVII; |
| 672 | bios_connectors[j]. |
| 673 | valid = false; |
| 674 | } |
| 675 | } |
| 676 | } |
| 677 | } |
| 678 | } |
| 679 | } |
| 680 | |
| 681 | /* add the connectors */ |
| 682 | for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 683 | if (bios_connectors[i].valid) { |
| 684 | uint16_t connector_object_id = |
| 685 | atombios_get_connector_object_id(dev, |
| 686 | bios_connectors[i].connector_type, |
| 687 | bios_connectors[i].devices); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 688 | radeon_add_atom_connector(dev, |
| 689 | bios_connectors[i].line_mux, |
| 690 | bios_connectors[i].devices, |
| 691 | bios_connectors[i]. |
| 692 | connector_type, |
| 693 | &bios_connectors[i].ddc_bus, |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 694 | false, 0, |
| 695 | connector_object_id); |
| 696 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 697 | } |
| 698 | |
| 699 | radeon_link_encoder_connector(dev); |
| 700 | |
| 701 | return true; |
| 702 | } |
| 703 | |
| 704 | union firmware_info { |
| 705 | ATOM_FIRMWARE_INFO info; |
| 706 | ATOM_FIRMWARE_INFO_V1_2 info_12; |
| 707 | ATOM_FIRMWARE_INFO_V1_3 info_13; |
| 708 | ATOM_FIRMWARE_INFO_V1_4 info_14; |
| 709 | }; |
| 710 | |
| 711 | bool radeon_atom_get_clock_info(struct drm_device *dev) |
| 712 | { |
| 713 | struct radeon_device *rdev = dev->dev_private; |
| 714 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 715 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); |
| 716 | union firmware_info *firmware_info; |
| 717 | uint8_t frev, crev; |
| 718 | struct radeon_pll *p1pll = &rdev->clock.p1pll; |
| 719 | struct radeon_pll *p2pll = &rdev->clock.p2pll; |
| 720 | struct radeon_pll *spll = &rdev->clock.spll; |
| 721 | struct radeon_pll *mpll = &rdev->clock.mpll; |
| 722 | uint16_t data_offset; |
| 723 | |
| 724 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, |
| 725 | &crev, &data_offset); |
| 726 | |
| 727 | firmware_info = |
| 728 | (union firmware_info *)(mode_info->atom_context->bios + |
| 729 | data_offset); |
| 730 | |
| 731 | if (firmware_info) { |
| 732 | /* pixel clocks */ |
| 733 | p1pll->reference_freq = |
| 734 | le16_to_cpu(firmware_info->info.usReferenceClock); |
| 735 | p1pll->reference_div = 0; |
| 736 | |
Mathias Fröhlich | bc293e5 | 2009-10-19 17:49:49 -0400 | [diff] [blame] | 737 | if (crev < 2) |
| 738 | p1pll->pll_out_min = |
| 739 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); |
| 740 | else |
| 741 | p1pll->pll_out_min = |
| 742 | le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 743 | p1pll->pll_out_max = |
| 744 | le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); |
| 745 | |
| 746 | if (p1pll->pll_out_min == 0) { |
| 747 | if (ASIC_IS_AVIVO(rdev)) |
| 748 | p1pll->pll_out_min = 64800; |
| 749 | else |
| 750 | p1pll->pll_out_min = 20000; |
Alex Deucher | 8f552a6 | 2009-10-27 11:16:09 -0400 | [diff] [blame] | 751 | } else if (p1pll->pll_out_min > 64800) { |
| 752 | /* Limiting the pll output range is a good thing generally as |
| 753 | * it limits the number of possible pll combinations for a given |
| 754 | * frequency presumably to the ones that work best on each card. |
| 755 | * However, certain duallink DVI monitors seem to like |
| 756 | * pll combinations that would be limited by this at least on |
| 757 | * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per |
| 758 | * family. |
| 759 | */ |
| 760 | p1pll->pll_out_min = 64800; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 761 | } |
| 762 | |
| 763 | p1pll->pll_in_min = |
| 764 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); |
| 765 | p1pll->pll_in_max = |
| 766 | le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); |
| 767 | |
| 768 | *p2pll = *p1pll; |
| 769 | |
| 770 | /* system clock */ |
| 771 | spll->reference_freq = |
| 772 | le16_to_cpu(firmware_info->info.usReferenceClock); |
| 773 | spll->reference_div = 0; |
| 774 | |
| 775 | spll->pll_out_min = |
| 776 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); |
| 777 | spll->pll_out_max = |
| 778 | le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); |
| 779 | |
| 780 | /* ??? */ |
| 781 | if (spll->pll_out_min == 0) { |
| 782 | if (ASIC_IS_AVIVO(rdev)) |
| 783 | spll->pll_out_min = 64800; |
| 784 | else |
| 785 | spll->pll_out_min = 20000; |
| 786 | } |
| 787 | |
| 788 | spll->pll_in_min = |
| 789 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); |
| 790 | spll->pll_in_max = |
| 791 | le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); |
| 792 | |
| 793 | /* memory clock */ |
| 794 | mpll->reference_freq = |
| 795 | le16_to_cpu(firmware_info->info.usReferenceClock); |
| 796 | mpll->reference_div = 0; |
| 797 | |
| 798 | mpll->pll_out_min = |
| 799 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); |
| 800 | mpll->pll_out_max = |
| 801 | le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); |
| 802 | |
| 803 | /* ??? */ |
| 804 | if (mpll->pll_out_min == 0) { |
| 805 | if (ASIC_IS_AVIVO(rdev)) |
| 806 | mpll->pll_out_min = 64800; |
| 807 | else |
| 808 | mpll->pll_out_min = 20000; |
| 809 | } |
| 810 | |
| 811 | mpll->pll_in_min = |
| 812 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); |
| 813 | mpll->pll_in_max = |
| 814 | le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); |
| 815 | |
| 816 | rdev->clock.default_sclk = |
| 817 | le32_to_cpu(firmware_info->info.ulDefaultEngineClock); |
| 818 | rdev->clock.default_mclk = |
| 819 | le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); |
| 820 | |
| 821 | return true; |
| 822 | } |
| 823 | return false; |
| 824 | } |
| 825 | |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 826 | bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
| 827 | struct radeon_encoder_int_tmds *tmds) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 828 | { |
| 829 | struct drm_device *dev = encoder->base.dev; |
| 830 | struct radeon_device *rdev = dev->dev_private; |
| 831 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 832 | int index = GetIndexIntoMasterTable(DATA, TMDS_Info); |
| 833 | uint16_t data_offset; |
| 834 | struct _ATOM_TMDS_INFO *tmds_info; |
| 835 | uint8_t frev, crev; |
| 836 | uint16_t maxfreq; |
| 837 | int i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 838 | |
| 839 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, |
| 840 | &crev, &data_offset); |
| 841 | |
| 842 | tmds_info = |
| 843 | (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + |
| 844 | data_offset); |
| 845 | |
| 846 | if (tmds_info) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 847 | maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); |
| 848 | for (i = 0; i < 4; i++) { |
| 849 | tmds->tmds_pll[i].freq = |
| 850 | le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); |
| 851 | tmds->tmds_pll[i].value = |
| 852 | tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; |
| 853 | tmds->tmds_pll[i].value |= |
| 854 | (tmds_info->asMiscInfo[i]. |
| 855 | ucPLL_VCO_Gain & 0x3f) << 6; |
| 856 | tmds->tmds_pll[i].value |= |
| 857 | (tmds_info->asMiscInfo[i]. |
| 858 | ucPLL_DutyCycle & 0xf) << 12; |
| 859 | tmds->tmds_pll[i].value |= |
| 860 | (tmds_info->asMiscInfo[i]. |
| 861 | ucPLL_VoltageSwing & 0xf) << 16; |
| 862 | |
| 863 | DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n", |
| 864 | tmds->tmds_pll[i].freq, |
| 865 | tmds->tmds_pll[i].value); |
| 866 | |
| 867 | if (maxfreq == tmds->tmds_pll[i].freq) { |
| 868 | tmds->tmds_pll[i].freq = 0xffffffff; |
| 869 | break; |
| 870 | } |
| 871 | } |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 872 | return true; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 873 | } |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 874 | return false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 875 | } |
| 876 | |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 877 | static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct |
| 878 | radeon_encoder |
| 879 | *encoder, |
| 880 | int id) |
| 881 | { |
| 882 | struct drm_device *dev = encoder->base.dev; |
| 883 | struct radeon_device *rdev = dev->dev_private; |
| 884 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 885 | int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); |
| 886 | uint16_t data_offset; |
| 887 | struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; |
| 888 | uint8_t frev, crev; |
| 889 | struct radeon_atom_ss *ss = NULL; |
| 890 | |
| 891 | if (id > ATOM_MAX_SS_ENTRY) |
| 892 | return NULL; |
| 893 | |
| 894 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, |
| 895 | &crev, &data_offset); |
| 896 | |
| 897 | ss_info = |
| 898 | (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); |
| 899 | |
| 900 | if (ss_info) { |
| 901 | ss = |
| 902 | kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL); |
| 903 | |
| 904 | if (!ss) |
| 905 | return NULL; |
| 906 | |
| 907 | ss->percentage = le16_to_cpu(ss_info->asSS_Info[id].usSpreadSpectrumPercentage); |
| 908 | ss->type = ss_info->asSS_Info[id].ucSpreadSpectrumType; |
| 909 | ss->step = ss_info->asSS_Info[id].ucSS_Step; |
| 910 | ss->delay = ss_info->asSS_Info[id].ucSS_Delay; |
| 911 | ss->range = ss_info->asSS_Info[id].ucSS_Range; |
| 912 | ss->refdiv = ss_info->asSS_Info[id].ucRecommendedRef_Div; |
| 913 | } |
| 914 | return ss; |
| 915 | } |
| 916 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 917 | union lvds_info { |
| 918 | struct _ATOM_LVDS_INFO info; |
| 919 | struct _ATOM_LVDS_INFO_V12 info_12; |
| 920 | }; |
| 921 | |
| 922 | struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct |
| 923 | radeon_encoder |
| 924 | *encoder) |
| 925 | { |
| 926 | struct drm_device *dev = encoder->base.dev; |
| 927 | struct radeon_device *rdev = dev->dev_private; |
| 928 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 929 | int index = GetIndexIntoMasterTable(DATA, LVDS_Info); |
Alex Deucher | 7dde8a19 | 2009-11-30 01:40:24 -0500 | [diff] [blame] | 930 | uint16_t data_offset, misc; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 931 | union lvds_info *lvds_info; |
| 932 | uint8_t frev, crev; |
| 933 | struct radeon_encoder_atom_dig *lvds = NULL; |
| 934 | |
| 935 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, |
| 936 | &crev, &data_offset); |
| 937 | |
| 938 | lvds_info = |
| 939 | (union lvds_info *)(mode_info->atom_context->bios + data_offset); |
| 940 | |
| 941 | if (lvds_info) { |
| 942 | lvds = |
| 943 | kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
| 944 | |
| 945 | if (!lvds) |
| 946 | return NULL; |
| 947 | |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 948 | lvds->native_mode.clock = |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 949 | le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 950 | lvds->native_mode.hdisplay = |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 951 | le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 952 | lvds->native_mode.vdisplay = |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 953 | le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 954 | lvds->native_mode.htotal = lvds->native_mode.hdisplay + |
| 955 | le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); |
| 956 | lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + |
| 957 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); |
| 958 | lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + |
| 959 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); |
| 960 | lvds->native_mode.vtotal = lvds->native_mode.vdisplay + |
| 961 | le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); |
| 962 | lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + |
| 963 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); |
| 964 | lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + |
| 965 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 966 | lvds->panel_pwr_delay = |
| 967 | le16_to_cpu(lvds_info->info.usOffDelayInMs); |
| 968 | lvds->lvds_misc = lvds_info->info.ucLVDS_Misc; |
Alex Deucher | 7dde8a19 | 2009-11-30 01:40:24 -0500 | [diff] [blame] | 969 | |
| 970 | misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); |
| 971 | if (misc & ATOM_VSYNC_POLARITY) |
| 972 | lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
| 973 | if (misc & ATOM_HSYNC_POLARITY) |
| 974 | lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
| 975 | if (misc & ATOM_COMPOSITESYNC) |
| 976 | lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; |
| 977 | if (misc & ATOM_INTERLACE) |
| 978 | lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
| 979 | if (misc & ATOM_DOUBLE_CLOCK_MODE) |
| 980 | lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; |
| 981 | |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 982 | /* set crtc values */ |
| 983 | drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 984 | |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 985 | lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id); |
| 986 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 987 | encoder->native_mode = lvds->native_mode; |
| 988 | } |
| 989 | return lvds; |
| 990 | } |
| 991 | |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 992 | struct radeon_encoder_primary_dac * |
| 993 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) |
| 994 | { |
| 995 | struct drm_device *dev = encoder->base.dev; |
| 996 | struct radeon_device *rdev = dev->dev_private; |
| 997 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 998 | int index = GetIndexIntoMasterTable(DATA, CompassionateData); |
| 999 | uint16_t data_offset; |
| 1000 | struct _COMPASSIONATE_DATA *dac_info; |
| 1001 | uint8_t frev, crev; |
| 1002 | uint8_t bg, dac; |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1003 | struct radeon_encoder_primary_dac *p_dac = NULL; |
| 1004 | |
| 1005 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); |
| 1006 | |
| 1007 | dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset); |
| 1008 | |
| 1009 | if (dac_info) { |
| 1010 | p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); |
| 1011 | |
| 1012 | if (!p_dac) |
| 1013 | return NULL; |
| 1014 | |
| 1015 | bg = dac_info->ucDAC1_BG_Adjustment; |
| 1016 | dac = dac_info->ucDAC1_DAC_Adjustment; |
| 1017 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
| 1018 | |
| 1019 | } |
| 1020 | return p_dac; |
| 1021 | } |
| 1022 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1023 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1024 | struct drm_display_mode *mode) |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1025 | { |
| 1026 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1027 | ATOM_ANALOG_TV_INFO *tv_info; |
| 1028 | ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; |
| 1029 | ATOM_DTD_FORMAT *dtd_timings; |
| 1030 | int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); |
| 1031 | u8 frev, crev; |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1032 | u16 data_offset, misc; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1033 | |
| 1034 | atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset); |
| 1035 | |
| 1036 | switch (crev) { |
| 1037 | case 1: |
| 1038 | tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); |
| 1039 | if (index > MAX_SUPPORTED_TV_TIMING) |
| 1040 | return false; |
| 1041 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1042 | mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); |
| 1043 | mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); |
| 1044 | mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); |
| 1045 | mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + |
| 1046 | le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1047 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1048 | mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); |
| 1049 | mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); |
| 1050 | mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); |
| 1051 | mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + |
| 1052 | le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1053 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1054 | mode->flags = 0; |
| 1055 | misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); |
| 1056 | if (misc & ATOM_VSYNC_POLARITY) |
| 1057 | mode->flags |= DRM_MODE_FLAG_NVSYNC; |
| 1058 | if (misc & ATOM_HSYNC_POLARITY) |
| 1059 | mode->flags |= DRM_MODE_FLAG_NHSYNC; |
| 1060 | if (misc & ATOM_COMPOSITESYNC) |
| 1061 | mode->flags |= DRM_MODE_FLAG_CSYNC; |
| 1062 | if (misc & ATOM_INTERLACE) |
| 1063 | mode->flags |= DRM_MODE_FLAG_INTERLACE; |
| 1064 | if (misc & ATOM_DOUBLE_CLOCK_MODE) |
| 1065 | mode->flags |= DRM_MODE_FLAG_DBLSCAN; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1066 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1067 | mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1068 | |
| 1069 | if (index == 1) { |
| 1070 | /* PAL timings appear to have wrong values for totals */ |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1071 | mode->crtc_htotal -= 1; |
| 1072 | mode->crtc_vtotal -= 1; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1073 | } |
| 1074 | break; |
| 1075 | case 2: |
| 1076 | tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); |
| 1077 | if (index > MAX_SUPPORTED_TV_TIMING_V1_2) |
| 1078 | return false; |
| 1079 | |
| 1080 | dtd_timings = &tv_info_v1_2->aModeTimings[index]; |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1081 | mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + |
| 1082 | le16_to_cpu(dtd_timings->usHBlanking_Time); |
| 1083 | mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); |
| 1084 | mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + |
| 1085 | le16_to_cpu(dtd_timings->usHSyncOffset); |
| 1086 | mode->crtc_hsync_end = mode->crtc_hsync_start + |
| 1087 | le16_to_cpu(dtd_timings->usHSyncWidth); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1088 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1089 | mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + |
| 1090 | le16_to_cpu(dtd_timings->usVBlanking_Time); |
| 1091 | mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); |
| 1092 | mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + |
| 1093 | le16_to_cpu(dtd_timings->usVSyncOffset); |
| 1094 | mode->crtc_vsync_end = mode->crtc_vsync_start + |
| 1095 | le16_to_cpu(dtd_timings->usVSyncWidth); |
| 1096 | |
| 1097 | mode->flags = 0; |
| 1098 | misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); |
| 1099 | if (misc & ATOM_VSYNC_POLARITY) |
| 1100 | mode->flags |= DRM_MODE_FLAG_NVSYNC; |
| 1101 | if (misc & ATOM_HSYNC_POLARITY) |
| 1102 | mode->flags |= DRM_MODE_FLAG_NHSYNC; |
| 1103 | if (misc & ATOM_COMPOSITESYNC) |
| 1104 | mode->flags |= DRM_MODE_FLAG_CSYNC; |
| 1105 | if (misc & ATOM_INTERLACE) |
| 1106 | mode->flags |= DRM_MODE_FLAG_INTERLACE; |
| 1107 | if (misc & ATOM_DOUBLE_CLOCK_MODE) |
| 1108 | mode->flags |= DRM_MODE_FLAG_DBLSCAN; |
| 1109 | |
| 1110 | mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1111 | break; |
| 1112 | } |
| 1113 | return true; |
| 1114 | } |
| 1115 | |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1116 | struct radeon_encoder_tv_dac * |
| 1117 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) |
| 1118 | { |
| 1119 | struct drm_device *dev = encoder->base.dev; |
| 1120 | struct radeon_device *rdev = dev->dev_private; |
| 1121 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1122 | int index = GetIndexIntoMasterTable(DATA, CompassionateData); |
| 1123 | uint16_t data_offset; |
| 1124 | struct _COMPASSIONATE_DATA *dac_info; |
| 1125 | uint8_t frev, crev; |
| 1126 | uint8_t bg, dac; |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1127 | struct radeon_encoder_tv_dac *tv_dac = NULL; |
| 1128 | |
| 1129 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); |
| 1130 | |
| 1131 | dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset); |
| 1132 | |
| 1133 | if (dac_info) { |
| 1134 | tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); |
| 1135 | |
| 1136 | if (!tv_dac) |
| 1137 | return NULL; |
| 1138 | |
| 1139 | bg = dac_info->ucDAC2_CRT2_BG_Adjustment; |
| 1140 | dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; |
| 1141 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); |
| 1142 | |
| 1143 | bg = dac_info->ucDAC2_PAL_BG_Adjustment; |
| 1144 | dac = dac_info->ucDAC2_PAL_DAC_Adjustment; |
| 1145 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
| 1146 | |
| 1147 | bg = dac_info->ucDAC2_NTSC_BG_Adjustment; |
| 1148 | dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; |
| 1149 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
| 1150 | |
| 1151 | } |
| 1152 | return tv_dac; |
| 1153 | } |
| 1154 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1155 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) |
| 1156 | { |
| 1157 | DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; |
| 1158 | int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); |
| 1159 | |
| 1160 | args.ucEnable = enable; |
| 1161 | |
| 1162 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1163 | } |
| 1164 | |
| 1165 | void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable) |
| 1166 | { |
| 1167 | ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args; |
| 1168 | int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt); |
| 1169 | |
| 1170 | args.ucEnable = enable; |
| 1171 | |
| 1172 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1173 | } |
| 1174 | |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1175 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) |
| 1176 | { |
| 1177 | GET_ENGINE_CLOCK_PS_ALLOCATION args; |
| 1178 | int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); |
| 1179 | |
| 1180 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1181 | return args.ulReturnEngineClock; |
| 1182 | } |
| 1183 | |
| 1184 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) |
| 1185 | { |
| 1186 | GET_MEMORY_CLOCK_PS_ALLOCATION args; |
| 1187 | int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); |
| 1188 | |
| 1189 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1190 | return args.ulReturnMemoryClock; |
| 1191 | } |
| 1192 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1193 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, |
| 1194 | uint32_t eng_clock) |
| 1195 | { |
| 1196 | SET_ENGINE_CLOCK_PS_ALLOCATION args; |
| 1197 | int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); |
| 1198 | |
| 1199 | args.ulTargetEngineClock = eng_clock; /* 10 khz */ |
| 1200 | |
| 1201 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1202 | } |
| 1203 | |
| 1204 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, |
| 1205 | uint32_t mem_clock) |
| 1206 | { |
| 1207 | SET_MEMORY_CLOCK_PS_ALLOCATION args; |
| 1208 | int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); |
| 1209 | |
| 1210 | if (rdev->flags & RADEON_IS_IGP) |
| 1211 | return; |
| 1212 | |
| 1213 | args.ulTargetMemoryClock = mem_clock; /* 10 khz */ |
| 1214 | |
| 1215 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1216 | } |
| 1217 | |
| 1218 | void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) |
| 1219 | { |
| 1220 | struct radeon_device *rdev = dev->dev_private; |
| 1221 | uint32_t bios_2_scratch, bios_6_scratch; |
| 1222 | |
| 1223 | if (rdev->family >= CHIP_R600) { |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1224 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1225 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
| 1226 | } else { |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1227 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1228 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
| 1229 | } |
| 1230 | |
| 1231 | /* let the bios control the backlight */ |
| 1232 | bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; |
| 1233 | |
| 1234 | /* tell the bios not to handle mode switching */ |
| 1235 | bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE); |
| 1236 | |
| 1237 | if (rdev->family >= CHIP_R600) { |
| 1238 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); |
| 1239 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
| 1240 | } else { |
| 1241 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); |
| 1242 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
| 1243 | } |
| 1244 | |
| 1245 | } |
| 1246 | |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 1247 | void radeon_save_bios_scratch_regs(struct radeon_device *rdev) |
| 1248 | { |
| 1249 | uint32_t scratch_reg; |
| 1250 | int i; |
| 1251 | |
| 1252 | if (rdev->family >= CHIP_R600) |
| 1253 | scratch_reg = R600_BIOS_0_SCRATCH; |
| 1254 | else |
| 1255 | scratch_reg = RADEON_BIOS_0_SCRATCH; |
| 1256 | |
| 1257 | for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) |
| 1258 | rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); |
| 1259 | } |
| 1260 | |
| 1261 | void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) |
| 1262 | { |
| 1263 | uint32_t scratch_reg; |
| 1264 | int i; |
| 1265 | |
| 1266 | if (rdev->family >= CHIP_R600) |
| 1267 | scratch_reg = R600_BIOS_0_SCRATCH; |
| 1268 | else |
| 1269 | scratch_reg = RADEON_BIOS_0_SCRATCH; |
| 1270 | |
| 1271 | for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) |
| 1272 | WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); |
| 1273 | } |
| 1274 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1275 | void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) |
| 1276 | { |
| 1277 | struct drm_device *dev = encoder->dev; |
| 1278 | struct radeon_device *rdev = dev->dev_private; |
| 1279 | uint32_t bios_6_scratch; |
| 1280 | |
| 1281 | if (rdev->family >= CHIP_R600) |
| 1282 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
| 1283 | else |
| 1284 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
| 1285 | |
| 1286 | if (lock) |
| 1287 | bios_6_scratch |= ATOM_S6_CRITICAL_STATE; |
| 1288 | else |
| 1289 | bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; |
| 1290 | |
| 1291 | if (rdev->family >= CHIP_R600) |
| 1292 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
| 1293 | else |
| 1294 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
| 1295 | } |
| 1296 | |
| 1297 | /* at some point we may want to break this out into individual functions */ |
| 1298 | void |
| 1299 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, |
| 1300 | struct drm_encoder *encoder, |
| 1301 | bool connected) |
| 1302 | { |
| 1303 | struct drm_device *dev = connector->dev; |
| 1304 | struct radeon_device *rdev = dev->dev_private; |
| 1305 | struct radeon_connector *radeon_connector = |
| 1306 | to_radeon_connector(connector); |
| 1307 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1308 | uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; |
| 1309 | |
| 1310 | if (rdev->family >= CHIP_R600) { |
| 1311 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
| 1312 | bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); |
| 1313 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
| 1314 | } else { |
| 1315 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
| 1316 | bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); |
| 1317 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
| 1318 | } |
| 1319 | |
| 1320 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && |
| 1321 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { |
| 1322 | if (connected) { |
| 1323 | DRM_DEBUG("TV1 connected\n"); |
| 1324 | bios_3_scratch |= ATOM_S3_TV1_ACTIVE; |
| 1325 | bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; |
| 1326 | } else { |
| 1327 | DRM_DEBUG("TV1 disconnected\n"); |
| 1328 | bios_0_scratch &= ~ATOM_S0_TV1_MASK; |
| 1329 | bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; |
| 1330 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; |
| 1331 | } |
| 1332 | } |
| 1333 | if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && |
| 1334 | (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { |
| 1335 | if (connected) { |
| 1336 | DRM_DEBUG("CV connected\n"); |
| 1337 | bios_3_scratch |= ATOM_S3_CV_ACTIVE; |
| 1338 | bios_6_scratch |= ATOM_S6_ACC_REQ_CV; |
| 1339 | } else { |
| 1340 | DRM_DEBUG("CV disconnected\n"); |
| 1341 | bios_0_scratch &= ~ATOM_S0_CV_MASK; |
| 1342 | bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; |
| 1343 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; |
| 1344 | } |
| 1345 | } |
| 1346 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && |
| 1347 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { |
| 1348 | if (connected) { |
| 1349 | DRM_DEBUG("LCD1 connected\n"); |
| 1350 | bios_0_scratch |= ATOM_S0_LCD1; |
| 1351 | bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; |
| 1352 | bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; |
| 1353 | } else { |
| 1354 | DRM_DEBUG("LCD1 disconnected\n"); |
| 1355 | bios_0_scratch &= ~ATOM_S0_LCD1; |
| 1356 | bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; |
| 1357 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; |
| 1358 | } |
| 1359 | } |
| 1360 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && |
| 1361 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { |
| 1362 | if (connected) { |
| 1363 | DRM_DEBUG("CRT1 connected\n"); |
| 1364 | bios_0_scratch |= ATOM_S0_CRT1_COLOR; |
| 1365 | bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; |
| 1366 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; |
| 1367 | } else { |
| 1368 | DRM_DEBUG("CRT1 disconnected\n"); |
| 1369 | bios_0_scratch &= ~ATOM_S0_CRT1_MASK; |
| 1370 | bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; |
| 1371 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; |
| 1372 | } |
| 1373 | } |
| 1374 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && |
| 1375 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { |
| 1376 | if (connected) { |
| 1377 | DRM_DEBUG("CRT2 connected\n"); |
| 1378 | bios_0_scratch |= ATOM_S0_CRT2_COLOR; |
| 1379 | bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; |
| 1380 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; |
| 1381 | } else { |
| 1382 | DRM_DEBUG("CRT2 disconnected\n"); |
| 1383 | bios_0_scratch &= ~ATOM_S0_CRT2_MASK; |
| 1384 | bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; |
| 1385 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; |
| 1386 | } |
| 1387 | } |
| 1388 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && |
| 1389 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { |
| 1390 | if (connected) { |
| 1391 | DRM_DEBUG("DFP1 connected\n"); |
| 1392 | bios_0_scratch |= ATOM_S0_DFP1; |
| 1393 | bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; |
| 1394 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; |
| 1395 | } else { |
| 1396 | DRM_DEBUG("DFP1 disconnected\n"); |
| 1397 | bios_0_scratch &= ~ATOM_S0_DFP1; |
| 1398 | bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; |
| 1399 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; |
| 1400 | } |
| 1401 | } |
| 1402 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && |
| 1403 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
| 1404 | if (connected) { |
| 1405 | DRM_DEBUG("DFP2 connected\n"); |
| 1406 | bios_0_scratch |= ATOM_S0_DFP2; |
| 1407 | bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; |
| 1408 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; |
| 1409 | } else { |
| 1410 | DRM_DEBUG("DFP2 disconnected\n"); |
| 1411 | bios_0_scratch &= ~ATOM_S0_DFP2; |
| 1412 | bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; |
| 1413 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; |
| 1414 | } |
| 1415 | } |
| 1416 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && |
| 1417 | (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { |
| 1418 | if (connected) { |
| 1419 | DRM_DEBUG("DFP3 connected\n"); |
| 1420 | bios_0_scratch |= ATOM_S0_DFP3; |
| 1421 | bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; |
| 1422 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; |
| 1423 | } else { |
| 1424 | DRM_DEBUG("DFP3 disconnected\n"); |
| 1425 | bios_0_scratch &= ~ATOM_S0_DFP3; |
| 1426 | bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; |
| 1427 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; |
| 1428 | } |
| 1429 | } |
| 1430 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && |
| 1431 | (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { |
| 1432 | if (connected) { |
| 1433 | DRM_DEBUG("DFP4 connected\n"); |
| 1434 | bios_0_scratch |= ATOM_S0_DFP4; |
| 1435 | bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; |
| 1436 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; |
| 1437 | } else { |
| 1438 | DRM_DEBUG("DFP4 disconnected\n"); |
| 1439 | bios_0_scratch &= ~ATOM_S0_DFP4; |
| 1440 | bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; |
| 1441 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; |
| 1442 | } |
| 1443 | } |
| 1444 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && |
| 1445 | (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { |
| 1446 | if (connected) { |
| 1447 | DRM_DEBUG("DFP5 connected\n"); |
| 1448 | bios_0_scratch |= ATOM_S0_DFP5; |
| 1449 | bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; |
| 1450 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; |
| 1451 | } else { |
| 1452 | DRM_DEBUG("DFP5 disconnected\n"); |
| 1453 | bios_0_scratch &= ~ATOM_S0_DFP5; |
| 1454 | bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; |
| 1455 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; |
| 1456 | } |
| 1457 | } |
| 1458 | |
| 1459 | if (rdev->family >= CHIP_R600) { |
| 1460 | WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); |
| 1461 | WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); |
| 1462 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
| 1463 | } else { |
| 1464 | WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); |
| 1465 | WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); |
| 1466 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
| 1467 | } |
| 1468 | } |
| 1469 | |
| 1470 | void |
| 1471 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) |
| 1472 | { |
| 1473 | struct drm_device *dev = encoder->dev; |
| 1474 | struct radeon_device *rdev = dev->dev_private; |
| 1475 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1476 | uint32_t bios_3_scratch; |
| 1477 | |
| 1478 | if (rdev->family >= CHIP_R600) |
| 1479 | bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); |
| 1480 | else |
| 1481 | bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); |
| 1482 | |
| 1483 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
| 1484 | bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; |
| 1485 | bios_3_scratch |= (crtc << 18); |
| 1486 | } |
| 1487 | if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { |
| 1488 | bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; |
| 1489 | bios_3_scratch |= (crtc << 24); |
| 1490 | } |
| 1491 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
| 1492 | bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; |
| 1493 | bios_3_scratch |= (crtc << 16); |
| 1494 | } |
| 1495 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
| 1496 | bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; |
| 1497 | bios_3_scratch |= (crtc << 20); |
| 1498 | } |
| 1499 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
| 1500 | bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; |
| 1501 | bios_3_scratch |= (crtc << 17); |
| 1502 | } |
| 1503 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { |
| 1504 | bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; |
| 1505 | bios_3_scratch |= (crtc << 19); |
| 1506 | } |
| 1507 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { |
| 1508 | bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; |
| 1509 | bios_3_scratch |= (crtc << 23); |
| 1510 | } |
| 1511 | if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { |
| 1512 | bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; |
| 1513 | bios_3_scratch |= (crtc << 25); |
| 1514 | } |
| 1515 | |
| 1516 | if (rdev->family >= CHIP_R600) |
| 1517 | WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); |
| 1518 | else |
| 1519 | WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); |
| 1520 | } |
| 1521 | |
| 1522 | void |
| 1523 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) |
| 1524 | { |
| 1525 | struct drm_device *dev = encoder->dev; |
| 1526 | struct radeon_device *rdev = dev->dev_private; |
| 1527 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1528 | uint32_t bios_2_scratch; |
| 1529 | |
| 1530 | if (rdev->family >= CHIP_R600) |
| 1531 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
| 1532 | else |
| 1533 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
| 1534 | |
| 1535 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
| 1536 | if (on) |
| 1537 | bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; |
| 1538 | else |
| 1539 | bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; |
| 1540 | } |
| 1541 | if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { |
| 1542 | if (on) |
| 1543 | bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; |
| 1544 | else |
| 1545 | bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; |
| 1546 | } |
| 1547 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
| 1548 | if (on) |
| 1549 | bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; |
| 1550 | else |
| 1551 | bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; |
| 1552 | } |
| 1553 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
| 1554 | if (on) |
| 1555 | bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; |
| 1556 | else |
| 1557 | bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; |
| 1558 | } |
| 1559 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
| 1560 | if (on) |
| 1561 | bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; |
| 1562 | else |
| 1563 | bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; |
| 1564 | } |
| 1565 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { |
| 1566 | if (on) |
| 1567 | bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; |
| 1568 | else |
| 1569 | bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; |
| 1570 | } |
| 1571 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { |
| 1572 | if (on) |
| 1573 | bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; |
| 1574 | else |
| 1575 | bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; |
| 1576 | } |
| 1577 | if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { |
| 1578 | if (on) |
| 1579 | bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; |
| 1580 | else |
| 1581 | bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; |
| 1582 | } |
| 1583 | if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { |
| 1584 | if (on) |
| 1585 | bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; |
| 1586 | else |
| 1587 | bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; |
| 1588 | } |
| 1589 | if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { |
| 1590 | if (on) |
| 1591 | bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; |
| 1592 | else |
| 1593 | bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; |
| 1594 | } |
| 1595 | |
| 1596 | if (rdev->family >= CHIP_R600) |
| 1597 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); |
| 1598 | else |
| 1599 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); |
| 1600 | } |