Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/delay.h> |
| 14 | #include <linux/highmem.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/dma-mapping.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/scatterlist.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/blkdev.h> |
| 22 | |
| 23 | #include <linux/mmc/mmc.h> |
| 24 | #include <linux/mmc/host.h> |
| 25 | #include <linux/mmc/card.h> |
| 26 | |
| 27 | #include "cmdq_hci.h" |
| 28 | |
| 29 | #define DCMD_SLOT 31 |
| 30 | #define NUM_SLOTS 32 |
| 31 | |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame^] | 32 | /* 1 sec */ |
| 33 | #define HALT_TIMEOUT_MS 1000 |
| 34 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 35 | static inline u8 *get_desc(struct cmdq_host *cq_host, u8 tag) |
| 36 | { |
| 37 | return cq_host->desc_base + (tag * cq_host->slot_sz); |
| 38 | } |
| 39 | |
| 40 | static inline u8 *get_link_desc(struct cmdq_host *cq_host, u8 tag) |
| 41 | { |
| 42 | u8 *desc = get_desc(cq_host, tag); |
| 43 | |
| 44 | return desc + cq_host->task_desc_len; |
| 45 | } |
| 46 | |
| 47 | static inline dma_addr_t get_trans_desc_dma(struct cmdq_host *cq_host, u8 tag) |
| 48 | { |
| 49 | return cq_host->trans_desc_dma_base + |
| 50 | (cq_host->mmc->max_segs * tag * |
| 51 | cq_host->trans_desc_len); |
| 52 | } |
| 53 | |
| 54 | static inline u8 *get_trans_desc(struct cmdq_host *cq_host, u8 tag) |
| 55 | { |
| 56 | return cq_host->trans_desc_base + |
| 57 | (cq_host->trans_desc_len * cq_host->mmc->max_segs * tag); |
| 58 | } |
| 59 | |
| 60 | static void setup_trans_desc(struct cmdq_host *cq_host, u8 tag) |
| 61 | { |
| 62 | u8 *link_temp; |
| 63 | dma_addr_t trans_temp; |
| 64 | |
| 65 | link_temp = get_link_desc(cq_host, tag); |
| 66 | trans_temp = get_trans_desc_dma(cq_host, tag); |
| 67 | |
| 68 | memset(link_temp, 0, cq_host->link_desc_len); |
| 69 | if (cq_host->link_desc_len > 8) |
| 70 | *(link_temp + 8) = 0; |
| 71 | |
| 72 | if (tag == DCMD_SLOT) { |
| 73 | *link_temp = VALID(0) | ACT(0) | END(1); |
| 74 | return; |
| 75 | } |
| 76 | |
| 77 | *link_temp = VALID(1) | ACT(0x6) | END(0); |
| 78 | |
| 79 | if (cq_host->dma64) { |
| 80 | __le64 *data_addr = (__le64 __force *)(link_temp + 4); |
| 81 | data_addr[0] = cpu_to_le64(trans_temp); |
| 82 | } else { |
| 83 | __le32 *data_addr = (__le32 __force *)(link_temp + 4); |
| 84 | data_addr[0] = cpu_to_le32(trans_temp); |
| 85 | } |
| 86 | } |
| 87 | |
| 88 | static void cmdq_clear_set_irqs(struct cmdq_host *cq_host, u32 clear, u32 set) |
| 89 | { |
| 90 | u32 ier; |
| 91 | |
| 92 | ier = cmdq_readl(cq_host, CQISTE); |
| 93 | ier &= ~clear; |
| 94 | ier |= set; |
| 95 | cmdq_writel(cq_host, ier, CQISTE); |
| 96 | cmdq_writel(cq_host, ier, CQISGE); |
| 97 | /* ensure the writes are done */ |
| 98 | mb(); |
| 99 | } |
| 100 | |
| 101 | |
| 102 | #define DRV_NAME "cmdq-host" |
| 103 | |
| 104 | static void cmdq_dump_debug_ram(struct cmdq_host *cq_host) |
| 105 | { |
| 106 | int i = 0; |
| 107 | |
| 108 | pr_err("---- Debug RAM dump ----\n"); |
| 109 | pr_err(DRV_NAME ": Debug RAM wrap-around: 0x%08x | Debug RAM overlap: 0x%08x\n", |
| 110 | cmdq_readl(cq_host, CQ_CMD_DBG_RAM_WA), |
| 111 | cmdq_readl(cq_host, CQ_CMD_DBG_RAM_OL)); |
| 112 | |
| 113 | while (i < 16) { |
| 114 | pr_err(DRV_NAME ": Debug RAM dump [%d]: 0x%08x\n", i, |
| 115 | cmdq_readl(cq_host, CQ_CMD_DBG_RAM + (0x4 * i))); |
| 116 | i++; |
| 117 | } |
| 118 | pr_err("-------------------------\n"); |
| 119 | } |
| 120 | |
| 121 | static void cmdq_dumpregs(struct cmdq_host *cq_host) |
| 122 | { |
| 123 | struct mmc_host *mmc = cq_host->mmc; |
| 124 | |
| 125 | pr_info(DRV_NAME ": ========== REGISTER DUMP (%s)==========\n", |
| 126 | mmc_hostname(mmc)); |
| 127 | |
| 128 | pr_info(DRV_NAME ": Caps: 0x%08x | Version: 0x%08x\n", |
| 129 | cmdq_readl(cq_host, CQCAP), |
| 130 | cmdq_readl(cq_host, CQVER)); |
| 131 | pr_info(DRV_NAME ": Queing config: 0x%08x | Queue Ctrl: 0x%08x\n", |
| 132 | cmdq_readl(cq_host, CQCFG), |
| 133 | cmdq_readl(cq_host, CQCTL)); |
| 134 | pr_info(DRV_NAME ": Int stat: 0x%08x | Int enab: 0x%08x\n", |
| 135 | cmdq_readl(cq_host, CQIS), |
| 136 | cmdq_readl(cq_host, CQISTE)); |
| 137 | pr_info(DRV_NAME ": Int sig: 0x%08x | Int Coal: 0x%08x\n", |
| 138 | cmdq_readl(cq_host, CQISGE), |
| 139 | cmdq_readl(cq_host, CQIC)); |
| 140 | pr_info(DRV_NAME ": TDL base: 0x%08x | TDL up32: 0x%08x\n", |
| 141 | cmdq_readl(cq_host, CQTDLBA), |
| 142 | cmdq_readl(cq_host, CQTDLBAU)); |
| 143 | pr_info(DRV_NAME ": Doorbell: 0x%08x | Comp Notif: 0x%08x\n", |
| 144 | cmdq_readl(cq_host, CQTDBR), |
| 145 | cmdq_readl(cq_host, CQTCN)); |
| 146 | pr_info(DRV_NAME ": Dev queue: 0x%08x | Dev Pend: 0x%08x\n", |
| 147 | cmdq_readl(cq_host, CQDQS), |
| 148 | cmdq_readl(cq_host, CQDPT)); |
| 149 | pr_info(DRV_NAME ": Task clr: 0x%08x | Send stat 1: 0x%08x\n", |
| 150 | cmdq_readl(cq_host, CQTCLR), |
| 151 | cmdq_readl(cq_host, CQSSC1)); |
| 152 | pr_info(DRV_NAME ": Send stat 2: 0x%08x | DCMD resp: 0x%08x\n", |
| 153 | cmdq_readl(cq_host, CQSSC2), |
| 154 | cmdq_readl(cq_host, CQCRDCT)); |
| 155 | pr_info(DRV_NAME ": Resp err mask: 0x%08x | Task err: 0x%08x\n", |
| 156 | cmdq_readl(cq_host, CQRMEM), |
| 157 | cmdq_readl(cq_host, CQTERRI)); |
| 158 | pr_info(DRV_NAME ": Resp idx 0x%08x | Resp arg: 0x%08x\n", |
| 159 | cmdq_readl(cq_host, CQCRI), |
| 160 | cmdq_readl(cq_host, CQCRA)); |
| 161 | pr_info(DRV_NAME ": ===========================================\n"); |
| 162 | |
| 163 | cmdq_dump_debug_ram(cq_host); |
| 164 | if (cq_host->ops->dump_vendor_regs) |
| 165 | cq_host->ops->dump_vendor_regs(mmc); |
| 166 | } |
| 167 | |
| 168 | /** |
| 169 | * The allocated descriptor table for task, link & transfer descritors |
| 170 | * looks like: |
| 171 | * |----------| |
| 172 | * |task desc | |->|----------| |
| 173 | * |----------| | |trans desc| |
| 174 | * |link desc-|->| |----------| |
| 175 | * |----------| . |
| 176 | * . . |
| 177 | * no. of slots max-segs |
| 178 | * . |----------| |
| 179 | * |----------| |
| 180 | * The idea here is to create the [task+trans] table and mark & point the |
| 181 | * link desc to the transfer desc table on a per slot basis. |
| 182 | */ |
| 183 | static int cmdq_host_alloc_tdl(struct cmdq_host *cq_host) |
| 184 | { |
| 185 | |
| 186 | size_t desc_size; |
| 187 | size_t data_size; |
| 188 | int i = 0; |
| 189 | |
| 190 | /* task descriptor can be 64/128 bit irrespective of arch */ |
| 191 | if (cq_host->caps & CMDQ_TASK_DESC_SZ_128) { |
| 192 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQCFG) | |
| 193 | CQ_TASK_DESC_SZ, CQCFG); |
| 194 | cq_host->task_desc_len = 16; |
| 195 | } else { |
| 196 | cq_host->task_desc_len = 8; |
| 197 | } |
| 198 | |
| 199 | /* |
| 200 | * 96 bits length of transfer desc instead of 128 bits which means |
| 201 | * ADMA would expect next valid descriptor at the 96th bit |
| 202 | * or 128th bit |
| 203 | */ |
| 204 | if (cq_host->dma64) { |
| 205 | if (cq_host->quirks & CMDQ_QUIRK_SHORT_TXFR_DESC_SZ) |
| 206 | cq_host->trans_desc_len = 12; |
| 207 | else |
| 208 | cq_host->trans_desc_len = 16; |
| 209 | cq_host->link_desc_len = 16; |
| 210 | } else { |
| 211 | cq_host->trans_desc_len = 8; |
| 212 | cq_host->link_desc_len = 8; |
| 213 | } |
| 214 | |
| 215 | /* total size of a slot: 1 task & 1 transfer (link) */ |
| 216 | cq_host->slot_sz = cq_host->task_desc_len + cq_host->link_desc_len; |
| 217 | |
| 218 | desc_size = cq_host->slot_sz * cq_host->num_slots; |
| 219 | |
| 220 | data_size = cq_host->trans_desc_len * cq_host->mmc->max_segs * |
| 221 | (cq_host->num_slots - 1); |
| 222 | |
| 223 | pr_info("%s: desc_size: %d data_sz: %d slot-sz: %d\n", __func__, |
| 224 | (int)desc_size, (int)data_size, cq_host->slot_sz); |
| 225 | |
| 226 | /* |
| 227 | * allocate a dma-mapped chunk of memory for the descriptors |
| 228 | * allocate a dma-mapped chunk of memory for link descriptors |
| 229 | * setup each link-desc memory offset per slot-number to |
| 230 | * the descriptor table. |
| 231 | */ |
| 232 | cq_host->desc_base = dmam_alloc_coherent(mmc_dev(cq_host->mmc), |
| 233 | desc_size, |
| 234 | &cq_host->desc_dma_base, |
| 235 | GFP_KERNEL); |
| 236 | cq_host->trans_desc_base = dmam_alloc_coherent(mmc_dev(cq_host->mmc), |
| 237 | data_size, |
| 238 | &cq_host->trans_desc_dma_base, |
| 239 | GFP_KERNEL); |
| 240 | if (!cq_host->desc_base || !cq_host->trans_desc_base) |
| 241 | return -ENOMEM; |
| 242 | |
| 243 | pr_info("desc-base: 0x%p trans-base: 0x%p\n desc_dma 0x%llx trans_dma: 0x%llx\n", |
| 244 | cq_host->desc_base, cq_host->trans_desc_base, |
| 245 | (unsigned long long)cq_host->desc_dma_base, |
| 246 | (unsigned long long) cq_host->trans_desc_dma_base); |
| 247 | |
| 248 | for (; i < (cq_host->num_slots); i++) |
| 249 | setup_trans_desc(cq_host, i); |
| 250 | |
| 251 | return 0; |
| 252 | } |
| 253 | |
| 254 | static int cmdq_enable(struct mmc_host *mmc) |
| 255 | { |
| 256 | int err = 0; |
| 257 | u32 cqcfg; |
| 258 | bool dcmd_enable; |
| 259 | struct cmdq_host *cq_host = mmc_cmdq_private(mmc); |
| 260 | |
| 261 | if (!cq_host || !mmc->card || !mmc_card_cmdq(mmc->card)) { |
| 262 | err = -EINVAL; |
| 263 | goto out; |
| 264 | } |
| 265 | |
| 266 | if (cq_host->enabled) |
| 267 | goto out; |
| 268 | |
| 269 | cqcfg = cmdq_readl(cq_host, CQCFG); |
| 270 | if (cqcfg & 0x1) { |
| 271 | pr_info("%s: %s: cq_host is already enabled\n", |
| 272 | mmc_hostname(mmc), __func__); |
| 273 | WARN_ON(1); |
| 274 | goto out; |
| 275 | } |
| 276 | |
| 277 | if (cq_host->quirks & CMDQ_QUIRK_NO_DCMD) |
| 278 | dcmd_enable = false; |
| 279 | else |
| 280 | dcmd_enable = true; |
| 281 | |
| 282 | cqcfg = ((cq_host->caps & CMDQ_TASK_DESC_SZ_128 ? CQ_TASK_DESC_SZ : 0) | |
| 283 | (dcmd_enable ? CQ_DCMD : 0)); |
| 284 | |
| 285 | cmdq_writel(cq_host, cqcfg, CQCFG); |
| 286 | /* enable CQ_HOST */ |
| 287 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQCFG) | CQ_ENABLE, |
| 288 | CQCFG); |
| 289 | |
| 290 | if (!cq_host->desc_base || |
| 291 | !cq_host->trans_desc_base) { |
| 292 | err = cmdq_host_alloc_tdl(cq_host); |
| 293 | if (err) |
| 294 | goto out; |
| 295 | cmdq_writel(cq_host, lower_32_bits(cq_host->desc_dma_base), |
| 296 | CQTDLBA); |
| 297 | cmdq_writel(cq_host, upper_32_bits(cq_host->desc_dma_base), |
| 298 | CQTDLBAU); |
| 299 | cmdq_dumpregs(cq_host); |
| 300 | } |
| 301 | |
| 302 | /* |
| 303 | * disable all vendor interrupts |
| 304 | * enable CMDQ interrupts |
| 305 | * enable the vendor error interrupts |
| 306 | */ |
| 307 | if (cq_host->ops->clear_set_irqs) |
| 308 | cq_host->ops->clear_set_irqs(mmc, true); |
| 309 | |
| 310 | cmdq_clear_set_irqs(cq_host, 0x0, CQ_INT_ALL); |
| 311 | |
| 312 | /* cq_host would use this rca to address the card */ |
| 313 | cmdq_writel(cq_host, mmc->card->rca, CQSSC2); |
| 314 | |
| 315 | /* send QSR at lesser intervals than the default */ |
| 316 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQSSC1) | SEND_QSR_INTERVAL, |
| 317 | CQSSC1); |
| 318 | |
| 319 | /* ensure the writes are done before enabling CQE */ |
| 320 | mb(); |
| 321 | |
| 322 | cq_host->enabled = true; |
| 323 | |
| 324 | if (cq_host->ops->set_block_size) |
| 325 | cq_host->ops->set_block_size(cq_host->mmc); |
| 326 | |
| 327 | if (cq_host->ops->set_data_timeout) |
| 328 | cq_host->ops->set_data_timeout(mmc, 0xf); |
| 329 | |
| 330 | if (cq_host->ops->clear_set_dumpregs) |
| 331 | cq_host->ops->clear_set_dumpregs(mmc, 1); |
| 332 | |
| 333 | out: |
| 334 | return err; |
| 335 | } |
| 336 | |
| 337 | static void cmdq_disable(struct mmc_host *mmc, bool soft) |
| 338 | { |
| 339 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 340 | |
| 341 | if (soft) { |
| 342 | cmdq_writel(cq_host, cmdq_readl( |
| 343 | cq_host, CQCFG) & ~(CQ_ENABLE), |
| 344 | CQCFG); |
| 345 | } |
| 346 | |
| 347 | cq_host->enabled = false; |
| 348 | } |
| 349 | |
| 350 | static void cmdq_prep_task_desc(struct mmc_request *mrq, |
| 351 | u64 *data, bool intr, bool qbr) |
| 352 | { |
| 353 | struct mmc_cmdq_req *cmdq_req = mrq->cmdq_req; |
| 354 | u32 req_flags = cmdq_req->cmdq_req_flags; |
| 355 | |
| 356 | pr_debug("%s: %s: data-tag: 0x%08x - dir: %d - prio: %d - cnt: 0x%08x - addr: 0x%llx\n", |
| 357 | mmc_hostname(mrq->host), __func__, |
| 358 | !!(req_flags & DAT_TAG), !!(req_flags & DIR), |
| 359 | !!(req_flags & PRIO), cmdq_req->data.blocks, |
| 360 | (u64)mrq->cmdq_req->blk_addr); |
| 361 | |
| 362 | *data = VALID(1) | |
| 363 | END(1) | |
| 364 | INT(intr) | |
| 365 | ACT(0x5) | |
| 366 | FORCED_PROG(!!(req_flags & FORCED_PRG)) | |
| 367 | CONTEXT(mrq->cmdq_req->ctx_id) | |
| 368 | DATA_TAG(!!(req_flags & DAT_TAG)) | |
| 369 | DATA_DIR(!!(req_flags & DIR)) | |
| 370 | PRIORITY(!!(req_flags & PRIO)) | |
| 371 | QBAR(qbr) | |
| 372 | REL_WRITE(!!(req_flags & REL_WR)) | |
| 373 | BLK_COUNT(mrq->cmdq_req->data.blocks) | |
| 374 | BLK_ADDR((u64)mrq->cmdq_req->blk_addr); |
| 375 | } |
| 376 | |
| 377 | static int cmdq_dma_map(struct mmc_host *host, struct mmc_request *mrq) |
| 378 | { |
| 379 | int sg_count; |
| 380 | struct mmc_data *data = mrq->data; |
| 381 | |
| 382 | if (!data) |
| 383 | return -EINVAL; |
| 384 | |
| 385 | sg_count = dma_map_sg(mmc_dev(host), data->sg, |
| 386 | data->sg_len, |
| 387 | (data->flags & MMC_DATA_WRITE) ? |
| 388 | DMA_TO_DEVICE : DMA_FROM_DEVICE); |
| 389 | if (!sg_count) { |
| 390 | pr_err("%s: sg-len: %d\n", __func__, data->sg_len); |
| 391 | return -ENOMEM; |
| 392 | } |
| 393 | |
| 394 | return sg_count; |
| 395 | } |
| 396 | |
| 397 | static void cmdq_set_tran_desc(u8 *desc, |
| 398 | dma_addr_t addr, int len, bool end) |
| 399 | { |
| 400 | __le64 *dataddr = (__le64 __force *)(desc + 4); |
| 401 | __le32 *attr = (__le32 __force *)desc; |
| 402 | |
| 403 | *attr = (VALID(1) | |
| 404 | END(end ? 1 : 0) | |
| 405 | INT(0) | |
| 406 | ACT(0x4) | |
| 407 | DAT_LENGTH(len)); |
| 408 | |
| 409 | dataddr[0] = cpu_to_le64(addr); |
| 410 | } |
| 411 | |
| 412 | static int cmdq_prep_tran_desc(struct mmc_request *mrq, |
| 413 | struct cmdq_host *cq_host, int tag) |
| 414 | { |
| 415 | struct mmc_data *data = mrq->data; |
| 416 | int i, sg_count, len; |
| 417 | bool end = false; |
| 418 | dma_addr_t addr; |
| 419 | u8 *desc; |
| 420 | struct scatterlist *sg; |
| 421 | |
| 422 | sg_count = cmdq_dma_map(mrq->host, mrq); |
| 423 | if (sg_count < 0) { |
| 424 | pr_err("%s: %s: unable to map sg lists, %d\n", |
| 425 | mmc_hostname(mrq->host), __func__, sg_count); |
| 426 | return sg_count; |
| 427 | } |
| 428 | |
| 429 | desc = get_trans_desc(cq_host, tag); |
| 430 | memset(desc, 0, cq_host->trans_desc_len * cq_host->mmc->max_segs); |
| 431 | |
| 432 | for_each_sg(data->sg, sg, sg_count, i) { |
| 433 | addr = sg_dma_address(sg); |
| 434 | len = sg_dma_len(sg); |
| 435 | |
| 436 | if ((i+1) == sg_count) |
| 437 | end = true; |
| 438 | cmdq_set_tran_desc(desc, addr, len, end); |
| 439 | desc += cq_host->trans_desc_len; |
| 440 | } |
| 441 | |
| 442 | pr_debug("%s: req: 0x%p tag: %d calc_trans_des: 0x%p sg-cnt: %d\n", |
| 443 | __func__, mrq->req, tag, desc, sg_count); |
| 444 | |
| 445 | return 0; |
| 446 | } |
| 447 | |
| 448 | static void cmdq_prep_dcmd_desc(struct mmc_host *mmc, |
| 449 | struct mmc_request *mrq) |
| 450 | { |
| 451 | u64 *task_desc = NULL; |
| 452 | u64 data = 0; |
| 453 | u8 resp_type; |
| 454 | u8 *desc; |
| 455 | __le64 *dataddr; |
| 456 | struct cmdq_host *cq_host = mmc_cmdq_private(mmc); |
| 457 | u8 timing; |
| 458 | |
| 459 | if (!(mrq->cmd->flags & MMC_RSP_PRESENT)) { |
| 460 | resp_type = 0x0; |
| 461 | timing = 0x1; |
| 462 | } else { |
| 463 | if (mrq->cmd->flags & MMC_RSP_R1B) { |
| 464 | resp_type = 0x3; |
| 465 | timing = 0x0; |
| 466 | } else { |
| 467 | resp_type = 0x2; |
| 468 | timing = 0x1; |
| 469 | } |
| 470 | } |
| 471 | |
| 472 | task_desc = (__le64 __force *)get_desc(cq_host, cq_host->dcmd_slot); |
| 473 | memset(task_desc, 0, cq_host->task_desc_len); |
| 474 | data |= (VALID(1) | |
| 475 | END(1) | |
| 476 | INT(1) | |
| 477 | QBAR(1) | |
| 478 | ACT(0x5) | |
| 479 | CMD_INDEX(mrq->cmd->opcode) | |
| 480 | CMD_TIMING(timing) | RESP_TYPE(resp_type)); |
| 481 | *task_desc |= data; |
| 482 | desc = (u8 *)task_desc; |
| 483 | pr_debug("cmdq: dcmd: cmd: %d timing: %d resp: %d\n", |
| 484 | mrq->cmd->opcode, timing, resp_type); |
| 485 | dataddr = (__le64 __force *)(desc + 4); |
| 486 | dataddr[0] = cpu_to_le64((u64)mrq->cmd->arg); |
| 487 | |
| 488 | } |
| 489 | |
| 490 | static int cmdq_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 491 | { |
| 492 | int err; |
| 493 | u64 data = 0; |
| 494 | u64 *task_desc = NULL; |
| 495 | u32 tag = mrq->cmdq_req->tag; |
| 496 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 497 | |
| 498 | if (!cq_host->enabled) { |
| 499 | pr_err("%s: CMDQ host not enabled yet !!!\n", |
| 500 | mmc_hostname(mmc)); |
| 501 | err = -EINVAL; |
| 502 | goto out; |
| 503 | } |
| 504 | |
| 505 | if (mrq->cmdq_req->cmdq_req_flags & DCMD) { |
| 506 | cmdq_prep_dcmd_desc(mmc, mrq); |
| 507 | cq_host->mrq_slot[DCMD_SLOT] = mrq; |
| 508 | cmdq_writel(cq_host, 1 << DCMD_SLOT, CQTDBR); |
| 509 | return 0; |
| 510 | } |
| 511 | |
| 512 | task_desc = (__le64 __force *)get_desc(cq_host, tag); |
| 513 | |
| 514 | cmdq_prep_task_desc(mrq, &data, 1, |
| 515 | (mrq->cmdq_req->cmdq_req_flags & QBR)); |
| 516 | *task_desc = cpu_to_le64(data); |
| 517 | |
| 518 | err = cmdq_prep_tran_desc(mrq, cq_host, tag); |
| 519 | if (err) { |
| 520 | pr_err("%s: %s: failed to setup tx desc: %d\n", |
| 521 | mmc_hostname(mmc), __func__, err); |
| 522 | return err; |
| 523 | } |
| 524 | |
| 525 | BUG_ON(cmdq_readl(cq_host, CQTDBR) & (1 << tag)); |
| 526 | |
| 527 | cq_host->mrq_slot[tag] = mrq; |
| 528 | if (cq_host->ops->set_tranfer_params) |
| 529 | cq_host->ops->set_tranfer_params(mmc); |
| 530 | |
| 531 | cmdq_writel(cq_host, 1 << tag, CQTDBR); |
| 532 | |
| 533 | out: |
| 534 | return err; |
| 535 | } |
| 536 | |
| 537 | static void cmdq_finish_data(struct mmc_host *mmc, unsigned int tag) |
| 538 | { |
| 539 | struct mmc_request *mrq; |
| 540 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 541 | |
| 542 | mrq = cq_host->mrq_slot[tag]; |
| 543 | mrq->done(mrq); |
| 544 | } |
| 545 | |
| 546 | irqreturn_t cmdq_irq(struct mmc_host *mmc, u32 intmask) |
| 547 | { |
| 548 | u32 status; |
| 549 | unsigned long tag = 0, comp_status; |
| 550 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 551 | |
| 552 | status = cmdq_readl(cq_host, CQIS); |
| 553 | cmdq_writel(cq_host, status, CQIS); |
| 554 | |
| 555 | if (status & CQIS_TCC) { |
| 556 | /* read QCTCN and complete the request */ |
| 557 | comp_status = cmdq_readl(cq_host, CQTCN); |
| 558 | if (!comp_status) |
| 559 | goto out; |
| 560 | |
| 561 | for_each_set_bit(tag, &comp_status, cq_host->num_slots) { |
| 562 | /* complete the corresponding mrq */ |
| 563 | pr_debug("%s: completing tag -> %lu\n", |
| 564 | mmc_hostname(mmc), tag); |
| 565 | cmdq_finish_data(mmc, tag); |
| 566 | } |
| 567 | cmdq_writel(cq_host, comp_status, CQTCN); |
| 568 | } |
| 569 | |
| 570 | if (status & CQIS_RED) { |
| 571 | /* task response has an error */ |
| 572 | pr_err("%s: RED error %d !!!\n", mmc_hostname(mmc), status); |
| 573 | cmdq_dumpregs(cq_host); |
| 574 | } |
| 575 | |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame^] | 576 | if (status & CQIS_HAC) { |
| 577 | /* halt is completed, wakeup waiting thread */ |
| 578 | complete(&cq_host->halt_comp); |
| 579 | } |
| 580 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 581 | out: |
| 582 | return IRQ_HANDLED; |
| 583 | } |
| 584 | EXPORT_SYMBOL(cmdq_irq); |
| 585 | |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame^] | 586 | /* May sleep */ |
| 587 | static int cmdq_halt(struct mmc_host *mmc, bool halt) |
| 588 | { |
| 589 | struct cmdq_host *cq_host = (struct cmdq_host *)mmc_cmdq_private(mmc); |
| 590 | u32 val; |
| 591 | |
| 592 | if (halt) { |
| 593 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQCTL) | HALT, |
| 594 | CQCTL); |
| 595 | val = wait_for_completion_timeout(&cq_host->halt_comp, |
| 596 | msecs_to_jiffies(HALT_TIMEOUT_MS)); |
| 597 | /* halt done: re-enable legacy interrupts */ |
| 598 | if (cq_host->ops->clear_set_irqs) |
| 599 | cq_host->ops->clear_set_irqs(mmc, false); |
| 600 | |
| 601 | return val ? 0 : -ETIMEDOUT; |
| 602 | } else { |
| 603 | if (cq_host->ops->clear_set_irqs) |
| 604 | cq_host->ops->clear_set_irqs(mmc, true); |
| 605 | cmdq_writel(cq_host, cmdq_readl(cq_host, CQCTL) & ~HALT, |
| 606 | CQCTL); |
| 607 | } |
| 608 | |
| 609 | return 0; |
| 610 | } |
| 611 | |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 612 | static void cmdq_post_req(struct mmc_host *host, struct mmc_request *mrq, |
| 613 | int err) |
| 614 | { |
| 615 | struct mmc_data *data = mrq->data; |
| 616 | |
| 617 | if (data) { |
| 618 | data->error = err; |
| 619 | dma_unmap_sg(mmc_dev(host), data->sg, data->sg_len, |
| 620 | (data->flags & MMC_DATA_READ) ? |
| 621 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
| 622 | if (err) |
| 623 | data->bytes_xfered = 0; |
| 624 | else |
| 625 | data->bytes_xfered = blk_rq_bytes(mrq->req); |
| 626 | } |
| 627 | } |
| 628 | |
| 629 | static const struct mmc_cmdq_host_ops cmdq_host_ops = { |
| 630 | .enable = cmdq_enable, |
| 631 | .disable = cmdq_disable, |
| 632 | .request = cmdq_request, |
| 633 | .post_req = cmdq_post_req, |
Asutosh Das | aa1e1c7 | 2015-05-21 17:22:10 +0530 | [diff] [blame^] | 634 | .halt = cmdq_halt, |
Venkat Gopalakrishnan | 0225ff9 | 2015-05-29 17:25:46 -0700 | [diff] [blame] | 635 | }; |
| 636 | |
| 637 | struct cmdq_host *cmdq_pltfm_init(struct platform_device *pdev) |
| 638 | { |
| 639 | struct cmdq_host *cq_host; |
| 640 | struct resource *cmdq_memres = NULL; |
| 641 | |
| 642 | /* check and setup CMDQ interface */ |
| 643 | cmdq_memres = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 644 | "cmdq_mem"); |
| 645 | if (!cmdq_memres) { |
| 646 | dev_dbg(&pdev->dev, "CMDQ not supported\n"); |
| 647 | return ERR_PTR(-EINVAL); |
| 648 | } |
| 649 | |
| 650 | cq_host = kzalloc(sizeof(*cq_host), GFP_KERNEL); |
| 651 | if (!cq_host) { |
| 652 | dev_err(&pdev->dev, "failed to allocate memory for CMDQ\n"); |
| 653 | return ERR_PTR(-ENOMEM); |
| 654 | } |
| 655 | cq_host->mmio = devm_ioremap(&pdev->dev, |
| 656 | cmdq_memres->start, |
| 657 | resource_size(cmdq_memres)); |
| 658 | if (!cq_host->mmio) { |
| 659 | dev_err(&pdev->dev, "failed to remap cmdq regs\n"); |
| 660 | kfree(cq_host); |
| 661 | return ERR_PTR(-EBUSY); |
| 662 | } |
| 663 | dev_dbg(&pdev->dev, "CMDQ ioremap: done\n"); |
| 664 | |
| 665 | return cq_host; |
| 666 | } |
| 667 | EXPORT_SYMBOL(cmdq_pltfm_init); |
| 668 | |
| 669 | int cmdq_init(struct cmdq_host *cq_host, struct mmc_host *mmc, |
| 670 | bool dma64) |
| 671 | { |
| 672 | int err = 0; |
| 673 | |
| 674 | cq_host->dma64 = dma64; |
| 675 | cq_host->mmc = mmc; |
| 676 | cq_host->mmc->cmdq_private = cq_host; |
| 677 | |
| 678 | cq_host->num_slots = NUM_SLOTS; |
| 679 | cq_host->dcmd_slot = DCMD_SLOT; |
| 680 | |
| 681 | mmc->cmdq_ops = &cmdq_host_ops; |
| 682 | |
| 683 | cq_host->mrq_slot = kzalloc(sizeof(cq_host->mrq_slot) * |
| 684 | cq_host->num_slots, GFP_KERNEL); |
| 685 | if (!cq_host->mrq_slot) |
| 686 | return -ENOMEM; |
| 687 | |
| 688 | init_completion(&cq_host->halt_comp); |
| 689 | return err; |
| 690 | } |
| 691 | EXPORT_SYMBOL(cmdq_init); |