PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel 10 Gigabit PCI Express Linux driver |
| 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #include <linux/pci.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/sched.h> |
| 31 | |
| 32 | #include "ixgbe.h" |
| 33 | #include "ixgbe_phy.h" |
| 34 | |
| 35 | #define IXGBE_82599_MAX_TX_QUEUES 128 |
| 36 | #define IXGBE_82599_MAX_RX_QUEUES 128 |
| 37 | #define IXGBE_82599_RAR_ENTRIES 128 |
| 38 | #define IXGBE_82599_MC_TBL_SIZE 128 |
| 39 | #define IXGBE_82599_VFT_TBL_SIZE 128 |
| 40 | |
| 41 | s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, |
| 42 | ixgbe_link_speed *speed, |
| 43 | bool *autoneg); |
| 44 | enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw); |
| 45 | s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw); |
| 46 | s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw, |
| 47 | ixgbe_link_speed speed, bool autoneg, |
| 48 | bool autoneg_wait_to_complete); |
| 49 | s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw); |
| 50 | s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, |
| 51 | ixgbe_link_speed *speed, |
| 52 | bool *link_up, bool link_up_wait_to_complete); |
| 53 | s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw, |
| 54 | ixgbe_link_speed speed, |
| 55 | bool autoneg, |
| 56 | bool autoneg_wait_to_complete); |
| 57 | static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw, |
| 58 | ixgbe_link_speed *speed, |
| 59 | bool *autoneg); |
| 60 | static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw); |
| 61 | static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw, |
| 62 | ixgbe_link_speed speed, |
| 63 | bool autoneg, |
| 64 | bool autoneg_wait_to_complete); |
| 65 | s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw); |
| 66 | s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq); |
| 67 | s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq); |
| 68 | s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, |
| 69 | u32 vind, bool vlan_on); |
| 70 | s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 71 | s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw); |
| 72 | s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val); |
| 73 | s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val); |
| 74 | s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw); |
| 75 | s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw); |
| 76 | s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw); |
| 77 | u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw); |
| 78 | |
| 79 | void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) |
| 80 | { |
| 81 | struct ixgbe_mac_info *mac = &hw->mac; |
| 82 | if (hw->phy.multispeed_fiber) { |
| 83 | /* Set up dual speed SFP+ support */ |
| 84 | mac->ops.setup_link = |
| 85 | &ixgbe_setup_mac_link_multispeed_fiber; |
| 86 | mac->ops.setup_link_speed = |
| 87 | &ixgbe_setup_mac_link_speed_multispeed_fiber; |
| 88 | } else { |
| 89 | mac->ops.setup_link = |
| 90 | &ixgbe_setup_mac_link_82599; |
| 91 | mac->ops.setup_link_speed = |
| 92 | &ixgbe_setup_mac_link_speed_82599; |
| 93 | } |
| 94 | } |
| 95 | |
| 96 | s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) |
| 97 | { |
| 98 | s32 ret_val = 0; |
| 99 | u16 list_offset, data_offset, data_value; |
| 100 | |
| 101 | if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { |
| 102 | ixgbe_init_mac_link_ops_82599(hw); |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 103 | |
| 104 | hw->phy.ops.reset = NULL; |
| 105 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 106 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, |
| 107 | &data_offset); |
| 108 | |
| 109 | if (ret_val != 0) |
| 110 | goto setup_sfp_out; |
| 111 | |
Peter P Waskiewicz Jr | aa5aec8 | 2009-05-19 09:18:34 +0000 | [diff] [blame^] | 112 | /* PHY config will finish before releasing the semaphore */ |
| 113 | ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); |
| 114 | if (ret_val != 0) { |
| 115 | ret_val = IXGBE_ERR_SWFW_SYNC; |
| 116 | goto setup_sfp_out; |
| 117 | } |
| 118 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 119 | hw->eeprom.ops.read(hw, ++data_offset, &data_value); |
| 120 | while (data_value != 0xffff) { |
| 121 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); |
| 122 | IXGBE_WRITE_FLUSH(hw); |
| 123 | hw->eeprom.ops.read(hw, ++data_offset, &data_value); |
| 124 | } |
| 125 | /* Now restart DSP */ |
| 126 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000102); |
| 127 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000b1d); |
| 128 | IXGBE_WRITE_FLUSH(hw); |
Peter P Waskiewicz Jr | aa5aec8 | 2009-05-19 09:18:34 +0000 | [diff] [blame^] | 129 | |
| 130 | /* Release the semaphore */ |
| 131 | ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); |
| 132 | /* Delay obtaining semaphore again to allow FW access */ |
| 133 | msleep(hw->eeprom.semaphore_delay); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 134 | } |
| 135 | |
| 136 | setup_sfp_out: |
| 137 | return ret_val; |
| 138 | } |
| 139 | |
| 140 | /** |
| 141 | * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count |
| 142 | * @hw: pointer to hardware structure |
| 143 | * |
| 144 | * Read PCIe configuration space, and get the MSI-X vector count from |
| 145 | * the capabilities table. |
| 146 | **/ |
| 147 | u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw) |
| 148 | { |
| 149 | struct ixgbe_adapter *adapter = hw->back; |
| 150 | u16 msix_count; |
| 151 | pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS, |
| 152 | &msix_count); |
| 153 | msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; |
| 154 | |
| 155 | /* MSI-X count is zero-based in HW, so increment to give proper value */ |
| 156 | msix_count++; |
| 157 | |
| 158 | return msix_count; |
| 159 | } |
| 160 | |
| 161 | static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) |
| 162 | { |
| 163 | struct ixgbe_mac_info *mac = &hw->mac; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 164 | |
| 165 | ixgbe_init_mac_link_ops_82599(hw); |
| 166 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 167 | mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; |
| 168 | mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; |
| 169 | mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; |
| 170 | mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; |
| 171 | mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; |
| 172 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw); |
| 173 | |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 174 | return 0; |
| 175 | } |
| 176 | |
| 177 | /** |
| 178 | * ixgbe_init_phy_ops_82599 - PHY/SFP specific init |
| 179 | * @hw: pointer to hardware structure |
| 180 | * |
| 181 | * Initialize any function pointers that were not able to be |
| 182 | * set during get_invariants because the PHY/SFP type was |
| 183 | * not known. Perform the SFP init if necessary. |
| 184 | * |
| 185 | **/ |
| 186 | s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) |
| 187 | { |
| 188 | struct ixgbe_mac_info *mac = &hw->mac; |
| 189 | struct ixgbe_phy_info *phy = &hw->phy; |
| 190 | s32 ret_val = 0; |
| 191 | |
| 192 | /* Identify the PHY or SFP module */ |
| 193 | ret_val = phy->ops.identify(hw); |
| 194 | |
| 195 | /* Setup function pointers based on detected SFP module and speeds */ |
| 196 | ixgbe_init_mac_link_ops_82599(hw); |
| 197 | |
| 198 | /* If copper media, overwrite with copper function pointers */ |
| 199 | if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { |
| 200 | mac->ops.setup_link = &ixgbe_setup_copper_link_82599; |
| 201 | mac->ops.setup_link_speed = |
| 202 | &ixgbe_setup_copper_link_speed_82599; |
| 203 | mac->ops.get_link_capabilities = |
| 204 | &ixgbe_get_copper_link_capabilities_82599; |
| 205 | } |
| 206 | |
| 207 | /* Set necessary function pointers based on phy type */ |
| 208 | switch (hw->phy.type) { |
| 209 | case ixgbe_phy_tn: |
| 210 | phy->ops.check_link = &ixgbe_check_phy_link_tnx; |
| 211 | phy->ops.get_firmware_version = |
| 212 | &ixgbe_get_phy_firmware_version_tnx; |
| 213 | break; |
| 214 | default: |
| 215 | break; |
| 216 | } |
| 217 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 218 | return ret_val; |
| 219 | } |
| 220 | |
| 221 | /** |
| 222 | * ixgbe_get_link_capabilities_82599 - Determines link capabilities |
| 223 | * @hw: pointer to hardware structure |
| 224 | * @speed: pointer to link speed |
| 225 | * @negotiation: true when autoneg or autotry is enabled |
| 226 | * |
| 227 | * Determines the link capabilities by reading the AUTOC register. |
| 228 | **/ |
| 229 | s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, |
| 230 | ixgbe_link_speed *speed, |
| 231 | bool *negotiation) |
| 232 | { |
| 233 | s32 status = 0; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 234 | u32 autoc = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 235 | |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 236 | /* |
| 237 | * Determine link capabilities based on the stored value of AUTOC, |
| 238 | * which represents EEPROM defaults. If AUTOC value has not been |
| 239 | * stored, use the current register value. |
| 240 | */ |
| 241 | if (hw->mac.orig_link_settings_stored) |
| 242 | autoc = hw->mac.orig_autoc; |
| 243 | else |
| 244 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 245 | |
| 246 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 247 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
| 248 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 249 | *negotiation = false; |
| 250 | break; |
| 251 | |
| 252 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
| 253 | *speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 254 | *negotiation = false; |
| 255 | break; |
| 256 | |
| 257 | case IXGBE_AUTOC_LMS_1G_AN: |
| 258 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 259 | *negotiation = true; |
| 260 | break; |
| 261 | |
| 262 | case IXGBE_AUTOC_LMS_10G_SERIAL: |
| 263 | *speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 264 | *negotiation = false; |
| 265 | break; |
| 266 | |
| 267 | case IXGBE_AUTOC_LMS_KX4_KX_KR: |
| 268 | case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: |
| 269 | *speed = IXGBE_LINK_SPEED_UNKNOWN; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 270 | if (autoc & IXGBE_AUTOC_KR_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 271 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 272 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 273 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 274 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 275 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
| 276 | *negotiation = true; |
| 277 | break; |
| 278 | |
| 279 | case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: |
| 280 | *speed = IXGBE_LINK_SPEED_100_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 281 | if (autoc & IXGBE_AUTOC_KR_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 282 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 283 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 284 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 285 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 286 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
| 287 | *negotiation = true; |
| 288 | break; |
| 289 | |
| 290 | case IXGBE_AUTOC_LMS_SGMII_1G_100M: |
| 291 | *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; |
| 292 | *negotiation = false; |
| 293 | break; |
| 294 | |
| 295 | default: |
| 296 | status = IXGBE_ERR_LINK_SETUP; |
| 297 | goto out; |
| 298 | break; |
| 299 | } |
| 300 | |
| 301 | if (hw->phy.multispeed_fiber) { |
| 302 | *speed |= IXGBE_LINK_SPEED_10GB_FULL | |
| 303 | IXGBE_LINK_SPEED_1GB_FULL; |
| 304 | *negotiation = true; |
| 305 | } |
| 306 | |
| 307 | out: |
| 308 | return status; |
| 309 | } |
| 310 | |
| 311 | /** |
| 312 | * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities |
| 313 | * @hw: pointer to hardware structure |
| 314 | * @speed: pointer to link speed |
| 315 | * @autoneg: boolean auto-negotiation value |
| 316 | * |
| 317 | * Determines the link capabilities by reading the AUTOC register. |
| 318 | **/ |
| 319 | static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw, |
| 320 | ixgbe_link_speed *speed, |
| 321 | bool *autoneg) |
| 322 | { |
| 323 | s32 status = IXGBE_ERR_LINK_SETUP; |
| 324 | u16 speed_ability; |
| 325 | |
| 326 | *speed = 0; |
| 327 | *autoneg = true; |
| 328 | |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 329 | status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 330 | &speed_ability); |
| 331 | |
| 332 | if (status == 0) { |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 333 | if (speed_ability & MDIO_SPEED_10G) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 334 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 335 | if (speed_ability & MDIO_PMA_SPEED_1000) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 336 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
| 337 | } |
| 338 | |
| 339 | return status; |
| 340 | } |
| 341 | |
| 342 | /** |
| 343 | * ixgbe_get_media_type_82599 - Get media type |
| 344 | * @hw: pointer to hardware structure |
| 345 | * |
| 346 | * Returns the media type (fiber, copper, backplane) |
| 347 | **/ |
| 348 | enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) |
| 349 | { |
| 350 | enum ixgbe_media_type media_type; |
| 351 | |
| 352 | /* Detect if there is a copper PHY attached. */ |
| 353 | if (hw->phy.type == ixgbe_phy_cu_unknown || |
| 354 | hw->phy.type == ixgbe_phy_tn) { |
| 355 | media_type = ixgbe_media_type_copper; |
| 356 | goto out; |
| 357 | } |
| 358 | |
| 359 | switch (hw->device_id) { |
| 360 | case IXGBE_DEV_ID_82599: |
| 361 | case IXGBE_DEV_ID_82599_KX4: |
Peter P Waskiewicz Jr | 1fcf03e | 2009-05-17 20:58:04 +0000 | [diff] [blame] | 362 | case IXGBE_DEV_ID_82599_XAUI_LOM: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 363 | /* Default device ID is mezzanine card KX/KX4 */ |
| 364 | media_type = ixgbe_media_type_backplane; |
| 365 | break; |
| 366 | case IXGBE_DEV_ID_82599_SFP: |
| 367 | media_type = ixgbe_media_type_fiber; |
| 368 | break; |
| 369 | default: |
| 370 | media_type = ixgbe_media_type_unknown; |
| 371 | break; |
| 372 | } |
| 373 | out: |
| 374 | return media_type; |
| 375 | } |
| 376 | |
| 377 | /** |
| 378 | * ixgbe_setup_mac_link_82599 - Setup MAC link settings |
| 379 | * @hw: pointer to hardware structure |
| 380 | * |
| 381 | * Configures link settings based on values in the ixgbe_hw struct. |
| 382 | * Restarts the link. Performs autonegotiation if needed. |
| 383 | **/ |
| 384 | s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw) |
| 385 | { |
| 386 | u32 autoc_reg; |
| 387 | u32 links_reg; |
| 388 | u32 i; |
| 389 | s32 status = 0; |
| 390 | |
| 391 | /* Restart link */ |
| 392 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 393 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; |
| 394 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); |
| 395 | |
| 396 | /* Only poll for autoneg to complete if specified to do so */ |
| 397 | if (hw->phy.autoneg_wait_to_complete) { |
| 398 | if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
| 399 | IXGBE_AUTOC_LMS_KX4_KX_KR || |
| 400 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
| 401 | IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || |
| 402 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
| 403 | IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { |
| 404 | links_reg = 0; /* Just in case Autoneg time = 0 */ |
| 405 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { |
| 406 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); |
| 407 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) |
| 408 | break; |
| 409 | msleep(100); |
| 410 | } |
| 411 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { |
| 412 | status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; |
| 413 | hw_dbg(hw, "Autoneg did not complete.\n"); |
| 414 | } |
| 415 | } |
| 416 | } |
| 417 | |
| 418 | /* Set up flow control */ |
| 419 | status = ixgbe_setup_fc_generic(hw, 0); |
| 420 | |
| 421 | /* Add delay to filter out noises during initial link setup */ |
| 422 | msleep(50); |
| 423 | |
| 424 | return status; |
| 425 | } |
| 426 | |
| 427 | /** |
| 428 | * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings |
| 429 | * @hw: pointer to hardware structure |
| 430 | * |
| 431 | * Configures link settings based on values in the ixgbe_hw struct. |
| 432 | * Restarts the link for multi-speed fiber at 1G speed, if link |
| 433 | * fails at 10G. |
| 434 | * Performs autonegotiation if needed. |
| 435 | **/ |
| 436 | s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw) |
| 437 | { |
| 438 | s32 status = 0; |
| 439 | ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG; |
Jesse Brandeburg | 4df1046 | 2009-03-13 22:15:31 +0000 | [diff] [blame] | 440 | status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 441 | true, true); |
| 442 | return status; |
| 443 | } |
| 444 | |
| 445 | /** |
| 446 | * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed |
| 447 | * @hw: pointer to hardware structure |
| 448 | * @speed: new link speed |
| 449 | * @autoneg: true if autonegotiation enabled |
| 450 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
| 451 | * |
| 452 | * Set the link speed in the AUTOC register and restarts link. |
| 453 | **/ |
| 454 | s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw, |
| 455 | ixgbe_link_speed speed, |
| 456 | bool autoneg, |
| 457 | bool autoneg_wait_to_complete) |
| 458 | { |
| 459 | s32 status = 0; |
| 460 | ixgbe_link_speed phy_link_speed; |
| 461 | ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; |
| 462 | u32 speedcnt = 0; |
| 463 | u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); |
| 464 | bool link_up = false; |
| 465 | bool negotiation; |
| 466 | |
| 467 | /* Mask off requested but non-supported speeds */ |
| 468 | hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation); |
| 469 | speed &= phy_link_speed; |
| 470 | |
| 471 | /* |
| 472 | * Try each speed one by one, highest priority first. We do this in |
| 473 | * software because 10gb fiber doesn't support speed autonegotiation. |
| 474 | */ |
| 475 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) { |
| 476 | speedcnt++; |
| 477 | highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 478 | |
| 479 | /* Set hardware SDP's */ |
| 480 | esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); |
| 481 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
| 482 | |
| 483 | ixgbe_setup_mac_link_speed_82599(hw, |
| 484 | IXGBE_LINK_SPEED_10GB_FULL, |
| 485 | autoneg, |
| 486 | autoneg_wait_to_complete); |
| 487 | |
| 488 | msleep(50); |
| 489 | |
| 490 | /* If we have link, just jump out */ |
| 491 | hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); |
| 492 | if (link_up) |
| 493 | goto out; |
| 494 | } |
| 495 | |
| 496 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) { |
| 497 | speedcnt++; |
| 498 | if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) |
| 499 | highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 500 | |
| 501 | /* Set hardware SDP's */ |
| 502 | esdp_reg &= ~IXGBE_ESDP_SDP5; |
| 503 | esdp_reg |= IXGBE_ESDP_SDP5_DIR; |
| 504 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
| 505 | |
| 506 | ixgbe_setup_mac_link_speed_82599( |
| 507 | hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg, |
| 508 | autoneg_wait_to_complete); |
| 509 | |
| 510 | msleep(50); |
| 511 | |
| 512 | /* If we have link, just jump out */ |
| 513 | hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); |
| 514 | if (link_up) |
| 515 | goto out; |
| 516 | } |
| 517 | |
| 518 | /* |
| 519 | * We didn't get link. Configure back to the highest speed we tried, |
| 520 | * (if there was more than one). We call ourselves back with just the |
| 521 | * single highest speed that the user requested. |
| 522 | */ |
| 523 | if (speedcnt > 1) |
| 524 | status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, |
| 525 | highest_link_speed, |
| 526 | autoneg, |
| 527 | autoneg_wait_to_complete); |
| 528 | |
| 529 | out: |
| 530 | return status; |
| 531 | } |
| 532 | |
| 533 | /** |
| 534 | * ixgbe_check_mac_link_82599 - Determine link and speed status |
| 535 | * @hw: pointer to hardware structure |
| 536 | * @speed: pointer to link speed |
| 537 | * @link_up: true when link is up |
| 538 | * @link_up_wait_to_complete: bool used to wait for link up or not |
| 539 | * |
| 540 | * Reads the links register to determine if link is up and the current speed |
| 541 | **/ |
| 542 | s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed, |
| 543 | bool *link_up, bool link_up_wait_to_complete) |
| 544 | { |
| 545 | u32 links_reg; |
| 546 | u32 i; |
| 547 | |
| 548 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); |
| 549 | if (link_up_wait_to_complete) { |
| 550 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { |
| 551 | if (links_reg & IXGBE_LINKS_UP) { |
| 552 | *link_up = true; |
| 553 | break; |
| 554 | } else { |
| 555 | *link_up = false; |
| 556 | } |
| 557 | msleep(100); |
| 558 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); |
| 559 | } |
| 560 | } else { |
| 561 | if (links_reg & IXGBE_LINKS_UP) |
| 562 | *link_up = true; |
| 563 | else |
| 564 | *link_up = false; |
| 565 | } |
| 566 | |
| 567 | if ((links_reg & IXGBE_LINKS_SPEED_82599) == |
| 568 | IXGBE_LINKS_SPEED_10G_82599) |
| 569 | *speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 570 | else if ((links_reg & IXGBE_LINKS_SPEED_82599) == |
| 571 | IXGBE_LINKS_SPEED_1G_82599) |
| 572 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 573 | else |
| 574 | *speed = IXGBE_LINK_SPEED_100_FULL; |
| 575 | |
| 576 | |
| 577 | return 0; |
| 578 | } |
| 579 | |
| 580 | /** |
| 581 | * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed |
| 582 | * @hw: pointer to hardware structure |
| 583 | * @speed: new link speed |
| 584 | * @autoneg: true if autonegotiation enabled |
| 585 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
| 586 | * |
| 587 | * Set the link speed in the AUTOC register and restarts link. |
| 588 | **/ |
| 589 | s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw, |
| 590 | ixgbe_link_speed speed, bool autoneg, |
| 591 | bool autoneg_wait_to_complete) |
| 592 | { |
| 593 | s32 status = 0; |
| 594 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 595 | u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 596 | u32 orig_autoc = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 597 | u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; |
| 598 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; |
| 599 | u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; |
| 600 | u32 links_reg; |
| 601 | u32 i; |
| 602 | ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; |
| 603 | |
| 604 | /* Check to see if speed passed in is supported. */ |
| 605 | hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg); |
| 606 | speed &= link_capabilities; |
| 607 | |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 608 | /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ |
| 609 | if (hw->mac.orig_link_settings_stored) |
| 610 | orig_autoc = hw->mac.orig_autoc; |
| 611 | else |
| 612 | orig_autoc = autoc; |
| 613 | |
| 614 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 615 | if (speed == IXGBE_LINK_SPEED_UNKNOWN) { |
| 616 | status = IXGBE_ERR_LINK_SETUP; |
| 617 | } else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || |
| 618 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || |
| 619 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { |
| 620 | /* Set KX4/KX/KR support according to speed requested */ |
| 621 | autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); |
| 622 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 623 | if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 624 | autoc |= IXGBE_AUTOC_KX4_SUPP; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 625 | if (orig_autoc & IXGBE_AUTOC_KR_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 626 | autoc |= IXGBE_AUTOC_KR_SUPP; |
| 627 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) |
| 628 | autoc |= IXGBE_AUTOC_KX_SUPP; |
| 629 | } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && |
| 630 | (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || |
| 631 | link_mode == IXGBE_AUTOC_LMS_1G_AN)) { |
| 632 | /* Switch from 1G SFI to 10G SFI if requested */ |
| 633 | if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && |
| 634 | (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { |
| 635 | autoc &= ~IXGBE_AUTOC_LMS_MASK; |
| 636 | autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; |
| 637 | } |
| 638 | } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && |
| 639 | (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { |
| 640 | /* Switch from 10G SFI to 1G SFI if requested */ |
| 641 | if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && |
| 642 | (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { |
| 643 | autoc &= ~IXGBE_AUTOC_LMS_MASK; |
| 644 | if (autoneg) |
| 645 | autoc |= IXGBE_AUTOC_LMS_1G_AN; |
| 646 | else |
| 647 | autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; |
| 648 | } |
| 649 | } |
| 650 | |
| 651 | if (status == 0) { |
| 652 | /* Restart link */ |
| 653 | autoc |= IXGBE_AUTOC_AN_RESTART; |
| 654 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); |
| 655 | |
| 656 | /* Only poll for autoneg to complete if specified to do so */ |
| 657 | if (autoneg_wait_to_complete) { |
| 658 | if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || |
| 659 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || |
| 660 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { |
| 661 | links_reg = 0; /*Just in case Autoneg time=0*/ |
| 662 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { |
| 663 | links_reg = |
| 664 | IXGBE_READ_REG(hw, IXGBE_LINKS); |
| 665 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) |
| 666 | break; |
| 667 | msleep(100); |
| 668 | } |
| 669 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { |
| 670 | status = |
| 671 | IXGBE_ERR_AUTONEG_NOT_COMPLETE; |
| 672 | hw_dbg(hw, "Autoneg did not " |
| 673 | "complete.\n"); |
| 674 | } |
| 675 | } |
| 676 | } |
| 677 | |
| 678 | /* Set up flow control */ |
| 679 | status = ixgbe_setup_fc_generic(hw, 0); |
| 680 | |
| 681 | /* Add delay to filter out noises during initial link setup */ |
| 682 | msleep(50); |
| 683 | } |
| 684 | |
| 685 | return status; |
| 686 | } |
| 687 | |
| 688 | /** |
| 689 | * ixgbe_setup_copper_link_82599 - Setup copper link settings |
| 690 | * @hw: pointer to hardware structure |
| 691 | * |
| 692 | * Restarts the link on PHY and then MAC. Performs autonegotiation if needed. |
| 693 | **/ |
| 694 | static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw) |
| 695 | { |
| 696 | s32 status; |
| 697 | |
| 698 | /* Restart autonegotiation on PHY */ |
| 699 | status = hw->phy.ops.setup_link(hw); |
| 700 | |
| 701 | /* Set up MAC */ |
| 702 | ixgbe_setup_mac_link_82599(hw); |
| 703 | |
| 704 | return status; |
| 705 | } |
| 706 | |
| 707 | /** |
| 708 | * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field |
| 709 | * @hw: pointer to hardware structure |
| 710 | * @speed: new link speed |
| 711 | * @autoneg: true if autonegotiation enabled |
| 712 | * @autoneg_wait_to_complete: true if waiting is needed to complete |
| 713 | * |
| 714 | * Restarts link on PHY and MAC based on settings passed in. |
| 715 | **/ |
| 716 | static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw, |
| 717 | ixgbe_link_speed speed, |
| 718 | bool autoneg, |
| 719 | bool autoneg_wait_to_complete) |
| 720 | { |
| 721 | s32 status; |
| 722 | |
| 723 | /* Setup the PHY according to input speed */ |
| 724 | status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, |
| 725 | autoneg_wait_to_complete); |
| 726 | /* Set up MAC */ |
| 727 | ixgbe_setup_mac_link_82599(hw); |
| 728 | |
| 729 | return status; |
| 730 | } |
| 731 | |
| 732 | /** |
| 733 | * ixgbe_reset_hw_82599 - Perform hardware reset |
| 734 | * @hw: pointer to hardware structure |
| 735 | * |
| 736 | * Resets the hardware by resetting the transmit and receive units, masks |
| 737 | * and clears all interrupts, perform a PHY reset, and perform a link (MAC) |
| 738 | * reset. |
| 739 | **/ |
| 740 | s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) |
| 741 | { |
| 742 | s32 status = 0; |
| 743 | u32 ctrl, ctrl_ext; |
| 744 | u32 i; |
| 745 | u32 autoc; |
| 746 | u32 autoc2; |
| 747 | |
| 748 | /* Call adapter stop to disable tx/rx and clear interrupts */ |
| 749 | hw->mac.ops.stop_adapter(hw); |
| 750 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 751 | /* PHY ops must be identified and initialized prior to reset */ |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 752 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 753 | /* Init PHY and function pointers, perform SFP setup */ |
| 754 | status = hw->phy.ops.init(hw); |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 755 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 756 | if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) |
| 757 | goto reset_hw_out; |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 758 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 759 | /* Setup SFP module if there is one present. */ |
| 760 | if (hw->phy.sfp_setup_needed) { |
| 761 | status = hw->mac.ops.setup_sfp(hw); |
| 762 | hw->phy.sfp_setup_needed = false; |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 763 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 764 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 765 | /* Reset PHY */ |
| 766 | if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) |
| 767 | hw->phy.ops.reset(hw); |
| 768 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 769 | /* |
| 770 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master |
| 771 | * access and verify no pending requests before reset |
| 772 | */ |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 773 | status = ixgbe_disable_pcie_master(hw); |
| 774 | if (status != 0) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 775 | status = IXGBE_ERR_MASTER_REQUESTS_PENDING; |
| 776 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); |
| 777 | } |
| 778 | |
| 779 | /* |
| 780 | * Issue global reset to the MAC. This needs to be a SW reset. |
| 781 | * If link reset is used, it might reset the MAC when mng is using it |
| 782 | */ |
| 783 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); |
| 784 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); |
| 785 | IXGBE_WRITE_FLUSH(hw); |
| 786 | |
| 787 | /* Poll for reset bit to self-clear indicating reset is complete */ |
| 788 | for (i = 0; i < 10; i++) { |
| 789 | udelay(1); |
| 790 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); |
| 791 | if (!(ctrl & IXGBE_CTRL_RST)) |
| 792 | break; |
| 793 | } |
| 794 | if (ctrl & IXGBE_CTRL_RST) { |
| 795 | status = IXGBE_ERR_RESET_FAILED; |
| 796 | hw_dbg(hw, "Reset polling failed to complete.\n"); |
| 797 | } |
| 798 | /* Clear PF Reset Done bit so PF/VF Mail Ops can work */ |
| 799 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); |
| 800 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; |
| 801 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); |
| 802 | |
| 803 | msleep(50); |
| 804 | |
| 805 | |
| 806 | |
| 807 | /* |
| 808 | * Store the original AUTOC/AUTOC2 values if they have not been |
| 809 | * stored off yet. Otherwise restore the stored original |
| 810 | * values since the reset operation sets back to defaults. |
| 811 | */ |
| 812 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 813 | autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); |
| 814 | if (hw->mac.orig_link_settings_stored == false) { |
| 815 | hw->mac.orig_autoc = autoc; |
| 816 | hw->mac.orig_autoc2 = autoc2; |
| 817 | hw->mac.orig_link_settings_stored = true; |
Jesse Brandeburg | 4df1046 | 2009-03-13 22:15:31 +0000 | [diff] [blame] | 818 | } else { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 819 | if (autoc != hw->mac.orig_autoc) |
| 820 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | |
| 821 | IXGBE_AUTOC_AN_RESTART)); |
| 822 | |
| 823 | if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != |
| 824 | (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { |
| 825 | autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; |
| 826 | autoc2 |= (hw->mac.orig_autoc2 & |
| 827 | IXGBE_AUTOC2_UPPER_MASK); |
| 828 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); |
| 829 | } |
| 830 | } |
| 831 | |
Waskiewicz Jr, Peter P | aca6bee | 2009-05-17 12:32:48 +0000 | [diff] [blame] | 832 | /* |
| 833 | * Store MAC address from RAR0, clear receive address registers, and |
| 834 | * clear the multicast table. Also reset num_rar_entries to 128, |
| 835 | * since we modify this value when programming the SAN MAC address. |
| 836 | */ |
| 837 | hw->mac.num_rar_entries = 128; |
| 838 | hw->mac.ops.init_rx_addrs(hw); |
| 839 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 840 | /* Store the permanent mac address */ |
| 841 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); |
| 842 | |
PJ Waskiewicz | 0365e6e | 2009-05-17 12:32:25 +0000 | [diff] [blame] | 843 | /* Store the permanent SAN mac address */ |
| 844 | hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); |
| 845 | |
Waskiewicz Jr, Peter P | aca6bee | 2009-05-17 12:32:48 +0000 | [diff] [blame] | 846 | /* Add the SAN MAC address to the RAR only if it's a valid address */ |
| 847 | if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { |
| 848 | hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, |
| 849 | hw->mac.san_addr, 0, IXGBE_RAH_AV); |
| 850 | |
| 851 | /* Reserve the last RAR for the SAN MAC address */ |
| 852 | hw->mac.num_rar_entries--; |
| 853 | } |
| 854 | |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 855 | reset_hw_out: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 856 | return status; |
| 857 | } |
| 858 | |
| 859 | /** |
| 860 | * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address |
| 861 | * @hw: pointer to hardware struct |
| 862 | * @rar: receive address register index to disassociate |
| 863 | * @vmdq: VMDq pool index to remove from the rar |
| 864 | **/ |
| 865 | s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq) |
| 866 | { |
| 867 | u32 mpsar_lo, mpsar_hi; |
| 868 | u32 rar_entries = hw->mac.num_rar_entries; |
| 869 | |
| 870 | if (rar < rar_entries) { |
| 871 | mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); |
| 872 | mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); |
| 873 | |
| 874 | if (!mpsar_lo && !mpsar_hi) |
| 875 | goto done; |
| 876 | |
| 877 | if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { |
| 878 | if (mpsar_lo) { |
| 879 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); |
| 880 | mpsar_lo = 0; |
| 881 | } |
| 882 | if (mpsar_hi) { |
| 883 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); |
| 884 | mpsar_hi = 0; |
| 885 | } |
| 886 | } else if (vmdq < 32) { |
| 887 | mpsar_lo &= ~(1 << vmdq); |
| 888 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); |
| 889 | } else { |
| 890 | mpsar_hi &= ~(1 << (vmdq - 32)); |
| 891 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); |
| 892 | } |
| 893 | |
| 894 | /* was that the last pool using this rar? */ |
| 895 | if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) |
| 896 | hw->mac.ops.clear_rar(hw, rar); |
| 897 | } else { |
| 898 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); |
| 899 | } |
| 900 | |
| 901 | done: |
| 902 | return 0; |
| 903 | } |
| 904 | |
| 905 | /** |
| 906 | * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address |
| 907 | * @hw: pointer to hardware struct |
| 908 | * @rar: receive address register index to associate with a VMDq index |
| 909 | * @vmdq: VMDq pool index |
| 910 | **/ |
| 911 | s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq) |
| 912 | { |
| 913 | u32 mpsar; |
| 914 | u32 rar_entries = hw->mac.num_rar_entries; |
| 915 | |
| 916 | if (rar < rar_entries) { |
| 917 | if (vmdq < 32) { |
| 918 | mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); |
| 919 | mpsar |= 1 << vmdq; |
| 920 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); |
| 921 | } else { |
| 922 | mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); |
| 923 | mpsar |= 1 << (vmdq - 32); |
| 924 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); |
| 925 | } |
| 926 | } else { |
| 927 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); |
| 928 | } |
| 929 | return 0; |
| 930 | } |
| 931 | |
| 932 | /** |
| 933 | * ixgbe_set_vfta_82599 - Set VLAN filter table |
| 934 | * @hw: pointer to hardware structure |
| 935 | * @vlan: VLAN id to write to VLAN filter |
| 936 | * @vind: VMDq output index that maps queue to VLAN id in VFVFB |
| 937 | * @vlan_on: boolean flag to turn on/off VLAN in VFVF |
| 938 | * |
| 939 | * Turn on/off specified VLAN in the VLAN filter table. |
| 940 | **/ |
| 941 | s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind, |
| 942 | bool vlan_on) |
| 943 | { |
| 944 | u32 regindex; |
| 945 | u32 bitindex; |
| 946 | u32 bits; |
| 947 | u32 first_empty_slot; |
| 948 | |
| 949 | if (vlan > 4095) |
| 950 | return IXGBE_ERR_PARAM; |
| 951 | |
| 952 | /* |
| 953 | * this is a 2 part operation - first the VFTA, then the |
| 954 | * VLVF and VLVFB if vind is set |
| 955 | */ |
| 956 | |
| 957 | /* Part 1 |
| 958 | * The VFTA is a bitstring made up of 128 32-bit registers |
| 959 | * that enable the particular VLAN id, much like the MTA: |
| 960 | * bits[11-5]: which register |
| 961 | * bits[4-0]: which bit in the register |
| 962 | */ |
| 963 | regindex = (vlan >> 5) & 0x7F; |
| 964 | bitindex = vlan & 0x1F; |
| 965 | bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); |
| 966 | if (vlan_on) |
| 967 | bits |= (1 << bitindex); |
| 968 | else |
| 969 | bits &= ~(1 << bitindex); |
| 970 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); |
| 971 | |
| 972 | |
| 973 | /* Part 2 |
| 974 | * If the vind is set |
| 975 | * Either vlan_on |
| 976 | * make sure the vlan is in VLVF |
| 977 | * set the vind bit in the matching VLVFB |
| 978 | * Or !vlan_on |
| 979 | * clear the pool bit and possibly the vind |
| 980 | */ |
| 981 | if (vind) { |
| 982 | /* find the vlanid or the first empty slot */ |
| 983 | first_empty_slot = 0; |
| 984 | |
| 985 | for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { |
| 986 | bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); |
| 987 | if (!bits && !first_empty_slot) |
| 988 | first_empty_slot = regindex; |
| 989 | else if ((bits & 0x0FFF) == vlan) |
| 990 | break; |
| 991 | } |
| 992 | |
| 993 | if (regindex >= IXGBE_VLVF_ENTRIES) { |
| 994 | if (first_empty_slot) |
| 995 | regindex = first_empty_slot; |
| 996 | else { |
| 997 | hw_dbg(hw, "No space in VLVF.\n"); |
| 998 | goto out; |
| 999 | } |
| 1000 | } |
| 1001 | |
| 1002 | if (vlan_on) { |
| 1003 | /* set the pool bit */ |
| 1004 | if (vind < 32) { |
| 1005 | bits = IXGBE_READ_REG(hw, |
| 1006 | IXGBE_VLVFB(regindex * 2)); |
| 1007 | bits |= (1 << vind); |
| 1008 | IXGBE_WRITE_REG(hw, |
| 1009 | IXGBE_VLVFB(regindex * 2), bits); |
| 1010 | } else { |
| 1011 | bits = IXGBE_READ_REG(hw, |
| 1012 | IXGBE_VLVFB((regindex * 2) + 1)); |
| 1013 | bits |= (1 << vind); |
| 1014 | IXGBE_WRITE_REG(hw, |
| 1015 | IXGBE_VLVFB((regindex * 2) + 1), bits); |
| 1016 | } |
| 1017 | } else { |
| 1018 | /* clear the pool bit */ |
| 1019 | if (vind < 32) { |
| 1020 | bits = IXGBE_READ_REG(hw, |
| 1021 | IXGBE_VLVFB(regindex * 2)); |
| 1022 | bits &= ~(1 << vind); |
| 1023 | IXGBE_WRITE_REG(hw, |
| 1024 | IXGBE_VLVFB(regindex * 2), bits); |
| 1025 | bits |= IXGBE_READ_REG(hw, |
| 1026 | IXGBE_VLVFB((regindex * 2) + 1)); |
| 1027 | } else { |
| 1028 | bits = IXGBE_READ_REG(hw, |
| 1029 | IXGBE_VLVFB((regindex * 2) + 1)); |
| 1030 | bits &= ~(1 << vind); |
| 1031 | IXGBE_WRITE_REG(hw, |
| 1032 | IXGBE_VLVFB((regindex * 2) + 1), bits); |
| 1033 | bits |= IXGBE_READ_REG(hw, |
| 1034 | IXGBE_VLVFB(regindex * 2)); |
| 1035 | } |
| 1036 | } |
| 1037 | |
| 1038 | if (bits) |
| 1039 | IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), |
| 1040 | (IXGBE_VLVF_VIEN | vlan)); |
| 1041 | else |
| 1042 | IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0); |
| 1043 | } |
| 1044 | |
| 1045 | out: |
| 1046 | return 0; |
| 1047 | } |
| 1048 | |
| 1049 | /** |
| 1050 | * ixgbe_clear_vfta_82599 - Clear VLAN filter table |
| 1051 | * @hw: pointer to hardware structure |
| 1052 | * |
| 1053 | * Clears the VLAN filer table, and the VMDq index associated with the filter |
| 1054 | **/ |
| 1055 | s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw) |
| 1056 | { |
| 1057 | u32 offset; |
| 1058 | |
| 1059 | for (offset = 0; offset < hw->mac.vft_size; offset++) |
| 1060 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); |
| 1061 | |
| 1062 | for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { |
| 1063 | IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); |
| 1064 | IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); |
| 1065 | IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0); |
| 1066 | } |
| 1067 | |
| 1068 | return 0; |
| 1069 | } |
| 1070 | |
| 1071 | /** |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1072 | * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array |
| 1073 | * @hw: pointer to hardware structure |
| 1074 | **/ |
| 1075 | s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw) |
| 1076 | { |
| 1077 | int i; |
| 1078 | hw_dbg(hw, " Clearing UTA\n"); |
| 1079 | |
| 1080 | for (i = 0; i < 128; i++) |
| 1081 | IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); |
| 1082 | |
| 1083 | return 0; |
| 1084 | } |
| 1085 | |
| 1086 | /** |
| 1087 | * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register |
| 1088 | * @hw: pointer to hardware structure |
| 1089 | * @reg: analog register to read |
| 1090 | * @val: read value |
| 1091 | * |
| 1092 | * Performs read operation to Omer analog register specified. |
| 1093 | **/ |
| 1094 | s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) |
| 1095 | { |
| 1096 | u32 core_ctl; |
| 1097 | |
| 1098 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | |
| 1099 | (reg << 8)); |
| 1100 | IXGBE_WRITE_FLUSH(hw); |
| 1101 | udelay(10); |
| 1102 | core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); |
| 1103 | *val = (u8)core_ctl; |
| 1104 | |
| 1105 | return 0; |
| 1106 | } |
| 1107 | |
| 1108 | /** |
| 1109 | * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register |
| 1110 | * @hw: pointer to hardware structure |
| 1111 | * @reg: atlas register to write |
| 1112 | * @val: value to write |
| 1113 | * |
| 1114 | * Performs write operation to Omer analog register specified. |
| 1115 | **/ |
| 1116 | s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) |
| 1117 | { |
| 1118 | u32 core_ctl; |
| 1119 | |
| 1120 | core_ctl = (reg << 8) | val; |
| 1121 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); |
| 1122 | IXGBE_WRITE_FLUSH(hw); |
| 1123 | udelay(10); |
| 1124 | |
| 1125 | return 0; |
| 1126 | } |
| 1127 | |
| 1128 | /** |
| 1129 | * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx |
| 1130 | * @hw: pointer to hardware structure |
| 1131 | * |
| 1132 | * Starts the hardware using the generic start_hw function. |
| 1133 | * Then performs device-specific: |
| 1134 | * Clears the rate limiter registers. |
| 1135 | **/ |
| 1136 | s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) |
| 1137 | { |
| 1138 | u32 q_num; |
| 1139 | |
| 1140 | ixgbe_start_hw_generic(hw); |
| 1141 | |
| 1142 | /* Clear the rate limiters */ |
| 1143 | for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) { |
| 1144 | IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num); |
| 1145 | IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); |
| 1146 | } |
| 1147 | IXGBE_WRITE_FLUSH(hw); |
| 1148 | |
| 1149 | return 0; |
| 1150 | } |
| 1151 | |
| 1152 | /** |
| 1153 | * ixgbe_identify_phy_82599 - Get physical layer module |
| 1154 | * @hw: pointer to hardware structure |
| 1155 | * |
| 1156 | * Determines the physical layer module found on the current adapter. |
| 1157 | **/ |
| 1158 | s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) |
| 1159 | { |
| 1160 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; |
| 1161 | status = ixgbe_identify_phy_generic(hw); |
| 1162 | if (status != 0) |
| 1163 | status = ixgbe_identify_sfp_module_generic(hw); |
| 1164 | return status; |
| 1165 | } |
| 1166 | |
| 1167 | /** |
| 1168 | * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type |
| 1169 | * @hw: pointer to hardware structure |
| 1170 | * |
| 1171 | * Determines physical layer capabilities of the current configuration. |
| 1172 | **/ |
| 1173 | u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) |
| 1174 | { |
| 1175 | u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1176 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 1177 | u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); |
| 1178 | u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; |
| 1179 | u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; |
| 1180 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; |
| 1181 | u16 ext_ability = 0; |
PJ Waskiewicz | 1339b9e | 2009-03-13 22:12:29 +0000 | [diff] [blame] | 1182 | u8 comp_codes_10g = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1183 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1184 | hw->phy.ops.identify(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1185 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1186 | if (hw->phy.type == ixgbe_phy_tn || |
| 1187 | hw->phy.type == ixgbe_phy_cu_unknown) { |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 1188 | hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, |
| 1189 | &ext_ability); |
| 1190 | if (ext_ability & MDIO_PMA_EXTABLE_10GBT) |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1191 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 1192 | if (ext_ability & MDIO_PMA_EXTABLE_1000BT) |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1193 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 1194 | if (ext_ability & MDIO_PMA_EXTABLE_100BTX) |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1195 | physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; |
| 1196 | goto out; |
| 1197 | } |
| 1198 | |
| 1199 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { |
| 1200 | case IXGBE_AUTOC_LMS_1G_AN: |
| 1201 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
| 1202 | if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { |
| 1203 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | |
| 1204 | IXGBE_PHYSICAL_LAYER_1000BASE_BX; |
| 1205 | goto out; |
| 1206 | } else |
| 1207 | /* SFI mode so read SFP module */ |
| 1208 | goto sfp_check; |
| 1209 | break; |
| 1210 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
| 1211 | if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) |
| 1212 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; |
| 1213 | else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) |
| 1214 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; |
Peter P Waskiewicz Jr | 1fcf03e | 2009-05-17 20:58:04 +0000 | [diff] [blame] | 1215 | else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) |
| 1216 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1217 | goto out; |
| 1218 | break; |
| 1219 | case IXGBE_AUTOC_LMS_10G_SERIAL: |
| 1220 | if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { |
| 1221 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; |
| 1222 | goto out; |
| 1223 | } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) |
| 1224 | goto sfp_check; |
| 1225 | break; |
| 1226 | case IXGBE_AUTOC_LMS_KX4_KX_KR: |
| 1227 | case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: |
| 1228 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
| 1229 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; |
| 1230 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
| 1231 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; |
| 1232 | if (autoc & IXGBE_AUTOC_KR_SUPP) |
| 1233 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; |
| 1234 | goto out; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1235 | break; |
| 1236 | default: |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1237 | goto out; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1238 | break; |
| 1239 | } |
| 1240 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1241 | sfp_check: |
| 1242 | /* SFP check must be done last since DA modules are sometimes used to |
| 1243 | * test KR mode - we need to id KR mode correctly before SFP module. |
| 1244 | * Call identify_sfp because the pluggable module may have changed */ |
| 1245 | hw->phy.ops.identify_sfp(hw); |
| 1246 | if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) |
| 1247 | goto out; |
| 1248 | |
| 1249 | switch (hw->phy.type) { |
| 1250 | case ixgbe_phy_tw_tyco: |
| 1251 | case ixgbe_phy_tw_unknown: |
| 1252 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; |
| 1253 | break; |
| 1254 | case ixgbe_phy_sfp_avago: |
| 1255 | case ixgbe_phy_sfp_ftl: |
| 1256 | case ixgbe_phy_sfp_intel: |
| 1257 | case ixgbe_phy_sfp_unknown: |
| 1258 | hw->phy.ops.read_i2c_eeprom(hw, |
| 1259 | IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); |
| 1260 | if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) |
| 1261 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; |
| 1262 | else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) |
| 1263 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; |
| 1264 | break; |
| 1265 | default: |
| 1266 | break; |
| 1267 | } |
| 1268 | |
| 1269 | out: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1270 | return physical_layer; |
| 1271 | } |
| 1272 | |
| 1273 | /** |
| 1274 | * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 |
| 1275 | * @hw: pointer to hardware structure |
| 1276 | * @regval: register value to write to RXCTRL |
| 1277 | * |
| 1278 | * Enables the Rx DMA unit for 82599 |
| 1279 | **/ |
| 1280 | s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) |
| 1281 | { |
| 1282 | #define IXGBE_MAX_SECRX_POLL 30 |
| 1283 | int i; |
| 1284 | int secrxreg; |
| 1285 | |
| 1286 | /* |
| 1287 | * Workaround for 82599 silicon errata when enabling the Rx datapath. |
| 1288 | * If traffic is incoming before we enable the Rx unit, it could hang |
| 1289 | * the Rx DMA unit. Therefore, make sure the security engine is |
| 1290 | * completely disabled prior to enabling the Rx unit. |
| 1291 | */ |
| 1292 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); |
| 1293 | secrxreg |= IXGBE_SECRXCTRL_RX_DIS; |
| 1294 | IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); |
| 1295 | for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { |
| 1296 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); |
| 1297 | if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) |
| 1298 | break; |
| 1299 | else |
| 1300 | udelay(10); |
| 1301 | } |
| 1302 | |
| 1303 | /* For informational purposes only */ |
| 1304 | if (i >= IXGBE_MAX_SECRX_POLL) |
| 1305 | hw_dbg(hw, "Rx unit being enabled before security " |
| 1306 | "path fully disabled. Continuing with init.\n"); |
| 1307 | |
| 1308 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); |
| 1309 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); |
| 1310 | secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; |
| 1311 | IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); |
| 1312 | IXGBE_WRITE_FLUSH(hw); |
| 1313 | |
| 1314 | return 0; |
| 1315 | } |
| 1316 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1317 | /** |
| 1318 | * ixgbe_get_device_caps_82599 - Get additional device capabilities |
| 1319 | * @hw: pointer to hardware structure |
| 1320 | * @device_caps: the EEPROM word with the extra device capabilities |
| 1321 | * |
| 1322 | * This function will read the EEPROM location for the device capabilities, |
| 1323 | * and return the word through device_caps. |
| 1324 | **/ |
| 1325 | s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps) |
| 1326 | { |
| 1327 | hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); |
| 1328 | |
| 1329 | return 0; |
| 1330 | } |
| 1331 | |
PJ Waskiewicz | 0365e6e | 2009-05-17 12:32:25 +0000 | [diff] [blame] | 1332 | /** |
| 1333 | * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599 |
| 1334 | * @hw: pointer to hardware structure |
| 1335 | * @san_mac_offset: SAN MAC address offset |
| 1336 | * |
| 1337 | * This function will read the EEPROM location for the SAN MAC address |
| 1338 | * pointer, and returns the value at that location. This is used in both |
| 1339 | * get and set mac_addr routines. |
| 1340 | **/ |
| 1341 | s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw, |
| 1342 | u16 *san_mac_offset) |
| 1343 | { |
| 1344 | /* |
| 1345 | * First read the EEPROM pointer to see if the MAC addresses are |
| 1346 | * available. |
| 1347 | */ |
| 1348 | hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset); |
| 1349 | |
| 1350 | return 0; |
| 1351 | } |
| 1352 | |
| 1353 | /** |
| 1354 | * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599 |
| 1355 | * @hw: pointer to hardware structure |
| 1356 | * @san_mac_addr: SAN MAC address |
| 1357 | * |
| 1358 | * Reads the SAN MAC address from the EEPROM, if it's available. This is |
| 1359 | * per-port, so set_lan_id() must be called before reading the addresses. |
| 1360 | * set_lan_id() is called by identify_sfp(), but this cannot be relied |
| 1361 | * upon for non-SFP connections, so we must call it here. |
| 1362 | **/ |
| 1363 | s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr) |
| 1364 | { |
| 1365 | u16 san_mac_data, san_mac_offset; |
| 1366 | u8 i; |
| 1367 | |
| 1368 | /* |
| 1369 | * First read the EEPROM pointer to see if the MAC addresses are |
| 1370 | * available. If they're not, no point in calling set_lan_id() here. |
| 1371 | */ |
| 1372 | ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset); |
| 1373 | |
| 1374 | if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { |
| 1375 | /* |
| 1376 | * No addresses available in this EEPROM. It's not an |
| 1377 | * error though, so just wipe the local address and return. |
| 1378 | */ |
| 1379 | for (i = 0; i < 6; i++) |
| 1380 | san_mac_addr[i] = 0xFF; |
| 1381 | |
| 1382 | goto san_mac_addr_out; |
| 1383 | } |
| 1384 | |
| 1385 | /* make sure we know which port we need to program */ |
| 1386 | hw->mac.ops.set_lan_id(hw); |
| 1387 | /* apply the port offset to the address offset */ |
| 1388 | (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : |
| 1389 | (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); |
| 1390 | for (i = 0; i < 3; i++) { |
| 1391 | hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data); |
| 1392 | san_mac_addr[i * 2] = (u8)(san_mac_data); |
| 1393 | san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); |
| 1394 | san_mac_offset++; |
| 1395 | } |
| 1396 | |
| 1397 | san_mac_addr_out: |
| 1398 | return 0; |
| 1399 | } |
| 1400 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1401 | static struct ixgbe_mac_operations mac_ops_82599 = { |
| 1402 | .init_hw = &ixgbe_init_hw_generic, |
| 1403 | .reset_hw = &ixgbe_reset_hw_82599, |
| 1404 | .start_hw = &ixgbe_start_hw_82599, |
| 1405 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
| 1406 | .get_media_type = &ixgbe_get_media_type_82599, |
| 1407 | .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599, |
| 1408 | .enable_rx_dma = &ixgbe_enable_rx_dma_82599, |
| 1409 | .get_mac_addr = &ixgbe_get_mac_addr_generic, |
PJ Waskiewicz | 0365e6e | 2009-05-17 12:32:25 +0000 | [diff] [blame] | 1410 | .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599, |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1411 | .get_device_caps = &ixgbe_get_device_caps_82599, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1412 | .stop_adapter = &ixgbe_stop_adapter_generic, |
| 1413 | .get_bus_info = &ixgbe_get_bus_info_generic, |
| 1414 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, |
| 1415 | .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, |
| 1416 | .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, |
| 1417 | .setup_link = &ixgbe_setup_mac_link_82599, |
| 1418 | .setup_link_speed = &ixgbe_setup_mac_link_speed_82599, |
| 1419 | .check_link = &ixgbe_check_mac_link_82599, |
| 1420 | .get_link_capabilities = &ixgbe_get_link_capabilities_82599, |
| 1421 | .led_on = &ixgbe_led_on_generic, |
| 1422 | .led_off = &ixgbe_led_off_generic, |
PJ Waskiewicz | 87c1201 | 2009-04-08 13:20:31 +0000 | [diff] [blame] | 1423 | .blink_led_start = &ixgbe_blink_led_start_generic, |
| 1424 | .blink_led_stop = &ixgbe_blink_led_stop_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1425 | .set_rar = &ixgbe_set_rar_generic, |
| 1426 | .clear_rar = &ixgbe_clear_rar_generic, |
| 1427 | .set_vmdq = &ixgbe_set_vmdq_82599, |
| 1428 | .clear_vmdq = &ixgbe_clear_vmdq_82599, |
| 1429 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, |
| 1430 | .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic, |
| 1431 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, |
| 1432 | .enable_mc = &ixgbe_enable_mc_generic, |
| 1433 | .disable_mc = &ixgbe_disable_mc_generic, |
| 1434 | .clear_vfta = &ixgbe_clear_vfta_82599, |
| 1435 | .set_vfta = &ixgbe_set_vfta_82599, |
| 1436 | .setup_fc = &ixgbe_setup_fc_generic, |
| 1437 | .init_uta_tables = &ixgbe_init_uta_tables_82599, |
| 1438 | .setup_sfp = &ixgbe_setup_sfp_modules_82599, |
| 1439 | }; |
| 1440 | |
| 1441 | static struct ixgbe_eeprom_operations eeprom_ops_82599 = { |
| 1442 | .init_params = &ixgbe_init_eeprom_params_generic, |
| 1443 | .read = &ixgbe_read_eeprom_generic, |
| 1444 | .write = &ixgbe_write_eeprom_generic, |
| 1445 | .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, |
| 1446 | .update_checksum = &ixgbe_update_eeprom_checksum_generic, |
| 1447 | }; |
| 1448 | |
| 1449 | static struct ixgbe_phy_operations phy_ops_82599 = { |
| 1450 | .identify = &ixgbe_identify_phy_82599, |
| 1451 | .identify_sfp = &ixgbe_identify_sfp_module_generic, |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 1452 | .init = &ixgbe_init_phy_ops_82599, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1453 | .reset = &ixgbe_reset_phy_generic, |
| 1454 | .read_reg = &ixgbe_read_phy_reg_generic, |
| 1455 | .write_reg = &ixgbe_write_phy_reg_generic, |
| 1456 | .setup_link = &ixgbe_setup_phy_link_generic, |
| 1457 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, |
| 1458 | .read_i2c_byte = &ixgbe_read_i2c_byte_generic, |
| 1459 | .write_i2c_byte = &ixgbe_write_i2c_byte_generic, |
| 1460 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, |
| 1461 | .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, |
| 1462 | }; |
| 1463 | |
| 1464 | struct ixgbe_info ixgbe_82599_info = { |
| 1465 | .mac = ixgbe_mac_82599EB, |
| 1466 | .get_invariants = &ixgbe_get_invariants_82599, |
| 1467 | .mac_ops = &mac_ops_82599, |
| 1468 | .eeprom_ops = &eeprom_ops_82599, |
| 1469 | .phy_ops = &phy_ops_82599, |
| 1470 | }; |