Michal Simek | aa7eb2b | 2013-03-20 13:50:12 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This file contains Xilinx specific SMP code, used to start up |
| 3 | * the second processor. |
| 4 | * |
| 5 | * Copyright (C) 2011-2013 Xilinx |
| 6 | * |
| 7 | * based on linux/arch/arm/mach-realview/platsmp.c |
| 8 | * |
| 9 | * Copyright (C) 2002 ARM Ltd. |
| 10 | * |
| 11 | * This software is licensed under the terms of the GNU General Public |
| 12 | * License version 2, as published by the Free Software Foundation, and |
| 13 | * may be copied, distributed, and modified under those terms. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/export.h> |
| 22 | #include <linux/jiffies.h> |
| 23 | #include <linux/init.h> |
| 24 | #include <linux/io.h> |
| 25 | #include <asm/cacheflush.h> |
| 26 | #include <asm/smp_scu.h> |
| 27 | #include <linux/irqchip/arm-gic.h> |
| 28 | #include "common.h" |
| 29 | |
| 30 | /* |
| 31 | * Store number of cores in the system |
| 32 | * Because of scu_get_core_count() must be in __init section and can't |
| 33 | * be called from zynq_cpun_start() because it is in __cpuinit section. |
| 34 | */ |
| 35 | static int ncores; |
| 36 | |
| 37 | /* Secondary CPU kernel startup is a 2 step process. The primary CPU |
| 38 | * starts the secondary CPU by giving it the address of the kernel and |
| 39 | * then sending it an event to wake it up. The secondary CPU then |
| 40 | * starts the kernel and tells the primary CPU it's up and running. |
| 41 | */ |
| 42 | static void __cpuinit zynq_secondary_init(unsigned int cpu) |
| 43 | { |
| 44 | /* |
| 45 | * if any interrupts are already enabled for the primary |
| 46 | * core (e.g. timer irq), then they will not have been enabled |
| 47 | * for us: do so |
| 48 | */ |
| 49 | gic_secondary_init(0); |
| 50 | } |
| 51 | |
| 52 | int __cpuinit zynq_cpun_start(u32 address, int cpu) |
| 53 | { |
| 54 | u32 trampoline_code_size = &zynq_secondary_trampoline_end - |
| 55 | &zynq_secondary_trampoline; |
| 56 | |
| 57 | if (cpu > ncores) { |
| 58 | pr_warn("CPU No. is not available in the system\n"); |
| 59 | return -1; |
| 60 | } |
| 61 | |
| 62 | /* MS: Expectation that SLCR are directly map and accessible */ |
| 63 | /* Not possible to jump to non aligned address */ |
| 64 | if (!(address & 3) && (!address || (address >= trampoline_code_size))) { |
| 65 | /* Store pointer to ioremap area which points to address 0x0 */ |
| 66 | static u8 __iomem *zero; |
| 67 | u32 trampoline_size = &zynq_secondary_trampoline_jump - |
| 68 | &zynq_secondary_trampoline; |
| 69 | |
| 70 | zynq_slcr_cpu_stop(cpu); |
| 71 | |
| 72 | if (__pa(PAGE_OFFSET)) { |
| 73 | zero = ioremap(0, trampoline_code_size); |
| 74 | if (!zero) { |
| 75 | pr_warn("BOOTUP jump vectors not accessible\n"); |
| 76 | return -1; |
| 77 | } |
| 78 | } else { |
| 79 | zero = (__force u8 __iomem *)PAGE_OFFSET; |
| 80 | } |
| 81 | |
| 82 | /* |
| 83 | * This is elegant way how to jump to any address |
| 84 | * 0x0: Load address at 0x8 to r0 |
| 85 | * 0x4: Jump by mov instruction |
| 86 | * 0x8: Jumping address |
| 87 | */ |
| 88 | memcpy((__force void *)zero, &zynq_secondary_trampoline, |
| 89 | trampoline_size); |
| 90 | writel(address, zero + trampoline_size); |
| 91 | |
| 92 | flush_cache_all(); |
| 93 | outer_flush_range(0, trampoline_code_size); |
| 94 | smp_wmb(); |
| 95 | |
| 96 | if (__pa(PAGE_OFFSET)) |
| 97 | iounmap(zero); |
| 98 | |
| 99 | zynq_slcr_cpu_start(cpu); |
| 100 | |
| 101 | return 0; |
| 102 | } |
| 103 | |
| 104 | pr_warn("Can't start CPU%d: Wrong starting address %x\n", cpu, address); |
| 105 | |
| 106 | return -1; |
| 107 | } |
| 108 | EXPORT_SYMBOL(zynq_cpun_start); |
| 109 | |
| 110 | static int __cpuinit zynq_boot_secondary(unsigned int cpu, |
| 111 | struct task_struct *idle) |
| 112 | { |
| 113 | return zynq_cpun_start(virt_to_phys(secondary_startup), cpu); |
| 114 | } |
| 115 | |
| 116 | /* |
| 117 | * Initialise the CPU possible map early - this describes the CPUs |
| 118 | * which may be present or become present in the system. |
| 119 | */ |
| 120 | static void __init zynq_smp_init_cpus(void) |
| 121 | { |
| 122 | int i; |
| 123 | |
| 124 | ncores = scu_get_core_count(zynq_scu_base); |
| 125 | |
| 126 | for (i = 0; i < ncores && i < CONFIG_NR_CPUS; i++) |
| 127 | set_cpu_possible(i, true); |
| 128 | } |
| 129 | |
| 130 | static void __init zynq_smp_prepare_cpus(unsigned int max_cpus) |
| 131 | { |
| 132 | int i; |
| 133 | |
| 134 | /* |
| 135 | * Initialise the present map, which describes the set of CPUs |
| 136 | * actually populated at the present time. |
| 137 | */ |
| 138 | for (i = 0; i < max_cpus; i++) |
| 139 | set_cpu_present(i, true); |
| 140 | |
| 141 | scu_enable(zynq_scu_base); |
| 142 | } |
| 143 | |
| 144 | struct smp_operations zynq_smp_ops __initdata = { |
| 145 | .smp_init_cpus = zynq_smp_init_cpus, |
| 146 | .smp_prepare_cpus = zynq_smp_prepare_cpus, |
| 147 | .smp_secondary_init = zynq_secondary_init, |
| 148 | .smp_boot_secondary = zynq_boot_secondary, |
| 149 | }; |