Raja Mallik | aac1e599 | 2018-02-16 14:54:12 +0530 | [diff] [blame^] | 1 | * Qualcomm Application CPU clock driver |
| 2 | |
| 3 | clock-a7 is the driver for the Root Clock Generator (rcg) hw which controls |
| 4 | the cpu rate. RCGs support selecting one of several clock inputs, as well as |
| 5 | a configurable divider. This hw is different than normal rcgs in that it may |
| 6 | optionally have a register which encodes the maximum rate supported by hw. |
| 7 | |
| 8 | Required properties: |
| 9 | - compatible: "qcom,clock-a53-8916", "qcom,clock-a7-9650", |
| 10 | "qcom,clock-a7-mdm9607", "qcom,clock-a7-sdx20" |
| 11 | - reg: pairs of physical address and region size |
| 12 | - reg-names: "rcg-base" is expected |
| 13 | - clock-names: list of names of clock inputs |
| 14 | - qcom,speedX-bin-vZ: |
| 15 | A table of CPU frequency (Hz) to regulator voltage (uV) mapping. |
| 16 | Format: <freq uV> |
| 17 | This represents the max frequency possible for each possible |
| 18 | power configuration for a CPU that's binned as speed bin X, |
| 19 | speed bin revision Z. Speed bin values can be between [0-7] |
| 20 | and the version can be between [0-3]. |
| 21 | |
| 22 | - cpu-vdd-supply: regulator phandle for cpu power domain. |
| 23 | |
| 24 | Optional properties: |
| 25 | - reg-names: "efuse", "efuse1" |
| 26 | - qcom,safe-freq: Frequency in HZ |
| 27 | When switching rates from A to B, the mux div clock will |
| 28 | instead switch from A -> safe_freq -> B. |
| 29 | - qcom,enable-opp: This will allow to register the cpu clock with OPP |
| 30 | framework. |
| 31 | |
| 32 | Example: |
| 33 | qcom,acpuclk@f9011050 { |
| 34 | compatible = "qcom,clock-a7-8226"; |
| 35 | reg = <0xf9011050 0x8>; |
| 36 | reg-names = "rcg_base"; |
| 37 | cpu-vdd-supply = <&apc_vreg_corner>; |
| 38 | |
| 39 | clock-names = "clk-4", "clk-5"; |
| 40 | qcom,speed0-bin-v0 = |
| 41 | <384000000 1150000>, |
| 42 | <600000000 1200000>; |
| 43 | }; |