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Daniel Drakeec62bd92006-08-12 17:59:46 +01001/* zd_rf_al7230b.c: Functions for the AL7230B RF controller
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18#include <linux/kernel.h>
19
20#include "zd_rf.h"
21#include "zd_usb.h"
22#include "zd_chip.h"
23
24static const u32 chan_rv[][2] = {
25 RF_CHANNEL( 1) = { 0x09ec00, 0x8cccc8 },
26 RF_CHANNEL( 2) = { 0x09ec00, 0x8cccd8 },
27 RF_CHANNEL( 3) = { 0x09ec00, 0x8cccc0 },
28 RF_CHANNEL( 4) = { 0x09ec00, 0x8cccd0 },
29 RF_CHANNEL( 5) = { 0x05ec00, 0x8cccc8 },
30 RF_CHANNEL( 6) = { 0x05ec00, 0x8cccd8 },
31 RF_CHANNEL( 7) = { 0x05ec00, 0x8cccc0 },
32 RF_CHANNEL( 8) = { 0x05ec00, 0x8cccd0 },
33 RF_CHANNEL( 9) = { 0x0dec00, 0x8cccc8 },
34 RF_CHANNEL(10) = { 0x0dec00, 0x8cccd8 },
35 RF_CHANNEL(11) = { 0x0dec00, 0x8cccc0 },
36 RF_CHANNEL(12) = { 0x0dec00, 0x8cccd0 },
37 RF_CHANNEL(13) = { 0x03ec00, 0x8cccc8 },
38 RF_CHANNEL(14) = { 0x03ec00, 0x866660 },
39};
40
41static const u32 std_rv[] = {
42 0x4ff821,
43 0xc5fbfc,
44 0x21ebfe,
45 0xafd401, /* freq shift 0xaad401 */
46 0x6cf56a,
47 0xe04073,
48 0x193d76,
49 0x9dd844,
50 0x500007,
51 0xd8c010,
52};
53
Daniel Drakeba528c42007-04-07 16:00:30 +010054static const u32 rv_init1[] = {
55 0x3c9000,
56 0xbfffff,
57 0x700000,
58 0xf15d58,
59};
60
61static const u32 rv_init2[] = {
62 0xf15d59,
63 0xf15d5c,
64 0xf15d58,
65};
66
67static const struct zd_ioreq16 ioreqs_sw[] = {
68 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
69 { CR38, 0x38 }, { CR136, 0xdf },
70};
71
72static int zd1211b_al7230b_finalize(struct zd_chip *chip)
Daniel Drakeec62bd92006-08-12 17:59:46 +010073{
Daniel Drakeba528c42007-04-07 16:00:30 +010074 int r;
75 static const struct zd_ioreq16 ioreqs[] = {
76 { CR80, 0x30 }, { CR81, 0x30 }, { CR79, 0x58 },
77 { CR12, 0xf0 }, { CR77, 0x1b }, { CR78, 0x58 },
78 { CR203, 0x04 },
79 { },
80 { CR240, 0x80 },
81 };
82
83 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
84 if (r)
85 return r;
86
87 if (chip->new_phy_layout) {
88 /* antenna selection? */
89 r = zd_iowrite16_locked(chip, 0xe5, CR9);
90 if (r)
91 return r;
92 }
93
94 return zd_iowrite16_locked(chip, 0x04, CR203);
95}
96
97static int zd1211_al7230b_init_hw(struct zd_rf *rf)
98{
99 int r;
Daniel Drakeec62bd92006-08-12 17:59:46 +0100100 struct zd_chip *chip = zd_rf_to_chip(rf);
101
102 /* All of these writes are identical to AL2230 unless otherwise
103 * specified */
104 static const struct zd_ioreq16 ioreqs_1[] = {
105 /* This one is 7230-specific, and happens before the rest */
106 { CR240, 0x57 },
107 { },
108
109 { CR15, 0x20 }, { CR23, 0x40 }, { CR24, 0x20 },
110 { CR26, 0x11 }, { CR28, 0x3e }, { CR29, 0x00 },
111 { CR44, 0x33 },
112 /* This value is different for 7230 (was: 0x2a) */
113 { CR106, 0x22 },
114 { CR107, 0x1a }, { CR109, 0x09 }, { CR110, 0x27 },
115 { CR111, 0x2b }, { CR112, 0x2b }, { CR119, 0x0a },
116 /* This happened further down in AL2230,
117 * and the value changed (was: 0xe0) */
118 { CR122, 0xfc },
119 { CR10, 0x89 },
120 /* for newest (3rd cut) AL2300 */
121 { CR17, 0x28 },
122 { CR26, 0x93 }, { CR34, 0x30 },
123 /* for newest (3rd cut) AL2300 */
124 { CR35, 0x3e },
125 { CR41, 0x24 }, { CR44, 0x32 },
126 /* for newest (3rd cut) AL2300 */
127 { CR46, 0x96 },
128 { CR47, 0x1e }, { CR79, 0x58 }, { CR80, 0x30 },
129 { CR81, 0x30 }, { CR87, 0x0a }, { CR89, 0x04 },
130 { CR92, 0x0a }, { CR99, 0x28 },
131 /* This value is different for 7230 (was: 0x00) */
132 { CR100, 0x02 },
133 { CR101, 0x13 }, { CR102, 0x27 },
134 /* This value is different for 7230 (was: 0x24) */
135 { CR106, 0x22 },
136 /* This value is different for 7230 (was: 0x2a) */
137 { CR107, 0x3f },
138 { CR109, 0x09 },
139 /* This value is different for 7230 (was: 0x13) */
140 { CR110, 0x1f },
141 { CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 },
142 { CR114, 0x27 },
143 /* for newest (3rd cut) AL2300 */
144 { CR115, 0x24 },
145 /* This value is different for 7230 (was: 0x24) */
146 { CR116, 0x3f },
147 /* This value is different for 7230 (was: 0xf4) */
148 { CR117, 0xfa },
149 { CR118, 0xfc }, { CR119, 0x10 }, { CR120, 0x4f },
150 { CR121, 0x77 }, { CR137, 0x88 },
151 /* This one is 7230-specific */
152 { CR138, 0xa8 },
153 /* This value is different for 7230 (was: 0xff) */
154 { CR252, 0x34 },
155 /* This value is different for 7230 (was: 0xff) */
156 { CR253, 0x34 },
157
158 /* PLL_OFF */
159 { CR251, 0x2f },
160 };
161
162 static const struct zd_ioreq16 ioreqs_2[] = {
Daniel Drakeba528c42007-04-07 16:00:30 +0100163 { CR251, 0x3f }, /* PLL_ON */
Daniel Drakeec62bd92006-08-12 17:59:46 +0100164 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
Daniel Drakeba528c42007-04-07 16:00:30 +0100165 { CR38, 0x38 }, { CR136, 0xdf },
Daniel Drakeec62bd92006-08-12 17:59:46 +0100166 };
167
168 r = zd_iowrite16a_locked(chip, ioreqs_1, ARRAY_SIZE(ioreqs_1));
169 if (r)
170 return r;
171
Daniel Drakeba528c42007-04-07 16:00:30 +0100172 r = zd_rfwritev_cr_locked(chip, chan_rv[0], ARRAY_SIZE(chan_rv[0]));
Daniel Drakeec62bd92006-08-12 17:59:46 +0100173 if (r)
174 return r;
175
Daniel Drakeba528c42007-04-07 16:00:30 +0100176 r = zd_rfwritev_cr_locked(chip, std_rv, ARRAY_SIZE(std_rv));
177 if (r)
178 return r;
Daniel Drakeec62bd92006-08-12 17:59:46 +0100179
Daniel Drakeba528c42007-04-07 16:00:30 +0100180 r = zd_rfwritev_cr_locked(chip, rv_init1, ARRAY_SIZE(rv_init1));
Daniel Drakeec62bd92006-08-12 17:59:46 +0100181 if (r)
182 return r;
183
184 r = zd_iowrite16a_locked(chip, ioreqs_2, ARRAY_SIZE(ioreqs_2));
185 if (r)
186 return r;
187
Daniel Drakeba528c42007-04-07 16:00:30 +0100188 r = zd_rfwritev_cr_locked(chip, rv_init2, ARRAY_SIZE(rv_init2));
Daniel Drakeec62bd92006-08-12 17:59:46 +0100189 if (r)
190 return r;
191
192 r = zd_iowrite16_locked(chip, 0x06, CR203);
193 if (r)
194 return r;
195 r = zd_iowrite16_locked(chip, 0x80, CR240);
196 if (r)
197 return r;
198
199 return 0;
200}
201
Daniel Drakeba528c42007-04-07 16:00:30 +0100202static int zd1211b_al7230b_init_hw(struct zd_rf *rf)
Daniel Drakeec62bd92006-08-12 17:59:46 +0100203{
Daniel Drakeba528c42007-04-07 16:00:30 +0100204 int r;
Daniel Drakeec62bd92006-08-12 17:59:46 +0100205 struct zd_chip *chip = zd_rf_to_chip(rf);
206
Daniel Draked2d7c052007-03-26 00:59:18 +0100207 static const struct zd_ioreq16 ioreqs_1[] = {
Daniel Drakeba528c42007-04-07 16:00:30 +0100208 { CR240, 0x57 }, { CR9, 0x9 },
209 { },
210 { CR10, 0x8b }, { CR15, 0x20 },
211 { CR17, 0x2B }, /* for newest (3rd cut) AL2230 */
212 { CR20, 0x10 }, /* 4N25->Stone Request */
213 { CR23, 0x40 }, { CR24, 0x20 }, { CR26, 0x93 },
214 { CR28, 0x3e }, { CR29, 0x00 },
215 { CR33, 0x28 }, /* 5613 */
216 { CR34, 0x30 },
217 { CR35, 0x3e }, /* for newest (3rd cut) AL2230 */
218 { CR41, 0x24 }, { CR44, 0x32 },
219 { CR46, 0x99 }, /* for newest (3rd cut) AL2230 */
220 { CR47, 0x1e },
221
222 /* ZD1215 5610 */
223 { CR48, 0x00 }, { CR49, 0x00 }, { CR51, 0x01 },
224 { CR52, 0x80 }, { CR53, 0x7e }, { CR65, 0x00 },
225 { CR66, 0x00 }, { CR67, 0x00 }, { CR68, 0x00 },
226 { CR69, 0x28 },
227
228 { CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 },
229 { CR87, 0x0A }, { CR89, 0x04 },
230 { CR90, 0x58 }, /* 5112 */
231 { CR91, 0x00 }, /* 5613 */
232 { CR92, 0x0a },
233 { CR98, 0x8d }, /* 4804, for 1212 new algorithm */
234 { CR99, 0x00 }, { CR100, 0x02 }, { CR101, 0x13 },
235 { CR102, 0x27 },
236 { CR106, 0x20 }, /* change to 0x24 for AL7230B */
237 { CR109, 0x13 }, /* 4804, for 1212 new algorithm */
238 { CR112, 0x1f },
239 };
240
241 static const struct zd_ioreq16 ioreqs_new_phy[] = {
242 { CR107, 0x28 },
243 { CR110, 0x1f }, /* 5127, 0x13->0x1f */
244 { CR111, 0x1f }, /* 0x13 to 0x1f for AL7230B */
245 { CR116, 0x2a }, { CR118, 0xfa }, { CR119, 0x12 },
246 { CR121, 0x6c }, /* 5613 */
247 };
248
249 static const struct zd_ioreq16 ioreqs_old_phy[] = {
250 { CR107, 0x24 },
251 { CR110, 0x13 }, /* 5127, 0x13->0x1f */
252 { CR111, 0x13 }, /* 0x13 to 0x1f for AL7230B */
253 { CR116, 0x24 }, { CR118, 0xfc }, { CR119, 0x11 },
254 { CR121, 0x6a }, /* 5613 */
255 };
256
257 static const struct zd_ioreq16 ioreqs_2[] = {
258 { CR113, 0x27 }, { CR114, 0x27 }, { CR115, 0x24 },
259 { CR117, 0xfa }, { CR120, 0x4f },
260 { CR122, 0xfc }, /* E0->FCh at 4901 */
261 { CR123, 0x57 }, /* 5613 */
262 { CR125, 0xad }, /* 4804, for 1212 new algorithm */
263 { CR126, 0x6c }, /* 5613 */
264 { CR127, 0x03 }, /* 4804, for 1212 new algorithm */
265 { CR130, 0x10 },
266 { CR131, 0x00 }, /* 5112 */
267 { CR137, 0x50 }, /* 5613 */
268 { CR138, 0xa8 }, /* 5112 */
269 { CR144, 0xac }, /* 5613 */
270 { CR148, 0x40 }, /* 5112 */
271 { CR149, 0x40 }, /* 4O07, 50->40 */
272 { CR150, 0x1a }, /* 5112, 0C->1A */
273 { CR252, 0x34 }, { CR253, 0x34 },
274 { CR251, 0x2f }, /* PLL_OFF */
275 };
276
277 static const struct zd_ioreq16 ioreqs_3[] = {
278 { CR251, 0x7f }, /* PLL_ON */
Daniel Drakeec62bd92006-08-12 17:59:46 +0100279 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
280 { CR38, 0x38 }, { CR136, 0xdf },
281 };
282
Daniel Drakeba528c42007-04-07 16:00:30 +0100283 r = zd_iowrite16a_locked(chip, ioreqs_1, ARRAY_SIZE(ioreqs_1));
284 if (r)
285 return r;
286
287 if (chip->new_phy_layout)
288 r = zd_iowrite16a_locked(chip, ioreqs_new_phy,
289 ARRAY_SIZE(ioreqs_new_phy));
290 else
291 r = zd_iowrite16a_locked(chip, ioreqs_old_phy,
292 ARRAY_SIZE(ioreqs_old_phy));
293 if (r)
294 return r;
295
296 r = zd_iowrite16a_locked(chip, ioreqs_2, ARRAY_SIZE(ioreqs_2));
297 if (r)
298 return r;
299
300 r = zd_rfwritev_cr_locked(chip, chan_rv[0], ARRAY_SIZE(chan_rv[0]));
301 if (r)
302 return r;
303
304 r = zd_rfwritev_cr_locked(chip, std_rv, ARRAY_SIZE(std_rv));
305 if (r)
306 return r;
307
308 r = zd_rfwritev_cr_locked(chip, rv_init1, ARRAY_SIZE(rv_init1));
309 if (r)
310 return r;
311
312 r = zd_iowrite16a_locked(chip, ioreqs_3, ARRAY_SIZE(ioreqs_3));
313 if (r)
314 return r;
315
316 r = zd_rfwritev_cr_locked(chip, rv_init2, ARRAY_SIZE(rv_init2));
317 if (r)
318 return r;
319
320 return zd1211b_al7230b_finalize(chip);
321}
322
323static int zd1211_al7230b_set_channel(struct zd_rf *rf, u8 channel)
324{
325 int r;
326 const u32 *rv = chan_rv[channel-1];
327 struct zd_chip *chip = zd_rf_to_chip(rf);
328
329 static const struct zd_ioreq16 ioreqs[] = {
Daniel Drakeec62bd92006-08-12 17:59:46 +0100330 /* PLL_ON */
331 { CR251, 0x3f },
332 { CR203, 0x06 }, { CR240, 0x08 },
333 };
334
335 r = zd_iowrite16_locked(chip, 0x57, CR240);
336 if (r)
337 return r;
338
339 /* PLL_OFF */
340 r = zd_iowrite16_locked(chip, 0x2f, CR251);
341 if (r)
342 return r;
343
Daniel Drakeba528c42007-04-07 16:00:30 +0100344 r = zd_rfwritev_cr_locked(chip, std_rv, ARRAY_SIZE(std_rv));
345 if (r)
346 return r;
Daniel Drakeec62bd92006-08-12 17:59:46 +0100347
348 r = zd_rfwrite_cr_locked(chip, 0x3c9000);
349 if (r)
350 return r;
351 r = zd_rfwrite_cr_locked(chip, 0xf15d58);
352 if (r)
353 return r;
354
Daniel Drakeba528c42007-04-07 16:00:30 +0100355 r = zd_iowrite16a_locked(chip, ioreqs_sw, ARRAY_SIZE(ioreqs_sw));
Daniel Drakeec62bd92006-08-12 17:59:46 +0100356 if (r)
357 return r;
358
Daniel Drakeba528c42007-04-07 16:00:30 +0100359 r = zd_rfwritev_cr_locked(chip, rv, 2);
360 if (r)
361 return r;
Daniel Drakeec62bd92006-08-12 17:59:46 +0100362
363 r = zd_rfwrite_cr_locked(chip, 0x3c9000);
364 if (r)
365 return r;
366
Daniel Drakeba528c42007-04-07 16:00:30 +0100367 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
Daniel Drakeec62bd92006-08-12 17:59:46 +0100368}
369
Daniel Drakeba528c42007-04-07 16:00:30 +0100370static int zd1211b_al7230b_set_channel(struct zd_rf *rf, u8 channel)
371{
372 int r;
373 const u32 *rv = chan_rv[channel-1];
374 struct zd_chip *chip = zd_rf_to_chip(rf);
375
376 r = zd_iowrite16_locked(chip, 0x57, CR240);
377 if (r)
378 return r;
379 r = zd_iowrite16_locked(chip, 0xe4, CR9);
380 if (r)
381 return r;
382
383 /* PLL_OFF */
384 r = zd_iowrite16_locked(chip, 0x2f, CR251);
385 if (r)
386 return r;
387 r = zd_rfwritev_cr_locked(chip, std_rv, ARRAY_SIZE(std_rv));
388 if (r)
389 return r;
390
391 r = zd_rfwrite_cr_locked(chip, 0x3c9000);
392 if (r)
393 return r;
394 r = zd_rfwrite_cr_locked(chip, 0xf15d58);
395 if (r)
396 return r;
397
398 r = zd_iowrite16a_locked(chip, ioreqs_sw, ARRAY_SIZE(ioreqs_sw));
399 if (r)
400 return r;
401
402 r = zd_rfwritev_cr_locked(chip, rv, 2);
403 if (r)
404 return r;
405
406 r = zd_rfwrite_cr_locked(chip, 0x3c9000);
407 if (r)
408 return r;
409
410 r = zd_iowrite16_locked(chip, 0x7f, CR251);
411 if (r)
412 return r;
413
414 return zd1211b_al7230b_finalize(chip);
415}
416
417static int zd1211_al7230b_switch_radio_on(struct zd_rf *rf)
Daniel Drakeec62bd92006-08-12 17:59:46 +0100418{
419 struct zd_chip *chip = zd_rf_to_chip(rf);
420 static const struct zd_ioreq16 ioreqs[] = {
421 { CR11, 0x00 },
422 { CR251, 0x3f },
423 };
424
425 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
426}
427
Daniel Drakeba528c42007-04-07 16:00:30 +0100428static int zd1211b_al7230b_switch_radio_on(struct zd_rf *rf)
429{
430 struct zd_chip *chip = zd_rf_to_chip(rf);
431 static const struct zd_ioreq16 ioreqs[] = {
432 { CR11, 0x00 },
433 { CR251, 0x7f },
434 };
435
436 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
437}
438
Daniel Drakeec62bd92006-08-12 17:59:46 +0100439static int al7230b_switch_radio_off(struct zd_rf *rf)
440{
441 struct zd_chip *chip = zd_rf_to_chip(rf);
442 static const struct zd_ioreq16 ioreqs[] = {
443 { CR11, 0x04 },
444 { CR251, 0x2f },
445 };
446
447 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
448}
449
Daniel Drakeba528c42007-04-07 16:00:30 +0100450/* ZD1211B+AL7230B 6m band edge patching differs slightly from other
451 * configurations */
452static int zd1211b_al7230b_patch_6m(struct zd_rf *rf, u8 channel)
453{
454 struct zd_chip *chip = zd_rf_to_chip(rf);
455 struct zd_ioreq16 ioreqs[] = {
456 { CR128, 0x14 }, { CR129, 0x12 },
457 };
458
459 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
460 if (channel == 1) {
461 ioreqs[0].value = 0x0e;
462 ioreqs[1].value = 0x10;
463 } else if (channel == 11) {
464 ioreqs[0].value = 0x10;
465 ioreqs[1].value = 0x10;
466 }
467
468 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
469 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
470}
471
Daniel Drakeec62bd92006-08-12 17:59:46 +0100472int zd_rf_init_al7230b(struct zd_rf *rf)
473{
474 struct zd_chip *chip = zd_rf_to_chip(rf);
475
476 if (chip->is_zd1211b) {
Daniel Drakeba528c42007-04-07 16:00:30 +0100477 rf->init_hw = zd1211b_al7230b_init_hw;
478 rf->switch_radio_on = zd1211b_al7230b_switch_radio_on;
479 rf->set_channel = zd1211b_al7230b_set_channel;
480 rf->patch_6m_band_edge = zd1211b_al7230b_patch_6m;
481 } else {
482 rf->init_hw = zd1211_al7230b_init_hw;
483 rf->switch_radio_on = zd1211_al7230b_switch_radio_on;
484 rf->set_channel = zd1211_al7230b_set_channel;
485 rf->patch_6m_band_edge = zd_rf_generic_patch_6m;
Daniel Drakeaaf83d42007-05-24 01:07:15 +0100486 rf->patch_cck_gain = 1;
Daniel Drakeec62bd92006-08-12 17:59:46 +0100487 }
488
Daniel Drakeec62bd92006-08-12 17:59:46 +0100489 rf->switch_radio_off = al7230b_switch_radio_off;
Daniel Drakeba528c42007-04-07 16:00:30 +0100490
Daniel Drakeec62bd92006-08-12 17:59:46 +0100491 return 0;
492}