Uwe Bugla | 1589a99 | 2009-03-29 07:46:58 -0300 | [diff] [blame] | 1 | /* Linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III |
Patrick Boettcher | 2819639b | 2005-07-07 17:57:48 -0700 | [diff] [blame] | 2 | * register descriptions |
Uwe Bugla | 1589a99 | 2009-03-29 07:46:58 -0300 | [diff] [blame] | 3 | * see flexcop.c for copyright information |
Patrick Boettcher | 2819639b | 2005-07-07 17:57:48 -0700 | [diff] [blame] | 4 | */ |
Patrick Boettcher | 2819639b | 2005-07-07 17:57:48 -0700 | [diff] [blame] | 5 | /* This file is automatically generated, do not edit things here. */ |
| 6 | #ifndef __FLEXCOP_IBI_VALUE_INCLUDED__ |
| 7 | #define __FLEXCOP_IBI_VALUE_INCLUDED__ |
| 8 | |
| 9 | typedef union { |
| 10 | u32 raw; |
| 11 | |
| 12 | struct { |
| 13 | u32 dma_address0 :30; |
| 14 | u32 dma_0No_update : 1; |
| 15 | u32 dma_0start : 1; |
| 16 | } dma_0x0; |
| 17 | |
| 18 | struct { |
| 19 | u32 dma_addr_size :24; |
| 20 | u32 DMA_maxpackets : 8; |
| 21 | } dma_0x4_remap; |
| 22 | |
| 23 | struct { |
| 24 | u32 dma_addr_size :24; |
| 25 | u32 unused : 1; |
| 26 | u32 dma1timer : 7; |
| 27 | } dma_0x4_read; |
| 28 | |
| 29 | struct { |
| 30 | u32 dma_addr_size :24; |
| 31 | u32 dmatimer : 7; |
| 32 | u32 unused : 1; |
| 33 | } dma_0x4_write; |
| 34 | |
| 35 | struct { |
| 36 | u32 dma_cur_addr :30; |
| 37 | u32 unused : 2; |
| 38 | } dma_0x8; |
| 39 | |
| 40 | struct { |
| 41 | u32 dma_address1 :30; |
| 42 | u32 remap_enable : 1; |
| 43 | u32 dma_1start : 1; |
| 44 | } dma_0xc; |
| 45 | |
| 46 | struct { |
| 47 | u32 st_done : 1; |
| 48 | u32 no_base_addr_ack_error : 1; |
| 49 | u32 twoWS_port_reg : 2; |
| 50 | u32 total_bytes : 2; |
| 51 | u32 twoWS_rw : 1; |
| 52 | u32 working_start : 1; |
| 53 | u32 data1_reg : 8; |
| 54 | u32 baseaddr : 8; |
| 55 | u32 reserved1 : 1; |
| 56 | u32 chipaddr : 7; |
| 57 | } tw_sm_c_100; |
| 58 | |
| 59 | struct { |
| 60 | u32 unused : 6; |
| 61 | u32 force_stop : 1; |
| 62 | u32 exlicit_stops : 1; |
| 63 | u32 data4_reg : 8; |
| 64 | u32 data3_reg : 8; |
| 65 | u32 data2_reg : 8; |
| 66 | } tw_sm_c_104; |
| 67 | |
| 68 | struct { |
| 69 | u32 reserved2 :19; |
| 70 | u32 tlo1 : 5; |
| 71 | u32 reserved1 : 2; |
| 72 | u32 thi1 : 6; |
| 73 | } tw_sm_c_108; |
| 74 | |
| 75 | struct { |
| 76 | u32 reserved2 :19; |
| 77 | u32 tlo1 : 5; |
| 78 | u32 reserved1 : 2; |
| 79 | u32 thi1 : 6; |
| 80 | } tw_sm_c_10c; |
| 81 | |
| 82 | struct { |
| 83 | u32 reserved2 :19; |
| 84 | u32 tlo1 : 5; |
| 85 | u32 reserved1 : 2; |
| 86 | u32 thi1 : 6; |
| 87 | } tw_sm_c_110; |
| 88 | |
| 89 | struct { |
| 90 | u32 LNB_CTLPrescaler_sig : 2; |
| 91 | u32 LNB_CTLLowCount_sig :15; |
| 92 | u32 LNB_CTLHighCount_sig :15; |
| 93 | } lnb_switch_freq_200; |
| 94 | |
| 95 | struct { |
| 96 | u32 Rev_N_sig_reserved2 : 1; |
| 97 | u32 Rev_N_sig_caps : 1; |
| 98 | u32 Rev_N_sig_reserved1 : 2; |
| 99 | u32 Rev_N_sig_revision_hi : 4; |
| 100 | u32 reserved :20; |
| 101 | u32 Per_reset_sig : 1; |
| 102 | u32 LNB_L_H_sig : 1; |
| 103 | u32 ACPI3_sig : 1; |
| 104 | u32 ACPI1_sig : 1; |
| 105 | } misc_204; |
| 106 | |
| 107 | struct { |
| 108 | u32 unused : 9; |
| 109 | u32 Mailbox_from_V8_Enable_sig : 1; |
| 110 | u32 DMA2_Size_IRQ_Enable_sig : 1; |
| 111 | u32 DMA1_Size_IRQ_Enable_sig : 1; |
| 112 | u32 DMA2_Timer_Enable_sig : 1; |
| 113 | u32 DMA2_IRQ_Enable_sig : 1; |
| 114 | u32 DMA1_Timer_Enable_sig : 1; |
| 115 | u32 DMA1_IRQ_Enable_sig : 1; |
| 116 | u32 Rcv_Data_sig : 1; |
| 117 | u32 MAC_filter_Mode_sig : 1; |
| 118 | u32 Multi2_Enable_sig : 1; |
| 119 | u32 Per_CA_Enable_sig : 1; |
| 120 | u32 SMC_Enable_sig : 1; |
| 121 | u32 CA_Enable_sig : 1; |
| 122 | u32 WAN_CA_Enable_sig : 1; |
| 123 | u32 WAN_Enable_sig : 1; |
| 124 | u32 Mask_filter_sig : 1; |
| 125 | u32 Null_filter_sig : 1; |
| 126 | u32 ECM_filter_sig : 1; |
| 127 | u32 EMM_filter_sig : 1; |
| 128 | u32 PMT_filter_sig : 1; |
| 129 | u32 PCR_filter_sig : 1; |
| 130 | u32 Stream2_filter_sig : 1; |
| 131 | u32 Stream1_filter_sig : 1; |
| 132 | } ctrl_208; |
| 133 | |
| 134 | struct { |
| 135 | u32 reserved :21; |
| 136 | u32 Transport_Error : 1; |
| 137 | u32 LLC_SNAP_FLAG_set : 1; |
| 138 | u32 Continuity_error_flag : 1; |
| 139 | u32 Data_receiver_error : 1; |
| 140 | u32 Mailbox_from_V8_Status_sig : 1; |
| 141 | u32 DMA2_Size_IRQ_Status : 1; |
| 142 | u32 DMA1_Size_IRQ_Status : 1; |
| 143 | u32 DMA2_Timer_Status : 1; |
| 144 | u32 DMA2_IRQ_Status : 1; |
| 145 | u32 DMA1_Timer_Status : 1; |
| 146 | u32 DMA1_IRQ_Status : 1; |
| 147 | } irq_20c; |
| 148 | |
| 149 | struct { |
| 150 | u32 Special_controls :16; |
| 151 | u32 Block_reset_enable : 8; |
Patrick Boettcher | 64221be | 2005-07-07 17:57:49 -0700 | [diff] [blame] | 152 | u32 reset_block_700 : 1; |
| 153 | u32 reset_block_600 : 1; |
| 154 | u32 reset_block_500 : 1; |
| 155 | u32 reset_block_400 : 1; |
| 156 | u32 reset_block_300 : 1; |
| 157 | u32 reset_block_200 : 1; |
| 158 | u32 reset_block_100 : 1; |
| 159 | u32 reset_block_000 : 1; |
Patrick Boettcher | 2819639b | 2005-07-07 17:57:48 -0700 | [diff] [blame] | 160 | } sw_reset_210; |
| 161 | |
| 162 | struct { |
| 163 | u32 unused2 :20; |
| 164 | u32 polarity_PS_ERR_sig : 1; |
| 165 | u32 polarity_PS_SYNC_sig : 1; |
| 166 | u32 polarity_PS_VALID_sig : 1; |
| 167 | u32 polarity_PS_CLK_sig : 1; |
| 168 | u32 unused1 : 3; |
| 169 | u32 s2p_sel_sig : 1; |
| 170 | u32 section_pkg_enable_sig : 1; |
| 171 | u32 halt_V8_sig : 1; |
| 172 | u32 v2WS_oe_sig : 1; |
| 173 | u32 vuart_oe_sig : 1; |
| 174 | } misc_214; |
| 175 | |
| 176 | struct { |
| 177 | u32 Mailbox_from_V8 :32; |
| 178 | } mbox_v8_to_host_218; |
| 179 | |
| 180 | struct { |
| 181 | u32 sysramaccess_busmuster : 1; |
| 182 | u32 sysramaccess_write : 1; |
| 183 | u32 unused : 7; |
| 184 | u32 sysramaccess_addr :15; |
| 185 | u32 sysramaccess_data : 8; |
| 186 | } mbox_host_to_v8_21c; |
| 187 | |
| 188 | struct { |
| 189 | u32 debug_fifo_problem : 1; |
| 190 | u32 debug_flag_write_status00 : 1; |
| 191 | u32 Stream2_trans : 1; |
| 192 | u32 Stream2_PID :13; |
| 193 | u32 debug_flag_pid_saved : 1; |
| 194 | u32 MAC_Multicast_filter : 1; |
| 195 | u32 Stream1_trans : 1; |
| 196 | u32 Stream1_PID :13; |
| 197 | } pid_filter_300; |
| 198 | |
| 199 | struct { |
| 200 | u32 reserved : 2; |
| 201 | u32 PMT_trans : 1; |
| 202 | u32 PMT_PID :13; |
| 203 | u32 debug_overrun2 : 1; |
| 204 | u32 debug_overrun3 : 1; |
| 205 | u32 PCR_trans : 1; |
| 206 | u32 PCR_PID :13; |
| 207 | } pid_filter_304; |
| 208 | |
| 209 | struct { |
| 210 | u32 reserved : 2; |
| 211 | u32 ECM_trans : 1; |
| 212 | u32 ECM_PID :13; |
| 213 | u32 EMM_filter_6 : 1; |
| 214 | u32 EMM_filter_4 : 1; |
| 215 | u32 EMM_trans : 1; |
| 216 | u32 EMM_PID :13; |
| 217 | } pid_filter_308; |
| 218 | |
| 219 | struct { |
| 220 | u32 unused2 : 3; |
| 221 | u32 Group_mask :13; |
| 222 | u32 unused1 : 2; |
| 223 | u32 Group_trans : 1; |
| 224 | u32 Group_PID :13; |
| 225 | } pid_filter_30c_ext_ind_0_7; |
| 226 | |
| 227 | struct { |
| 228 | u32 unused :15; |
| 229 | u32 net_master_read :17; |
| 230 | } pid_filter_30c_ext_ind_1; |
| 231 | |
| 232 | struct { |
| 233 | u32 unused :15; |
| 234 | u32 net_master_write :17; |
| 235 | } pid_filter_30c_ext_ind_2; |
| 236 | |
| 237 | struct { |
| 238 | u32 unused :15; |
| 239 | u32 next_net_master_write :17; |
| 240 | } pid_filter_30c_ext_ind_3; |
| 241 | |
| 242 | struct { |
| 243 | u32 reserved2 : 5; |
| 244 | u32 stack_read :10; |
| 245 | u32 reserved1 : 6; |
| 246 | u32 state_write :10; |
| 247 | u32 unused1 : 1; |
| 248 | } pid_filter_30c_ext_ind_4; |
| 249 | |
| 250 | struct { |
| 251 | u32 unused :22; |
| 252 | u32 stack_cnt :10; |
| 253 | } pid_filter_30c_ext_ind_5; |
| 254 | |
| 255 | struct { |
| 256 | u32 unused : 4; |
| 257 | u32 data_size_reg :12; |
| 258 | u32 write_status4 : 2; |
| 259 | u32 write_status1 : 2; |
| 260 | u32 pid_fsm_save_reg300 : 2; |
| 261 | u32 pid_fsm_save_reg4 : 2; |
| 262 | u32 pid_fsm_save_reg3 : 2; |
| 263 | u32 pid_fsm_save_reg2 : 2; |
| 264 | u32 pid_fsm_save_reg1 : 2; |
| 265 | u32 pid_fsm_save_reg0 : 2; |
| 266 | } pid_filter_30c_ext_ind_6; |
| 267 | |
| 268 | struct { |
| 269 | u32 unused :22; |
| 270 | u32 pass_alltables : 1; |
| 271 | u32 AB_select : 1; |
| 272 | u32 extra_index_reg : 3; |
| 273 | u32 index_reg : 5; |
| 274 | } index_reg_310; |
| 275 | |
| 276 | struct { |
| 277 | u32 reserved :17; |
| 278 | u32 PID_enable_bit : 1; |
| 279 | u32 PID_trans : 1; |
| 280 | u32 PID :13; |
| 281 | } pid_n_reg_314; |
| 282 | |
| 283 | struct { |
| 284 | u32 reserved : 6; |
| 285 | u32 HighAB_bit : 1; |
| 286 | u32 Enable_bit : 1; |
| 287 | u32 A6_byte : 8; |
| 288 | u32 A5_byte : 8; |
| 289 | u32 A4_byte : 8; |
| 290 | } mac_low_reg_318; |
| 291 | |
| 292 | struct { |
| 293 | u32 reserved : 8; |
| 294 | u32 A3_byte : 8; |
| 295 | u32 A2_byte : 8; |
| 296 | u32 A1_byte : 8; |
| 297 | } mac_high_reg_31c; |
| 298 | |
| 299 | struct { |
| 300 | u32 data_Tag_ID :16; |
| 301 | u32 reserved :16; |
| 302 | } data_tag_400; |
| 303 | |
| 304 | struct { |
| 305 | u32 Card_IDbyte3 : 8; |
| 306 | u32 Card_IDbyte4 : 8; |
| 307 | u32 Card_IDbyte5 : 8; |
| 308 | u32 Card_IDbyte6 : 8; |
| 309 | } card_id_408; |
| 310 | |
| 311 | struct { |
| 312 | u32 Card_IDbyte1 : 8; |
| 313 | u32 Card_IDbyte2 : 8; |
| 314 | } card_id_40c; |
| 315 | |
| 316 | struct { |
| 317 | u32 MAC6 : 8; |
| 318 | u32 MAC3 : 8; |
| 319 | u32 MAC2 : 8; |
| 320 | u32 MAC1 : 8; |
| 321 | } mac_address_418; |
| 322 | |
| 323 | struct { |
| 324 | u32 reserved :16; |
| 325 | u32 MAC8 : 8; |
| 326 | u32 MAC7 : 8; |
| 327 | } mac_address_41c; |
| 328 | |
| 329 | struct { |
| 330 | u32 reserved :21; |
| 331 | u32 txbuffempty : 1; |
| 332 | u32 ReceiveByteFrameError : 1; |
| 333 | u32 ReceiveDataReady : 1; |
| 334 | u32 transmitter_data_byte : 8; |
| 335 | } ci_600; |
| 336 | |
| 337 | struct { |
| 338 | u32 pi_component_reg : 3; |
| 339 | u32 pi_rw : 1; |
| 340 | u32 pi_ha :20; |
| 341 | u32 pi_d : 8; |
| 342 | } pi_604; |
| 343 | |
| 344 | struct { |
| 345 | u32 pi_busy_n : 1; |
| 346 | u32 pi_wait_n : 1; |
| 347 | u32 pi_timeout_status : 1; |
| 348 | u32 pi_CiMax_IRQ_n : 1; |
| 349 | u32 config_cclk : 1; |
| 350 | u32 config_cs_n : 1; |
| 351 | u32 config_wr_n : 1; |
| 352 | u32 config_Prog_n : 1; |
| 353 | u32 config_Init_stat : 1; |
| 354 | u32 config_Done_stat : 1; |
| 355 | u32 pcmcia_b_mod_pwr_n : 1; |
| 356 | u32 pcmcia_a_mod_pwr_n : 1; |
| 357 | u32 reserved : 3; |
| 358 | u32 Timer_addr : 5; |
| 359 | u32 unused : 1; |
| 360 | u32 timer_data : 7; |
| 361 | u32 Timer_Load_req : 1; |
| 362 | u32 Timer_Read_req : 1; |
| 363 | u32 oncecycle_read : 1; |
| 364 | u32 serialReset : 1; |
| 365 | } pi_608; |
| 366 | |
| 367 | struct { |
| 368 | u32 reserved : 6; |
| 369 | u32 rw_flag : 1; |
| 370 | u32 dvb_en : 1; |
| 371 | u32 key_array_row : 5; |
| 372 | u32 key_array_col : 3; |
| 373 | u32 key_code : 2; |
| 374 | u32 key_enable : 1; |
| 375 | u32 PID :13; |
| 376 | } dvb_reg_60c; |
| 377 | |
| 378 | struct { |
| 379 | u32 start_sram_ibi : 1; |
| 380 | u32 reserved2 : 1; |
| 381 | u32 ce_pin_reg : 1; |
| 382 | u32 oe_pin_reg : 1; |
| 383 | u32 reserved1 : 3; |
| 384 | u32 sc_xfer_bit : 1; |
| 385 | u32 sram_data : 8; |
| 386 | u32 sram_rw : 1; |
| 387 | u32 sram_addr :15; |
| 388 | } sram_ctrl_reg_700; |
| 389 | |
| 390 | struct { |
| 391 | u32 net_addr_write :16; |
| 392 | u32 net_addr_read :16; |
| 393 | } net_buf_reg_704; |
| 394 | |
| 395 | struct { |
| 396 | u32 cai_cnt : 4; |
| 397 | u32 reserved2 : 6; |
| 398 | u32 cai_write :11; |
| 399 | u32 reserved1 : 5; |
| 400 | u32 cai_read :11; |
| 401 | } cai_buf_reg_708; |
| 402 | |
| 403 | struct { |
| 404 | u32 cao_cnt : 4; |
| 405 | u32 reserved2 : 6; |
| 406 | u32 cap_write :11; |
| 407 | u32 reserved1 : 5; |
| 408 | u32 cao_read :11; |
| 409 | } cao_buf_reg_70c; |
| 410 | |
| 411 | struct { |
| 412 | u32 media_cnt : 4; |
| 413 | u32 reserved2 : 6; |
| 414 | u32 media_write :11; |
| 415 | u32 reserved1 : 5; |
| 416 | u32 media_read :11; |
| 417 | } media_buf_reg_710; |
| 418 | |
| 419 | struct { |
| 420 | u32 reserved :17; |
| 421 | u32 ctrl_maximumfill : 1; |
| 422 | u32 ctrl_sramdma : 1; |
| 423 | u32 ctrl_usb_wan : 1; |
| 424 | u32 cao_ovflow_error : 1; |
| 425 | u32 cai_ovflow_error : 1; |
| 426 | u32 media_ovflow_error : 1; |
| 427 | u32 net_ovflow_error : 1; |
| 428 | u32 MEDIA_Dest : 2; |
| 429 | u32 CAO_Dest : 2; |
| 430 | u32 CAI_Dest : 2; |
| 431 | u32 NET_Dest : 2; |
| 432 | } sram_dest_reg_714; |
| 433 | |
| 434 | struct { |
| 435 | u32 reserved3 :11; |
| 436 | u32 net_addr_write : 1; |
| 437 | u32 reserved2 : 3; |
| 438 | u32 net_addr_read : 1; |
| 439 | u32 reserved1 : 4; |
| 440 | u32 net_cnt :12; |
| 441 | } net_buf_reg_718; |
| 442 | |
| 443 | struct { |
| 444 | u32 reserved3 : 4; |
| 445 | u32 wan_pkt_frame : 4; |
| 446 | u32 reserved2 : 4; |
| 447 | u32 sram_memmap : 2; |
| 448 | u32 sram_chip : 2; |
| 449 | u32 wan_wait_state : 8; |
| 450 | u32 reserved1 : 6; |
| 451 | u32 wan_speed_sig : 2; |
| 452 | } wan_ctrl_reg_71c; |
| 453 | } flexcop_ibi_value; |
| 454 | |
| 455 | #endif |