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Ajay Singh Parmar571e3012016-05-16 17:55:52 -07001/*
Padmanabhan Komandurudbd2fb02016-12-02 15:18:49 +05302 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
Ajay Singh Parmar571e3012016-05-16 17:55:52 -07003 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#ifndef _DSI_DISPLAY_H_
16#define _DSI_DISPLAY_H_
17
18#include <linux/types.h>
19#include <linux/bitops.h>
Ajay Singh Parmar48ea4272016-06-27 11:44:34 -070020#include <linux/debugfs.h>
Ajay Singh Parmar571e3012016-05-16 17:55:52 -070021#include <linux/of_device.h>
22#include <drm/drmP.h>
23#include <drm/drm_crtc.h>
24
Clarence Ipa4039322016-07-15 16:23:59 -040025#include "msm_drv.h"
Ajay Singh Parmar571e3012016-05-16 17:55:52 -070026#include "dsi_defs.h"
27#include "dsi_ctrl.h"
28#include "dsi_phy.h"
29#include "dsi_panel.h"
30
31#define MAX_DSI_CTRLS_PER_DISPLAY 2
32
Ajay Singh Parmar62f795b2016-06-10 23:20:23 -070033/*
34 * DSI Validate Mode modifiers
35 * @DSI_VALIDATE_FLAG_ALLOW_ADJUST: Allow mode validation to also do fixup
36 */
37#define DSI_VALIDATE_FLAG_ALLOW_ADJUST 0x1
38
Ajay Singh Parmar571e3012016-05-16 17:55:52 -070039/**
40 * enum dsi_display_type - enumerates DSI display types
41 * @DSI_DISPLAY_SINGLE: A panel connected on a single DSI interface.
42 * @DSI_DISPLAY_EXT_BRIDGE: A bridge is connected between panel and DSI host.
43 * It utilizes a single DSI interface.
44 * @DSI_DISPLAY_SPLIT: A panel that utilizes more than one DSI
45 * interfaces.
46 * @DSI_DISPLAY_SPLIT_EXT_BRIDGE: A bridge is present between panel and DSI
47 * host. It utilizes more than one DSI interface.
48 */
49enum dsi_display_type {
50 DSI_DISPLAY_SINGLE = 0,
51 DSI_DISPLAY_EXT_BRIDGE,
52 DSI_DISPLAY_SPLIT,
53 DSI_DISPLAY_SPLIT_EXT_BRIDGE,
54 DSI_DISPLAY_MAX,
55};
56
57/**
Ajay Singh Parmar571e3012016-05-16 17:55:52 -070058 * struct dsi_display_ctrl - dsi ctrl/phy information for the display
59 * @ctrl: Handle to the DSI controller device.
60 * @ctrl_of_node: pHandle to the DSI controller device.
61 * @dsi_ctrl_idx: DSI controller instance id.
62 * @power_state: Current power state of the DSI controller.
Ajay Singh Parmar571e3012016-05-16 17:55:52 -070063 * @phy: Handle to the DSI PHY device.
64 * @phy_of_node: pHandle to the DSI PHY device.
65 * @phy_enabled: PHY power status.
66 */
67struct dsi_display_ctrl {
68 /* controller info */
69 struct dsi_ctrl *ctrl;
70 struct device_node *ctrl_of_node;
71 u32 dsi_ctrl_idx;
72
73 enum dsi_power_state power_state;
Ajay Singh Parmar571e3012016-05-16 17:55:52 -070074
75 /* phy info */
76 struct msm_dsi_phy *phy;
77 struct device_node *phy_of_node;
78
79 bool phy_enabled;
80};
81
82/**
83 * struct dsi_display_clk_info - dsi display clock source information
84 * @src_clks: Source clocks for DSI display.
85 * @mux_clks: Mux clocks used for DFPS.
86 * @shadow_clks: Used for DFPS.
87 */
88struct dsi_display_clk_info {
89 struct dsi_clk_link_set src_clks;
90 struct dsi_clk_link_set mux_clks;
91 struct dsi_clk_link_set shadow_clks;
92};
93
94/**
95 * struct dsi_display - dsi display information
96 * @pdev: Pointer to platform device.
97 * @drm_dev: DRM device associated with the display.
98 * @name: Name of the display.
99 * @display_type: Display type as defined in device tree.
100 * @list: List pointer.
101 * @is_active: Is display active.
102 * @display_lock: Mutex for dsi_display interface.
103 * @ctrl_count: Number of DSI interfaces required by panel.
104 * @ctrl: Controller information for DSI display.
105 * @panel: Handle to DSI panel.
106 * @panel_of: pHandle to DSI panel.
107 * @type: DSI display type.
108 * @clk_master_idx: The master controller for controlling clocks. This is an
109 * index into the ctrl[MAX_DSI_CTRLS_PER_DISPLAY] array.
110 * @cmd_master_idx: The master controller for sending DSI commands to panel.
111 * @video_master_idx: The master controller for enabling video engine.
112 * @clock_info: Clock sourcing for DSI display.
Padmanabhan Komandurudbd2fb02016-12-02 15:18:49 +0530113 * @config: DSI host configuration information.
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700114 * @lane_map: Lane mapping between DSI host and Panel.
115 * @num_of_modes: Number of modes supported by display.
116 * @is_tpg_enabled: TPG state.
Padmanabhan Komandurudbd2fb02016-12-02 15:18:49 +0530117 * @ulps_enabled: ulps state.
118 * @clamp_enabled: clamp state.
119 * @phy_idle_power_off: PHY power state.
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700120 * @host: DRM MIPI DSI Host.
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700121 * @bridge: Pointer to DRM bridge object.
Lloyd Atkinsone404caf2016-07-13 17:26:45 -0400122 * @cmd_engine_refcount: Reference count enforcing single instance of cmd eng
Padmanabhan Komandurudbd2fb02016-12-02 15:18:49 +0530123 * @clk_mngr: DSI clock manager.
124 * @dsi_clk_handle: DSI clock handle.
125 * @mdp_clk_handle: MDP clock handle.
126 * @root: Debugfs root directory
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700127 */
128struct dsi_display {
129 struct platform_device *pdev;
130 struct drm_device *drm_dev;
131
132 const char *name;
133 const char *display_type;
134 struct list_head list;
135 bool is_active;
136 struct mutex display_lock;
137
138 u32 ctrl_count;
139 struct dsi_display_ctrl ctrl[MAX_DSI_CTRLS_PER_DISPLAY];
140
141 /* panel info */
142 struct dsi_panel *panel;
143 struct device_node *panel_of;
144
145 enum dsi_display_type type;
146 u32 clk_master_idx;
147 u32 cmd_master_idx;
148 u32 video_master_idx;
149
150 struct dsi_display_clk_info clock_info;
151 struct dsi_host_config config;
Padmanabhan Komanduru8ee8ee52016-12-19 12:10:51 +0530152 struct dsi_lane_map lane_map;
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700153 u32 num_of_modes;
154 bool is_tpg_enabled;
Padmanabhan Komandurudbd2fb02016-12-02 15:18:49 +0530155 bool ulps_enabled;
156 bool clamp_enabled;
157 bool phy_idle_power_off;
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700158
159 struct mipi_dsi_host host;
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700160 struct dsi_bridge *bridge;
Ajay Singh Parmaraa9152d2016-05-16 18:02:07 -0700161 u32 cmd_engine_refcount;
Ajay Singh Parmar48ea4272016-06-27 11:44:34 -0700162
Padmanabhan Komandurudbd2fb02016-12-02 15:18:49 +0530163 void *clk_mngr;
164 void *dsi_clk_handle;
165 void *mdp_clk_handle;
166
Ajay Singh Parmar48ea4272016-06-27 11:44:34 -0700167 /* DEBUG FS */
168 struct dentry *root;
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700169};
170
171int dsi_display_dev_probe(struct platform_device *pdev);
172int dsi_display_dev_remove(struct platform_device *pdev);
173
174/**
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700175 * dsi_display_get_num_of_displays() - returns number of display devices
176 * supported.
177 *
178 * Return: number of displays.
179 */
Clarence Ip3649f8b2016-10-31 09:59:44 -0400180int dsi_display_get_num_of_displays(void);
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700181
182/**
Clarence Ipa36c92e2016-07-26 14:33:46 -0400183 * dsi_display_get_active_displays - returns pointers for active display devices
184 * @display_array: Pointer to display array to be filled
185 * @max_display_count: Size of display_array
186 * @Returns: Number of display entries filled
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700187 */
Clarence Ipa36c92e2016-07-26 14:33:46 -0400188int dsi_display_get_active_displays(void **display_array,
189 u32 max_display_count);
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700190
191/**
192 * dsi_display_get_display_by_name()- finds display by name
193 * @index: name of the display.
194 *
195 * Return: handle to the display or error code.
196 */
197struct dsi_display *dsi_display_get_display_by_name(const char *name);
198
199/**
200 * dsi_display_set_active_state() - sets the state of the display
201 * @display: Handle to display.
202 * @is_active: state
203 */
204void dsi_display_set_active_state(struct dsi_display *display, bool is_active);
205
206/**
Clarence Ip40d7d592016-07-15 16:02:26 -0400207 * dsi_display_drm_bridge_init() - initializes DRM bridge object for DSI
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700208 * @display: Handle to the display.
209 * @encoder: Pointer to the encoder object which is connected to the
210 * display.
211 *
212 * Return: error code.
213 */
Clarence Ip40d7d592016-07-15 16:02:26 -0400214int dsi_display_drm_bridge_init(struct dsi_display *display,
215 struct drm_encoder *enc);
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700216
217/**
Clarence Ip40d7d592016-07-15 16:02:26 -0400218 * dsi_display_drm_bridge_deinit() - destroys DRM bridge for the display
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700219 * @display: Handle to the display.
220 *
221 * Return: error code.
222 */
Clarence Ip40d7d592016-07-15 16:02:26 -0400223int dsi_display_drm_bridge_deinit(struct dsi_display *display);
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700224
225/**
226 * dsi_display_get_info() - returns the display properties
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700227 * @info: Pointer to the structure where info is stored.
Clarence Ipa4039322016-07-15 16:23:59 -0400228 * @disp: Handle to the display.
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700229 *
230 * Return: error code.
231 */
Clarence Ipa4039322016-07-15 16:23:59 -0400232int dsi_display_get_info(struct msm_display_info *info, void *disp);
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700233
234/**
235 * dsi_display_get_modes() - get modes supported by display
236 * @display: Handle to display.
237 * @modes; Pointer to array of modes. Memory allocated should be
238 * big enough to store (count * struct dsi_display_mode)
239 * elements. If modes pointer is NULL, number of modes will
240 * be stored in the memory pointed to by count.
241 * @count: If modes is NULL, number of modes will be stored. If
242 * not, mode information will be copied (number of modes
243 * copied will be equal to *count).
244 *
245 * Return: error code.
246 */
247int dsi_display_get_modes(struct dsi_display *display,
248 struct dsi_display_mode *modes,
249 u32 *count);
250
251/**
252 * dsi_display_validate_mode() - validates if mode is supported by display
253 * @display: Handle to display.
254 * @mode: Mode to be validated.
Ajay Singh Parmar62f795b2016-06-10 23:20:23 -0700255 * @flags: Modifier flags.
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700256 *
257 * Return: 0 if supported or error code.
258 */
259int dsi_display_validate_mode(struct dsi_display *display,
Ajay Singh Parmar62f795b2016-06-10 23:20:23 -0700260 struct dsi_display_mode *mode,
261 u32 flags);
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700262
263/**
264 * dsi_display_set_mode() - Set mode on the display.
265 * @display: Handle to display.
266 * @mode: mode to be set.
267 * @flags: Modifier flags.
268 *
269 * Return: error code.
270 */
271int dsi_display_set_mode(struct dsi_display *display,
272 struct dsi_display_mode *mode,
273 u32 flags);
274
275/**
276 * dsi_display_prepare() - prepare display
277 * @display: Handle to display.
278 *
279 * Prepare will perform power up sequences for the host and panel hardware.
280 * Power and clock resources might be turned on (depending on the panel mode).
281 * The video engine is not enabled.
282 *
283 * Return: error code.
284 */
285int dsi_display_prepare(struct dsi_display *display);
286
287/**
288 * dsi_display_enable() - enable display
289 * @display: Handle to display.
290 *
291 * Enable will turn on the host engine and the panel. At the end of the enable
292 * function, Host and panel hardware are ready to accept pixel data from
293 * upstream.
294 *
295 * Return: error code.
296 */
297int dsi_display_enable(struct dsi_display *display);
298
299/**
300 * dsi_display_post_enable() - perform post enable operations.
301 * @display: Handle to display.
302 *
303 * Some panels might require some commands to be sent after pixel data
304 * transmission has started. Such commands are sent as part of the post_enable
305 * function.
306 *
307 * Return: error code.
308 */
309int dsi_display_post_enable(struct dsi_display *display);
310
311/**
312 * dsi_display_pre_disable() - perform pre disable operations.
313 * @display: Handle to display.
314 *
315 * If a panel requires commands to be sent before pixel data transmission is
316 * stopped, those can be sent as part of pre_disable.
317 *
318 * Return: error code.
319 */
320int dsi_display_pre_disable(struct dsi_display *display);
321
322/**
323 * dsi_display_disable() - disable panel and host hardware.
324 * @display: Handle to display.
325 *
326 * Disable host and panel hardware and pixel data transmission can not continue.
327 *
328 * Return: error code.
329 */
330int dsi_display_disable(struct dsi_display *display);
331
332/**
Padmanabhan Komandurudbd2fb02016-12-02 15:18:49 +0530333 * dsi_pre_clkoff_cb() - Callback before clock is turned off
334 * @priv: private data pointer.
335 * @clk_type: clock which is being turned on.
336 * @new_state: next state for the clock.
337 *
338 * @return: error code.
339 */
340int dsi_pre_clkoff_cb(void *priv, enum dsi_clk_type clk_type,
341 enum dsi_clk_state new_state);
342
343/**
Alexander Beykunac182352017-02-27 17:46:51 -0500344 * dsi_display_update_pps() - update PPS buffer.
345 * @pps_cmd: PPS buffer.
346 * @display: Handle to display.
347 *
348 * Copies new PPS buffer into display structure.
349 *
350 * Return: error code.
351 */
352int dsi_display_update_pps(char *pps_cmd, void *display);
353
354/**
Padmanabhan Komandurudbd2fb02016-12-02 15:18:49 +0530355 * dsi_post_clkoff_cb() - Callback after clock is turned off
356 * @priv: private data pointer.
357 * @clk_type: clock which is being turned on.
358 * @curr_state: current state for the clock.
359 *
360 * @return: error code.
361 */
362int dsi_post_clkoff_cb(void *priv, enum dsi_clk_type clk_type,
363 enum dsi_clk_state curr_state);
364
365/**
366 * dsi_post_clkon_cb() - Callback after clock is turned on
367 * @priv: private data pointer.
368 * @clk_type: clock which is being turned on.
369 * @curr_state: current state for the clock.
370 *
371 * @return: error code.
372 */
373int dsi_post_clkon_cb(void *priv, enum dsi_clk_type clk_type,
374 enum dsi_clk_state curr_state);
375
376
377/**
378 * dsi_pre_clkon_cb() - Callback before clock is turned on
379 * @priv: private data pointer.
380 * @clk_type: clock which is being turned on.
381 * @new_state: next state for the clock.
382 *
383 * @return: error code.
384 */
385int dsi_pre_clkon_cb(void *priv, enum dsi_clk_type clk_type,
386 enum dsi_clk_state new_state);
387
388/**
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700389 * dsi_display_unprepare() - power off display hardware.
390 * @display: Handle to display.
391 *
392 * Host and panel hardware is turned off. Panel will be in reset state at the
393 * end of the function.
394 *
395 * Return: error code.
396 */
397int dsi_display_unprepare(struct dsi_display *display);
398
399int dsi_display_set_tpg_state(struct dsi_display *display, bool enable);
400
401int dsi_display_clock_gate(struct dsi_display *display, bool enable);
402int dsi_dispaly_static_frame(struct dsi_display *display, bool enable);
403
Vishnuvardhan Prodduturi75b96802016-10-17 18:45:55 +0530404int dsi_display_set_backlight(void *display, u32 bl_lvl);
Lloyd Atkinson8c49c582016-11-18 14:23:54 -0500405
406/**
407 * dsi_display_soft_reset() - perform a soft reset on DSI controller
408 * @display: Handle to display
409 *
410 * The video, command and controller engines will be disabled before the
411 * reset is triggered. After, the engines will be re-enabled to the same state
412 * as before the reset.
413 *
414 * If the reset is done while MDP timing engine is turned on, the video
415 * engine should be re-enabled only during the vertical blanking time.
416 *
417 * Return: error code
418 */
419int dsi_display_soft_reset(void *display);
Ajay Singh Parmar571e3012016-05-16 17:55:52 -0700420#endif /* _DSI_DISPLAY_H_ */