Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Driver for it913x-fe Frontend |
| 3 | * |
| 4 | * with support for on chip it9137 integral tuner |
| 5 | * |
| 6 | * Copyright (C) 2011 Malcolm Priestley (tvboxspy@gmail.com) |
| 7 | * IT9137 Copyright (C) ITE Tech Inc. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= |
| 23 | */ |
| 24 | |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/init.h> |
| 27 | #include <linux/slab.h> |
| 28 | #include <linux/types.h> |
| 29 | |
| 30 | #include "dvb_frontend.h" |
| 31 | #include "it913x-fe.h" |
| 32 | #include "it913x-fe-priv.h" |
| 33 | |
| 34 | static int it913x_debug; |
| 35 | |
| 36 | module_param_named(debug, it913x_debug, int, 0644); |
| 37 | MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able))."); |
| 38 | |
| 39 | #define dprintk(level, args...) do { \ |
| 40 | if (level & it913x_debug) \ |
| 41 | printk(KERN_DEBUG "it913x-fe: " args); \ |
| 42 | } while (0) |
| 43 | |
| 44 | #define deb_info(args...) dprintk(0x01, args) |
| 45 | #define debug_data_snipet(level, name, p) \ |
| 46 | dprintk(level, name" (%02x%02x%02x%02x%02x%02x%02x%02x)", \ |
| 47 | *p, *(p+1), *(p+2), *(p+3), *(p+4), \ |
| 48 | *(p+5), *(p+6), *(p+7)); |
Malcolm Priestley | ed942c5 | 2011-11-27 18:14:05 -0300 | [diff] [blame] | 49 | #define info(format, arg...) \ |
| 50 | printk(KERN_INFO "it913x-fe: " format "\n" , ## arg) |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 51 | |
| 52 | struct it913x_fe_state { |
| 53 | struct dvb_frontend frontend; |
| 54 | struct i2c_adapter *i2c_adap; |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 55 | struct ite_config *config; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 56 | u8 i2c_addr; |
| 57 | u32 frequency; |
Malcolm Priestley | 3339a5b | 2011-11-06 11:19:14 -0300 | [diff] [blame] | 58 | fe_modulation_t constellation; |
| 59 | fe_transmit_mode_t transmission_mode; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 60 | u32 crystalFrequency; |
| 61 | u32 adcFrequency; |
| 62 | u8 tuner_type; |
| 63 | struct adctable *table; |
| 64 | fe_status_t it913x_status; |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 65 | u16 tun_xtal; |
| 66 | u8 tun_fdiv; |
| 67 | u8 tun_clk_mode; |
| 68 | u32 tun_fn_min; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 69 | }; |
| 70 | |
| 71 | static int it913x_read_reg(struct it913x_fe_state *state, |
| 72 | u32 reg, u8 *data, u8 count) |
| 73 | { |
| 74 | int ret; |
| 75 | u8 pro = PRO_DMOD; /* All reads from demodulator */ |
| 76 | u8 b[4]; |
| 77 | struct i2c_msg msg[2] = { |
| 78 | { .addr = state->i2c_addr + (pro << 1), .flags = 0, |
| 79 | .buf = b, .len = sizeof(b) }, |
| 80 | { .addr = state->i2c_addr + (pro << 1), .flags = I2C_M_RD, |
| 81 | .buf = data, .len = count } |
| 82 | }; |
| 83 | b[0] = (u8) reg >> 24; |
| 84 | b[1] = (u8)(reg >> 16) & 0xff; |
| 85 | b[2] = (u8)(reg >> 8) & 0xff; |
| 86 | b[3] = (u8) reg & 0xff; |
| 87 | |
| 88 | ret = i2c_transfer(state->i2c_adap, msg, 2); |
| 89 | |
| 90 | return ret; |
| 91 | } |
| 92 | |
| 93 | static int it913x_read_reg_u8(struct it913x_fe_state *state, u32 reg) |
| 94 | { |
| 95 | int ret; |
| 96 | u8 b[1]; |
| 97 | ret = it913x_read_reg(state, reg, &b[0], sizeof(b)); |
| 98 | return (ret < 0) ? -ENODEV : b[0]; |
| 99 | } |
| 100 | |
| 101 | static int it913x_write(struct it913x_fe_state *state, |
| 102 | u8 pro, u32 reg, u8 buf[], u8 count) |
| 103 | { |
| 104 | u8 b[256]; |
| 105 | struct i2c_msg msg[1] = { |
| 106 | { .addr = state->i2c_addr + (pro << 1), .flags = 0, |
| 107 | .buf = b, .len = count + 4 } |
| 108 | }; |
| 109 | int ret; |
| 110 | |
| 111 | b[0] = (u8) reg >> 24; |
| 112 | b[1] = (u8)(reg >> 16) & 0xff; |
| 113 | b[2] = (u8)(reg >> 8) & 0xff; |
| 114 | b[3] = (u8) reg & 0xff; |
| 115 | memcpy(&b[4], buf, count); |
| 116 | |
| 117 | ret = i2c_transfer(state->i2c_adap, msg, 1); |
| 118 | |
| 119 | if (ret < 0) |
| 120 | return -EIO; |
| 121 | |
| 122 | return 0; |
| 123 | } |
| 124 | |
| 125 | static int it913x_write_reg(struct it913x_fe_state *state, |
| 126 | u8 pro, u32 reg, u32 data) |
| 127 | { |
| 128 | int ret; |
| 129 | u8 b[4]; |
| 130 | u8 s; |
| 131 | |
| 132 | b[0] = data >> 24; |
| 133 | b[1] = (data >> 16) & 0xff; |
| 134 | b[2] = (data >> 8) & 0xff; |
| 135 | b[3] = data & 0xff; |
| 136 | /* expand write as needed */ |
| 137 | if (data < 0x100) |
| 138 | s = 3; |
| 139 | else if (data < 0x1000) |
| 140 | s = 2; |
| 141 | else if (data < 0x100000) |
| 142 | s = 1; |
| 143 | else |
| 144 | s = 0; |
| 145 | |
| 146 | ret = it913x_write(state, pro, reg, &b[s], sizeof(b) - s); |
| 147 | |
| 148 | return ret; |
| 149 | } |
| 150 | |
| 151 | static int it913x_fe_script_loader(struct it913x_fe_state *state, |
| 152 | struct it913xset *loadscript) |
| 153 | { |
| 154 | int ret, i; |
| 155 | if (loadscript == NULL) |
| 156 | return -EINVAL; |
| 157 | |
| 158 | for (i = 0; i < 1000; ++i) { |
| 159 | if (loadscript[i].pro == 0xff) |
| 160 | break; |
| 161 | ret = it913x_write(state, loadscript[i].pro, |
| 162 | loadscript[i].address, |
| 163 | loadscript[i].reg, loadscript[i].count); |
| 164 | if (ret < 0) |
| 165 | return -ENODEV; |
| 166 | } |
| 167 | return 0; |
| 168 | } |
| 169 | |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 170 | static int it913x_init_tuner(struct it913x_fe_state *state) |
| 171 | { |
| 172 | int ret, i, reg; |
| 173 | u8 val, nv_val; |
| 174 | u8 nv[] = {48, 32, 24, 16, 12, 8, 6, 4, 2}; |
| 175 | u8 b[2]; |
| 176 | |
| 177 | reg = it913x_read_reg_u8(state, 0xec86); |
| 178 | switch (reg) { |
| 179 | case 0: |
| 180 | state->tun_clk_mode = reg; |
| 181 | state->tun_xtal = 2000; |
| 182 | state->tun_fdiv = 3; |
| 183 | val = 16; |
| 184 | break; |
| 185 | case -ENODEV: |
| 186 | return -ENODEV; |
| 187 | case 1: |
| 188 | default: |
| 189 | state->tun_clk_mode = reg; |
| 190 | state->tun_xtal = 640; |
| 191 | state->tun_fdiv = 1; |
| 192 | val = 6; |
| 193 | break; |
| 194 | } |
| 195 | |
| 196 | reg = it913x_read_reg_u8(state, 0xed03); |
| 197 | |
| 198 | if (reg < 0) |
| 199 | return -ENODEV; |
| 200 | else if (reg < sizeof(nv)) |
| 201 | nv_val = nv[reg]; |
| 202 | else |
| 203 | nv_val = 2; |
| 204 | |
| 205 | for (i = 0; i < 50; i++) { |
| 206 | ret = it913x_read_reg(state, 0xed23, &b[0], sizeof(b)); |
| 207 | reg = (b[1] << 8) + b[0]; |
| 208 | if (reg > 0) |
| 209 | break; |
| 210 | if (ret < 0) |
| 211 | return -ENODEV; |
| 212 | udelay(2000); |
| 213 | } |
| 214 | state->tun_fn_min = state->tun_xtal * reg; |
| 215 | state->tun_fn_min /= (state->tun_fdiv * nv_val); |
| 216 | deb_info("Tuner fn_min %d", state->tun_fn_min); |
| 217 | |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 218 | if (state->config->chip_ver > 1) |
| 219 | msleep(50); |
| 220 | else { |
| 221 | for (i = 0; i < 50; i++) { |
| 222 | reg = it913x_read_reg_u8(state, 0xec82); |
| 223 | if (reg > 0) |
| 224 | break; |
| 225 | if (reg < 0) |
| 226 | return -ENODEV; |
| 227 | udelay(2000); |
| 228 | } |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 229 | } |
| 230 | |
| 231 | return it913x_write_reg(state, PRO_DMOD, 0xed81, val); |
| 232 | } |
| 233 | |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 234 | static int it9137_set_tuner(struct it913x_fe_state *state, |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 235 | u32 bandwidth, u32 frequency_m) |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 236 | { |
| 237 | struct it913xset *set_tuner = set_it9137_template; |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 238 | int ret, reg; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 239 | u32 frequency = frequency_m / 1000; |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 240 | u32 freq, temp_f, tmp; |
| 241 | u16 iqik_m_cal; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 242 | u16 n_div; |
| 243 | u8 n; |
| 244 | u8 l_band; |
| 245 | u8 lna_band; |
| 246 | u8 bw; |
| 247 | |
Malcolm Priestley | 990f49a | 2011-11-28 18:04:21 -0300 | [diff] [blame] | 248 | if (state->config->firmware_ver == 1) |
| 249 | set_tuner = set_it9135_template; |
| 250 | else |
| 251 | set_tuner = set_it9137_template; |
| 252 | |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 253 | deb_info("Tuner Frequency %d Bandwidth %d", frequency, bandwidth); |
| 254 | |
| 255 | if (frequency >= 51000 && frequency <= 440000) { |
| 256 | l_band = 0; |
| 257 | lna_band = 0; |
| 258 | } else if (frequency > 440000 && frequency <= 484000) { |
| 259 | l_band = 1; |
| 260 | lna_band = 1; |
| 261 | } else if (frequency > 484000 && frequency <= 533000) { |
| 262 | l_band = 1; |
| 263 | lna_band = 2; |
| 264 | } else if (frequency > 533000 && frequency <= 587000) { |
| 265 | l_band = 1; |
| 266 | lna_band = 3; |
| 267 | } else if (frequency > 587000 && frequency <= 645000) { |
| 268 | l_band = 1; |
| 269 | lna_band = 4; |
| 270 | } else if (frequency > 645000 && frequency <= 710000) { |
| 271 | l_band = 1; |
| 272 | lna_band = 5; |
| 273 | } else if (frequency > 710000 && frequency <= 782000) { |
| 274 | l_band = 1; |
| 275 | lna_band = 6; |
| 276 | } else if (frequency > 782000 && frequency <= 860000) { |
| 277 | l_band = 1; |
| 278 | lna_band = 7; |
| 279 | } else if (frequency > 1450000 && frequency <= 1492000) { |
| 280 | l_band = 1; |
| 281 | lna_band = 0; |
| 282 | } else if (frequency > 1660000 && frequency <= 1685000) { |
| 283 | l_band = 1; |
| 284 | lna_band = 1; |
| 285 | } else |
| 286 | return -EINVAL; |
| 287 | set_tuner[0].reg[0] = lna_band; |
| 288 | |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 289 | switch (bandwidth) { |
| 290 | case 5000000: |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 291 | bw = 0; |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 292 | break; |
| 293 | case 6000000: |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 294 | bw = 2; |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 295 | break; |
| 296 | case 7000000: |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 297 | bw = 4; |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 298 | break; |
| 299 | default: |
| 300 | case 8000000: |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 301 | bw = 6; |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 302 | break; |
| 303 | } |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 304 | |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 305 | set_tuner[1].reg[0] = bw; |
| 306 | set_tuner[2].reg[0] = 0xa0 | (l_band << 3); |
| 307 | |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 308 | if (frequency > 53000 && frequency <= 74000) { |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 309 | n_div = 48; |
| 310 | n = 0; |
| 311 | } else if (frequency > 74000 && frequency <= 111000) { |
| 312 | n_div = 32; |
| 313 | n = 1; |
| 314 | } else if (frequency > 111000 && frequency <= 148000) { |
| 315 | n_div = 24; |
| 316 | n = 2; |
| 317 | } else if (frequency > 148000 && frequency <= 222000) { |
| 318 | n_div = 16; |
| 319 | n = 3; |
| 320 | } else if (frequency > 222000 && frequency <= 296000) { |
| 321 | n_div = 12; |
| 322 | n = 4; |
| 323 | } else if (frequency > 296000 && frequency <= 445000) { |
| 324 | n_div = 8; |
| 325 | n = 5; |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 326 | } else if (frequency > 445000 && frequency <= state->tun_fn_min) { |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 327 | n_div = 6; |
| 328 | n = 6; |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 329 | } else if (frequency > state->tun_fn_min && frequency <= 950000) { |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 330 | n_div = 4; |
| 331 | n = 7; |
| 332 | } else if (frequency > 1450000 && frequency <= 1680000) { |
| 333 | n_div = 2; |
| 334 | n = 0; |
| 335 | } else |
| 336 | return -EINVAL; |
| 337 | |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 338 | reg = it913x_read_reg_u8(state, 0xed81); |
| 339 | iqik_m_cal = (u16)reg * n_div; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 340 | |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 341 | if (reg < 0x20) { |
| 342 | if (state->tun_clk_mode == 0) |
| 343 | iqik_m_cal = (iqik_m_cal * 9) >> 5; |
| 344 | else |
| 345 | iqik_m_cal >>= 1; |
| 346 | } else { |
| 347 | iqik_m_cal = 0x40 - iqik_m_cal; |
| 348 | if (state->tun_clk_mode == 0) |
| 349 | iqik_m_cal = ~((iqik_m_cal * 9) >> 5); |
| 350 | else |
| 351 | iqik_m_cal = ~(iqik_m_cal >> 1); |
| 352 | } |
| 353 | |
| 354 | temp_f = frequency * (u32)n_div * (u32)state->tun_fdiv; |
| 355 | freq = temp_f / state->tun_xtal; |
| 356 | tmp = freq * state->tun_xtal; |
| 357 | |
| 358 | if ((temp_f - tmp) >= (state->tun_xtal >> 1)) |
| 359 | freq++; |
| 360 | |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 361 | freq += (u32) n << 13; |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 362 | /* Frequency OMEGA_IQIK_M_CAL_MID*/ |
| 363 | temp_f = freq + (u32)iqik_m_cal; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 364 | |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 365 | set_tuner[3].reg[0] = temp_f & 0xff; |
| 366 | set_tuner[4].reg[0] = (temp_f >> 8) & 0xff; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 367 | |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 368 | deb_info("High Frequency = %04x", temp_f); |
| 369 | |
| 370 | /* Lower frequency */ |
| 371 | set_tuner[5].reg[0] = freq & 0xff; |
| 372 | set_tuner[6].reg[0] = (freq >> 8) & 0xff; |
| 373 | |
| 374 | deb_info("low Frequency = %04x", freq); |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 375 | |
| 376 | ret = it913x_fe_script_loader(state, set_tuner); |
| 377 | |
| 378 | return (ret < 0) ? -ENODEV : 0; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 379 | } |
| 380 | |
| 381 | static int it913x_fe_select_bw(struct it913x_fe_state *state, |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 382 | u32 bandwidth, u32 adcFrequency) |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 383 | { |
| 384 | int ret, i; |
| 385 | u8 buffer[256]; |
| 386 | u32 coeff[8]; |
| 387 | u16 bfsfcw_fftinx_ratio; |
| 388 | u16 fftinx_bfsfcw_ratio; |
| 389 | u8 count; |
| 390 | u8 bw; |
| 391 | u8 adcmultiplier; |
| 392 | |
| 393 | deb_info("Bandwidth %d Adc %d", bandwidth, adcFrequency); |
| 394 | |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 395 | switch (bandwidth) { |
| 396 | case 5000000: |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 397 | bw = 3; |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 398 | break; |
| 399 | case 6000000: |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 400 | bw = 0; |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 401 | break; |
| 402 | case 7000000: |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 403 | bw = 1; |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 404 | break; |
| 405 | default: |
| 406 | case 8000000: |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 407 | bw = 2; |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 408 | break; |
| 409 | } |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 410 | ret = it913x_write_reg(state, PRO_DMOD, REG_BW, bw); |
| 411 | |
| 412 | if (state->table == NULL) |
| 413 | return -EINVAL; |
| 414 | |
| 415 | /* In write order */ |
| 416 | coeff[0] = state->table[bw].coeff_1_2048; |
| 417 | coeff[1] = state->table[bw].coeff_2_2k; |
| 418 | coeff[2] = state->table[bw].coeff_1_8191; |
| 419 | coeff[3] = state->table[bw].coeff_1_8192; |
| 420 | coeff[4] = state->table[bw].coeff_1_8193; |
| 421 | coeff[5] = state->table[bw].coeff_2_8k; |
| 422 | coeff[6] = state->table[bw].coeff_1_4096; |
| 423 | coeff[7] = state->table[bw].coeff_2_4k; |
| 424 | bfsfcw_fftinx_ratio = state->table[bw].bfsfcw_fftinx_ratio; |
| 425 | fftinx_bfsfcw_ratio = state->table[bw].fftinx_bfsfcw_ratio; |
| 426 | |
| 427 | /* ADC multiplier */ |
| 428 | ret = it913x_read_reg_u8(state, ADC_X_2); |
| 429 | if (ret < 0) |
| 430 | return -EINVAL; |
| 431 | |
| 432 | adcmultiplier = ret; |
| 433 | |
| 434 | count = 0; |
| 435 | |
| 436 | /* Build Buffer for COEFF Registers */ |
| 437 | for (i = 0; i < 8; i++) { |
| 438 | if (adcmultiplier == 1) |
| 439 | coeff[i] /= 2; |
| 440 | buffer[count++] = (coeff[i] >> 24) & 0x3; |
| 441 | buffer[count++] = (coeff[i] >> 16) & 0xff; |
| 442 | buffer[count++] = (coeff[i] >> 8) & 0xff; |
| 443 | buffer[count++] = coeff[i] & 0xff; |
| 444 | } |
| 445 | |
| 446 | /* bfsfcw_fftinx_ratio register 0x21-0x22 */ |
| 447 | buffer[count++] = bfsfcw_fftinx_ratio & 0xff; |
| 448 | buffer[count++] = (bfsfcw_fftinx_ratio >> 8) & 0xff; |
| 449 | /* fftinx_bfsfcw_ratio register 0x23-0x24 */ |
| 450 | buffer[count++] = fftinx_bfsfcw_ratio & 0xff; |
| 451 | buffer[count++] = (fftinx_bfsfcw_ratio >> 8) & 0xff; |
| 452 | /* start at COEFF_1_2048 and write through to fftinx_bfsfcw_ratio*/ |
| 453 | ret = it913x_write(state, PRO_DMOD, COEFF_1_2048, buffer, count); |
| 454 | |
| 455 | for (i = 0; i < 42; i += 8) |
| 456 | debug_data_snipet(0x1, "Buffer", &buffer[i]); |
| 457 | |
| 458 | return ret; |
| 459 | } |
| 460 | |
| 461 | |
| 462 | |
| 463 | static int it913x_fe_read_status(struct dvb_frontend *fe, fe_status_t *status) |
| 464 | { |
| 465 | struct it913x_fe_state *state = fe->demodulator_priv; |
| 466 | int ret, i; |
| 467 | fe_status_t old_status = state->it913x_status; |
| 468 | *status = 0; |
| 469 | |
| 470 | if (state->it913x_status == 0) { |
| 471 | ret = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS); |
| 472 | if (ret == 0x1) { |
| 473 | *status |= FE_HAS_SIGNAL; |
| 474 | for (i = 0; i < 40; i++) { |
| 475 | ret = it913x_read_reg_u8(state, MP2IF_SYNC_LK); |
| 476 | if (ret == 0x1) |
| 477 | break; |
| 478 | msleep(25); |
| 479 | } |
| 480 | if (ret == 0x1) |
| 481 | *status |= FE_HAS_CARRIER |
| 482 | | FE_HAS_VITERBI |
| 483 | | FE_HAS_SYNC; |
| 484 | state->it913x_status = *status; |
| 485 | } |
| 486 | } |
| 487 | |
| 488 | if (state->it913x_status & FE_HAS_SYNC) { |
| 489 | ret = it913x_read_reg_u8(state, TPSD_LOCK); |
| 490 | if (ret == 0x1) |
| 491 | *status |= FE_HAS_LOCK |
| 492 | | state->it913x_status; |
| 493 | else |
| 494 | state->it913x_status = 0; |
| 495 | if (old_status != state->it913x_status) |
| 496 | ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, ret); |
| 497 | } |
| 498 | |
| 499 | return 0; |
| 500 | } |
| 501 | |
| 502 | static int it913x_fe_read_signal_strength(struct dvb_frontend *fe, |
| 503 | u16 *strength) |
| 504 | { |
| 505 | struct it913x_fe_state *state = fe->demodulator_priv; |
| 506 | int ret = it913x_read_reg_u8(state, SIGNAL_LEVEL); |
| 507 | /*SIGNAL_LEVEL always returns 100%! so using FE_HAS_SIGNAL as switch*/ |
| 508 | if (state->it913x_status & FE_HAS_SIGNAL) |
| 509 | ret = (ret * 0xff) / 0x64; |
| 510 | else |
| 511 | ret = 0x0; |
| 512 | ret |= ret << 0x8; |
| 513 | *strength = ret; |
| 514 | return 0; |
| 515 | } |
| 516 | |
Malcolm Priestley | 3339a5b | 2011-11-06 11:19:14 -0300 | [diff] [blame] | 517 | static int it913x_fe_read_snr(struct dvb_frontend *fe, u16 *snr) |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 518 | { |
| 519 | struct it913x_fe_state *state = fe->demodulator_priv; |
Malcolm Priestley | 3339a5b | 2011-11-06 11:19:14 -0300 | [diff] [blame] | 520 | int ret; |
| 521 | u8 reg[3]; |
| 522 | u32 snr_val, snr_min, snr_max; |
| 523 | u32 temp; |
| 524 | |
| 525 | ret = it913x_read_reg(state, 0x2c, reg, sizeof(reg)); |
| 526 | |
| 527 | snr_val = (u32)(reg[2] << 16) | (reg[1] < 8) | reg[0]; |
| 528 | |
| 529 | ret |= it913x_read_reg(state, 0xf78b, reg, 1); |
| 530 | if (reg[0]) |
| 531 | snr_val /= reg[0]; |
| 532 | |
| 533 | if (state->transmission_mode == TRANSMISSION_MODE_2K) |
| 534 | snr_val *= 4; |
| 535 | else if (state->transmission_mode == TRANSMISSION_MODE_4K) |
| 536 | snr_val *= 2; |
| 537 | |
| 538 | if (state->constellation == QPSK) { |
| 539 | snr_min = 0xb4711; |
| 540 | snr_max = 0x191451; |
| 541 | } else if (state->constellation == QAM_16) { |
| 542 | snr_min = 0x4f0d5; |
| 543 | snr_max = 0xc7925; |
| 544 | } else if (state->constellation == QAM_64) { |
| 545 | snr_min = 0x256d0; |
| 546 | snr_max = 0x626be; |
| 547 | } else |
| 548 | return -EINVAL; |
| 549 | |
| 550 | if (snr_val < snr_min) |
| 551 | *snr = 0; |
| 552 | else if (snr_val < snr_max) { |
| 553 | temp = (snr_val - snr_min) >> 5; |
| 554 | temp *= 0xffff; |
| 555 | temp /= (snr_max - snr_min) >> 5; |
| 556 | *snr = (u16)temp; |
| 557 | } else |
| 558 | *snr = 0xffff; |
| 559 | |
| 560 | return (ret < 0) ? -ENODEV : 0; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 561 | } |
| 562 | |
| 563 | static int it913x_fe_read_ber(struct dvb_frontend *fe, u32 *ber) |
| 564 | { |
| 565 | *ber = 0; |
| 566 | return 0; |
| 567 | } |
| 568 | |
| 569 | static int it913x_fe_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) |
| 570 | { |
| 571 | *ucblocks = 0; |
| 572 | return 0; |
| 573 | } |
| 574 | |
| 575 | static int it913x_fe_get_frontend(struct dvb_frontend *fe, |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 576 | struct dtv_frontend_properties *p) |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 577 | { |
| 578 | struct it913x_fe_state *state = fe->demodulator_priv; |
| 579 | int ret; |
| 580 | u8 reg[8]; |
| 581 | |
| 582 | ret = it913x_read_reg(state, REG_TPSD_TX_MODE, reg, sizeof(reg)); |
| 583 | |
| 584 | if (reg[3] < 3) |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 585 | p->modulation = fe_con[reg[3]]; |
Malcolm Priestley | 3339a5b | 2011-11-06 11:19:14 -0300 | [diff] [blame] | 586 | |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 587 | if (reg[0] < 3) |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 588 | p->transmission_mode = fe_mode[reg[0]]; |
Malcolm Priestley | 3339a5b | 2011-11-06 11:19:14 -0300 | [diff] [blame] | 589 | |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 590 | if (reg[1] < 4) |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 591 | p->guard_interval = fe_gi[reg[1]]; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 592 | |
| 593 | if (reg[2] < 4) |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 594 | p->hierarchy = fe_hi[reg[2]]; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 595 | |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 596 | p->code_rate_HP = (reg[6] < 6) ? fe_code[reg[6]] : FEC_NONE; |
| 597 | p->code_rate_LP = (reg[7] < 6) ? fe_code[reg[7]] : FEC_NONE; |
| 598 | |
| 599 | /* Update internal state to reflect the autodetected props */ |
| 600 | state->constellation = p->modulation; |
| 601 | state->transmission_mode = p->transmission_mode; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 602 | |
| 603 | return 0; |
| 604 | } |
| 605 | |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 606 | static int it913x_fe_set_frontend(struct dvb_frontend *fe) |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 607 | { |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 608 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 609 | struct it913x_fe_state *state = fe->demodulator_priv; |
| 610 | int ret, i; |
| 611 | u8 empty_ch, last_ch; |
| 612 | |
| 613 | state->it913x_status = 0; |
| 614 | |
| 615 | /* Set bw*/ |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 616 | ret = it913x_fe_select_bw(state, p->bandwidth_hz, |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 617 | state->adcFrequency); |
| 618 | |
| 619 | /* Training Mode Off */ |
| 620 | ret = it913x_write_reg(state, PRO_LINK, TRAINING_MODE, 0x0); |
| 621 | |
| 622 | /* Clear Empty Channel */ |
| 623 | ret = it913x_write_reg(state, PRO_DMOD, EMPTY_CHANNEL_STATUS, 0x0); |
| 624 | |
| 625 | /* Clear bits */ |
| 626 | ret = it913x_write_reg(state, PRO_DMOD, MP2IF_SYNC_LK, 0x0); |
| 627 | /* LED on */ |
| 628 | ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1); |
| 629 | /* Select Band*/ |
| 630 | if ((p->frequency >= 51000000) && (p->frequency <= 230000000)) |
| 631 | i = 0; |
| 632 | else if ((p->frequency >= 350000000) && (p->frequency <= 900000000)) |
| 633 | i = 1; |
| 634 | else if ((p->frequency >= 1450000000) && (p->frequency <= 1680000000)) |
| 635 | i = 2; |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 636 | else |
| 637 | return -EOPNOTSUPP; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 638 | |
| 639 | ret = it913x_write_reg(state, PRO_DMOD, FREE_BAND, i); |
| 640 | |
| 641 | deb_info("Frontend Set Tuner Type %02x", state->tuner_type); |
| 642 | switch (state->tuner_type) { |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 643 | case IT9135_38: |
| 644 | case IT9135_51: |
| 645 | case IT9135_52: |
| 646 | case IT9135_60: |
| 647 | case IT9135_61: |
| 648 | case IT9135_62: |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 649 | ret = it9137_set_tuner(state, |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 650 | p->bandwidth_hz, p->frequency); |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 651 | break; |
| 652 | default: |
| 653 | if (fe->ops.tuner_ops.set_params) { |
Mauro Carvalho Chehab | 14d24d1 | 2011-12-24 12:24:33 -0300 | [diff] [blame] | 654 | fe->ops.tuner_ops.set_params(fe); |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 655 | if (fe->ops.i2c_gate_ctrl) |
| 656 | fe->ops.i2c_gate_ctrl(fe, 0); |
| 657 | } |
| 658 | break; |
| 659 | } |
| 660 | /* LED off */ |
| 661 | ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0); |
| 662 | /* Trigger ofsm */ |
| 663 | ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0); |
| 664 | last_ch = 2; |
| 665 | for (i = 0; i < 40; ++i) { |
| 666 | empty_ch = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS); |
| 667 | if (last_ch == 1 && empty_ch == 1) |
| 668 | break; |
| 669 | if (last_ch == 2 && empty_ch == 2) |
| 670 | return 0; |
| 671 | last_ch = empty_ch; |
| 672 | msleep(25); |
| 673 | } |
| 674 | for (i = 0; i < 40; ++i) { |
| 675 | if (it913x_read_reg_u8(state, D_TPSD_LOCK) == 1) |
| 676 | break; |
| 677 | msleep(25); |
| 678 | } |
| 679 | |
| 680 | state->frequency = p->frequency; |
| 681 | return 0; |
| 682 | } |
| 683 | |
| 684 | static int it913x_fe_suspend(struct it913x_fe_state *state) |
| 685 | { |
| 686 | int ret, i; |
| 687 | u8 b; |
| 688 | |
| 689 | ret = it913x_write_reg(state, PRO_DMOD, SUSPEND_FLAG, 0x1); |
| 690 | |
| 691 | ret |= it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0); |
| 692 | |
| 693 | for (i = 0; i < 128; i++) { |
| 694 | ret = it913x_read_reg(state, SUSPEND_FLAG, &b, 1); |
| 695 | if (ret < 0) |
Malcolm Priestley | e305288 | 2011-10-01 09:24:16 -0300 | [diff] [blame] | 696 | return -ENODEV; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 697 | if (b == 0) |
| 698 | break; |
| 699 | |
| 700 | } |
| 701 | |
| 702 | ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x8); |
| 703 | /* Turn LED off */ |
Malcolm Priestley | e305288 | 2011-10-01 09:24:16 -0300 | [diff] [blame] | 704 | ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0); |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 705 | |
Malcolm Priestley | e305288 | 2011-10-01 09:24:16 -0300 | [diff] [blame] | 706 | ret |= it913x_fe_script_loader(state, it9137_tuner_off); |
| 707 | |
| 708 | return (ret < 0) ? -ENODEV : 0; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 709 | } |
| 710 | |
Malcolm Priestley | e305288 | 2011-10-01 09:24:16 -0300 | [diff] [blame] | 711 | /* Power sequence */ |
| 712 | /* Power Up Tuner on -> Frontend suspend off -> Tuner clk on */ |
| 713 | /* Power Down Frontend suspend on -> Tuner clk off -> Tuner off */ |
| 714 | |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 715 | static int it913x_fe_sleep(struct dvb_frontend *fe) |
| 716 | { |
| 717 | struct it913x_fe_state *state = fe->demodulator_priv; |
| 718 | return it913x_fe_suspend(state); |
| 719 | } |
| 720 | |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 721 | static u32 compute_div(u32 a, u32 b, u32 x) |
| 722 | { |
| 723 | u32 res = 0; |
| 724 | u32 c = 0; |
| 725 | u32 i = 0; |
| 726 | |
| 727 | if (a > b) { |
| 728 | c = a / b; |
| 729 | a = a - c * b; |
| 730 | } |
| 731 | |
| 732 | for (i = 0; i < x; i++) { |
| 733 | if (a >= b) { |
| 734 | res += 1; |
| 735 | a -= b; |
| 736 | } |
| 737 | a <<= 1; |
| 738 | res <<= 1; |
| 739 | } |
| 740 | |
| 741 | res = (c << x) + res; |
| 742 | |
| 743 | return res; |
| 744 | } |
| 745 | |
| 746 | static int it913x_fe_start(struct it913x_fe_state *state) |
| 747 | { |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 748 | struct it913xset *set_lna; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 749 | struct it913xset *set_mode; |
| 750 | int ret; |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 751 | u8 adf = (state->config->adf & 0xf); |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 752 | u32 adc, xtal; |
| 753 | u8 b[4]; |
| 754 | |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 755 | if (state->config->chip_ver == 1) |
| 756 | ret = it913x_init_tuner(state); |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 757 | |
Malcolm Priestley | ed942c5 | 2011-11-27 18:14:05 -0300 | [diff] [blame] | 758 | info("ADF table value :%02x", adf); |
| 759 | |
tvboxspy | 2b3c13e | 2011-10-31 12:06:34 -0300 | [diff] [blame] | 760 | if (adf < 10) { |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 761 | state->crystalFrequency = fe_clockTable[adf].xtal ; |
| 762 | state->table = fe_clockTable[adf].table; |
| 763 | state->adcFrequency = state->table->adcFrequency; |
| 764 | |
| 765 | adc = compute_div(state->adcFrequency, 1000000ul, 19ul); |
| 766 | xtal = compute_div(state->crystalFrequency, 1000000ul, 19ul); |
| 767 | |
| 768 | } else |
| 769 | return -EINVAL; |
| 770 | |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 771 | /* Set LED indicator on GPIOH3 */ |
| 772 | ret = it913x_write_reg(state, PRO_LINK, GPIOH3_EN, 0x1); |
| 773 | ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_ON, 0x1); |
| 774 | ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1); |
| 775 | |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 776 | ret |= it913x_write_reg(state, PRO_LINK, 0xf641, state->tuner_type); |
| 777 | ret |= it913x_write_reg(state, PRO_DMOD, 0xf5ca, 0x01); |
| 778 | ret |= it913x_write_reg(state, PRO_DMOD, 0xf715, 0x01); |
| 779 | |
| 780 | b[0] = xtal & 0xff; |
| 781 | b[1] = (xtal >> 8) & 0xff; |
| 782 | b[2] = (xtal >> 16) & 0xff; |
| 783 | b[3] = (xtal >> 24); |
| 784 | ret |= it913x_write(state, PRO_DMOD, XTAL_CLK, b , 4); |
| 785 | |
| 786 | b[0] = adc & 0xff; |
| 787 | b[1] = (adc >> 8) & 0xff; |
| 788 | b[2] = (adc >> 16) & 0xff; |
| 789 | ret |= it913x_write(state, PRO_DMOD, ADC_FREQ, b, 3); |
Malcolm Priestley | ed942c5 | 2011-11-27 18:14:05 -0300 | [diff] [blame] | 790 | |
Malcolm Priestley | 990f49a | 2011-11-28 18:04:21 -0300 | [diff] [blame] | 791 | if (state->config->adc_x2) |
| 792 | ret |= it913x_write_reg(state, PRO_DMOD, ADC_X_2, 0x01); |
| 793 | b[0] = 0; |
| 794 | b[1] = 0; |
| 795 | b[2] = 0; |
| 796 | ret |= it913x_write(state, PRO_DMOD, 0x0029, b, 3); |
| 797 | |
| 798 | info("Crystal Frequency :%d Adc Frequency :%d ADC X2: %02x", |
| 799 | state->crystalFrequency, state->adcFrequency, |
| 800 | state->config->adc_x2); |
Malcolm Priestley | ed942c5 | 2011-11-27 18:14:05 -0300 | [diff] [blame] | 801 | deb_info("Xtal value :%04x Adc value :%04x", xtal, adc); |
| 802 | |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 803 | if (ret < 0) |
| 804 | return -ENODEV; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 805 | |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 806 | /* v1 or v2 tuner script */ |
| 807 | if (state->config->chip_ver > 1) |
| 808 | ret = it913x_fe_script_loader(state, it9135_v2); |
| 809 | else |
| 810 | ret = it913x_fe_script_loader(state, it9135_v1); |
| 811 | if (ret < 0) |
| 812 | return ret; |
| 813 | |
| 814 | /* LNA Scripts */ |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 815 | switch (state->tuner_type) { |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 816 | case IT9135_51: |
| 817 | set_lna = it9135_51; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 818 | break; |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 819 | case IT9135_52: |
| 820 | set_lna = it9135_52; |
| 821 | break; |
| 822 | case IT9135_60: |
| 823 | set_lna = it9135_60; |
| 824 | break; |
| 825 | case IT9135_61: |
| 826 | set_lna = it9135_61; |
| 827 | break; |
| 828 | case IT9135_62: |
| 829 | set_lna = it9135_62; |
| 830 | break; |
| 831 | case IT9135_38: |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 832 | default: |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 833 | set_lna = it9135_38; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 834 | } |
Malcolm Priestley | ed942c5 | 2011-11-27 18:14:05 -0300 | [diff] [blame] | 835 | info("Tuner LNA type :%02x", state->tuner_type); |
| 836 | |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 837 | ret = it913x_fe_script_loader(state, set_lna); |
| 838 | if (ret < 0) |
| 839 | return ret; |
tvboxspy | 7c2808e | 2011-09-21 19:06:58 -0300 | [diff] [blame] | 840 | |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 841 | if (state->config->chip_ver == 2) { |
| 842 | ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x1); |
| 843 | ret |= it913x_write_reg(state, PRO_LINK, PADODPU, 0x0); |
| 844 | ret |= it913x_write_reg(state, PRO_LINK, AGC_O_D, 0x0); |
| 845 | ret |= it913x_init_tuner(state); |
| 846 | } |
| 847 | if (ret < 0) |
| 848 | return -ENODEV; |
| 849 | |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 850 | /* Always solo frontend */ |
| 851 | set_mode = set_solo_fe; |
| 852 | ret |= it913x_fe_script_loader(state, set_mode); |
| 853 | |
| 854 | ret |= it913x_fe_suspend(state); |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 855 | return (ret < 0) ? -ENODEV : 0; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 856 | } |
| 857 | |
| 858 | static int it913x_fe_init(struct dvb_frontend *fe) |
| 859 | { |
| 860 | struct it913x_fe_state *state = fe->demodulator_priv; |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 861 | int ret = 0; |
Malcolm Priestley | e305288 | 2011-10-01 09:24:16 -0300 | [diff] [blame] | 862 | /* Power Up Tuner - common all versions */ |
| 863 | ret = it913x_write_reg(state, PRO_DMOD, 0xec40, 0x1); |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 864 | |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 865 | ret |= it913x_fe_script_loader(state, init_1); |
| 866 | |
Malcolm Priestley | 990f49a | 2011-11-28 18:04:21 -0300 | [diff] [blame] | 867 | ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x0); |
| 868 | |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 869 | ret |= it913x_write_reg(state, PRO_DMOD, 0xfba8, 0x0); |
Malcolm Priestley | e305288 | 2011-10-01 09:24:16 -0300 | [diff] [blame] | 870 | |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 871 | return (ret < 0) ? -ENODEV : 0; |
| 872 | } |
| 873 | |
| 874 | static void it913x_fe_release(struct dvb_frontend *fe) |
| 875 | { |
| 876 | struct it913x_fe_state *state = fe->demodulator_priv; |
| 877 | kfree(state); |
| 878 | } |
| 879 | |
| 880 | static struct dvb_frontend_ops it913x_fe_ofdm_ops; |
| 881 | |
| 882 | struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap, |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 883 | u8 i2c_addr, struct ite_config *config) |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 884 | { |
| 885 | struct it913x_fe_state *state = NULL; |
| 886 | int ret; |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 887 | |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 888 | /* allocate memory for the internal state */ |
| 889 | state = kzalloc(sizeof(struct it913x_fe_state), GFP_KERNEL); |
| 890 | if (state == NULL) |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 891 | return NULL; |
| 892 | if (config == NULL) |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 893 | goto error; |
| 894 | |
| 895 | state->i2c_adap = i2c_adap; |
| 896 | state->i2c_addr = i2c_addr; |
Malcolm Priestley | b7d425d39 | 2011-10-31 12:02:08 -0300 | [diff] [blame] | 897 | state->config = config; |
| 898 | |
| 899 | switch (state->config->tuner_id_0) { |
| 900 | case IT9135_51: |
| 901 | case IT9135_52: |
| 902 | case IT9135_60: |
| 903 | case IT9135_61: |
| 904 | case IT9135_62: |
| 905 | state->tuner_type = state->config->tuner_id_0; |
| 906 | break; |
| 907 | default: |
| 908 | case IT9135_38: |
| 909 | state->tuner_type = IT9135_38; |
| 910 | } |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 911 | |
| 912 | ret = it913x_fe_start(state); |
| 913 | if (ret < 0) |
| 914 | goto error; |
| 915 | |
| 916 | |
| 917 | /* create dvb_frontend */ |
| 918 | memcpy(&state->frontend.ops, &it913x_fe_ofdm_ops, |
| 919 | sizeof(struct dvb_frontend_ops)); |
| 920 | state->frontend.demodulator_priv = state; |
| 921 | |
| 922 | return &state->frontend; |
| 923 | error: |
| 924 | kfree(state); |
| 925 | return NULL; |
| 926 | } |
| 927 | EXPORT_SYMBOL(it913x_fe_attach); |
| 928 | |
| 929 | static struct dvb_frontend_ops it913x_fe_ofdm_ops = { |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 930 | .delsys = { SYS_DVBT }, |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 931 | .info = { |
| 932 | .name = "it913x-fe DVB-T", |
| 933 | .type = FE_OFDM, |
| 934 | .frequency_min = 51000000, |
| 935 | .frequency_max = 1680000000, |
| 936 | .frequency_stepsize = 62500, |
| 937 | .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | |
| 938 | FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | |
| 939 | FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO | |
| 940 | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | |
| 941 | FE_CAN_TRANSMISSION_MODE_AUTO | |
| 942 | FE_CAN_GUARD_INTERVAL_AUTO | |
| 943 | FE_CAN_HIERARCHY_AUTO, |
| 944 | }, |
| 945 | |
| 946 | .release = it913x_fe_release, |
| 947 | |
| 948 | .init = it913x_fe_init, |
| 949 | .sleep = it913x_fe_sleep, |
| 950 | |
Mauro Carvalho Chehab | f908cf1 | 2011-12-26 11:00:09 -0300 | [diff] [blame] | 951 | .set_frontend = it913x_fe_set_frontend, |
| 952 | .get_frontend = it913x_fe_get_frontend, |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 953 | |
| 954 | .read_status = it913x_fe_read_status, |
| 955 | .read_signal_strength = it913x_fe_read_signal_strength, |
| 956 | .read_snr = it913x_fe_read_snr, |
| 957 | .read_ber = it913x_fe_read_ber, |
| 958 | .read_ucblocks = it913x_fe_read_ucblocks, |
| 959 | }; |
| 960 | |
| 961 | MODULE_DESCRIPTION("it913x Frontend and it9137 tuner"); |
| 962 | MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com"); |
Malcolm Priestley | 990f49a | 2011-11-28 18:04:21 -0300 | [diff] [blame] | 963 | MODULE_VERSION("1.12"); |
Malcolm Priestley | 3dbbf82 | 2011-07-25 15:35:12 -0300 | [diff] [blame] | 964 | MODULE_LICENSE("GPL"); |