Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * offload engine driver for the Marvell XOR engine |
| 3 | * Copyright (C) 2007, 2008, Marvell International Ltd. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <linux/init.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 16 | #include <linux/slab.h> |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 17 | #include <linux/delay.h> |
| 18 | #include <linux/dma-mapping.h> |
| 19 | #include <linux/spinlock.h> |
| 20 | #include <linux/interrupt.h> |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 21 | #include <linux/of_device.h> |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/memory.h> |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 24 | #include <linux/clk.h> |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 25 | #include <linux/of.h> |
| 26 | #include <linux/of_irq.h> |
| 27 | #include <linux/irqdomain.h> |
Thomas Petazzoni | 7775729 | 2015-07-08 16:28:19 +0200 | [diff] [blame] | 28 | #include <linux/cpumask.h> |
Arnd Bergmann | c02cecb | 2012-08-24 15:21:54 +0200 | [diff] [blame] | 29 | #include <linux/platform_data/dma-mv_xor.h> |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 30 | |
| 31 | #include "dmaengine.h" |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 32 | #include "mv_xor.h" |
| 33 | |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame^] | 34 | enum mv_xor_type { |
| 35 | XOR_ORION, |
| 36 | XOR_ARMADA_38X, |
| 37 | }; |
| 38 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 39 | enum mv_xor_mode { |
| 40 | XOR_MODE_IN_REG, |
| 41 | XOR_MODE_IN_DESC, |
| 42 | }; |
| 43 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 44 | static void mv_xor_issue_pending(struct dma_chan *chan); |
| 45 | |
| 46 | #define to_mv_xor_chan(chan) \ |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 47 | container_of(chan, struct mv_xor_chan, dmachan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 48 | |
| 49 | #define to_mv_xor_slot(tx) \ |
| 50 | container_of(tx, struct mv_xor_desc_slot, async_tx) |
| 51 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 52 | #define mv_chan_to_devp(chan) \ |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 53 | ((chan)->dmadev.dev) |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 54 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 55 | static void mv_desc_init(struct mv_xor_desc_slot *desc, |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 56 | dma_addr_t addr, u32 byte_count, |
| 57 | enum dma_ctrl_flags flags) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 58 | { |
| 59 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 60 | |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 61 | hw_desc->status = XOR_DESC_DMA_OWNED; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 62 | hw_desc->phy_next_desc = 0; |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 63 | /* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */ |
| 64 | hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ? |
| 65 | XOR_DESC_EOD_INT_EN : 0; |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 66 | hw_desc->phy_dest_addr = addr; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 67 | hw_desc->byte_count = byte_count; |
| 68 | } |
| 69 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 70 | static void mv_desc_set_mode(struct mv_xor_desc_slot *desc) |
| 71 | { |
| 72 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 73 | |
| 74 | switch (desc->type) { |
| 75 | case DMA_XOR: |
| 76 | case DMA_INTERRUPT: |
| 77 | hw_desc->desc_command |= XOR_DESC_OPERATION_XOR; |
| 78 | break; |
| 79 | case DMA_MEMCPY: |
| 80 | hw_desc->desc_command |= XOR_DESC_OPERATION_MEMCPY; |
| 81 | break; |
| 82 | default: |
| 83 | BUG(); |
| 84 | return; |
| 85 | } |
| 86 | } |
| 87 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 88 | static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc, |
| 89 | u32 next_desc_addr) |
| 90 | { |
| 91 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 92 | BUG_ON(hw_desc->phy_next_desc); |
| 93 | hw_desc->phy_next_desc = next_desc_addr; |
| 94 | } |
| 95 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 96 | static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc, |
| 97 | int index, dma_addr_t addr) |
| 98 | { |
| 99 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
Thomas Petazzoni | e03bc65 | 2013-07-29 17:42:14 +0200 | [diff] [blame] | 100 | hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 101 | if (desc->type == DMA_XOR) |
| 102 | hw_desc->desc_command |= (1 << index); |
| 103 | } |
| 104 | |
| 105 | static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan) |
| 106 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 107 | return readl_relaxed(XOR_CURR_DESC(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan, |
| 111 | u32 next_desc_addr) |
| 112 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 113 | writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 114 | } |
| 115 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 116 | static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan) |
| 117 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 118 | u32 val = readl_relaxed(XOR_INTR_MASK(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 119 | val |= XOR_INTR_MASK_VALUE << (chan->idx * 16); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 120 | writel_relaxed(val, XOR_INTR_MASK(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan) |
| 124 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 125 | u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 126 | intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF; |
| 127 | return intr_cause; |
| 128 | } |
| 129 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 130 | static void mv_chan_clear_eoc_cause(struct mv_xor_chan *chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 131 | { |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 132 | u32 val; |
| 133 | |
| 134 | val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED; |
| 135 | val = ~(val << (chan->idx * 16)); |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 136 | dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 137 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 138 | } |
| 139 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 140 | static void mv_chan_clear_err_status(struct mv_xor_chan *chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 141 | { |
| 142 | u32 val = 0xFFFF0000 >> (chan->idx * 16); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 143 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 144 | } |
| 145 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 146 | static void mv_chan_set_mode(struct mv_xor_chan *chan, |
Thomas Petazzoni | 81aafb3 | 2015-12-22 11:43:28 +0100 | [diff] [blame] | 147 | u32 op_mode) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 148 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 149 | u32 config = readl_relaxed(XOR_CONFIG(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 150 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 151 | config &= ~0x7; |
| 152 | config |= op_mode; |
| 153 | |
Thomas Petazzoni | e03bc65 | 2013-07-29 17:42:14 +0200 | [diff] [blame] | 154 | #if defined(__BIG_ENDIAN) |
| 155 | config |= XOR_DESCRIPTOR_SWAP; |
| 156 | #else |
| 157 | config &= ~XOR_DESCRIPTOR_SWAP; |
| 158 | #endif |
| 159 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 160 | writel_relaxed(config, XOR_CONFIG(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | static void mv_chan_activate(struct mv_xor_chan *chan) |
| 164 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 165 | dev_dbg(mv_chan_to_devp(chan), " activate chan.\n"); |
Ezequiel Garcia | 5a9a55b | 2014-05-21 14:02:35 -0700 | [diff] [blame] | 166 | |
| 167 | /* writel ensures all descriptors are flushed before activation */ |
| 168 | writel(BIT(0), XOR_ACTIVATION(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 169 | } |
| 170 | |
| 171 | static char mv_chan_is_busy(struct mv_xor_chan *chan) |
| 172 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 173 | u32 state = readl_relaxed(XOR_ACTIVATION(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 174 | |
| 175 | state = (state >> 4) & 0x3; |
| 176 | |
| 177 | return (state == 1) ? 1 : 0; |
| 178 | } |
| 179 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 180 | /* |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 181 | * mv_chan_start_new_chain - program the engine to operate on new |
| 182 | * chain headed by sw_desc |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 183 | * Caller must hold &mv_chan->lock while calling this function |
| 184 | */ |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 185 | static void mv_chan_start_new_chain(struct mv_xor_chan *mv_chan, |
| 186 | struct mv_xor_desc_slot *sw_desc) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 187 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 188 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 189 | __func__, __LINE__, sw_desc); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 190 | |
Bartlomiej Zolnierkiewicz | 48a9db4 | 2013-07-03 15:05:06 -0700 | [diff] [blame] | 191 | /* set the hardware chain */ |
| 192 | mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys); |
| 193 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 194 | mv_chan->pending++; |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 195 | mv_xor_issue_pending(&mv_chan->dmachan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | static dma_cookie_t |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 199 | mv_desc_run_tx_complete_actions(struct mv_xor_desc_slot *desc, |
| 200 | struct mv_xor_chan *mv_chan, |
| 201 | dma_cookie_t cookie) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 202 | { |
| 203 | BUG_ON(desc->async_tx.cookie < 0); |
| 204 | |
| 205 | if (desc->async_tx.cookie > 0) { |
| 206 | cookie = desc->async_tx.cookie; |
| 207 | |
| 208 | /* call the callback (must not sleep or submit new |
| 209 | * operations to this channel) |
| 210 | */ |
| 211 | if (desc->async_tx.callback) |
| 212 | desc->async_tx.callback( |
| 213 | desc->async_tx.callback_param); |
| 214 | |
Dan Williams | d38a8c6 | 2013-10-18 19:35:23 +0200 | [diff] [blame] | 215 | dma_descriptor_unmap(&desc->async_tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 216 | } |
| 217 | |
| 218 | /* run dependent operations */ |
Dan Williams | 07f2211 | 2009-01-05 17:14:31 -0700 | [diff] [blame] | 219 | dma_run_dependencies(&desc->async_tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 220 | |
| 221 | return cookie; |
| 222 | } |
| 223 | |
| 224 | static int |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 225 | mv_chan_clean_completed_slots(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 226 | { |
| 227 | struct mv_xor_desc_slot *iter, *_iter; |
| 228 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 229 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 230 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 231 | node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 232 | |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 233 | if (async_tx_test_ack(&iter->async_tx)) |
| 234 | list_move_tail(&iter->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 235 | } |
| 236 | return 0; |
| 237 | } |
| 238 | |
| 239 | static int |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 240 | mv_desc_clean_slot(struct mv_xor_desc_slot *desc, |
| 241 | struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 242 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 243 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 244 | __func__, __LINE__, desc, desc->async_tx.flags); |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 245 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 246 | /* the client is allowed to attach dependent operations |
| 247 | * until 'ack' is set |
| 248 | */ |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 249 | if (!async_tx_test_ack(&desc->async_tx)) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 250 | /* move this slot to the completed_slots */ |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 251 | list_move_tail(&desc->node, &mv_chan->completed_slots); |
| 252 | else |
| 253 | list_move_tail(&desc->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 254 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 255 | return 0; |
| 256 | } |
| 257 | |
Ezequiel Garcia | fbeec99 | 2014-03-07 16:46:47 -0300 | [diff] [blame] | 258 | /* This function must be called with the mv_xor_chan spinlock held */ |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 259 | static void mv_chan_slot_cleanup(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 260 | { |
| 261 | struct mv_xor_desc_slot *iter, *_iter; |
| 262 | dma_cookie_t cookie = 0; |
| 263 | int busy = mv_chan_is_busy(mv_chan); |
| 264 | u32 current_desc = mv_chan_get_current_desc(mv_chan); |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 265 | int current_cleaned = 0; |
| 266 | struct mv_xor_desc *hw_desc; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 267 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 268 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
| 269 | dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 270 | mv_chan_clean_completed_slots(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 271 | |
| 272 | /* free completed slots from the chain starting with |
| 273 | * the oldest descriptor |
| 274 | */ |
| 275 | |
| 276 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 277 | node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 278 | |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 279 | /* clean finished descriptors */ |
| 280 | hw_desc = iter->hw_desc; |
| 281 | if (hw_desc->status & XOR_DESC_SUCCESS) { |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 282 | cookie = mv_desc_run_tx_complete_actions(iter, mv_chan, |
| 283 | cookie); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 284 | |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 285 | /* done processing desc, clean slot */ |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 286 | mv_desc_clean_slot(iter, mv_chan); |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 287 | |
| 288 | /* break if we did cleaned the current */ |
| 289 | if (iter->async_tx.phys == current_desc) { |
| 290 | current_cleaned = 1; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 291 | break; |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 292 | } |
| 293 | } else { |
| 294 | if (iter->async_tx.phys == current_desc) { |
| 295 | current_cleaned = 0; |
| 296 | break; |
| 297 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 298 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 299 | } |
| 300 | |
| 301 | if ((busy == 0) && !list_empty(&mv_chan->chain)) { |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 302 | if (current_cleaned) { |
| 303 | /* |
| 304 | * current descriptor cleaned and removed, run |
| 305 | * from list head |
| 306 | */ |
| 307 | iter = list_entry(mv_chan->chain.next, |
| 308 | struct mv_xor_desc_slot, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 309 | node); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 310 | mv_chan_start_new_chain(mv_chan, iter); |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 311 | } else { |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 312 | if (!list_is_last(&iter->node, &mv_chan->chain)) { |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 313 | /* |
| 314 | * descriptors are still waiting after |
| 315 | * current, trigger them |
| 316 | */ |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 317 | iter = list_entry(iter->node.next, |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 318 | struct mv_xor_desc_slot, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 319 | node); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 320 | mv_chan_start_new_chain(mv_chan, iter); |
Lior Amsalem | 9136291 | 2015-05-26 15:07:32 +0200 | [diff] [blame] | 321 | } else { |
| 322 | /* |
| 323 | * some descriptors are still waiting |
| 324 | * to be cleaned |
| 325 | */ |
| 326 | tasklet_schedule(&mv_chan->irq_tasklet); |
| 327 | } |
| 328 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 329 | } |
| 330 | |
| 331 | if (cookie > 0) |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 332 | mv_chan->dmachan.completed_cookie = cookie; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 333 | } |
| 334 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 335 | static void mv_xor_tasklet(unsigned long data) |
| 336 | { |
| 337 | struct mv_xor_chan *chan = (struct mv_xor_chan *) data; |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 338 | |
| 339 | spin_lock_bh(&chan->lock); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 340 | mv_chan_slot_cleanup(chan); |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 341 | spin_unlock_bh(&chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 342 | } |
| 343 | |
| 344 | static struct mv_xor_desc_slot * |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 345 | mv_chan_alloc_slot(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 346 | { |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 347 | struct mv_xor_desc_slot *iter; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 348 | |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 349 | spin_lock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 350 | |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 351 | if (!list_empty(&mv_chan->free_slots)) { |
| 352 | iter = list_first_entry(&mv_chan->free_slots, |
| 353 | struct mv_xor_desc_slot, |
| 354 | node); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 355 | |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 356 | list_move_tail(&iter->node, &mv_chan->allocated_slots); |
| 357 | |
| 358 | spin_unlock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 359 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 360 | /* pre-ack descriptor */ |
| 361 | async_tx_ack(&iter->async_tx); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 362 | iter->async_tx.cookie = -EBUSY; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 363 | |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 364 | return iter; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 365 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 366 | } |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 367 | |
| 368 | spin_unlock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 369 | |
| 370 | /* try to free some slots if the allocation fails */ |
| 371 | tasklet_schedule(&mv_chan->irq_tasklet); |
| 372 | |
| 373 | return NULL; |
| 374 | } |
| 375 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 376 | /************************ DMA engine API functions ****************************/ |
| 377 | static dma_cookie_t |
| 378 | mv_xor_tx_submit(struct dma_async_tx_descriptor *tx) |
| 379 | { |
| 380 | struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx); |
| 381 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 382 | struct mv_xor_desc_slot *old_chain_tail; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 383 | dma_cookie_t cookie; |
| 384 | int new_hw_chain = 1; |
| 385 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 386 | dev_dbg(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 387 | "%s sw_desc %p: async_tx %p\n", |
| 388 | __func__, sw_desc, &sw_desc->async_tx); |
| 389 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 390 | spin_lock_bh(&mv_chan->lock); |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 391 | cookie = dma_cookie_assign(tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 392 | |
| 393 | if (list_empty(&mv_chan->chain)) |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 394 | list_move_tail(&sw_desc->node, &mv_chan->chain); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 395 | else { |
| 396 | new_hw_chain = 0; |
| 397 | |
| 398 | old_chain_tail = list_entry(mv_chan->chain.prev, |
| 399 | struct mv_xor_desc_slot, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 400 | node); |
| 401 | list_move_tail(&sw_desc->node, &mv_chan->chain); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 402 | |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 403 | dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n", |
| 404 | &old_chain_tail->async_tx.phys); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 405 | |
| 406 | /* fix up the hardware chain */ |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 407 | mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 408 | |
| 409 | /* if the channel is not busy */ |
| 410 | if (!mv_chan_is_busy(mv_chan)) { |
| 411 | u32 current_desc = mv_chan_get_current_desc(mv_chan); |
| 412 | /* |
| 413 | * and the curren desc is the end of the chain before |
| 414 | * the append, then we need to start the channel |
| 415 | */ |
| 416 | if (current_desc == old_chain_tail->async_tx.phys) |
| 417 | new_hw_chain = 1; |
| 418 | } |
| 419 | } |
| 420 | |
| 421 | if (new_hw_chain) |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 422 | mv_chan_start_new_chain(mv_chan, sw_desc); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 423 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 424 | spin_unlock_bh(&mv_chan->lock); |
| 425 | |
| 426 | return cookie; |
| 427 | } |
| 428 | |
| 429 | /* returns the number of allocated descriptors */ |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 430 | static int mv_xor_alloc_chan_resources(struct dma_chan *chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 431 | { |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 432 | void *virt_desc; |
| 433 | dma_addr_t dma_desc; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 434 | int idx; |
| 435 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 436 | struct mv_xor_desc_slot *slot = NULL; |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 437 | int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 438 | |
| 439 | /* Allocate descriptor slots */ |
| 440 | idx = mv_chan->slots_allocated; |
| 441 | while (idx < num_descs_in_pool) { |
| 442 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); |
| 443 | if (!slot) { |
Ezequiel Garcia | b8291dd | 2014-08-27 10:52:49 -0300 | [diff] [blame] | 444 | dev_info(mv_chan_to_devp(mv_chan), |
| 445 | "channel only initialized %d descriptor slots", |
| 446 | idx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 447 | break; |
| 448 | } |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 449 | virt_desc = mv_chan->dma_desc_pool_virt; |
| 450 | slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 451 | |
| 452 | dma_async_tx_descriptor_init(&slot->async_tx, chan); |
| 453 | slot->async_tx.tx_submit = mv_xor_tx_submit; |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 454 | INIT_LIST_HEAD(&slot->node); |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 455 | dma_desc = mv_chan->dma_desc_pool; |
| 456 | slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 457 | slot->idx = idx++; |
| 458 | |
| 459 | spin_lock_bh(&mv_chan->lock); |
| 460 | mv_chan->slots_allocated = idx; |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 461 | list_add_tail(&slot->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 462 | spin_unlock_bh(&mv_chan->lock); |
| 463 | } |
| 464 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 465 | dev_dbg(mv_chan_to_devp(mv_chan), |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 466 | "allocated %d descriptor slots\n", |
| 467 | mv_chan->slots_allocated); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 468 | |
| 469 | return mv_chan->slots_allocated ? : -ENOMEM; |
| 470 | } |
| 471 | |
| 472 | static struct dma_async_tx_descriptor * |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 473 | mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
| 474 | unsigned int src_cnt, size_t len, unsigned long flags) |
| 475 | { |
| 476 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 477 | struct mv_xor_desc_slot *sw_desc; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 478 | |
| 479 | if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) |
| 480 | return NULL; |
| 481 | |
Coly Li | 7912d30 | 2011-03-27 01:26:53 +0800 | [diff] [blame] | 482 | BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 483 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 484 | dev_dbg(mv_chan_to_devp(mv_chan), |
Gregory CLEMENT | bc822e1 | 2016-04-29 09:49:05 +0200 | [diff] [blame] | 485 | "%s src_cnt: %d len: %zu dest %pad flags: %ld\n", |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 486 | __func__, src_cnt, len, &dest, flags); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 487 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 488 | sw_desc = mv_chan_alloc_slot(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 489 | if (sw_desc) { |
| 490 | sw_desc->type = DMA_XOR; |
| 491 | sw_desc->async_tx.flags = flags; |
Lior Amsalem | ba87d13 | 2014-08-27 10:52:53 -0300 | [diff] [blame] | 492 | mv_desc_init(sw_desc, dest, len, flags); |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 493 | if (mv_chan->op_in_desc == XOR_MODE_IN_DESC) |
| 494 | mv_desc_set_mode(sw_desc); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 495 | while (src_cnt--) |
Lior Amsalem | dfc9766 | 2014-08-27 10:52:51 -0300 | [diff] [blame] | 496 | mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 497 | } |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 498 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 499 | dev_dbg(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 500 | "%s sw_desc %p async_tx %p \n", |
| 501 | __func__, sw_desc, &sw_desc->async_tx); |
| 502 | return sw_desc ? &sw_desc->async_tx : NULL; |
| 503 | } |
| 504 | |
Lior Amsalem | 3e4f52e | 2014-08-27 10:52:50 -0300 | [diff] [blame] | 505 | static struct dma_async_tx_descriptor * |
| 506 | mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
| 507 | size_t len, unsigned long flags) |
| 508 | { |
| 509 | /* |
| 510 | * A MEMCPY operation is identical to an XOR operation with only |
| 511 | * a single source address. |
| 512 | */ |
| 513 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); |
| 514 | } |
| 515 | |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 516 | static struct dma_async_tx_descriptor * |
| 517 | mv_xor_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) |
| 518 | { |
| 519 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 520 | dma_addr_t src, dest; |
| 521 | size_t len; |
| 522 | |
| 523 | src = mv_chan->dummy_src_addr; |
| 524 | dest = mv_chan->dummy_dst_addr; |
| 525 | len = MV_XOR_MIN_BYTE_COUNT; |
| 526 | |
| 527 | /* |
| 528 | * We implement the DMA_INTERRUPT operation as a minimum sized |
| 529 | * XOR operation with a single dummy source address. |
| 530 | */ |
| 531 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); |
| 532 | } |
| 533 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 534 | static void mv_xor_free_chan_resources(struct dma_chan *chan) |
| 535 | { |
| 536 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 537 | struct mv_xor_desc_slot *iter, *_iter; |
| 538 | int in_use_descs = 0; |
| 539 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 540 | spin_lock_bh(&mv_chan->lock); |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 541 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 542 | mv_chan_slot_cleanup(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 543 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 544 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 545 | node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 546 | in_use_descs++; |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 547 | list_move_tail(&iter->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 548 | } |
| 549 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 550 | node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 551 | in_use_descs++; |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 552 | list_move_tail(&iter->node, &mv_chan->free_slots); |
| 553 | } |
| 554 | list_for_each_entry_safe(iter, _iter, &mv_chan->allocated_slots, |
| 555 | node) { |
| 556 | in_use_descs++; |
| 557 | list_move_tail(&iter->node, &mv_chan->free_slots); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 558 | } |
| 559 | list_for_each_entry_safe_reverse( |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 560 | iter, _iter, &mv_chan->free_slots, node) { |
| 561 | list_del(&iter->node); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 562 | kfree(iter); |
| 563 | mv_chan->slots_allocated--; |
| 564 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 565 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 566 | dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 567 | __func__, mv_chan->slots_allocated); |
| 568 | spin_unlock_bh(&mv_chan->lock); |
| 569 | |
| 570 | if (in_use_descs) |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 571 | dev_err(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 572 | "freeing %d in use descriptors!\n", in_use_descs); |
| 573 | } |
| 574 | |
| 575 | /** |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 576 | * mv_xor_status - poll the status of an XOR transaction |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 577 | * @chan: XOR channel handle |
| 578 | * @cookie: XOR transaction identifier |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 579 | * @txstate: XOR transactions state holder (or NULL) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 580 | */ |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 581 | static enum dma_status mv_xor_status(struct dma_chan *chan, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 582 | dma_cookie_t cookie, |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 583 | struct dma_tx_state *txstate) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 584 | { |
| 585 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 586 | enum dma_status ret; |
| 587 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 588 | ret = dma_cookie_status(chan, cookie, txstate); |
Ezequiel Garcia | 890766d | 2014-03-07 16:46:45 -0300 | [diff] [blame] | 589 | if (ret == DMA_COMPLETE) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 590 | return ret; |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 591 | |
| 592 | spin_lock_bh(&mv_chan->lock); |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 593 | mv_chan_slot_cleanup(mv_chan); |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame] | 594 | spin_unlock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 595 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 596 | return dma_cookie_status(chan, cookie, txstate); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 597 | } |
| 598 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 599 | static void mv_chan_dump_regs(struct mv_xor_chan *chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 600 | { |
| 601 | u32 val; |
| 602 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 603 | val = readl_relaxed(XOR_CONFIG(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 604 | dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 605 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 606 | val = readl_relaxed(XOR_ACTIVATION(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 607 | dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 608 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 609 | val = readl_relaxed(XOR_INTR_CAUSE(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 610 | dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 611 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 612 | val = readl_relaxed(XOR_INTR_MASK(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 613 | dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 614 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 615 | val = readl_relaxed(XOR_ERROR_CAUSE(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 616 | dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 617 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 618 | val = readl_relaxed(XOR_ERROR_ADDR(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 619 | dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 620 | } |
| 621 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 622 | static void mv_chan_err_interrupt_handler(struct mv_xor_chan *chan, |
| 623 | u32 intr_cause) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 624 | { |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 625 | if (intr_cause & XOR_INT_ERR_DECODE) { |
| 626 | dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n"); |
| 627 | return; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 628 | } |
| 629 | |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 630 | dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n", |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 631 | chan->idx, intr_cause); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 632 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 633 | mv_chan_dump_regs(chan); |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 634 | WARN_ON(1); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 635 | } |
| 636 | |
| 637 | static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) |
| 638 | { |
| 639 | struct mv_xor_chan *chan = data; |
| 640 | u32 intr_cause = mv_chan_get_intr_cause(chan); |
| 641 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 642 | dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 643 | |
Ezequiel Garcia | 0e7488e | 2014-08-27 10:52:52 -0300 | [diff] [blame] | 644 | if (intr_cause & XOR_INTR_ERRORS) |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 645 | mv_chan_err_interrupt_handler(chan, intr_cause); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 646 | |
| 647 | tasklet_schedule(&chan->irq_tasklet); |
| 648 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 649 | mv_chan_clear_eoc_cause(chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 650 | |
| 651 | return IRQ_HANDLED; |
| 652 | } |
| 653 | |
| 654 | static void mv_xor_issue_pending(struct dma_chan *chan) |
| 655 | { |
| 656 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 657 | |
| 658 | if (mv_chan->pending >= MV_XOR_THRESHOLD) { |
| 659 | mv_chan->pending = 0; |
| 660 | mv_chan_activate(mv_chan); |
| 661 | } |
| 662 | } |
| 663 | |
| 664 | /* |
| 665 | * Perform a transaction to verify the HW works. |
| 666 | */ |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 667 | |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 668 | static int mv_chan_memcpy_self_test(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 669 | { |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 670 | int i, ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 671 | void *src, *dest; |
| 672 | dma_addr_t src_dma, dest_dma; |
| 673 | struct dma_chan *dma_chan; |
| 674 | dma_cookie_t cookie; |
| 675 | struct dma_async_tx_descriptor *tx; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 676 | struct dmaengine_unmap_data *unmap; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 677 | int err = 0; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 678 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 679 | src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 680 | if (!src) |
| 681 | return -ENOMEM; |
| 682 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 683 | dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 684 | if (!dest) { |
| 685 | kfree(src); |
| 686 | return -ENOMEM; |
| 687 | } |
| 688 | |
| 689 | /* Fill in src buffer */ |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 690 | for (i = 0; i < PAGE_SIZE; i++) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 691 | ((u8 *) src)[i] = (u8)i; |
| 692 | |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 693 | dma_chan = &mv_chan->dmachan; |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 694 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 695 | err = -ENODEV; |
| 696 | goto out; |
| 697 | } |
| 698 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 699 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL); |
| 700 | if (!unmap) { |
| 701 | err = -ENOMEM; |
| 702 | goto free_resources; |
| 703 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 704 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 705 | src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), 0, |
| 706 | PAGE_SIZE, DMA_TO_DEVICE); |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 707 | unmap->addr[0] = src_dma; |
| 708 | |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 709 | ret = dma_mapping_error(dma_chan->device->dev, src_dma); |
| 710 | if (ret) { |
| 711 | err = -ENOMEM; |
| 712 | goto free_resources; |
| 713 | } |
| 714 | unmap->to_cnt = 1; |
| 715 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 716 | dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), 0, |
| 717 | PAGE_SIZE, DMA_FROM_DEVICE); |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 718 | unmap->addr[1] = dest_dma; |
| 719 | |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 720 | ret = dma_mapping_error(dma_chan->device->dev, dest_dma); |
| 721 | if (ret) { |
| 722 | err = -ENOMEM; |
| 723 | goto free_resources; |
| 724 | } |
| 725 | unmap->from_cnt = 1; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 726 | unmap->len = PAGE_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 727 | |
| 728 | tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 729 | PAGE_SIZE, 0); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 730 | if (!tx) { |
| 731 | dev_err(dma_chan->device->dev, |
| 732 | "Self-test cannot prepare operation, disabling\n"); |
| 733 | err = -ENODEV; |
| 734 | goto free_resources; |
| 735 | } |
| 736 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 737 | cookie = mv_xor_tx_submit(tx); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 738 | if (dma_submit_error(cookie)) { |
| 739 | dev_err(dma_chan->device->dev, |
| 740 | "Self-test submit error, disabling\n"); |
| 741 | err = -ENODEV; |
| 742 | goto free_resources; |
| 743 | } |
| 744 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 745 | mv_xor_issue_pending(dma_chan); |
| 746 | async_tx_ack(tx); |
| 747 | msleep(1); |
| 748 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 749 | if (mv_xor_status(dma_chan, cookie, NULL) != |
Vinod Koul | b3efb8f | 2013-10-16 20:51:04 +0530 | [diff] [blame] | 750 | DMA_COMPLETE) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 751 | dev_err(dma_chan->device->dev, |
| 752 | "Self-test copy timed out, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 753 | err = -ENODEV; |
| 754 | goto free_resources; |
| 755 | } |
| 756 | |
Thomas Petazzoni | c35064c | 2012-11-15 13:01:59 +0100 | [diff] [blame] | 757 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 758 | PAGE_SIZE, DMA_FROM_DEVICE); |
| 759 | if (memcmp(src, dest, PAGE_SIZE)) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 760 | dev_err(dma_chan->device->dev, |
| 761 | "Self-test copy failed compare, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 762 | err = -ENODEV; |
| 763 | goto free_resources; |
| 764 | } |
| 765 | |
| 766 | free_resources: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 767 | dmaengine_unmap_put(unmap); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 768 | mv_xor_free_chan_resources(dma_chan); |
| 769 | out: |
| 770 | kfree(src); |
| 771 | kfree(dest); |
| 772 | return err; |
| 773 | } |
| 774 | |
| 775 | #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */ |
Bill Pemberton | 463a1f8 | 2012-11-19 13:22:55 -0500 | [diff] [blame] | 776 | static int |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 777 | mv_chan_xor_self_test(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 778 | { |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 779 | int i, src_idx, ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 780 | struct page *dest; |
| 781 | struct page *xor_srcs[MV_XOR_NUM_SRC_TEST]; |
| 782 | dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST]; |
| 783 | dma_addr_t dest_dma; |
| 784 | struct dma_async_tx_descriptor *tx; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 785 | struct dmaengine_unmap_data *unmap; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 786 | struct dma_chan *dma_chan; |
| 787 | dma_cookie_t cookie; |
| 788 | u8 cmp_byte = 0; |
| 789 | u32 cmp_word; |
| 790 | int err = 0; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 791 | int src_count = MV_XOR_NUM_SRC_TEST; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 792 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 793 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 794 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 795 | if (!xor_srcs[src_idx]) { |
| 796 | while (src_idx--) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 797 | __free_page(xor_srcs[src_idx]); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 798 | return -ENOMEM; |
| 799 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 800 | } |
| 801 | |
| 802 | dest = alloc_page(GFP_KERNEL); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 803 | if (!dest) { |
| 804 | while (src_idx--) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 805 | __free_page(xor_srcs[src_idx]); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 806 | return -ENOMEM; |
| 807 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 808 | |
| 809 | /* Fill in src buffers */ |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 810 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 811 | u8 *ptr = page_address(xor_srcs[src_idx]); |
| 812 | for (i = 0; i < PAGE_SIZE; i++) |
| 813 | ptr[i] = (1 << src_idx); |
| 814 | } |
| 815 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 816 | for (src_idx = 0; src_idx < src_count; src_idx++) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 817 | cmp_byte ^= (u8) (1 << src_idx); |
| 818 | |
| 819 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | |
| 820 | (cmp_byte << 8) | cmp_byte; |
| 821 | |
| 822 | memset(page_address(dest), 0, PAGE_SIZE); |
| 823 | |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 824 | dma_chan = &mv_chan->dmachan; |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 825 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 826 | err = -ENODEV; |
| 827 | goto out; |
| 828 | } |
| 829 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 830 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1, |
| 831 | GFP_KERNEL); |
| 832 | if (!unmap) { |
| 833 | err = -ENOMEM; |
| 834 | goto free_resources; |
| 835 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 836 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 837 | /* test xor */ |
| 838 | for (i = 0; i < src_count; i++) { |
| 839 | unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], |
| 840 | 0, PAGE_SIZE, DMA_TO_DEVICE); |
| 841 | dma_srcs[i] = unmap->addr[i]; |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 842 | ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[i]); |
| 843 | if (ret) { |
| 844 | err = -ENOMEM; |
| 845 | goto free_resources; |
| 846 | } |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 847 | unmap->to_cnt++; |
| 848 | } |
| 849 | |
| 850 | unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE, |
| 851 | DMA_FROM_DEVICE); |
| 852 | dest_dma = unmap->addr[src_count]; |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 853 | ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[src_count]); |
| 854 | if (ret) { |
| 855 | err = -ENOMEM; |
| 856 | goto free_resources; |
| 857 | } |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 858 | unmap->from_cnt = 1; |
| 859 | unmap->len = PAGE_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 860 | |
| 861 | tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 862 | src_count, PAGE_SIZE, 0); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 863 | if (!tx) { |
| 864 | dev_err(dma_chan->device->dev, |
| 865 | "Self-test cannot prepare operation, disabling\n"); |
| 866 | err = -ENODEV; |
| 867 | goto free_resources; |
| 868 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 869 | |
| 870 | cookie = mv_xor_tx_submit(tx); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 871 | if (dma_submit_error(cookie)) { |
| 872 | dev_err(dma_chan->device->dev, |
| 873 | "Self-test submit error, disabling\n"); |
| 874 | err = -ENODEV; |
| 875 | goto free_resources; |
| 876 | } |
| 877 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 878 | mv_xor_issue_pending(dma_chan); |
| 879 | async_tx_ack(tx); |
| 880 | msleep(8); |
| 881 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 882 | if (mv_xor_status(dma_chan, cookie, NULL) != |
Vinod Koul | b3efb8f | 2013-10-16 20:51:04 +0530 | [diff] [blame] | 883 | DMA_COMPLETE) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 884 | dev_err(dma_chan->device->dev, |
| 885 | "Self-test xor timed out, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 886 | err = -ENODEV; |
| 887 | goto free_resources; |
| 888 | } |
| 889 | |
Thomas Petazzoni | c35064c | 2012-11-15 13:01:59 +0100 | [diff] [blame] | 890 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 891 | PAGE_SIZE, DMA_FROM_DEVICE); |
| 892 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { |
| 893 | u32 *ptr = page_address(dest); |
| 894 | if (ptr[i] != cmp_word) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 895 | dev_err(dma_chan->device->dev, |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 896 | "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n", |
| 897 | i, ptr[i], cmp_word); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 898 | err = -ENODEV; |
| 899 | goto free_resources; |
| 900 | } |
| 901 | } |
| 902 | |
| 903 | free_resources: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 904 | dmaengine_unmap_put(unmap); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 905 | mv_xor_free_chan_resources(dma_chan); |
| 906 | out: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 907 | src_idx = src_count; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 908 | while (src_idx--) |
| 909 | __free_page(xor_srcs[src_idx]); |
| 910 | __free_page(dest); |
| 911 | return err; |
| 912 | } |
| 913 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 914 | static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 915 | { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 916 | struct dma_chan *chan, *_chan; |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 917 | struct device *dev = mv_chan->dmadev.dev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 918 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 919 | dma_async_device_unregister(&mv_chan->dmadev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 920 | |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 921 | dma_free_coherent(dev, MV_XOR_POOL_SIZE, |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 922 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 923 | dma_unmap_single(dev, mv_chan->dummy_src_addr, |
| 924 | MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); |
| 925 | dma_unmap_single(dev, mv_chan->dummy_dst_addr, |
| 926 | MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 927 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 928 | list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels, |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 929 | device_node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 930 | list_del(&chan->device_node); |
| 931 | } |
| 932 | |
Thomas Petazzoni | 88eb92c | 2012-11-15 16:11:18 +0100 | [diff] [blame] | 933 | free_irq(mv_chan->irq, mv_chan); |
| 934 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 935 | return 0; |
| 936 | } |
| 937 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 938 | static struct mv_xor_chan * |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 939 | mv_xor_channel_add(struct mv_xor_device *xordev, |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 940 | struct platform_device *pdev, |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame^] | 941 | int idx, dma_cap_mask_t cap_mask, int irq) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 942 | { |
| 943 | int ret = 0; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 944 | struct mv_xor_chan *mv_chan; |
| 945 | struct dma_device *dma_dev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 946 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 947 | mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL); |
Sachin Kamat | a577659 | 2013-09-02 13:54:20 +0530 | [diff] [blame] | 948 | if (!mv_chan) |
| 949 | return ERR_PTR(-ENOMEM); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 950 | |
Thomas Petazzoni | 9aedbdb | 2012-11-15 15:36:37 +0100 | [diff] [blame] | 951 | mv_chan->idx = idx; |
Thomas Petazzoni | 88eb92c | 2012-11-15 16:11:18 +0100 | [diff] [blame] | 952 | mv_chan->irq = irq; |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame^] | 953 | if (xordev->xor_type == XOR_ORION) |
| 954 | mv_chan->op_in_desc = XOR_MODE_IN_REG; |
| 955 | else |
| 956 | mv_chan->op_in_desc = XOR_MODE_IN_DESC; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 957 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 958 | dma_dev = &mv_chan->dmadev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 959 | |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 960 | /* |
| 961 | * These source and destination dummy buffers are used to implement |
| 962 | * a DMA_INTERRUPT operation as a minimum-sized XOR operation. |
| 963 | * Hence, we only need to map the buffers at initialization-time. |
| 964 | */ |
| 965 | mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev, |
| 966 | mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); |
| 967 | mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev, |
| 968 | mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); |
| 969 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 970 | /* allocate coherent memory for hardware descriptors |
| 971 | * note: writecombine gives slightly better performance, but |
| 972 | * requires that we explicitly flush the writes |
| 973 | */ |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 974 | mv_chan->dma_desc_pool_virt = |
Luis R. Rodriguez | f6e4566 | 2016-01-22 18:34:22 -0800 | [diff] [blame] | 975 | dma_alloc_wc(&pdev->dev, MV_XOR_POOL_SIZE, &mv_chan->dma_desc_pool, |
| 976 | GFP_KERNEL); |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 977 | if (!mv_chan->dma_desc_pool_virt) |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 978 | return ERR_PTR(-ENOMEM); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 979 | |
| 980 | /* discover transaction capabilites from the platform data */ |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 981 | dma_dev->cap_mask = cap_mask; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 982 | |
| 983 | INIT_LIST_HEAD(&dma_dev->channels); |
| 984 | |
| 985 | /* set base routines */ |
| 986 | dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources; |
| 987 | dma_dev->device_free_chan_resources = mv_xor_free_chan_resources; |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 988 | dma_dev->device_tx_status = mv_xor_status; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 989 | dma_dev->device_issue_pending = mv_xor_issue_pending; |
| 990 | dma_dev->dev = &pdev->dev; |
| 991 | |
| 992 | /* set prep routines based on capability */ |
Lior Amsalem | 2284354 | 2014-08-27 10:52:55 -0300 | [diff] [blame] | 993 | if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) |
| 994 | dma_dev->device_prep_dma_interrupt = mv_xor_prep_dma_interrupt; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 995 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) |
| 996 | dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 997 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
Joe Perches | c019894 | 2009-06-28 09:26:21 -0700 | [diff] [blame] | 998 | dma_dev->max_xor = 8; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 999 | dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor; |
| 1000 | } |
| 1001 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1002 | mv_chan->mmr_base = xordev->xor_base; |
Ezequiel Garcia | 82a1402 | 2013-10-30 12:01:43 -0300 | [diff] [blame] | 1003 | mv_chan->mmr_high_base = xordev->xor_high_base; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1004 | tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long) |
| 1005 | mv_chan); |
| 1006 | |
| 1007 | /* clear errors before enabling interrupts */ |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 1008 | mv_chan_clear_err_status(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1009 | |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1010 | ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler, |
| 1011 | 0, dev_name(&pdev->dev), mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1012 | if (ret) |
| 1013 | goto err_free_dma; |
| 1014 | |
| 1015 | mv_chan_unmask_interrupts(mv_chan); |
| 1016 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1017 | if (mv_chan->op_in_desc == XOR_MODE_IN_DESC) |
Thomas Petazzoni | 81aafb3 | 2015-12-22 11:43:28 +0100 | [diff] [blame] | 1018 | mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_IN_DESC); |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1019 | else |
Thomas Petazzoni | 81aafb3 | 2015-12-22 11:43:28 +0100 | [diff] [blame] | 1020 | mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_XOR); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1021 | |
| 1022 | spin_lock_init(&mv_chan->lock); |
| 1023 | INIT_LIST_HEAD(&mv_chan->chain); |
| 1024 | INIT_LIST_HEAD(&mv_chan->completed_slots); |
Lior Amsalem | fbea28a | 2015-05-26 15:07:36 +0200 | [diff] [blame] | 1025 | INIT_LIST_HEAD(&mv_chan->free_slots); |
| 1026 | INIT_LIST_HEAD(&mv_chan->allocated_slots); |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 1027 | mv_chan->dmachan.device = dma_dev; |
| 1028 | dma_cookie_init(&mv_chan->dmachan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1029 | |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 1030 | list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1031 | |
| 1032 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 1033 | ret = mv_chan_memcpy_self_test(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1034 | dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); |
| 1035 | if (ret) |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1036 | goto err_free_irq; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1037 | } |
| 1038 | |
| 1039 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
Maxime Ripard | 0951e72 | 2015-05-26 15:07:33 +0200 | [diff] [blame] | 1040 | ret = mv_chan_xor_self_test(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1041 | dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); |
| 1042 | if (ret) |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1043 | goto err_free_irq; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1044 | } |
| 1045 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1046 | dev_info(&pdev->dev, "Marvell XOR (%s): ( %s%s%s)\n", |
| 1047 | mv_chan->op_in_desc ? "Descriptor Mode" : "Registers Mode", |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1048 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1049 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", |
| 1050 | dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1051 | |
| 1052 | dma_async_device_register(dma_dev); |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1053 | return mv_chan; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1054 | |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1055 | err_free_irq: |
| 1056 | free_irq(mv_chan->irq, mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1057 | err_free_dma: |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 1058 | dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE, |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1059 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 1060 | return ERR_PTR(ret); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1061 | } |
| 1062 | |
| 1063 | static void |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1064 | mv_xor_conf_mbus_windows(struct mv_xor_device *xordev, |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1065 | const struct mbus_dram_target_info *dram) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1066 | { |
Ezequiel Garcia | 82a1402 | 2013-10-30 12:01:43 -0300 | [diff] [blame] | 1067 | void __iomem *base = xordev->xor_high_base; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1068 | u32 win_enable = 0; |
| 1069 | int i; |
| 1070 | |
| 1071 | for (i = 0; i < 8; i++) { |
| 1072 | writel(0, base + WINDOW_BASE(i)); |
| 1073 | writel(0, base + WINDOW_SIZE(i)); |
| 1074 | if (i < 4) |
| 1075 | writel(0, base + WINDOW_REMAP_HIGH(i)); |
| 1076 | } |
| 1077 | |
| 1078 | for (i = 0; i < dram->num_cs; i++) { |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1079 | const struct mbus_dram_window *cs = dram->cs + i; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1080 | |
| 1081 | writel((cs->base & 0xffff0000) | |
| 1082 | (cs->mbus_attr << 8) | |
| 1083 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); |
| 1084 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); |
| 1085 | |
| 1086 | win_enable |= (1 << i); |
| 1087 | win_enable |= 3 << (16 + (2 * i)); |
| 1088 | } |
| 1089 | |
| 1090 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); |
| 1091 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); |
Thomas Petazzoni | c4b4b73 | 2012-11-22 18:16:37 +0100 | [diff] [blame] | 1092 | writel(0, base + WINDOW_OVERRIDE_CTRL(0)); |
| 1093 | writel(0, base + WINDOW_OVERRIDE_CTRL(1)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1094 | } |
| 1095 | |
Thomas Petazzoni | 8b64843 | 2015-12-22 11:43:29 +0100 | [diff] [blame] | 1096 | /* |
| 1097 | * Since this XOR driver is basically used only for RAID5, we don't |
| 1098 | * need to care about synchronizing ->suspend with DMA activity, |
| 1099 | * because the DMA engine will naturally be quiet due to the block |
| 1100 | * devices being suspended. |
| 1101 | */ |
| 1102 | static int mv_xor_suspend(struct platform_device *pdev, pm_message_t state) |
| 1103 | { |
| 1104 | struct mv_xor_device *xordev = platform_get_drvdata(pdev); |
| 1105 | int i; |
| 1106 | |
| 1107 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { |
| 1108 | struct mv_xor_chan *mv_chan = xordev->channels[i]; |
| 1109 | |
| 1110 | if (!mv_chan) |
| 1111 | continue; |
| 1112 | |
| 1113 | mv_chan->saved_config_reg = |
| 1114 | readl_relaxed(XOR_CONFIG(mv_chan)); |
| 1115 | mv_chan->saved_int_mask_reg = |
| 1116 | readl_relaxed(XOR_INTR_MASK(mv_chan)); |
| 1117 | } |
| 1118 | |
| 1119 | return 0; |
| 1120 | } |
| 1121 | |
| 1122 | static int mv_xor_resume(struct platform_device *dev) |
| 1123 | { |
| 1124 | struct mv_xor_device *xordev = platform_get_drvdata(dev); |
| 1125 | const struct mbus_dram_target_info *dram; |
| 1126 | int i; |
| 1127 | |
| 1128 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { |
| 1129 | struct mv_xor_chan *mv_chan = xordev->channels[i]; |
| 1130 | |
| 1131 | if (!mv_chan) |
| 1132 | continue; |
| 1133 | |
| 1134 | writel_relaxed(mv_chan->saved_config_reg, |
| 1135 | XOR_CONFIG(mv_chan)); |
| 1136 | writel_relaxed(mv_chan->saved_int_mask_reg, |
| 1137 | XOR_INTR_MASK(mv_chan)); |
| 1138 | } |
| 1139 | |
| 1140 | dram = mv_mbus_dram_info(); |
| 1141 | if (dram) |
| 1142 | mv_xor_conf_mbus_windows(xordev, dram); |
| 1143 | |
| 1144 | return 0; |
| 1145 | } |
| 1146 | |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1147 | static const struct of_device_id mv_xor_dt_ids[] = { |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame^] | 1148 | { .compatible = "marvell,orion-xor", .data = (void *)XOR_ORION }, |
| 1149 | { .compatible = "marvell,armada-380-xor", .data = (void *)XOR_ARMADA_38X }, |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1150 | {}, |
| 1151 | }; |
Lior Amsalem | 6f16631 | 2015-05-26 15:07:34 +0200 | [diff] [blame] | 1152 | |
Thomas Petazzoni | 7775729 | 2015-07-08 16:28:19 +0200 | [diff] [blame] | 1153 | static unsigned int mv_xor_engine_count; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1154 | |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 1155 | static int mv_xor_probe(struct platform_device *pdev) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1156 | { |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1157 | const struct mbus_dram_target_info *dram; |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1158 | struct mv_xor_device *xordev; |
Jingoo Han | d4adcc0 | 2013-07-30 17:09:11 +0900 | [diff] [blame] | 1159 | struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1160 | struct resource *res; |
Thomas Petazzoni | 7775729 | 2015-07-08 16:28:19 +0200 | [diff] [blame] | 1161 | unsigned int max_engines, max_channels; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1162 | int i, ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1163 | |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1164 | dev_notice(&pdev->dev, "Marvell shared XOR driver\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1165 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1166 | xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL); |
| 1167 | if (!xordev) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1168 | return -ENOMEM; |
| 1169 | |
| 1170 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1171 | if (!res) |
| 1172 | return -ENODEV; |
| 1173 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1174 | xordev->xor_base = devm_ioremap(&pdev->dev, res->start, |
| 1175 | resource_size(res)); |
| 1176 | if (!xordev->xor_base) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1177 | return -EBUSY; |
| 1178 | |
| 1179 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
| 1180 | if (!res) |
| 1181 | return -ENODEV; |
| 1182 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1183 | xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start, |
| 1184 | resource_size(res)); |
| 1185 | if (!xordev->xor_high_base) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1186 | return -EBUSY; |
| 1187 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1188 | platform_set_drvdata(pdev, xordev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1189 | |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame^] | 1190 | |
| 1191 | /* |
| 1192 | * We need to know which type of XOR device we use before |
| 1193 | * setting up. In non-dt case it can only be the legacy one. |
| 1194 | */ |
| 1195 | xordev->xor_type = XOR_ORION; |
| 1196 | if (pdev->dev.of_node) { |
| 1197 | const struct of_device_id *of_id = |
| 1198 | of_match_device(mv_xor_dt_ids, |
| 1199 | &pdev->dev); |
| 1200 | |
| 1201 | xordev->xor_type = (uintptr_t)of_id->data; |
| 1202 | } |
| 1203 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1204 | /* |
| 1205 | * (Re-)program MBUS remapping windows if we are asked to. |
| 1206 | */ |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1207 | dram = mv_mbus_dram_info(); |
| 1208 | if (dram) |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1209 | mv_xor_conf_mbus_windows(xordev, dram); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1210 | |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1211 | /* Not all platforms can gate the clock, so it is not |
| 1212 | * an error if the clock does not exists. |
| 1213 | */ |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1214 | xordev->clk = clk_get(&pdev->dev, NULL); |
| 1215 | if (!IS_ERR(xordev->clk)) |
| 1216 | clk_prepare_enable(xordev->clk); |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1217 | |
Thomas Petazzoni | 7775729 | 2015-07-08 16:28:19 +0200 | [diff] [blame] | 1218 | /* |
| 1219 | * We don't want to have more than one channel per CPU in |
| 1220 | * order for async_tx to perform well. So we limit the number |
| 1221 | * of engines and channels so that we take into account this |
| 1222 | * constraint. Note that we also want to use channels from |
| 1223 | * separate engines when possible. |
| 1224 | */ |
| 1225 | max_engines = num_present_cpus(); |
| 1226 | max_channels = min_t(unsigned int, |
| 1227 | MV_XOR_MAX_CHANNELS, |
| 1228 | DIV_ROUND_UP(num_present_cpus(), 2)); |
| 1229 | |
| 1230 | if (mv_xor_engine_count >= max_engines) |
| 1231 | return 0; |
| 1232 | |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1233 | if (pdev->dev.of_node) { |
| 1234 | struct device_node *np; |
| 1235 | int i = 0; |
| 1236 | |
| 1237 | for_each_child_of_node(pdev->dev.of_node, np) { |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1238 | struct mv_xor_chan *chan; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1239 | dma_cap_mask_t cap_mask; |
| 1240 | int irq; |
| 1241 | |
Thomas Petazzoni | 7775729 | 2015-07-08 16:28:19 +0200 | [diff] [blame] | 1242 | if (i >= max_channels) |
| 1243 | continue; |
| 1244 | |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1245 | dma_cap_zero(cap_mask); |
Thomas Petazzoni | 6d8f7ab | 2015-07-08 16:28:16 +0200 | [diff] [blame] | 1246 | dma_cap_set(DMA_MEMCPY, cap_mask); |
| 1247 | dma_cap_set(DMA_XOR, cap_mask); |
| 1248 | dma_cap_set(DMA_INTERRUPT, cap_mask); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1249 | |
| 1250 | irq = irq_of_parse_and_map(np, 0); |
Thomas Petazzoni | f8eb9e7 | 2012-11-22 18:22:12 +0100 | [diff] [blame] | 1251 | if (!irq) { |
| 1252 | ret = -ENODEV; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1253 | goto err_channel_add; |
| 1254 | } |
| 1255 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1256 | chan = mv_xor_channel_add(xordev, pdev, i, |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame^] | 1257 | cap_mask, irq); |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1258 | if (IS_ERR(chan)) { |
| 1259 | ret = PTR_ERR(chan); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1260 | irq_dispose_mapping(irq); |
| 1261 | goto err_channel_add; |
| 1262 | } |
| 1263 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1264 | xordev->channels[i] = chan; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1265 | i++; |
| 1266 | } |
| 1267 | } else if (pdata && pdata->channels) { |
Thomas Petazzoni | 7775729 | 2015-07-08 16:28:19 +0200 | [diff] [blame] | 1268 | for (i = 0; i < max_channels; i++) { |
Thomas Petazzoni | e39f6ec | 2012-10-30 11:56:26 +0100 | [diff] [blame] | 1269 | struct mv_xor_channel_data *cd; |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1270 | struct mv_xor_chan *chan; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1271 | int irq; |
| 1272 | |
| 1273 | cd = &pdata->channels[i]; |
| 1274 | if (!cd) { |
| 1275 | ret = -ENODEV; |
| 1276 | goto err_channel_add; |
| 1277 | } |
| 1278 | |
| 1279 | irq = platform_get_irq(pdev, i); |
| 1280 | if (irq < 0) { |
| 1281 | ret = irq; |
| 1282 | goto err_channel_add; |
| 1283 | } |
| 1284 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1285 | chan = mv_xor_channel_add(xordev, pdev, i, |
Gregory CLEMENT | dd130c6 | 2016-04-29 09:49:06 +0200 | [diff] [blame^] | 1286 | cd->cap_mask, irq); |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1287 | if (IS_ERR(chan)) { |
| 1288 | ret = PTR_ERR(chan); |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1289 | goto err_channel_add; |
| 1290 | } |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1291 | |
| 1292 | xordev->channels[i] = chan; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1293 | } |
| 1294 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1295 | |
| 1296 | return 0; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1297 | |
| 1298 | err_channel_add: |
| 1299 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1300 | if (xordev->channels[i]) { |
Thomas Petazzoni | ab6e439 | 2013-01-06 11:10:43 +0100 | [diff] [blame] | 1301 | mv_xor_channel_remove(xordev->channels[i]); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1302 | if (pdev->dev.of_node) |
| 1303 | irq_dispose_mapping(xordev->channels[i]->irq); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1304 | } |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1305 | |
Thomas Petazzoni | dab9206 | 2013-01-06 11:10:44 +0100 | [diff] [blame] | 1306 | if (!IS_ERR(xordev->clk)) { |
| 1307 | clk_disable_unprepare(xordev->clk); |
| 1308 | clk_put(xordev->clk); |
| 1309 | } |
| 1310 | |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1311 | return ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1312 | } |
| 1313 | |
Thomas Petazzoni | 6197165 | 2012-10-30 12:05:40 +0100 | [diff] [blame] | 1314 | static struct platform_driver mv_xor_driver = { |
| 1315 | .probe = mv_xor_probe, |
Thomas Petazzoni | 8b64843 | 2015-12-22 11:43:29 +0100 | [diff] [blame] | 1316 | .suspend = mv_xor_suspend, |
| 1317 | .resume = mv_xor_resume, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1318 | .driver = { |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1319 | .name = MV_XOR_NAME, |
| 1320 | .of_match_table = of_match_ptr(mv_xor_dt_ids), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1321 | }, |
| 1322 | }; |
| 1323 | |
| 1324 | |
| 1325 | static int __init mv_xor_init(void) |
| 1326 | { |
Thomas Petazzoni | 6197165 | 2012-10-30 12:05:40 +0100 | [diff] [blame] | 1327 | return platform_driver_register(&mv_xor_driver); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1328 | } |
Paul Gortmaker | 25cf68d | 2015-08-21 16:27:49 -0400 | [diff] [blame] | 1329 | device_initcall(mv_xor_init); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1330 | |
Paul Gortmaker | 25cf68d | 2015-08-21 16:27:49 -0400 | [diff] [blame] | 1331 | /* |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1332 | MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>"); |
| 1333 | MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine"); |
| 1334 | MODULE_LICENSE("GPL"); |
Paul Gortmaker | 25cf68d | 2015-08-21 16:27:49 -0400 | [diff] [blame] | 1335 | */ |