Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * offload engine driver for the Marvell XOR engine |
| 3 | * Copyright (C) 2007, 2008, Marvell International Ltd. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/module.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 21 | #include <linux/slab.h> |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 22 | #include <linux/delay.h> |
| 23 | #include <linux/dma-mapping.h> |
| 24 | #include <linux/spinlock.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/memory.h> |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 28 | #include <linux/clk.h> |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 29 | #include <linux/of.h> |
| 30 | #include <linux/of_irq.h> |
| 31 | #include <linux/irqdomain.h> |
Arnd Bergmann | c02cecb | 2012-08-24 15:21:54 +0200 | [diff] [blame] | 32 | #include <linux/platform_data/dma-mv_xor.h> |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 33 | |
| 34 | #include "dmaengine.h" |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 35 | #include "mv_xor.h" |
| 36 | |
| 37 | static void mv_xor_issue_pending(struct dma_chan *chan); |
| 38 | |
| 39 | #define to_mv_xor_chan(chan) \ |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 40 | container_of(chan, struct mv_xor_chan, dmachan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 41 | |
| 42 | #define to_mv_xor_slot(tx) \ |
| 43 | container_of(tx, struct mv_xor_desc_slot, async_tx) |
| 44 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 45 | #define mv_chan_to_devp(chan) \ |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 46 | ((chan)->dmadev.dev) |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 47 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 48 | static void mv_desc_init(struct mv_xor_desc_slot *desc, unsigned long flags) |
| 49 | { |
| 50 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 51 | |
| 52 | hw_desc->status = (1 << 31); |
| 53 | hw_desc->phy_next_desc = 0; |
| 54 | hw_desc->desc_command = (1 << 31); |
| 55 | } |
| 56 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 57 | static void mv_desc_set_byte_count(struct mv_xor_desc_slot *desc, |
| 58 | u32 byte_count) |
| 59 | { |
| 60 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 61 | hw_desc->byte_count = byte_count; |
| 62 | } |
| 63 | |
| 64 | static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc, |
| 65 | u32 next_desc_addr) |
| 66 | { |
| 67 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 68 | BUG_ON(hw_desc->phy_next_desc); |
| 69 | hw_desc->phy_next_desc = next_desc_addr; |
| 70 | } |
| 71 | |
| 72 | static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc) |
| 73 | { |
| 74 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 75 | hw_desc->phy_next_desc = 0; |
| 76 | } |
| 77 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 78 | static void mv_desc_set_dest_addr(struct mv_xor_desc_slot *desc, |
| 79 | dma_addr_t addr) |
| 80 | { |
| 81 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
| 82 | hw_desc->phy_dest_addr = addr; |
| 83 | } |
| 84 | |
| 85 | static int mv_chan_memset_slot_count(size_t len) |
| 86 | { |
| 87 | return 1; |
| 88 | } |
| 89 | |
| 90 | #define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c) |
| 91 | |
| 92 | static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc, |
| 93 | int index, dma_addr_t addr) |
| 94 | { |
| 95 | struct mv_xor_desc *hw_desc = desc->hw_desc; |
Thomas Petazzoni | e03bc65 | 2013-07-29 17:42:14 +0200 | [diff] [blame] | 96 | hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 97 | if (desc->type == DMA_XOR) |
| 98 | hw_desc->desc_command |= (1 << index); |
| 99 | } |
| 100 | |
| 101 | static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan) |
| 102 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 103 | return readl_relaxed(XOR_CURR_DESC(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan, |
| 107 | u32 next_desc_addr) |
| 108 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 109 | writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 110 | } |
| 111 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 112 | static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan) |
| 113 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 114 | u32 val = readl_relaxed(XOR_INTR_MASK(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 115 | val |= XOR_INTR_MASK_VALUE << (chan->idx * 16); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 116 | writel_relaxed(val, XOR_INTR_MASK(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 117 | } |
| 118 | |
| 119 | static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan) |
| 120 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 121 | u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 122 | intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF; |
| 123 | return intr_cause; |
| 124 | } |
| 125 | |
| 126 | static int mv_is_err_intr(u32 intr_cause) |
| 127 | { |
| 128 | if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9))) |
| 129 | return 1; |
| 130 | |
| 131 | return 0; |
| 132 | } |
| 133 | |
| 134 | static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan) |
| 135 | { |
Simon Guinot | 8636368 | 2010-09-17 23:33:51 +0200 | [diff] [blame] | 136 | u32 val = ~(1 << (chan->idx * 16)); |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 137 | dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 138 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan) |
| 142 | { |
| 143 | u32 val = 0xFFFF0000 >> (chan->idx * 16); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 144 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | static int mv_can_chain(struct mv_xor_desc_slot *desc) |
| 148 | { |
| 149 | struct mv_xor_desc_slot *chain_old_tail = list_entry( |
| 150 | desc->chain_node.prev, struct mv_xor_desc_slot, chain_node); |
| 151 | |
| 152 | if (chain_old_tail->type != desc->type) |
| 153 | return 0; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 154 | |
| 155 | return 1; |
| 156 | } |
| 157 | |
| 158 | static void mv_set_mode(struct mv_xor_chan *chan, |
| 159 | enum dma_transaction_type type) |
| 160 | { |
| 161 | u32 op_mode; |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 162 | u32 config = readl_relaxed(XOR_CONFIG(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 163 | |
| 164 | switch (type) { |
| 165 | case DMA_XOR: |
| 166 | op_mode = XOR_OPERATION_MODE_XOR; |
| 167 | break; |
| 168 | case DMA_MEMCPY: |
| 169 | op_mode = XOR_OPERATION_MODE_MEMCPY; |
| 170 | break; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 171 | default: |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 172 | dev_err(mv_chan_to_devp(chan), |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 173 | "error: unsupported operation %d\n", |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 174 | type); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 175 | BUG(); |
| 176 | return; |
| 177 | } |
| 178 | |
| 179 | config &= ~0x7; |
| 180 | config |= op_mode; |
Thomas Petazzoni | e03bc65 | 2013-07-29 17:42:14 +0200 | [diff] [blame] | 181 | |
| 182 | #if defined(__BIG_ENDIAN) |
| 183 | config |= XOR_DESCRIPTOR_SWAP; |
| 184 | #else |
| 185 | config &= ~XOR_DESCRIPTOR_SWAP; |
| 186 | #endif |
| 187 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 188 | writel_relaxed(config, XOR_CONFIG(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 189 | chan->current_type = type; |
| 190 | } |
| 191 | |
| 192 | static void mv_chan_activate(struct mv_xor_chan *chan) |
| 193 | { |
| 194 | u32 activation; |
| 195 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 196 | dev_dbg(mv_chan_to_devp(chan), " activate chan.\n"); |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 197 | activation = readl_relaxed(XOR_ACTIVATION(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 198 | activation |= 0x1; |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 199 | writel_relaxed(activation, XOR_ACTIVATION(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 200 | } |
| 201 | |
| 202 | static char mv_chan_is_busy(struct mv_xor_chan *chan) |
| 203 | { |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 204 | u32 state = readl_relaxed(XOR_ACTIVATION(chan)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 205 | |
| 206 | state = (state >> 4) & 0x3; |
| 207 | |
| 208 | return (state == 1) ? 1 : 0; |
| 209 | } |
| 210 | |
| 211 | static int mv_chan_xor_slot_count(size_t len, int src_cnt) |
| 212 | { |
| 213 | return 1; |
| 214 | } |
| 215 | |
| 216 | /** |
| 217 | * mv_xor_free_slots - flags descriptor slots for reuse |
| 218 | * @slot: Slot to free |
| 219 | * Caller must hold &mv_chan->lock while calling this function |
| 220 | */ |
| 221 | static void mv_xor_free_slots(struct mv_xor_chan *mv_chan, |
| 222 | struct mv_xor_desc_slot *slot) |
| 223 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 224 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d slot %p\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 225 | __func__, __LINE__, slot); |
| 226 | |
| 227 | slot->slots_per_op = 0; |
| 228 | |
| 229 | } |
| 230 | |
| 231 | /* |
| 232 | * mv_xor_start_new_chain - program the engine to operate on new chain headed by |
| 233 | * sw_desc |
| 234 | * Caller must hold &mv_chan->lock while calling this function |
| 235 | */ |
| 236 | static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan, |
| 237 | struct mv_xor_desc_slot *sw_desc) |
| 238 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 239 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 240 | __func__, __LINE__, sw_desc); |
| 241 | if (sw_desc->type != mv_chan->current_type) |
| 242 | mv_set_mode(mv_chan, sw_desc->type); |
| 243 | |
Bartlomiej Zolnierkiewicz | 48a9db4 | 2013-07-03 15:05:06 -0700 | [diff] [blame] | 244 | /* set the hardware chain */ |
| 245 | mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys); |
| 246 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 247 | mv_chan->pending += sw_desc->slot_cnt; |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 248 | mv_xor_issue_pending(&mv_chan->dmachan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | static dma_cookie_t |
| 252 | mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc, |
| 253 | struct mv_xor_chan *mv_chan, dma_cookie_t cookie) |
| 254 | { |
| 255 | BUG_ON(desc->async_tx.cookie < 0); |
| 256 | |
| 257 | if (desc->async_tx.cookie > 0) { |
| 258 | cookie = desc->async_tx.cookie; |
| 259 | |
| 260 | /* call the callback (must not sleep or submit new |
| 261 | * operations to this channel) |
| 262 | */ |
| 263 | if (desc->async_tx.callback) |
| 264 | desc->async_tx.callback( |
| 265 | desc->async_tx.callback_param); |
| 266 | |
Dan Williams | d38a8c6 | 2013-10-18 19:35:23 +0200 | [diff] [blame] | 267 | dma_descriptor_unmap(&desc->async_tx); |
Bartlomiej Zolnierkiewicz | 54f8d50 | 2013-10-18 19:35:32 +0200 | [diff] [blame] | 268 | if (desc->group_head) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 269 | desc->group_head = NULL; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 270 | } |
| 271 | |
| 272 | /* run dependent operations */ |
Dan Williams | 07f2211 | 2009-01-05 17:14:31 -0700 | [diff] [blame] | 273 | dma_run_dependencies(&desc->async_tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 274 | |
| 275 | return cookie; |
| 276 | } |
| 277 | |
| 278 | static int |
| 279 | mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan) |
| 280 | { |
| 281 | struct mv_xor_desc_slot *iter, *_iter; |
| 282 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 283 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 284 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
| 285 | completed_node) { |
| 286 | |
| 287 | if (async_tx_test_ack(&iter->async_tx)) { |
| 288 | list_del(&iter->completed_node); |
| 289 | mv_xor_free_slots(mv_chan, iter); |
| 290 | } |
| 291 | } |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | static int |
| 296 | mv_xor_clean_slot(struct mv_xor_desc_slot *desc, |
| 297 | struct mv_xor_chan *mv_chan) |
| 298 | { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 299 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 300 | __func__, __LINE__, desc, desc->async_tx.flags); |
| 301 | list_del(&desc->chain_node); |
| 302 | /* the client is allowed to attach dependent operations |
| 303 | * until 'ack' is set |
| 304 | */ |
| 305 | if (!async_tx_test_ack(&desc->async_tx)) { |
| 306 | /* move this slot to the completed_slots */ |
| 307 | list_add_tail(&desc->completed_node, &mv_chan->completed_slots); |
| 308 | return 0; |
| 309 | } |
| 310 | |
| 311 | mv_xor_free_slots(mv_chan, desc); |
| 312 | return 0; |
| 313 | } |
| 314 | |
| 315 | static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan) |
| 316 | { |
| 317 | struct mv_xor_desc_slot *iter, *_iter; |
| 318 | dma_cookie_t cookie = 0; |
| 319 | int busy = mv_chan_is_busy(mv_chan); |
| 320 | u32 current_desc = mv_chan_get_current_desc(mv_chan); |
| 321 | int seen_current = 0; |
| 322 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 323 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
| 324 | dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 325 | mv_xor_clean_completed_slots(mv_chan); |
| 326 | |
| 327 | /* free completed slots from the chain starting with |
| 328 | * the oldest descriptor |
| 329 | */ |
| 330 | |
| 331 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, |
| 332 | chain_node) { |
| 333 | prefetch(_iter); |
| 334 | prefetch(&_iter->async_tx); |
| 335 | |
| 336 | /* do not advance past the current descriptor loaded into the |
| 337 | * hardware channel, subsequent descriptors are either in |
| 338 | * process or have not been submitted |
| 339 | */ |
| 340 | if (seen_current) |
| 341 | break; |
| 342 | |
| 343 | /* stop the search if we reach the current descriptor and the |
| 344 | * channel is busy |
| 345 | */ |
| 346 | if (iter->async_tx.phys == current_desc) { |
| 347 | seen_current = 1; |
| 348 | if (busy) |
| 349 | break; |
| 350 | } |
| 351 | |
| 352 | cookie = mv_xor_run_tx_complete_actions(iter, mv_chan, cookie); |
| 353 | |
| 354 | if (mv_xor_clean_slot(iter, mv_chan)) |
| 355 | break; |
| 356 | } |
| 357 | |
| 358 | if ((busy == 0) && !list_empty(&mv_chan->chain)) { |
| 359 | struct mv_xor_desc_slot *chain_head; |
| 360 | chain_head = list_entry(mv_chan->chain.next, |
| 361 | struct mv_xor_desc_slot, |
| 362 | chain_node); |
| 363 | |
| 364 | mv_xor_start_new_chain(mv_chan, chain_head); |
| 365 | } |
| 366 | |
| 367 | if (cookie > 0) |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 368 | mv_chan->dmachan.completed_cookie = cookie; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 369 | } |
| 370 | |
| 371 | static void |
| 372 | mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan) |
| 373 | { |
| 374 | spin_lock_bh(&mv_chan->lock); |
| 375 | __mv_xor_slot_cleanup(mv_chan); |
| 376 | spin_unlock_bh(&mv_chan->lock); |
| 377 | } |
| 378 | |
| 379 | static void mv_xor_tasklet(unsigned long data) |
| 380 | { |
| 381 | struct mv_xor_chan *chan = (struct mv_xor_chan *) data; |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame^] | 382 | |
| 383 | spin_lock_bh(&chan->lock); |
| 384 | __mv_xor_slot_cleanup(chan); |
| 385 | spin_unlock_bh(&chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 386 | } |
| 387 | |
| 388 | static struct mv_xor_desc_slot * |
| 389 | mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots, |
| 390 | int slots_per_op) |
| 391 | { |
| 392 | struct mv_xor_desc_slot *iter, *_iter, *alloc_start = NULL; |
| 393 | LIST_HEAD(chain); |
| 394 | int slots_found, retry = 0; |
| 395 | |
| 396 | /* start search from the last allocated descrtiptor |
| 397 | * if a contiguous allocation can not be found start searching |
| 398 | * from the beginning of the list |
| 399 | */ |
| 400 | retry: |
| 401 | slots_found = 0; |
| 402 | if (retry == 0) |
| 403 | iter = mv_chan->last_used; |
| 404 | else |
| 405 | iter = list_entry(&mv_chan->all_slots, |
| 406 | struct mv_xor_desc_slot, |
| 407 | slot_node); |
| 408 | |
| 409 | list_for_each_entry_safe_continue( |
| 410 | iter, _iter, &mv_chan->all_slots, slot_node) { |
| 411 | prefetch(_iter); |
| 412 | prefetch(&_iter->async_tx); |
| 413 | if (iter->slots_per_op) { |
| 414 | /* give up after finding the first busy slot |
| 415 | * on the second pass through the list |
| 416 | */ |
| 417 | if (retry) |
| 418 | break; |
| 419 | |
| 420 | slots_found = 0; |
| 421 | continue; |
| 422 | } |
| 423 | |
| 424 | /* start the allocation if the slot is correctly aligned */ |
| 425 | if (!slots_found++) |
| 426 | alloc_start = iter; |
| 427 | |
| 428 | if (slots_found == num_slots) { |
| 429 | struct mv_xor_desc_slot *alloc_tail = NULL; |
| 430 | struct mv_xor_desc_slot *last_used = NULL; |
| 431 | iter = alloc_start; |
| 432 | while (num_slots) { |
| 433 | int i; |
| 434 | |
| 435 | /* pre-ack all but the last descriptor */ |
| 436 | async_tx_ack(&iter->async_tx); |
| 437 | |
| 438 | list_add_tail(&iter->chain_node, &chain); |
| 439 | alloc_tail = iter; |
| 440 | iter->async_tx.cookie = 0; |
| 441 | iter->slot_cnt = num_slots; |
| 442 | iter->xor_check_result = NULL; |
| 443 | for (i = 0; i < slots_per_op; i++) { |
| 444 | iter->slots_per_op = slots_per_op - i; |
| 445 | last_used = iter; |
| 446 | iter = list_entry(iter->slot_node.next, |
| 447 | struct mv_xor_desc_slot, |
| 448 | slot_node); |
| 449 | } |
| 450 | num_slots -= slots_per_op; |
| 451 | } |
| 452 | alloc_tail->group_head = alloc_start; |
| 453 | alloc_tail->async_tx.cookie = -EBUSY; |
Dan Williams | 64203b6 | 2009-09-08 17:53:03 -0700 | [diff] [blame] | 454 | list_splice(&chain, &alloc_tail->tx_list); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 455 | mv_chan->last_used = last_used; |
| 456 | mv_desc_clear_next_desc(alloc_start); |
| 457 | mv_desc_clear_next_desc(alloc_tail); |
| 458 | return alloc_tail; |
| 459 | } |
| 460 | } |
| 461 | if (!retry++) |
| 462 | goto retry; |
| 463 | |
| 464 | /* try to free some slots if the allocation fails */ |
| 465 | tasklet_schedule(&mv_chan->irq_tasklet); |
| 466 | |
| 467 | return NULL; |
| 468 | } |
| 469 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 470 | /************************ DMA engine API functions ****************************/ |
| 471 | static dma_cookie_t |
| 472 | mv_xor_tx_submit(struct dma_async_tx_descriptor *tx) |
| 473 | { |
| 474 | struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx); |
| 475 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan); |
| 476 | struct mv_xor_desc_slot *grp_start, *old_chain_tail; |
| 477 | dma_cookie_t cookie; |
| 478 | int new_hw_chain = 1; |
| 479 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 480 | dev_dbg(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 481 | "%s sw_desc %p: async_tx %p\n", |
| 482 | __func__, sw_desc, &sw_desc->async_tx); |
| 483 | |
| 484 | grp_start = sw_desc->group_head; |
| 485 | |
| 486 | spin_lock_bh(&mv_chan->lock); |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 487 | cookie = dma_cookie_assign(tx); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 488 | |
| 489 | if (list_empty(&mv_chan->chain)) |
Dan Williams | 64203b6 | 2009-09-08 17:53:03 -0700 | [diff] [blame] | 490 | list_splice_init(&sw_desc->tx_list, &mv_chan->chain); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 491 | else { |
| 492 | new_hw_chain = 0; |
| 493 | |
| 494 | old_chain_tail = list_entry(mv_chan->chain.prev, |
| 495 | struct mv_xor_desc_slot, |
| 496 | chain_node); |
Dan Williams | 64203b6 | 2009-09-08 17:53:03 -0700 | [diff] [blame] | 497 | list_splice_init(&grp_start->tx_list, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 498 | &old_chain_tail->chain_node); |
| 499 | |
| 500 | if (!mv_can_chain(grp_start)) |
| 501 | goto submit_done; |
| 502 | |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 503 | dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n", |
| 504 | &old_chain_tail->async_tx.phys); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 505 | |
| 506 | /* fix up the hardware chain */ |
| 507 | mv_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys); |
| 508 | |
| 509 | /* if the channel is not busy */ |
| 510 | if (!mv_chan_is_busy(mv_chan)) { |
| 511 | u32 current_desc = mv_chan_get_current_desc(mv_chan); |
| 512 | /* |
| 513 | * and the curren desc is the end of the chain before |
| 514 | * the append, then we need to start the channel |
| 515 | */ |
| 516 | if (current_desc == old_chain_tail->async_tx.phys) |
| 517 | new_hw_chain = 1; |
| 518 | } |
| 519 | } |
| 520 | |
| 521 | if (new_hw_chain) |
| 522 | mv_xor_start_new_chain(mv_chan, grp_start); |
| 523 | |
| 524 | submit_done: |
| 525 | spin_unlock_bh(&mv_chan->lock); |
| 526 | |
| 527 | return cookie; |
| 528 | } |
| 529 | |
| 530 | /* returns the number of allocated descriptors */ |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 531 | static int mv_xor_alloc_chan_resources(struct dma_chan *chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 532 | { |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 533 | void *virt_desc; |
| 534 | dma_addr_t dma_desc; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 535 | int idx; |
| 536 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 537 | struct mv_xor_desc_slot *slot = NULL; |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 538 | int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 539 | |
| 540 | /* Allocate descriptor slots */ |
| 541 | idx = mv_chan->slots_allocated; |
| 542 | while (idx < num_descs_in_pool) { |
| 543 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); |
| 544 | if (!slot) { |
| 545 | printk(KERN_INFO "MV XOR Channel only initialized" |
| 546 | " %d descriptor slots", idx); |
| 547 | break; |
| 548 | } |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 549 | virt_desc = mv_chan->dma_desc_pool_virt; |
| 550 | slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 551 | |
| 552 | dma_async_tx_descriptor_init(&slot->async_tx, chan); |
| 553 | slot->async_tx.tx_submit = mv_xor_tx_submit; |
| 554 | INIT_LIST_HEAD(&slot->chain_node); |
| 555 | INIT_LIST_HEAD(&slot->slot_node); |
Dan Williams | 64203b6 | 2009-09-08 17:53:03 -0700 | [diff] [blame] | 556 | INIT_LIST_HEAD(&slot->tx_list); |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 557 | dma_desc = mv_chan->dma_desc_pool; |
| 558 | slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 559 | slot->idx = idx++; |
| 560 | |
| 561 | spin_lock_bh(&mv_chan->lock); |
| 562 | mv_chan->slots_allocated = idx; |
| 563 | list_add_tail(&slot->slot_node, &mv_chan->all_slots); |
| 564 | spin_unlock_bh(&mv_chan->lock); |
| 565 | } |
| 566 | |
| 567 | if (mv_chan->slots_allocated && !mv_chan->last_used) |
| 568 | mv_chan->last_used = list_entry(mv_chan->all_slots.next, |
| 569 | struct mv_xor_desc_slot, |
| 570 | slot_node); |
| 571 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 572 | dev_dbg(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 573 | "allocated %d descriptor slots last_used: %p\n", |
| 574 | mv_chan->slots_allocated, mv_chan->last_used); |
| 575 | |
| 576 | return mv_chan->slots_allocated ? : -ENOMEM; |
| 577 | } |
| 578 | |
| 579 | static struct dma_async_tx_descriptor * |
| 580 | mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
| 581 | size_t len, unsigned long flags) |
| 582 | { |
| 583 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 584 | struct mv_xor_desc_slot *sw_desc, *grp_start; |
| 585 | int slot_cnt; |
| 586 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 587 | dev_dbg(mv_chan_to_devp(mv_chan), |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 588 | "%s dest: %pad src %pad len: %u flags: %ld\n", |
| 589 | __func__, &dest, &src, len, flags); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 590 | if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) |
| 591 | return NULL; |
| 592 | |
Coly Li | 7912d30 | 2011-03-27 01:26:53 +0800 | [diff] [blame] | 593 | BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 594 | |
| 595 | spin_lock_bh(&mv_chan->lock); |
| 596 | slot_cnt = mv_chan_memcpy_slot_count(len); |
| 597 | sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1); |
| 598 | if (sw_desc) { |
| 599 | sw_desc->type = DMA_MEMCPY; |
| 600 | sw_desc->async_tx.flags = flags; |
| 601 | grp_start = sw_desc->group_head; |
| 602 | mv_desc_init(grp_start, flags); |
| 603 | mv_desc_set_byte_count(grp_start, len); |
| 604 | mv_desc_set_dest_addr(sw_desc->group_head, dest); |
| 605 | mv_desc_set_src_addr(grp_start, 0, src); |
| 606 | sw_desc->unmap_src_cnt = 1; |
| 607 | sw_desc->unmap_len = len; |
| 608 | } |
| 609 | spin_unlock_bh(&mv_chan->lock); |
| 610 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 611 | dev_dbg(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 612 | "%s sw_desc %p async_tx %p\n", |
Jingoo Han | 4c14372 | 2013-08-06 19:37:08 +0900 | [diff] [blame] | 613 | __func__, sw_desc, sw_desc ? &sw_desc->async_tx : NULL); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 614 | |
| 615 | return sw_desc ? &sw_desc->async_tx : NULL; |
| 616 | } |
| 617 | |
| 618 | static struct dma_async_tx_descriptor * |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 619 | mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
| 620 | unsigned int src_cnt, size_t len, unsigned long flags) |
| 621 | { |
| 622 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 623 | struct mv_xor_desc_slot *sw_desc, *grp_start; |
| 624 | int slot_cnt; |
| 625 | |
| 626 | if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) |
| 627 | return NULL; |
| 628 | |
Coly Li | 7912d30 | 2011-03-27 01:26:53 +0800 | [diff] [blame] | 629 | BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 630 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 631 | dev_dbg(mv_chan_to_devp(mv_chan), |
Olof Johansson | 31fd8f5 | 2014-02-03 17:13:23 -0800 | [diff] [blame] | 632 | "%s src_cnt: %d len: %u dest %pad flags: %ld\n", |
| 633 | __func__, src_cnt, len, &dest, flags); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 634 | |
| 635 | spin_lock_bh(&mv_chan->lock); |
| 636 | slot_cnt = mv_chan_xor_slot_count(len, src_cnt); |
| 637 | sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1); |
| 638 | if (sw_desc) { |
| 639 | sw_desc->type = DMA_XOR; |
| 640 | sw_desc->async_tx.flags = flags; |
| 641 | grp_start = sw_desc->group_head; |
| 642 | mv_desc_init(grp_start, flags); |
| 643 | /* the byte count field is the same as in memcpy desc*/ |
| 644 | mv_desc_set_byte_count(grp_start, len); |
| 645 | mv_desc_set_dest_addr(sw_desc->group_head, dest); |
| 646 | sw_desc->unmap_src_cnt = src_cnt; |
| 647 | sw_desc->unmap_len = len; |
| 648 | while (src_cnt--) |
| 649 | mv_desc_set_src_addr(grp_start, src_cnt, src[src_cnt]); |
| 650 | } |
| 651 | spin_unlock_bh(&mv_chan->lock); |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 652 | dev_dbg(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 653 | "%s sw_desc %p async_tx %p \n", |
| 654 | __func__, sw_desc, &sw_desc->async_tx); |
| 655 | return sw_desc ? &sw_desc->async_tx : NULL; |
| 656 | } |
| 657 | |
| 658 | static void mv_xor_free_chan_resources(struct dma_chan *chan) |
| 659 | { |
| 660 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 661 | struct mv_xor_desc_slot *iter, *_iter; |
| 662 | int in_use_descs = 0; |
| 663 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 664 | spin_lock_bh(&mv_chan->lock); |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame^] | 665 | |
| 666 | __mv_xor_slot_cleanup(mv_chan); |
| 667 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 668 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, |
| 669 | chain_node) { |
| 670 | in_use_descs++; |
| 671 | list_del(&iter->chain_node); |
| 672 | } |
| 673 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
| 674 | completed_node) { |
| 675 | in_use_descs++; |
| 676 | list_del(&iter->completed_node); |
| 677 | } |
| 678 | list_for_each_entry_safe_reverse( |
| 679 | iter, _iter, &mv_chan->all_slots, slot_node) { |
| 680 | list_del(&iter->slot_node); |
| 681 | kfree(iter); |
| 682 | mv_chan->slots_allocated--; |
| 683 | } |
| 684 | mv_chan->last_used = NULL; |
| 685 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 686 | dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n", |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 687 | __func__, mv_chan->slots_allocated); |
| 688 | spin_unlock_bh(&mv_chan->lock); |
| 689 | |
| 690 | if (in_use_descs) |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 691 | dev_err(mv_chan_to_devp(mv_chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 692 | "freeing %d in use descriptors!\n", in_use_descs); |
| 693 | } |
| 694 | |
| 695 | /** |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 696 | * mv_xor_status - poll the status of an XOR transaction |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 697 | * @chan: XOR channel handle |
| 698 | * @cookie: XOR transaction identifier |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 699 | * @txstate: XOR transactions state holder (or NULL) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 700 | */ |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 701 | static enum dma_status mv_xor_status(struct dma_chan *chan, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 702 | dma_cookie_t cookie, |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 703 | struct dma_tx_state *txstate) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 704 | { |
| 705 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 706 | enum dma_status ret; |
| 707 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 708 | ret = dma_cookie_status(chan, cookie, txstate); |
Ezequiel Garcia | 890766d | 2014-03-07 16:46:45 -0300 | [diff] [blame] | 709 | if (ret == DMA_COMPLETE) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 710 | return ret; |
Ezequiel Garcia | e43147a | 2014-03-07 16:46:46 -0300 | [diff] [blame^] | 711 | |
| 712 | spin_lock_bh(&mv_chan->lock); |
| 713 | __mv_xor_slot_cleanup(mv_chan); |
| 714 | spin_unlock_bh(&mv_chan->lock); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 715 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 716 | return dma_cookie_status(chan, cookie, txstate); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 717 | } |
| 718 | |
| 719 | static void mv_dump_xor_regs(struct mv_xor_chan *chan) |
| 720 | { |
| 721 | u32 val; |
| 722 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 723 | val = readl_relaxed(XOR_CONFIG(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 724 | dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 725 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 726 | val = readl_relaxed(XOR_ACTIVATION(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 727 | dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 728 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 729 | val = readl_relaxed(XOR_INTR_CAUSE(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 730 | dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 731 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 732 | val = readl_relaxed(XOR_INTR_MASK(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 733 | dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 734 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 735 | val = readl_relaxed(XOR_ERROR_CAUSE(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 736 | dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 737 | |
Thomas Petazzoni | 5733c38 | 2013-07-29 17:42:13 +0200 | [diff] [blame] | 738 | val = readl_relaxed(XOR_ERROR_ADDR(chan)); |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 739 | dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 740 | } |
| 741 | |
| 742 | static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan, |
| 743 | u32 intr_cause) |
| 744 | { |
| 745 | if (intr_cause & (1 << 4)) { |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 746 | dev_dbg(mv_chan_to_devp(chan), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 747 | "ignore this error\n"); |
| 748 | return; |
| 749 | } |
| 750 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 751 | dev_err(mv_chan_to_devp(chan), |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 752 | "error on chan %d. intr cause 0x%08x\n", |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 753 | chan->idx, intr_cause); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 754 | |
| 755 | mv_dump_xor_regs(chan); |
| 756 | BUG(); |
| 757 | } |
| 758 | |
| 759 | static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) |
| 760 | { |
| 761 | struct mv_xor_chan *chan = data; |
| 762 | u32 intr_cause = mv_chan_get_intr_cause(chan); |
| 763 | |
Thomas Petazzoni | c98c178 | 2012-11-15 14:17:18 +0100 | [diff] [blame] | 764 | dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 765 | |
| 766 | if (mv_is_err_intr(intr_cause)) |
| 767 | mv_xor_err_interrupt_handler(chan, intr_cause); |
| 768 | |
| 769 | tasklet_schedule(&chan->irq_tasklet); |
| 770 | |
| 771 | mv_xor_device_clear_eoc_cause(chan); |
| 772 | |
| 773 | return IRQ_HANDLED; |
| 774 | } |
| 775 | |
| 776 | static void mv_xor_issue_pending(struct dma_chan *chan) |
| 777 | { |
| 778 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); |
| 779 | |
| 780 | if (mv_chan->pending >= MV_XOR_THRESHOLD) { |
| 781 | mv_chan->pending = 0; |
| 782 | mv_chan_activate(mv_chan); |
| 783 | } |
| 784 | } |
| 785 | |
| 786 | /* |
| 787 | * Perform a transaction to verify the HW works. |
| 788 | */ |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 789 | |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 790 | static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 791 | { |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 792 | int i, ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 793 | void *src, *dest; |
| 794 | dma_addr_t src_dma, dest_dma; |
| 795 | struct dma_chan *dma_chan; |
| 796 | dma_cookie_t cookie; |
| 797 | struct dma_async_tx_descriptor *tx; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 798 | struct dmaengine_unmap_data *unmap; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 799 | int err = 0; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 800 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 801 | src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 802 | if (!src) |
| 803 | return -ENOMEM; |
| 804 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 805 | dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 806 | if (!dest) { |
| 807 | kfree(src); |
| 808 | return -ENOMEM; |
| 809 | } |
| 810 | |
| 811 | /* Fill in src buffer */ |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 812 | for (i = 0; i < PAGE_SIZE; i++) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 813 | ((u8 *) src)[i] = (u8)i; |
| 814 | |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 815 | dma_chan = &mv_chan->dmachan; |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 816 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 817 | err = -ENODEV; |
| 818 | goto out; |
| 819 | } |
| 820 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 821 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL); |
| 822 | if (!unmap) { |
| 823 | err = -ENOMEM; |
| 824 | goto free_resources; |
| 825 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 826 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 827 | src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), 0, |
| 828 | PAGE_SIZE, DMA_TO_DEVICE); |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 829 | unmap->addr[0] = src_dma; |
| 830 | |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 831 | ret = dma_mapping_error(dma_chan->device->dev, src_dma); |
| 832 | if (ret) { |
| 833 | err = -ENOMEM; |
| 834 | goto free_resources; |
| 835 | } |
| 836 | unmap->to_cnt = 1; |
| 837 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 838 | dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), 0, |
| 839 | PAGE_SIZE, DMA_FROM_DEVICE); |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 840 | unmap->addr[1] = dest_dma; |
| 841 | |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 842 | ret = dma_mapping_error(dma_chan->device->dev, dest_dma); |
| 843 | if (ret) { |
| 844 | err = -ENOMEM; |
| 845 | goto free_resources; |
| 846 | } |
| 847 | unmap->from_cnt = 1; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 848 | unmap->len = PAGE_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 849 | |
| 850 | tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 851 | PAGE_SIZE, 0); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 852 | if (!tx) { |
| 853 | dev_err(dma_chan->device->dev, |
| 854 | "Self-test cannot prepare operation, disabling\n"); |
| 855 | err = -ENODEV; |
| 856 | goto free_resources; |
| 857 | } |
| 858 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 859 | cookie = mv_xor_tx_submit(tx); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 860 | if (dma_submit_error(cookie)) { |
| 861 | dev_err(dma_chan->device->dev, |
| 862 | "Self-test submit error, disabling\n"); |
| 863 | err = -ENODEV; |
| 864 | goto free_resources; |
| 865 | } |
| 866 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 867 | mv_xor_issue_pending(dma_chan); |
| 868 | async_tx_ack(tx); |
| 869 | msleep(1); |
| 870 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 871 | if (mv_xor_status(dma_chan, cookie, NULL) != |
Vinod Koul | b3efb8f | 2013-10-16 20:51:04 +0530 | [diff] [blame] | 872 | DMA_COMPLETE) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 873 | dev_err(dma_chan->device->dev, |
| 874 | "Self-test copy timed out, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 875 | err = -ENODEV; |
| 876 | goto free_resources; |
| 877 | } |
| 878 | |
Thomas Petazzoni | c35064c | 2012-11-15 13:01:59 +0100 | [diff] [blame] | 879 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 880 | PAGE_SIZE, DMA_FROM_DEVICE); |
| 881 | if (memcmp(src, dest, PAGE_SIZE)) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 882 | dev_err(dma_chan->device->dev, |
| 883 | "Self-test copy failed compare, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 884 | err = -ENODEV; |
| 885 | goto free_resources; |
| 886 | } |
| 887 | |
| 888 | free_resources: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 889 | dmaengine_unmap_put(unmap); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 890 | mv_xor_free_chan_resources(dma_chan); |
| 891 | out: |
| 892 | kfree(src); |
| 893 | kfree(dest); |
| 894 | return err; |
| 895 | } |
| 896 | |
| 897 | #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */ |
Bill Pemberton | 463a1f8 | 2012-11-19 13:22:55 -0500 | [diff] [blame] | 898 | static int |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 899 | mv_xor_xor_self_test(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 900 | { |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 901 | int i, src_idx, ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 902 | struct page *dest; |
| 903 | struct page *xor_srcs[MV_XOR_NUM_SRC_TEST]; |
| 904 | dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST]; |
| 905 | dma_addr_t dest_dma; |
| 906 | struct dma_async_tx_descriptor *tx; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 907 | struct dmaengine_unmap_data *unmap; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 908 | struct dma_chan *dma_chan; |
| 909 | dma_cookie_t cookie; |
| 910 | u8 cmp_byte = 0; |
| 911 | u32 cmp_word; |
| 912 | int err = 0; |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 913 | int src_count = MV_XOR_NUM_SRC_TEST; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 914 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 915 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 916 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 917 | if (!xor_srcs[src_idx]) { |
| 918 | while (src_idx--) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 919 | __free_page(xor_srcs[src_idx]); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 920 | return -ENOMEM; |
| 921 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 922 | } |
| 923 | |
| 924 | dest = alloc_page(GFP_KERNEL); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 925 | if (!dest) { |
| 926 | while (src_idx--) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 927 | __free_page(xor_srcs[src_idx]); |
Roel Kluin | a09b09a | 2009-02-25 13:56:21 +0100 | [diff] [blame] | 928 | return -ENOMEM; |
| 929 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 930 | |
| 931 | /* Fill in src buffers */ |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 932 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 933 | u8 *ptr = page_address(xor_srcs[src_idx]); |
| 934 | for (i = 0; i < PAGE_SIZE; i++) |
| 935 | ptr[i] = (1 << src_idx); |
| 936 | } |
| 937 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 938 | for (src_idx = 0; src_idx < src_count; src_idx++) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 939 | cmp_byte ^= (u8) (1 << src_idx); |
| 940 | |
| 941 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | |
| 942 | (cmp_byte << 8) | cmp_byte; |
| 943 | |
| 944 | memset(page_address(dest), 0, PAGE_SIZE); |
| 945 | |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 946 | dma_chan = &mv_chan->dmachan; |
Dan Williams | aa1e6f1 | 2009-01-06 11:38:17 -0700 | [diff] [blame] | 947 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 948 | err = -ENODEV; |
| 949 | goto out; |
| 950 | } |
| 951 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 952 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1, |
| 953 | GFP_KERNEL); |
| 954 | if (!unmap) { |
| 955 | err = -ENOMEM; |
| 956 | goto free_resources; |
| 957 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 958 | |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 959 | /* test xor */ |
| 960 | for (i = 0; i < src_count; i++) { |
| 961 | unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], |
| 962 | 0, PAGE_SIZE, DMA_TO_DEVICE); |
| 963 | dma_srcs[i] = unmap->addr[i]; |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 964 | ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[i]); |
| 965 | if (ret) { |
| 966 | err = -ENOMEM; |
| 967 | goto free_resources; |
| 968 | } |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 969 | unmap->to_cnt++; |
| 970 | } |
| 971 | |
| 972 | unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE, |
| 973 | DMA_FROM_DEVICE); |
| 974 | dest_dma = unmap->addr[src_count]; |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 975 | ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[src_count]); |
| 976 | if (ret) { |
| 977 | err = -ENOMEM; |
| 978 | goto free_resources; |
| 979 | } |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 980 | unmap->from_cnt = 1; |
| 981 | unmap->len = PAGE_SIZE; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 982 | |
| 983 | tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs, |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 984 | src_count, PAGE_SIZE, 0); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 985 | if (!tx) { |
| 986 | dev_err(dma_chan->device->dev, |
| 987 | "Self-test cannot prepare operation, disabling\n"); |
| 988 | err = -ENODEV; |
| 989 | goto free_resources; |
| 990 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 991 | |
| 992 | cookie = mv_xor_tx_submit(tx); |
Ezequiel Garcia | b8c01d2 | 2013-12-10 09:32:37 -0300 | [diff] [blame] | 993 | if (dma_submit_error(cookie)) { |
| 994 | dev_err(dma_chan->device->dev, |
| 995 | "Self-test submit error, disabling\n"); |
| 996 | err = -ENODEV; |
| 997 | goto free_resources; |
| 998 | } |
| 999 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1000 | mv_xor_issue_pending(dma_chan); |
| 1001 | async_tx_ack(tx); |
| 1002 | msleep(8); |
| 1003 | |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1004 | if (mv_xor_status(dma_chan, cookie, NULL) != |
Vinod Koul | b3efb8f | 2013-10-16 20:51:04 +0530 | [diff] [blame] | 1005 | DMA_COMPLETE) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 1006 | dev_err(dma_chan->device->dev, |
| 1007 | "Self-test xor timed out, disabling\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1008 | err = -ENODEV; |
| 1009 | goto free_resources; |
| 1010 | } |
| 1011 | |
Thomas Petazzoni | c35064c | 2012-11-15 13:01:59 +0100 | [diff] [blame] | 1012 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1013 | PAGE_SIZE, DMA_FROM_DEVICE); |
| 1014 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { |
| 1015 | u32 *ptr = page_address(dest); |
| 1016 | if (ptr[i] != cmp_word) { |
Thomas Petazzoni | a3fc74b | 2012-11-15 12:50:27 +0100 | [diff] [blame] | 1017 | dev_err(dma_chan->device->dev, |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1018 | "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n", |
| 1019 | i, ptr[i], cmp_word); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1020 | err = -ENODEV; |
| 1021 | goto free_resources; |
| 1022 | } |
| 1023 | } |
| 1024 | |
| 1025 | free_resources: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 1026 | dmaengine_unmap_put(unmap); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1027 | mv_xor_free_chan_resources(dma_chan); |
| 1028 | out: |
Ezequiel Garcia | d16695a | 2013-12-10 09:32:36 -0300 | [diff] [blame] | 1029 | src_idx = src_count; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1030 | while (src_idx--) |
| 1031 | __free_page(xor_srcs[src_idx]); |
| 1032 | __free_page(dest); |
| 1033 | return err; |
| 1034 | } |
| 1035 | |
Andrew Lunn | 34c93c8 | 2012-11-18 11:44:56 +0100 | [diff] [blame] | 1036 | /* This driver does not implement any of the optional DMA operations. */ |
| 1037 | static int |
| 1038 | mv_xor_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 1039 | unsigned long arg) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1040 | { |
Andrew Lunn | 34c93c8 | 2012-11-18 11:44:56 +0100 | [diff] [blame] | 1041 | return -ENOSYS; |
| 1042 | } |
| 1043 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1044 | static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1045 | { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1046 | struct dma_chan *chan, *_chan; |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1047 | struct device *dev = mv_chan->dmadev.dev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1048 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1049 | dma_async_device_unregister(&mv_chan->dmadev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1050 | |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 1051 | dma_free_coherent(dev, MV_XOR_POOL_SIZE, |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1052 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1053 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1054 | list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels, |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 1055 | device_node) { |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1056 | list_del(&chan->device_node); |
| 1057 | } |
| 1058 | |
Thomas Petazzoni | 88eb92c | 2012-11-15 16:11:18 +0100 | [diff] [blame] | 1059 | free_irq(mv_chan->irq, mv_chan); |
| 1060 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1061 | return 0; |
| 1062 | } |
| 1063 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1064 | static struct mv_xor_chan * |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1065 | mv_xor_channel_add(struct mv_xor_device *xordev, |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 1066 | struct platform_device *pdev, |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 1067 | int idx, dma_cap_mask_t cap_mask, int irq) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1068 | { |
| 1069 | int ret = 0; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1070 | struct mv_xor_chan *mv_chan; |
| 1071 | struct dma_device *dma_dev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1072 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1073 | mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL); |
Sachin Kamat | a577659 | 2013-09-02 13:54:20 +0530 | [diff] [blame] | 1074 | if (!mv_chan) |
| 1075 | return ERR_PTR(-ENOMEM); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1076 | |
Thomas Petazzoni | 9aedbdb | 2012-11-15 15:36:37 +0100 | [diff] [blame] | 1077 | mv_chan->idx = idx; |
Thomas Petazzoni | 88eb92c | 2012-11-15 16:11:18 +0100 | [diff] [blame] | 1078 | mv_chan->irq = irq; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1079 | |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1080 | dma_dev = &mv_chan->dmadev; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1081 | |
| 1082 | /* allocate coherent memory for hardware descriptors |
| 1083 | * note: writecombine gives slightly better performance, but |
| 1084 | * requires that we explicitly flush the writes |
| 1085 | */ |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1086 | mv_chan->dma_desc_pool_virt = |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 1087 | dma_alloc_writecombine(&pdev->dev, MV_XOR_POOL_SIZE, |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1088 | &mv_chan->dma_desc_pool, GFP_KERNEL); |
| 1089 | if (!mv_chan->dma_desc_pool_virt) |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 1090 | return ERR_PTR(-ENOMEM); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1091 | |
| 1092 | /* discover transaction capabilites from the platform data */ |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 1093 | dma_dev->cap_mask = cap_mask; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1094 | |
| 1095 | INIT_LIST_HEAD(&dma_dev->channels); |
| 1096 | |
| 1097 | /* set base routines */ |
| 1098 | dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources; |
| 1099 | dma_dev->device_free_chan_resources = mv_xor_free_chan_resources; |
Linus Walleij | 0793448 | 2010-03-26 16:50:49 -0700 | [diff] [blame] | 1100 | dma_dev->device_tx_status = mv_xor_status; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1101 | dma_dev->device_issue_pending = mv_xor_issue_pending; |
Andrew Lunn | 34c93c8 | 2012-11-18 11:44:56 +0100 | [diff] [blame] | 1102 | dma_dev->device_control = mv_xor_control; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1103 | dma_dev->dev = &pdev->dev; |
| 1104 | |
| 1105 | /* set prep routines based on capability */ |
| 1106 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) |
| 1107 | dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1108 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
Joe Perches | c019894 | 2009-06-28 09:26:21 -0700 | [diff] [blame] | 1109 | dma_dev->max_xor = 8; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1110 | dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor; |
| 1111 | } |
| 1112 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1113 | mv_chan->mmr_base = xordev->xor_base; |
Ezequiel Garcia | 82a1402 | 2013-10-30 12:01:43 -0300 | [diff] [blame] | 1114 | mv_chan->mmr_high_base = xordev->xor_high_base; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1115 | tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long) |
| 1116 | mv_chan); |
| 1117 | |
| 1118 | /* clear errors before enabling interrupts */ |
| 1119 | mv_xor_device_clear_err_status(mv_chan); |
| 1120 | |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1121 | ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler, |
| 1122 | 0, dev_name(&pdev->dev), mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1123 | if (ret) |
| 1124 | goto err_free_dma; |
| 1125 | |
| 1126 | mv_chan_unmask_interrupts(mv_chan); |
| 1127 | |
| 1128 | mv_set_mode(mv_chan, DMA_MEMCPY); |
| 1129 | |
| 1130 | spin_lock_init(&mv_chan->lock); |
| 1131 | INIT_LIST_HEAD(&mv_chan->chain); |
| 1132 | INIT_LIST_HEAD(&mv_chan->completed_slots); |
| 1133 | INIT_LIST_HEAD(&mv_chan->all_slots); |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 1134 | mv_chan->dmachan.device = dma_dev; |
| 1135 | dma_cookie_init(&mv_chan->dmachan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1136 | |
Thomas Petazzoni | 98817b9 | 2012-11-15 14:57:44 +0100 | [diff] [blame] | 1137 | list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1138 | |
| 1139 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 1140 | ret = mv_xor_memcpy_self_test(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1141 | dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); |
| 1142 | if (ret) |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1143 | goto err_free_irq; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1144 | } |
| 1145 | |
| 1146 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
Thomas Petazzoni | 275cc0c | 2012-11-15 15:09:42 +0100 | [diff] [blame] | 1147 | ret = mv_xor_xor_self_test(mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1148 | dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); |
| 1149 | if (ret) |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1150 | goto err_free_irq; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1151 | } |
| 1152 | |
Bartlomiej Zolnierkiewicz | 48a9db4 | 2013-07-03 15:05:06 -0700 | [diff] [blame] | 1153 | dev_info(&pdev->dev, "Marvell XOR: ( %s%s%s)\n", |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1154 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1155 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", |
| 1156 | dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1157 | |
| 1158 | dma_async_device_register(dma_dev); |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1159 | return mv_chan; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1160 | |
Thomas Petazzoni | 2d0a074 | 2012-11-22 18:19:09 +0100 | [diff] [blame] | 1161 | err_free_irq: |
| 1162 | free_irq(mv_chan->irq, mv_chan); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1163 | err_free_dma: |
Thomas Petazzoni | b503fa0 | 2012-11-15 15:55:30 +0100 | [diff] [blame] | 1164 | dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE, |
Thomas Petazzoni | 1ef48a2 | 2012-11-15 15:17:05 +0100 | [diff] [blame] | 1165 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
Thomas Petazzoni | a6b4a9d | 2012-10-29 16:45:46 +0100 | [diff] [blame] | 1166 | return ERR_PTR(ret); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1167 | } |
| 1168 | |
| 1169 | static void |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1170 | mv_xor_conf_mbus_windows(struct mv_xor_device *xordev, |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1171 | const struct mbus_dram_target_info *dram) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1172 | { |
Ezequiel Garcia | 82a1402 | 2013-10-30 12:01:43 -0300 | [diff] [blame] | 1173 | void __iomem *base = xordev->xor_high_base; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1174 | u32 win_enable = 0; |
| 1175 | int i; |
| 1176 | |
| 1177 | for (i = 0; i < 8; i++) { |
| 1178 | writel(0, base + WINDOW_BASE(i)); |
| 1179 | writel(0, base + WINDOW_SIZE(i)); |
| 1180 | if (i < 4) |
| 1181 | writel(0, base + WINDOW_REMAP_HIGH(i)); |
| 1182 | } |
| 1183 | |
| 1184 | for (i = 0; i < dram->num_cs; i++) { |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1185 | const struct mbus_dram_window *cs = dram->cs + i; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1186 | |
| 1187 | writel((cs->base & 0xffff0000) | |
| 1188 | (cs->mbus_attr << 8) | |
| 1189 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); |
| 1190 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); |
| 1191 | |
| 1192 | win_enable |= (1 << i); |
| 1193 | win_enable |= 3 << (16 + (2 * i)); |
| 1194 | } |
| 1195 | |
| 1196 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); |
| 1197 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); |
Thomas Petazzoni | c4b4b73 | 2012-11-22 18:16:37 +0100 | [diff] [blame] | 1198 | writel(0, base + WINDOW_OVERRIDE_CTRL(0)); |
| 1199 | writel(0, base + WINDOW_OVERRIDE_CTRL(1)); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1200 | } |
| 1201 | |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 1202 | static int mv_xor_probe(struct platform_device *pdev) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1203 | { |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1204 | const struct mbus_dram_target_info *dram; |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1205 | struct mv_xor_device *xordev; |
Jingoo Han | d4adcc0 | 2013-07-30 17:09:11 +0900 | [diff] [blame] | 1206 | struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1207 | struct resource *res; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1208 | int i, ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1209 | |
Joe Perches | 1ba151c | 2012-10-28 01:05:44 -0700 | [diff] [blame] | 1210 | dev_notice(&pdev->dev, "Marvell shared XOR driver\n"); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1211 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1212 | xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL); |
| 1213 | if (!xordev) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1214 | return -ENOMEM; |
| 1215 | |
| 1216 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1217 | if (!res) |
| 1218 | return -ENODEV; |
| 1219 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1220 | xordev->xor_base = devm_ioremap(&pdev->dev, res->start, |
| 1221 | resource_size(res)); |
| 1222 | if (!xordev->xor_base) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1223 | return -EBUSY; |
| 1224 | |
| 1225 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
| 1226 | if (!res) |
| 1227 | return -ENODEV; |
| 1228 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1229 | xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start, |
| 1230 | resource_size(res)); |
| 1231 | if (!xordev->xor_high_base) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1232 | return -EBUSY; |
| 1233 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1234 | platform_set_drvdata(pdev, xordev); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1235 | |
| 1236 | /* |
| 1237 | * (Re-)program MBUS remapping windows if we are asked to. |
| 1238 | */ |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 1239 | dram = mv_mbus_dram_info(); |
| 1240 | if (dram) |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1241 | mv_xor_conf_mbus_windows(xordev, dram); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1242 | |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1243 | /* Not all platforms can gate the clock, so it is not |
| 1244 | * an error if the clock does not exists. |
| 1245 | */ |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1246 | xordev->clk = clk_get(&pdev->dev, NULL); |
| 1247 | if (!IS_ERR(xordev->clk)) |
| 1248 | clk_prepare_enable(xordev->clk); |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1249 | |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1250 | if (pdev->dev.of_node) { |
| 1251 | struct device_node *np; |
| 1252 | int i = 0; |
| 1253 | |
| 1254 | for_each_child_of_node(pdev->dev.of_node, np) { |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1255 | struct mv_xor_chan *chan; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1256 | dma_cap_mask_t cap_mask; |
| 1257 | int irq; |
| 1258 | |
| 1259 | dma_cap_zero(cap_mask); |
| 1260 | if (of_property_read_bool(np, "dmacap,memcpy")) |
| 1261 | dma_cap_set(DMA_MEMCPY, cap_mask); |
| 1262 | if (of_property_read_bool(np, "dmacap,xor")) |
| 1263 | dma_cap_set(DMA_XOR, cap_mask); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1264 | if (of_property_read_bool(np, "dmacap,interrupt")) |
| 1265 | dma_cap_set(DMA_INTERRUPT, cap_mask); |
| 1266 | |
| 1267 | irq = irq_of_parse_and_map(np, 0); |
Thomas Petazzoni | f8eb9e7 | 2012-11-22 18:22:12 +0100 | [diff] [blame] | 1268 | if (!irq) { |
| 1269 | ret = -ENODEV; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1270 | goto err_channel_add; |
| 1271 | } |
| 1272 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1273 | chan = mv_xor_channel_add(xordev, pdev, i, |
| 1274 | cap_mask, irq); |
| 1275 | if (IS_ERR(chan)) { |
| 1276 | ret = PTR_ERR(chan); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1277 | irq_dispose_mapping(irq); |
| 1278 | goto err_channel_add; |
| 1279 | } |
| 1280 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1281 | xordev->channels[i] = chan; |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1282 | i++; |
| 1283 | } |
| 1284 | } else if (pdata && pdata->channels) { |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1285 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { |
Thomas Petazzoni | e39f6ec | 2012-10-30 11:56:26 +0100 | [diff] [blame] | 1286 | struct mv_xor_channel_data *cd; |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1287 | struct mv_xor_chan *chan; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1288 | int irq; |
| 1289 | |
| 1290 | cd = &pdata->channels[i]; |
| 1291 | if (!cd) { |
| 1292 | ret = -ENODEV; |
| 1293 | goto err_channel_add; |
| 1294 | } |
| 1295 | |
| 1296 | irq = platform_get_irq(pdev, i); |
| 1297 | if (irq < 0) { |
| 1298 | ret = irq; |
| 1299 | goto err_channel_add; |
| 1300 | } |
| 1301 | |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1302 | chan = mv_xor_channel_add(xordev, pdev, i, |
| 1303 | cd->cap_mask, irq); |
| 1304 | if (IS_ERR(chan)) { |
| 1305 | ret = PTR_ERR(chan); |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1306 | goto err_channel_add; |
| 1307 | } |
Russell King | 0be8253 | 2013-12-12 23:59:08 +0000 | [diff] [blame] | 1308 | |
| 1309 | xordev->channels[i] = chan; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1310 | } |
| 1311 | } |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1312 | |
| 1313 | return 0; |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1314 | |
| 1315 | err_channel_add: |
| 1316 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1317 | if (xordev->channels[i]) { |
Thomas Petazzoni | ab6e439 | 2013-01-06 11:10:43 +0100 | [diff] [blame] | 1318 | mv_xor_channel_remove(xordev->channels[i]); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1319 | if (pdev->dev.of_node) |
| 1320 | irq_dispose_mapping(xordev->channels[i]->irq); |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1321 | } |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1322 | |
Thomas Petazzoni | dab9206 | 2013-01-06 11:10:44 +0100 | [diff] [blame] | 1323 | if (!IS_ERR(xordev->clk)) { |
| 1324 | clk_disable_unprepare(xordev->clk); |
| 1325 | clk_put(xordev->clk); |
| 1326 | } |
| 1327 | |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1328 | return ret; |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1329 | } |
| 1330 | |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 1331 | static int mv_xor_remove(struct platform_device *pdev) |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1332 | { |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1333 | struct mv_xor_device *xordev = platform_get_drvdata(pdev); |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1334 | int i; |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1335 | |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1336 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1337 | if (xordev->channels[i]) |
| 1338 | mv_xor_channel_remove(xordev->channels[i]); |
Thomas Petazzoni | 60d151f | 2012-10-29 16:54:49 +0100 | [diff] [blame] | 1339 | } |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1340 | |
Thomas Petazzoni | 297eedb | 2012-11-15 15:29:53 +0100 | [diff] [blame] | 1341 | if (!IS_ERR(xordev->clk)) { |
| 1342 | clk_disable_unprepare(xordev->clk); |
| 1343 | clk_put(xordev->clk); |
Andrew Lunn | c510182 | 2012-02-19 13:30:26 +0100 | [diff] [blame] | 1344 | } |
| 1345 | |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1346 | return 0; |
| 1347 | } |
| 1348 | |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1349 | #ifdef CONFIG_OF |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 1350 | static struct of_device_id mv_xor_dt_ids[] = { |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1351 | { .compatible = "marvell,orion-xor", }, |
| 1352 | {}, |
| 1353 | }; |
| 1354 | MODULE_DEVICE_TABLE(of, mv_xor_dt_ids); |
| 1355 | #endif |
| 1356 | |
Thomas Petazzoni | 6197165 | 2012-10-30 12:05:40 +0100 | [diff] [blame] | 1357 | static struct platform_driver mv_xor_driver = { |
| 1358 | .probe = mv_xor_probe, |
Linus Torvalds | c271433 | 2012-12-14 14:54:26 -0800 | [diff] [blame] | 1359 | .remove = mv_xor_remove, |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1360 | .driver = { |
Thomas Petazzoni | f7d12ef | 2012-11-15 16:47:58 +0100 | [diff] [blame] | 1361 | .owner = THIS_MODULE, |
| 1362 | .name = MV_XOR_NAME, |
| 1363 | .of_match_table = of_match_ptr(mv_xor_dt_ids), |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1364 | }, |
| 1365 | }; |
| 1366 | |
| 1367 | |
| 1368 | static int __init mv_xor_init(void) |
| 1369 | { |
Thomas Petazzoni | 6197165 | 2012-10-30 12:05:40 +0100 | [diff] [blame] | 1370 | return platform_driver_register(&mv_xor_driver); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1371 | } |
| 1372 | module_init(mv_xor_init); |
| 1373 | |
| 1374 | /* it's currently unsafe to unload this module */ |
| 1375 | #if 0 |
| 1376 | static void __exit mv_xor_exit(void) |
| 1377 | { |
| 1378 | platform_driver_unregister(&mv_xor_driver); |
Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 1379 | return; |
| 1380 | } |
| 1381 | |
| 1382 | module_exit(mv_xor_exit); |
| 1383 | #endif |
| 1384 | |
| 1385 | MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>"); |
| 1386 | MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine"); |
| 1387 | MODULE_LICENSE("GPL"); |