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Chris Leech0bbd5f42006-05-23 17:35:34 -07001/*
Shannon Nelson43d6e362007-10-16 01:27:39 -07002 * Intel I/OAT DMA Linux driver
Maciej Sosnowski211a22c2009-02-26 11:05:43 +01003 * Copyright(c) 2004 - 2009 Intel Corporation.
Chris Leech0bbd5f42006-05-23 17:35:34 -07004 *
5 * This program is free software; you can redistribute it and/or modify it
Shannon Nelson43d6e362007-10-16 01:27:39 -07006 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
Chris Leech0bbd5f42006-05-23 17:35:34 -07008 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
Shannon Nelson43d6e362007-10-16 01:27:39 -070015 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
Chris Leech0bbd5f42006-05-23 17:35:34 -070017 *
Shannon Nelson43d6e362007-10-16 01:27:39 -070018 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
Chris Leech0bbd5f42006-05-23 17:35:34 -070021 */
22
23/*
24 * This driver supports an Intel I/OAT DMA engine, which does asynchronous
25 * copy operations.
26 */
27
28#include <linux/init.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
David S. Miller6b00c922006-05-23 17:37:58 -070034#include <linux/dma-mapping.h>
Maciej Sosnowski09177e82008-07-22 10:07:33 -070035#include <linux/workqueue.h>
Venki Pallipadi3ad0b022008-10-22 16:34:52 -070036#include <linux/i7300_idle.h>
Chris Leech0bbd5f42006-05-23 17:35:34 -070037#include "ioatdma.h"
Chris Leech0bbd5f42006-05-23 17:35:34 -070038#include "ioatdma_registers.h"
39#include "ioatdma_hw.h"
40
41#define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common)
Shannon Nelson8ab89562007-10-16 01:27:39 -070042#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
Chris Leech0bbd5f42006-05-23 17:35:34 -070043#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
Dan Williams7405f742007-01-02 11:10:43 -070044#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, async_tx)
Chris Leech0bbd5f42006-05-23 17:35:34 -070045
Maciej Sosnowski09177e82008-07-22 10:07:33 -070046#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
Shannon Nelson7bb67c12007-11-14 16:59:51 -080047static int ioat_pending_level = 4;
48module_param(ioat_pending_level, int, 0644);
49MODULE_PARM_DESC(ioat_pending_level,
50 "high-water mark for pushing ioat descriptors (default: 4)");
51
Maciej Sosnowski09177e82008-07-22 10:07:33 -070052#define RESET_DELAY msecs_to_jiffies(100)
53#define WATCHDOG_DELAY round_jiffies(msecs_to_jiffies(2000))
54static void ioat_dma_chan_reset_part2(struct work_struct *work);
55static void ioat_dma_chan_watchdog(struct work_struct *work);
56
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -070057/*
58 * workaround for IOAT ver.3.0 null descriptor issue
59 * (channel returns error when size is 0)
60 */
61#define NULL_DESC_BUFFER_SIZE 1
62
Chris Leech0bbd5f42006-05-23 17:35:34 -070063/* internal functions */
Shannon Nelson43d6e362007-10-16 01:27:39 -070064static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan);
65static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan);
Shannon Nelson7bb67c12007-11-14 16:59:51 -080066
Shannon Nelson7f2b2912007-10-18 03:07:14 -070067static struct ioat_desc_sw *
Shannon Nelson7bb67c12007-11-14 16:59:51 -080068ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
69static struct ioat_desc_sw *
70ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
Chris Leech0bbd5f42006-05-23 17:35:34 -070071
Shannon Nelson7f2b2912007-10-18 03:07:14 -070072static inline struct ioat_dma_chan *ioat_lookup_chan_by_index(
73 struct ioatdma_device *device,
74 int index)
Shannon Nelson3e037452007-10-16 01:27:40 -070075{
76 return device->idx[index];
77}
78
79/**
80 * ioat_dma_do_interrupt - handler used for single vector interrupt mode
81 * @irq: interrupt id
82 * @data: interrupt data
83 */
84static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
85{
86 struct ioatdma_device *instance = data;
87 struct ioat_dma_chan *ioat_chan;
88 unsigned long attnstatus;
89 int bit;
90 u8 intrctrl;
91
92 intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
93
94 if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
95 return IRQ_NONE;
96
97 if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
98 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
99 return IRQ_NONE;
100 }
101
102 attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
103 for_each_bit(bit, &attnstatus, BITS_PER_LONG) {
104 ioat_chan = ioat_lookup_chan_by_index(instance, bit);
105 tasklet_schedule(&ioat_chan->cleanup_task);
106 }
107
108 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
109 return IRQ_HANDLED;
110}
111
112/**
113 * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
114 * @irq: interrupt id
115 * @data: interrupt data
116 */
117static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
118{
119 struct ioat_dma_chan *ioat_chan = data;
120
121 tasklet_schedule(&ioat_chan->cleanup_task);
122
123 return IRQ_HANDLED;
124}
125
126static void ioat_dma_cleanup_tasklet(unsigned long data);
127
128/**
129 * ioat_dma_enumerate_channels - find and initialize the device's channels
130 * @device: the device to be enumerated
131 */
Shannon Nelson8ab89562007-10-16 01:27:39 -0700132static int ioat_dma_enumerate_channels(struct ioatdma_device *device)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700133{
134 u8 xfercap_scale;
135 u32 xfercap;
136 int i;
137 struct ioat_dma_chan *ioat_chan;
138
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700139 /*
140 * IOAT ver.3 workarounds
141 */
142 if (device->version == IOAT_VER_3_0) {
143 u32 chan_err_mask;
144 u16 dev_id;
145 u32 dmauncerrsts;
146
147 /*
148 * Write CHANERRMSK_INT with 3E07h to mask out the errors
149 * that can cause stability issues for IOAT ver.3
150 */
151 chan_err_mask = 0x3E07;
152 pci_write_config_dword(device->pdev,
153 IOAT_PCI_CHANERRMASK_INT_OFFSET,
154 chan_err_mask);
155
156 /*
157 * Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
158 * (workaround for spurious config parity error after restart)
159 */
160 pci_read_config_word(device->pdev,
161 IOAT_PCI_DEVICE_ID_OFFSET,
162 &dev_id);
163 if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) {
164 dmauncerrsts = 0x10;
165 pci_write_config_dword(device->pdev,
166 IOAT_PCI_DMAUNCERRSTS_OFFSET,
167 dmauncerrsts);
168 }
169 }
170
Chris Leeche3828812007-03-08 09:57:35 -0800171 device->common.chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
172 xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700173 xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
174
Venki Pallipadif371be62008-10-23 15:39:06 -0700175#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
Venki Pallipadi3ad0b022008-10-22 16:34:52 -0700176 if (i7300_idle_platform_probe(NULL, NULL) == 0) {
177 device->common.chancnt--;
178 }
Andy Henroid27471fd2008-10-09 11:45:22 -0700179#endif
Chris Leech0bbd5f42006-05-23 17:35:34 -0700180 for (i = 0; i < device->common.chancnt; i++) {
181 ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL);
182 if (!ioat_chan) {
183 device->common.chancnt = i;
184 break;
185 }
186
187 ioat_chan->device = device;
188 ioat_chan->reg_base = device->reg_base + (0x80 * (i + 1));
189 ioat_chan->xfercap = xfercap;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800190 ioat_chan->desccount = 0;
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700191 INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2);
Maciej Sosnowskiea9c7172009-02-26 11:04:38 +0100192 if (ioat_chan->device->version == IOAT_VER_2_0)
193 writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE |
194 IOAT_DMA_DCA_ANY_CPU,
195 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
196 else if (ioat_chan->device->version == IOAT_VER_3_0)
197 writel(IOAT_DMA_DCA_ANY_CPU,
198 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700199 spin_lock_init(&ioat_chan->cleanup_lock);
200 spin_lock_init(&ioat_chan->desc_lock);
201 INIT_LIST_HEAD(&ioat_chan->free_desc);
202 INIT_LIST_HEAD(&ioat_chan->used_desc);
203 /* This should be made common somewhere in dmaengine.c */
204 ioat_chan->common.device = &device->common;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700205 list_add_tail(&ioat_chan->common.device_node,
Shannon Nelson43d6e362007-10-16 01:27:39 -0700206 &device->common.channels);
Shannon Nelson3e037452007-10-16 01:27:40 -0700207 device->idx[i] = ioat_chan;
208 tasklet_init(&ioat_chan->cleanup_task,
209 ioat_dma_cleanup_tasklet,
210 (unsigned long) ioat_chan);
211 tasklet_disable(&ioat_chan->cleanup_task);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700212 }
213 return device->common.chancnt;
214}
215
Shannon Nelson711924b2007-12-17 16:20:08 -0800216/**
217 * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
218 * descriptors to hw
219 * @chan: DMA channel handle
220 */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800221static inline void __ioat1_dma_memcpy_issue_pending(
Shannon Nelson711924b2007-12-17 16:20:08 -0800222 struct ioat_dma_chan *ioat_chan)
223{
224 ioat_chan->pending = 0;
225 writeb(IOAT_CHANCMD_APPEND, ioat_chan->reg_base + IOAT1_CHANCMD_OFFSET);
226}
227
228static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
229{
230 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
231
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700232 if (ioat_chan->pending > 0) {
Shannon Nelson711924b2007-12-17 16:20:08 -0800233 spin_lock_bh(&ioat_chan->desc_lock);
234 __ioat1_dma_memcpy_issue_pending(ioat_chan);
235 spin_unlock_bh(&ioat_chan->desc_lock);
236 }
237}
238
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800239static inline void __ioat2_dma_memcpy_issue_pending(
Shannon Nelson711924b2007-12-17 16:20:08 -0800240 struct ioat_dma_chan *ioat_chan)
241{
242 ioat_chan->pending = 0;
243 writew(ioat_chan->dmacount,
244 ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
245}
246
247static void ioat2_dma_memcpy_issue_pending(struct dma_chan *chan)
248{
249 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
250
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700251 if (ioat_chan->pending > 0) {
Shannon Nelson711924b2007-12-17 16:20:08 -0800252 spin_lock_bh(&ioat_chan->desc_lock);
253 __ioat2_dma_memcpy_issue_pending(ioat_chan);
254 spin_unlock_bh(&ioat_chan->desc_lock);
255 }
256}
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800257
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700258
259/**
260 * ioat_dma_chan_reset_part2 - reinit the channel after a reset
261 */
262static void ioat_dma_chan_reset_part2(struct work_struct *work)
263{
264 struct ioat_dma_chan *ioat_chan =
265 container_of(work, struct ioat_dma_chan, work.work);
266 struct ioat_desc_sw *desc;
267
268 spin_lock_bh(&ioat_chan->cleanup_lock);
269 spin_lock_bh(&ioat_chan->desc_lock);
270
271 ioat_chan->completion_virt->low = 0;
272 ioat_chan->completion_virt->high = 0;
273 ioat_chan->pending = 0;
274
275 /*
276 * count the descriptors waiting, and be sure to do it
277 * right for both the CB1 line and the CB2 ring
278 */
279 ioat_chan->dmacount = 0;
280 if (ioat_chan->used_desc.prev) {
281 desc = to_ioat_desc(ioat_chan->used_desc.prev);
282 do {
283 ioat_chan->dmacount++;
284 desc = to_ioat_desc(desc->node.next);
285 } while (&desc->node != ioat_chan->used_desc.next);
286 }
287
288 /*
289 * write the new starting descriptor address
290 * this puts channel engine into ARMED state
291 */
292 desc = to_ioat_desc(ioat_chan->used_desc.prev);
293 switch (ioat_chan->device->version) {
294 case IOAT_VER_1_2:
295 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
296 ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
297 writel(((u64) desc->async_tx.phys) >> 32,
298 ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
299
300 writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
301 + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
302 break;
303 case IOAT_VER_2_0:
304 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
305 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
306 writel(((u64) desc->async_tx.phys) >> 32,
307 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
308
309 /* tell the engine to go with what's left to be done */
310 writew(ioat_chan->dmacount,
311 ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
312
313 break;
314 }
315 dev_err(&ioat_chan->device->pdev->dev,
316 "chan%d reset - %d descs waiting, %d total desc\n",
317 chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
318
319 spin_unlock_bh(&ioat_chan->desc_lock);
320 spin_unlock_bh(&ioat_chan->cleanup_lock);
321}
322
323/**
324 * ioat_dma_reset_channel - restart a channel
325 * @ioat_chan: IOAT DMA channel handle
326 */
327static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat_chan)
328{
329 u32 chansts, chanerr;
330
331 if (!ioat_chan->used_desc.prev)
332 return;
333
334 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
335 chansts = (ioat_chan->completion_virt->low
336 & IOAT_CHANSTS_DMA_TRANSFER_STATUS);
337 if (chanerr) {
338 dev_err(&ioat_chan->device->pdev->dev,
339 "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
340 chan_num(ioat_chan), chansts, chanerr);
341 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
342 }
343
344 /*
345 * whack it upside the head with a reset
346 * and wait for things to settle out.
347 * force the pending count to a really big negative
348 * to make sure no one forces an issue_pending
349 * while we're waiting.
350 */
351
352 spin_lock_bh(&ioat_chan->desc_lock);
353 ioat_chan->pending = INT_MIN;
354 writeb(IOAT_CHANCMD_RESET,
355 ioat_chan->reg_base
356 + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
357 spin_unlock_bh(&ioat_chan->desc_lock);
358
359 /* schedule the 2nd half instead of sleeping a long time */
360 schedule_delayed_work(&ioat_chan->work, RESET_DELAY);
361}
362
363/**
364 * ioat_dma_chan_watchdog - watch for stuck channels
365 */
366static void ioat_dma_chan_watchdog(struct work_struct *work)
367{
368 struct ioatdma_device *device =
369 container_of(work, struct ioatdma_device, work.work);
370 struct ioat_dma_chan *ioat_chan;
371 int i;
372
373 union {
374 u64 full;
375 struct {
376 u32 low;
377 u32 high;
378 };
379 } completion_hw;
380 unsigned long compl_desc_addr_hw;
381
382 for (i = 0; i < device->common.chancnt; i++) {
383 ioat_chan = ioat_lookup_chan_by_index(device, i);
384
385 if (ioat_chan->device->version == IOAT_VER_1_2
386 /* have we started processing anything yet */
387 && ioat_chan->last_completion
388 /* have we completed any since last watchdog cycle? */
389 && (ioat_chan->last_completion ==
390 ioat_chan->watchdog_completion)
391 /* has TCP stuck on one cookie since last watchdog? */
392 && (ioat_chan->watchdog_tcp_cookie ==
393 ioat_chan->watchdog_last_tcp_cookie)
394 && (ioat_chan->watchdog_tcp_cookie !=
395 ioat_chan->completed_cookie)
396 /* is there something in the chain to be processed? */
397 /* CB1 chain always has at least the last one processed */
398 && (ioat_chan->used_desc.prev != ioat_chan->used_desc.next)
399 && ioat_chan->pending == 0) {
400
401 /*
402 * check CHANSTS register for completed
403 * descriptor address.
404 * if it is different than completion writeback,
405 * it is not zero
406 * and it has changed since the last watchdog
407 * we can assume that channel
408 * is still working correctly
409 * and the problem is in completion writeback.
410 * update completion writeback
411 * with actual CHANSTS value
412 * else
413 * try resetting the channel
414 */
415
416 completion_hw.low = readl(ioat_chan->reg_base +
417 IOAT_CHANSTS_OFFSET_LOW(ioat_chan->device->version));
418 completion_hw.high = readl(ioat_chan->reg_base +
419 IOAT_CHANSTS_OFFSET_HIGH(ioat_chan->device->version));
420#if (BITS_PER_LONG == 64)
421 compl_desc_addr_hw =
422 completion_hw.full
423 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
424#else
425 compl_desc_addr_hw =
426 completion_hw.low & IOAT_LOW_COMPLETION_MASK;
427#endif
428
429 if ((compl_desc_addr_hw != 0)
430 && (compl_desc_addr_hw != ioat_chan->watchdog_completion)
431 && (compl_desc_addr_hw != ioat_chan->last_compl_desc_addr_hw)) {
432 ioat_chan->last_compl_desc_addr_hw = compl_desc_addr_hw;
433 ioat_chan->completion_virt->low = completion_hw.low;
434 ioat_chan->completion_virt->high = completion_hw.high;
435 } else {
436 ioat_dma_reset_channel(ioat_chan);
437 ioat_chan->watchdog_completion = 0;
438 ioat_chan->last_compl_desc_addr_hw = 0;
439 }
440
441 /*
442 * for version 2.0 if there are descriptors yet to be processed
443 * and the last completed hasn't changed since the last watchdog
444 * if they haven't hit the pending level
445 * issue the pending to push them through
446 * else
447 * try resetting the channel
448 */
449 } else if (ioat_chan->device->version == IOAT_VER_2_0
450 && ioat_chan->used_desc.prev
451 && ioat_chan->last_completion
452 && ioat_chan->last_completion == ioat_chan->watchdog_completion) {
453
454 if (ioat_chan->pending < ioat_pending_level)
455 ioat2_dma_memcpy_issue_pending(&ioat_chan->common);
456 else {
457 ioat_dma_reset_channel(ioat_chan);
458 ioat_chan->watchdog_completion = 0;
459 }
460 } else {
461 ioat_chan->last_compl_desc_addr_hw = 0;
462 ioat_chan->watchdog_completion
463 = ioat_chan->last_completion;
464 }
465
466 ioat_chan->watchdog_last_tcp_cookie =
467 ioat_chan->watchdog_tcp_cookie;
468 }
469
470 schedule_delayed_work(&device->work, WATCHDOG_DELAY);
471}
472
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800473static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
Dan Williams7405f742007-01-02 11:10:43 -0700474{
475 struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700476 struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
477 struct ioat_desc_sw *prev, *new;
478 struct ioat_dma_descriptor *hw;
Dan Williams7405f742007-01-02 11:10:43 -0700479 dma_cookie_t cookie;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700480 LIST_HEAD(new_chain);
481 u32 copy;
482 size_t len;
483 dma_addr_t src, dst;
Dan Williams636bdea2008-04-17 20:17:26 -0700484 unsigned long orig_flags;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700485 unsigned int desc_count = 0;
Dan Williams7405f742007-01-02 11:10:43 -0700486
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700487 /* src and dest and len are stored in the initial descriptor */
488 len = first->len;
489 src = first->src;
490 dst = first->dst;
Dan Williams636bdea2008-04-17 20:17:26 -0700491 orig_flags = first->async_tx.flags;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700492 new = first;
493
Dan Williams7405f742007-01-02 11:10:43 -0700494 spin_lock_bh(&ioat_chan->desc_lock);
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700495 prev = to_ioat_desc(ioat_chan->used_desc.prev);
496 prefetch(prev->hw);
497 do {
Shannon Nelson711924b2007-12-17 16:20:08 -0800498 copy = min_t(size_t, len, ioat_chan->xfercap);
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700499
Dan Williams636bdea2008-04-17 20:17:26 -0700500 async_tx_ack(&new->async_tx);
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700501
502 hw = new->hw;
503 hw->size = copy;
504 hw->ctl = 0;
505 hw->src_addr = src;
506 hw->dst_addr = dst;
507 hw->next = 0;
508
509 /* chain together the physical address list for the HW */
510 wmb();
511 prev->hw->next = (u64) new->async_tx.phys;
512
513 len -= copy;
514 dst += copy;
515 src += copy;
516
517 list_add_tail(&new->node, &new_chain);
518 desc_count++;
519 prev = new;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800520 } while (len && (new = ioat1_dma_get_next_descriptor(ioat_chan)));
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700521
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700522 if (!new) {
523 dev_err(&ioat_chan->device->pdev->dev,
524 "tx submit failed\n");
525 spin_unlock_bh(&ioat_chan->desc_lock);
526 return -ENOMEM;
527 }
528
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700529 hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
Maciej Sosnowski12ccea22008-11-07 01:46:55 +0000530 if (first->async_tx.callback) {
Shannon Nelson95218432007-10-18 03:07:15 -0700531 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
532 if (first != new) {
533 /* move callback into to last desc */
534 new->async_tx.callback = first->async_tx.callback;
535 new->async_tx.callback_param
536 = first->async_tx.callback_param;
537 first->async_tx.callback = NULL;
538 first->async_tx.callback_param = NULL;
539 }
540 }
541
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700542 new->tx_cnt = desc_count;
Dan Williams636bdea2008-04-17 20:17:26 -0700543 new->async_tx.flags = orig_flags; /* client is in control of this ack */
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700544
545 /* store the original values for use in later cleanup */
546 if (new != first) {
547 new->src = first->src;
548 new->dst = first->dst;
549 new->len = first->len;
550 }
551
Dan Williams7405f742007-01-02 11:10:43 -0700552 /* cookie incr and addition to used_list must be atomic */
553 cookie = ioat_chan->common.cookie;
554 cookie++;
555 if (cookie < 0)
556 cookie = 1;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700557 ioat_chan->common.cookie = new->async_tx.cookie = cookie;
Dan Williams7405f742007-01-02 11:10:43 -0700558
559 /* write address into NextDescriptor field of last desc in chain */
560 to_ioat_desc(ioat_chan->used_desc.prev)->hw->next =
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700561 first->async_tx.phys;
Luis R. Rodriguez7d283ae2008-08-06 15:21:26 -0700562 list_splice_tail(&new_chain, &ioat_chan->used_desc);
Dan Williams7405f742007-01-02 11:10:43 -0700563
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800564 ioat_chan->dmacount += desc_count;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700565 ioat_chan->pending += desc_count;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800566 if (ioat_chan->pending >= ioat_pending_level)
567 __ioat1_dma_memcpy_issue_pending(ioat_chan);
Dan Williams7405f742007-01-02 11:10:43 -0700568 spin_unlock_bh(&ioat_chan->desc_lock);
569
Dan Williams7405f742007-01-02 11:10:43 -0700570 return cookie;
571}
572
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800573static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
574{
575 struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
576 struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
577 struct ioat_desc_sw *new;
578 struct ioat_dma_descriptor *hw;
579 dma_cookie_t cookie;
580 u32 copy;
581 size_t len;
582 dma_addr_t src, dst;
Dan Williams636bdea2008-04-17 20:17:26 -0700583 unsigned long orig_flags;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800584 unsigned int desc_count = 0;
585
586 /* src and dest and len are stored in the initial descriptor */
587 len = first->len;
588 src = first->src;
589 dst = first->dst;
Dan Williams636bdea2008-04-17 20:17:26 -0700590 orig_flags = first->async_tx.flags;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800591 new = first;
592
Shannon Nelson711924b2007-12-17 16:20:08 -0800593 /*
594 * ioat_chan->desc_lock is still in force in version 2 path
595 * it gets unlocked at end of this function
596 */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800597 do {
Shannon Nelson711924b2007-12-17 16:20:08 -0800598 copy = min_t(size_t, len, ioat_chan->xfercap);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800599
Dan Williams636bdea2008-04-17 20:17:26 -0700600 async_tx_ack(&new->async_tx);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800601
602 hw = new->hw;
603 hw->size = copy;
604 hw->ctl = 0;
605 hw->src_addr = src;
606 hw->dst_addr = dst;
607
608 len -= copy;
609 dst += copy;
610 src += copy;
611 desc_count++;
612 } while (len && (new = ioat2_dma_get_next_descriptor(ioat_chan)));
613
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700614 if (!new) {
615 dev_err(&ioat_chan->device->pdev->dev,
616 "tx submit failed\n");
617 spin_unlock_bh(&ioat_chan->desc_lock);
618 return -ENOMEM;
619 }
620
621 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
Maciej Sosnowski12ccea22008-11-07 01:46:55 +0000622 if (first->async_tx.callback) {
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800623 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
624 if (first != new) {
625 /* move callback into to last desc */
626 new->async_tx.callback = first->async_tx.callback;
627 new->async_tx.callback_param
628 = first->async_tx.callback_param;
629 first->async_tx.callback = NULL;
630 first->async_tx.callback_param = NULL;
631 }
632 }
633
634 new->tx_cnt = desc_count;
Dan Williams636bdea2008-04-17 20:17:26 -0700635 new->async_tx.flags = orig_flags; /* client is in control of this ack */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800636
637 /* store the original values for use in later cleanup */
638 if (new != first) {
639 new->src = first->src;
640 new->dst = first->dst;
641 new->len = first->len;
642 }
643
644 /* cookie incr and addition to used_list must be atomic */
645 cookie = ioat_chan->common.cookie;
646 cookie++;
647 if (cookie < 0)
648 cookie = 1;
649 ioat_chan->common.cookie = new->async_tx.cookie = cookie;
650
651 ioat_chan->dmacount += desc_count;
652 ioat_chan->pending += desc_count;
653 if (ioat_chan->pending >= ioat_pending_level)
654 __ioat2_dma_memcpy_issue_pending(ioat_chan);
655 spin_unlock_bh(&ioat_chan->desc_lock);
656
657 return cookie;
658}
659
660/**
661 * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
662 * @ioat_chan: the channel supplying the memory pool for the descriptors
663 * @flags: allocation flags
664 */
Chris Leech0bbd5f42006-05-23 17:35:34 -0700665static struct ioat_desc_sw *ioat_dma_alloc_descriptor(
Shannon Nelson43d6e362007-10-16 01:27:39 -0700666 struct ioat_dma_chan *ioat_chan,
667 gfp_t flags)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700668{
669 struct ioat_dma_descriptor *desc;
670 struct ioat_desc_sw *desc_sw;
Shannon Nelson8ab89562007-10-16 01:27:39 -0700671 struct ioatdma_device *ioatdma_device;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700672 dma_addr_t phys;
673
Shannon Nelson8ab89562007-10-16 01:27:39 -0700674 ioatdma_device = to_ioatdma_device(ioat_chan->common.device);
675 desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700676 if (unlikely(!desc))
677 return NULL;
678
679 desc_sw = kzalloc(sizeof(*desc_sw), flags);
680 if (unlikely(!desc_sw)) {
Shannon Nelson8ab89562007-10-16 01:27:39 -0700681 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700682 return NULL;
683 }
684
685 memset(desc, 0, sizeof(*desc));
Dan Williams7405f742007-01-02 11:10:43 -0700686 dma_async_tx_descriptor_init(&desc_sw->async_tx, &ioat_chan->common);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800687 switch (ioat_chan->device->version) {
688 case IOAT_VER_1_2:
689 desc_sw->async_tx.tx_submit = ioat1_tx_submit;
690 break;
691 case IOAT_VER_2_0:
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700692 case IOAT_VER_3_0:
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800693 desc_sw->async_tx.tx_submit = ioat2_tx_submit;
694 break;
695 }
Dan Williams7405f742007-01-02 11:10:43 -0700696 INIT_LIST_HEAD(&desc_sw->async_tx.tx_list);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800697
Chris Leech0bbd5f42006-05-23 17:35:34 -0700698 desc_sw->hw = desc;
Dan Williams7405f742007-01-02 11:10:43 -0700699 desc_sw->async_tx.phys = phys;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700700
701 return desc_sw;
702}
703
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800704static int ioat_initial_desc_count = 256;
705module_param(ioat_initial_desc_count, int, 0644);
706MODULE_PARM_DESC(ioat_initial_desc_count,
707 "initial descriptors per channel (default: 256)");
708
709/**
710 * ioat2_dma_massage_chan_desc - link the descriptors into a circle
711 * @ioat_chan: the channel to be massaged
712 */
713static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat_chan)
714{
715 struct ioat_desc_sw *desc, *_desc;
716
717 /* setup used_desc */
718 ioat_chan->used_desc.next = ioat_chan->free_desc.next;
719 ioat_chan->used_desc.prev = NULL;
720
721 /* pull free_desc out of the circle so that every node is a hw
722 * descriptor, but leave it pointing to the list
723 */
724 ioat_chan->free_desc.prev->next = ioat_chan->free_desc.next;
725 ioat_chan->free_desc.next->prev = ioat_chan->free_desc.prev;
726
727 /* circle link the hw descriptors */
728 desc = to_ioat_desc(ioat_chan->free_desc.next);
729 desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
730 list_for_each_entry_safe(desc, _desc, ioat_chan->free_desc.next, node) {
731 desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
732 }
733}
734
735/**
736 * ioat_dma_alloc_chan_resources - returns the number of allocated descriptors
737 * @chan: the channel to be filled out
738 */
Dan Williamsaa1e6f12009-01-06 11:38:17 -0700739static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700740{
741 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
Shannon Nelson711924b2007-12-17 16:20:08 -0800742 struct ioat_desc_sw *desc;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700743 u16 chanctrl;
744 u32 chanerr;
745 int i;
746 LIST_HEAD(tmp_list);
747
Shannon Nelsone4223972007-08-24 23:02:53 -0700748 /* have we already been set up? */
749 if (!list_empty(&ioat_chan->free_desc))
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800750 return ioat_chan->desccount;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700751
Shannon Nelson43d6e362007-10-16 01:27:39 -0700752 /* Setup register to interrupt and write completion status on error */
Shannon Nelsone4223972007-08-24 23:02:53 -0700753 chanctrl = IOAT_CHANCTRL_ERR_INT_EN |
Chris Leech0bbd5f42006-05-23 17:35:34 -0700754 IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
755 IOAT_CHANCTRL_ERR_COMPLETION_EN;
Shannon Nelson43d6e362007-10-16 01:27:39 -0700756 writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700757
Chris Leeche3828812007-03-08 09:57:35 -0800758 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700759 if (chanerr) {
Shannon Nelson43d6e362007-10-16 01:27:39 -0700760 dev_err(&ioat_chan->device->pdev->dev,
Shannon Nelson5149fd02007-10-18 03:07:13 -0700761 "CHANERR = %x, clearing\n", chanerr);
Chris Leeche3828812007-03-08 09:57:35 -0800762 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700763 }
764
765 /* Allocate descriptors */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800766 for (i = 0; i < ioat_initial_desc_count; i++) {
Chris Leech0bbd5f42006-05-23 17:35:34 -0700767 desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL);
768 if (!desc) {
Shannon Nelson43d6e362007-10-16 01:27:39 -0700769 dev_err(&ioat_chan->device->pdev->dev,
Shannon Nelson5149fd02007-10-18 03:07:13 -0700770 "Only %d initial descriptors\n", i);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700771 break;
772 }
773 list_add_tail(&desc->node, &tmp_list);
774 }
775 spin_lock_bh(&ioat_chan->desc_lock);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800776 ioat_chan->desccount = i;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700777 list_splice(&tmp_list, &ioat_chan->free_desc);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800778 if (ioat_chan->device->version != IOAT_VER_1_2)
779 ioat2_dma_massage_chan_desc(ioat_chan);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700780 spin_unlock_bh(&ioat_chan->desc_lock);
781
782 /* allocate a completion writeback area */
783 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
784 ioat_chan->completion_virt =
785 pci_pool_alloc(ioat_chan->device->completion_pool,
Shannon Nelson43d6e362007-10-16 01:27:39 -0700786 GFP_KERNEL,
787 &ioat_chan->completion_addr);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700788 memset(ioat_chan->completion_virt, 0,
789 sizeof(*ioat_chan->completion_virt));
Chris Leeche3828812007-03-08 09:57:35 -0800790 writel(((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF,
791 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
792 writel(((u64) ioat_chan->completion_addr) >> 32,
793 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700794
Shannon Nelson3e037452007-10-16 01:27:40 -0700795 tasklet_enable(&ioat_chan->cleanup_task);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800796 ioat_dma_start_null_desc(ioat_chan); /* give chain to dma device */
797 return ioat_chan->desccount;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700798}
799
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800800/**
801 * ioat_dma_free_chan_resources - release all the descriptors
802 * @chan: the channel to be cleaned
803 */
Chris Leech0bbd5f42006-05-23 17:35:34 -0700804static void ioat_dma_free_chan_resources(struct dma_chan *chan)
805{
806 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
Shannon Nelson8ab89562007-10-16 01:27:39 -0700807 struct ioatdma_device *ioatdma_device = to_ioatdma_device(chan->device);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700808 struct ioat_desc_sw *desc, *_desc;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700809 int in_use_descs = 0;
810
Maciej Sosnowskic3d4f442008-11-07 01:45:52 +0000811 /* Before freeing channel resources first check
812 * if they have been previously allocated for this channel.
813 */
814 if (ioat_chan->desccount == 0)
815 return;
816
Shannon Nelson3e037452007-10-16 01:27:40 -0700817 tasklet_disable(&ioat_chan->cleanup_task);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700818 ioat_dma_memcpy_cleanup(ioat_chan);
819
Shannon Nelson3e037452007-10-16 01:27:40 -0700820 /* Delay 100ms after reset to allow internal DMA logic to quiesce
821 * before removing DMA descriptor resources.
822 */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800823 writeb(IOAT_CHANCMD_RESET,
824 ioat_chan->reg_base
825 + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
Shannon Nelson3e037452007-10-16 01:27:40 -0700826 mdelay(100);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700827
828 spin_lock_bh(&ioat_chan->desc_lock);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800829 switch (ioat_chan->device->version) {
830 case IOAT_VER_1_2:
831 list_for_each_entry_safe(desc, _desc,
832 &ioat_chan->used_desc, node) {
833 in_use_descs++;
834 list_del(&desc->node);
835 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
836 desc->async_tx.phys);
837 kfree(desc);
838 }
839 list_for_each_entry_safe(desc, _desc,
840 &ioat_chan->free_desc, node) {
841 list_del(&desc->node);
842 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
843 desc->async_tx.phys);
844 kfree(desc);
845 }
846 break;
847 case IOAT_VER_2_0:
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700848 case IOAT_VER_3_0:
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800849 list_for_each_entry_safe(desc, _desc,
850 ioat_chan->free_desc.next, node) {
851 list_del(&desc->node);
852 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
853 desc->async_tx.phys);
854 kfree(desc);
855 }
856 desc = to_ioat_desc(ioat_chan->free_desc.next);
Shannon Nelson8ab89562007-10-16 01:27:39 -0700857 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
Dan Williams7405f742007-01-02 11:10:43 -0700858 desc->async_tx.phys);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700859 kfree(desc);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800860 INIT_LIST_HEAD(&ioat_chan->free_desc);
861 INIT_LIST_HEAD(&ioat_chan->used_desc);
862 break;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700863 }
864 spin_unlock_bh(&ioat_chan->desc_lock);
865
Shannon Nelson8ab89562007-10-16 01:27:39 -0700866 pci_pool_free(ioatdma_device->completion_pool,
Shannon Nelson43d6e362007-10-16 01:27:39 -0700867 ioat_chan->completion_virt,
868 ioat_chan->completion_addr);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700869
870 /* one is ok since we left it on there on purpose */
871 if (in_use_descs > 1)
Shannon Nelson43d6e362007-10-16 01:27:39 -0700872 dev_err(&ioat_chan->device->pdev->dev,
Shannon Nelson5149fd02007-10-18 03:07:13 -0700873 "Freeing %d in use descriptors!\n",
Chris Leech0bbd5f42006-05-23 17:35:34 -0700874 in_use_descs - 1);
875
876 ioat_chan->last_completion = ioat_chan->completion_addr = 0;
Shannon Nelson3e037452007-10-16 01:27:40 -0700877 ioat_chan->pending = 0;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800878 ioat_chan->dmacount = 0;
Maciej Sosnowskic3d4f442008-11-07 01:45:52 +0000879 ioat_chan->desccount = 0;
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700880 ioat_chan->watchdog_completion = 0;
881 ioat_chan->last_compl_desc_addr_hw = 0;
882 ioat_chan->watchdog_tcp_cookie =
883 ioat_chan->watchdog_last_tcp_cookie = 0;
Shannon Nelson3e037452007-10-16 01:27:40 -0700884}
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700885
Shannon Nelson3e037452007-10-16 01:27:40 -0700886/**
887 * ioat_dma_get_next_descriptor - return the next available descriptor
888 * @ioat_chan: IOAT DMA channel handle
889 *
890 * Gets the next descriptor from the chain, and must be called with the
891 * channel's desc_lock held. Allocates more descriptors if the channel
892 * has run out.
893 */
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700894static struct ioat_desc_sw *
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800895ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
Shannon Nelson3e037452007-10-16 01:27:40 -0700896{
Shannon Nelson711924b2007-12-17 16:20:08 -0800897 struct ioat_desc_sw *new;
Shannon Nelson3e037452007-10-16 01:27:40 -0700898
899 if (!list_empty(&ioat_chan->free_desc)) {
900 new = to_ioat_desc(ioat_chan->free_desc.next);
901 list_del(&new->node);
902 } else {
903 /* try to get another desc */
904 new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
Shannon Nelson711924b2007-12-17 16:20:08 -0800905 if (!new) {
906 dev_err(&ioat_chan->device->pdev->dev,
907 "alloc failed\n");
908 return NULL;
909 }
Shannon Nelson3e037452007-10-16 01:27:40 -0700910 }
911
912 prefetch(new->hw);
913 return new;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700914}
915
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800916static struct ioat_desc_sw *
917ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
918{
Shannon Nelson711924b2007-12-17 16:20:08 -0800919 struct ioat_desc_sw *new;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800920
921 /*
922 * used.prev points to where to start processing
923 * used.next points to next free descriptor
924 * if used.prev == NULL, there are none waiting to be processed
925 * if used.next == used.prev.prev, there is only one free descriptor,
926 * and we need to use it to as a noop descriptor before
927 * linking in a new set of descriptors, since the device
928 * has probably already read the pointer to it
929 */
930 if (ioat_chan->used_desc.prev &&
931 ioat_chan->used_desc.next == ioat_chan->used_desc.prev->prev) {
932
Shannon Nelson711924b2007-12-17 16:20:08 -0800933 struct ioat_desc_sw *desc;
934 struct ioat_desc_sw *noop_desc;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800935 int i;
936
937 /* set up the noop descriptor */
938 noop_desc = to_ioat_desc(ioat_chan->used_desc.next);
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700939 /* set size to non-zero value (channel returns error when size is 0) */
940 noop_desc->hw->size = NULL_DESC_BUFFER_SIZE;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800941 noop_desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL;
942 noop_desc->hw->src_addr = 0;
943 noop_desc->hw->dst_addr = 0;
944
945 ioat_chan->used_desc.next = ioat_chan->used_desc.next->next;
946 ioat_chan->pending++;
947 ioat_chan->dmacount++;
948
Shannon Nelson711924b2007-12-17 16:20:08 -0800949 /* try to get a few more descriptors */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800950 for (i = 16; i; i--) {
951 desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
Shannon Nelson711924b2007-12-17 16:20:08 -0800952 if (!desc) {
953 dev_err(&ioat_chan->device->pdev->dev,
954 "alloc failed\n");
955 break;
956 }
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800957 list_add_tail(&desc->node, ioat_chan->used_desc.next);
958
959 desc->hw->next
960 = to_ioat_desc(desc->node.next)->async_tx.phys;
961 to_ioat_desc(desc->node.prev)->hw->next
962 = desc->async_tx.phys;
963 ioat_chan->desccount++;
964 }
965
966 ioat_chan->used_desc.next = noop_desc->node.next;
967 }
968 new = to_ioat_desc(ioat_chan->used_desc.next);
969 prefetch(new);
970 ioat_chan->used_desc.next = new->node.next;
971
972 if (ioat_chan->used_desc.prev == NULL)
973 ioat_chan->used_desc.prev = &new->node;
974
975 prefetch(new->hw);
976 return new;
977}
978
979static struct ioat_desc_sw *ioat_dma_get_next_descriptor(
980 struct ioat_dma_chan *ioat_chan)
981{
982 if (!ioat_chan)
983 return NULL;
984
985 switch (ioat_chan->device->version) {
986 case IOAT_VER_1_2:
987 return ioat1_dma_get_next_descriptor(ioat_chan);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800988 case IOAT_VER_2_0:
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700989 case IOAT_VER_3_0:
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800990 return ioat2_dma_get_next_descriptor(ioat_chan);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800991 }
992 return NULL;
993}
994
995static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy(
Shannon Nelson43d6e362007-10-16 01:27:39 -0700996 struct dma_chan *chan,
Dan Williams00367312008-02-02 19:49:57 -0700997 dma_addr_t dma_dest,
998 dma_addr_t dma_src,
Shannon Nelson43d6e362007-10-16 01:27:39 -0700999 size_t len,
Dan Williamsd4c56f92008-02-02 19:49:58 -07001000 unsigned long flags)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001001{
Dan Williams7405f742007-01-02 11:10:43 -07001002 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001003 struct ioat_desc_sw *new;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001004
1005 spin_lock_bh(&ioat_chan->desc_lock);
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001006 new = ioat_dma_get_next_descriptor(ioat_chan);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001007 spin_unlock_bh(&ioat_chan->desc_lock);
1008
Shannon Nelson711924b2007-12-17 16:20:08 -08001009 if (new) {
1010 new->len = len;
Dan Williams00367312008-02-02 19:49:57 -07001011 new->dst = dma_dest;
1012 new->src = dma_src;
Dan Williams636bdea2008-04-17 20:17:26 -07001013 new->async_tx.flags = flags;
Shannon Nelson711924b2007-12-17 16:20:08 -08001014 return &new->async_tx;
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001015 } else {
1016 dev_err(&ioat_chan->device->pdev->dev,
1017 "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n",
1018 chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
Shannon Nelson711924b2007-12-17 16:20:08 -08001019 return NULL;
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001020 }
Chris Leech0bbd5f42006-05-23 17:35:34 -07001021}
1022
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001023static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy(
1024 struct dma_chan *chan,
Dan Williams00367312008-02-02 19:49:57 -07001025 dma_addr_t dma_dest,
1026 dma_addr_t dma_src,
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001027 size_t len,
Dan Williamsd4c56f92008-02-02 19:49:58 -07001028 unsigned long flags)
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001029{
1030 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
1031 struct ioat_desc_sw *new;
1032
1033 spin_lock_bh(&ioat_chan->desc_lock);
1034 new = ioat2_dma_get_next_descriptor(ioat_chan);
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001035
Shannon Nelson711924b2007-12-17 16:20:08 -08001036 /*
1037 * leave ioat_chan->desc_lock set in ioat 2 path
1038 * it will get unlocked at end of tx_submit
1039 */
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001040
Shannon Nelson711924b2007-12-17 16:20:08 -08001041 if (new) {
1042 new->len = len;
Dan Williams00367312008-02-02 19:49:57 -07001043 new->dst = dma_dest;
1044 new->src = dma_src;
Dan Williams636bdea2008-04-17 20:17:26 -07001045 new->async_tx.flags = flags;
Shannon Nelson711924b2007-12-17 16:20:08 -08001046 return &new->async_tx;
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001047 } else {
1048 spin_unlock_bh(&ioat_chan->desc_lock);
1049 dev_err(&ioat_chan->device->pdev->dev,
1050 "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n",
1051 chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
Shannon Nelson711924b2007-12-17 16:20:08 -08001052 return NULL;
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001053 }
Chris Leech0bbd5f42006-05-23 17:35:34 -07001054}
1055
Shannon Nelson3e037452007-10-16 01:27:40 -07001056static void ioat_dma_cleanup_tasklet(unsigned long data)
1057{
1058 struct ioat_dma_chan *chan = (void *)data;
1059 ioat_dma_memcpy_cleanup(chan);
1060 writew(IOAT_CHANCTRL_INT_DISABLE,
1061 chan->reg_base + IOAT_CHANCTRL_OFFSET);
1062}
1063
Dan Williamse1d181e2008-07-04 00:13:40 -07001064static void
1065ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc)
1066{
1067 /*
1068 * yes we are unmapping both _page and _single
1069 * alloc'd regions with unmap_page. Is this
1070 * *really* that bad?
1071 */
1072 if (!(desc->async_tx.flags & DMA_COMPL_SKIP_DEST_UNMAP))
1073 pci_unmap_page(ioat_chan->device->pdev,
1074 pci_unmap_addr(desc, dst),
1075 pci_unmap_len(desc, len),
1076 PCI_DMA_FROMDEVICE);
1077
1078 if (!(desc->async_tx.flags & DMA_COMPL_SKIP_SRC_UNMAP))
1079 pci_unmap_page(ioat_chan->device->pdev,
1080 pci_unmap_addr(desc, src),
1081 pci_unmap_len(desc, len),
1082 PCI_DMA_TODEVICE);
1083}
1084
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001085/**
1086 * ioat_dma_memcpy_cleanup - cleanup up finished descriptors
1087 * @chan: ioat channel to be cleaned up
1088 */
Shannon Nelson43d6e362007-10-16 01:27:39 -07001089static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001090{
1091 unsigned long phys_complete;
1092 struct ioat_desc_sw *desc, *_desc;
1093 dma_cookie_t cookie = 0;
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001094 unsigned long desc_phys;
1095 struct ioat_desc_sw *latest_desc;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001096
Shannon Nelson43d6e362007-10-16 01:27:39 -07001097 prefetch(ioat_chan->completion_virt);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001098
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001099 if (!spin_trylock_bh(&ioat_chan->cleanup_lock))
Chris Leech0bbd5f42006-05-23 17:35:34 -07001100 return;
1101
1102 /* The completion writeback can happen at any time,
1103 so reads by the driver need to be atomic operations
1104 The descriptor physical addresses are limited to 32-bits
1105 when the CPU can only do a 32-bit mov */
1106
1107#if (BITS_PER_LONG == 64)
1108 phys_complete =
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001109 ioat_chan->completion_virt->full
1110 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001111#else
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001112 phys_complete =
1113 ioat_chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001114#endif
1115
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001116 if ((ioat_chan->completion_virt->full
1117 & IOAT_CHANSTS_DMA_TRANSFER_STATUS) ==
Shannon Nelson43d6e362007-10-16 01:27:39 -07001118 IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) {
1119 dev_err(&ioat_chan->device->pdev->dev,
Shannon Nelson5149fd02007-10-18 03:07:13 -07001120 "Channel halted, chanerr = %x\n",
Shannon Nelson43d6e362007-10-16 01:27:39 -07001121 readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET));
Chris Leech0bbd5f42006-05-23 17:35:34 -07001122
1123 /* TODO do something to salvage the situation */
1124 }
1125
Shannon Nelson43d6e362007-10-16 01:27:39 -07001126 if (phys_complete == ioat_chan->last_completion) {
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001127 spin_unlock_bh(&ioat_chan->cleanup_lock);
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001128 /*
1129 * perhaps we're stuck so hard that the watchdog can't go off?
1130 * try to catch it after 2 seconds
1131 */
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -07001132 if (ioat_chan->device->version != IOAT_VER_3_0) {
1133 if (time_after(jiffies,
1134 ioat_chan->last_completion_time + HZ*WATCHDOG_DELAY)) {
1135 ioat_dma_chan_watchdog(&(ioat_chan->device->work.work));
1136 ioat_chan->last_completion_time = jiffies;
1137 }
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001138 }
1139 return;
1140 }
1141 ioat_chan->last_completion_time = jiffies;
1142
1143 cookie = 0;
1144 if (!spin_trylock_bh(&ioat_chan->desc_lock)) {
1145 spin_unlock_bh(&ioat_chan->cleanup_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001146 return;
1147 }
1148
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001149 switch (ioat_chan->device->version) {
1150 case IOAT_VER_1_2:
1151 list_for_each_entry_safe(desc, _desc,
1152 &ioat_chan->used_desc, node) {
Chris Leech0bbd5f42006-05-23 17:35:34 -07001153
Shannon Nelson43d6e362007-10-16 01:27:39 -07001154 /*
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001155 * Incoming DMA requests may use multiple descriptors,
1156 * due to exceeding xfercap, perhaps. If so, only the
1157 * last one will have a cookie, and require unmapping.
Shannon Nelson43d6e362007-10-16 01:27:39 -07001158 */
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001159 if (desc->async_tx.cookie) {
1160 cookie = desc->async_tx.cookie;
Dan Williamse1d181e2008-07-04 00:13:40 -07001161 ioat_dma_unmap(ioat_chan, desc);
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001162 if (desc->async_tx.callback) {
1163 desc->async_tx.callback(desc->async_tx.callback_param);
1164 desc->async_tx.callback = NULL;
1165 }
1166 }
1167
1168 if (desc->async_tx.phys != phys_complete) {
1169 /*
1170 * a completed entry, but not the last, so clean
1171 * up if the client is done with the descriptor
1172 */
Dan Williams636bdea2008-04-17 20:17:26 -07001173 if (async_tx_test_ack(&desc->async_tx)) {
Eric Sesterhennaa2d0b82009-02-26 11:05:30 +01001174 list_move_tail(&desc->node,
1175 &ioat_chan->free_desc);
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001176 } else
1177 desc->async_tx.cookie = 0;
1178 } else {
1179 /*
1180 * last used desc. Do not remove, so we can
1181 * append from it, but don't look at it next
1182 * time, either
1183 */
1184 desc->async_tx.cookie = 0;
1185
1186 /* TODO check status bits? */
1187 break;
Shannon Nelson95218432007-10-18 03:07:15 -07001188 }
Chris Leech0bbd5f42006-05-23 17:35:34 -07001189 }
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001190 break;
1191 case IOAT_VER_2_0:
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -07001192 case IOAT_VER_3_0:
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001193 /* has some other thread has already cleaned up? */
1194 if (ioat_chan->used_desc.prev == NULL)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001195 break;
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001196
1197 /* work backwards to find latest finished desc */
1198 desc = to_ioat_desc(ioat_chan->used_desc.next);
1199 latest_desc = NULL;
1200 do {
1201 desc = to_ioat_desc(desc->node.prev);
1202 desc_phys = (unsigned long)desc->async_tx.phys
1203 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
1204 if (desc_phys == phys_complete) {
1205 latest_desc = desc;
1206 break;
1207 }
1208 } while (&desc->node != ioat_chan->used_desc.prev);
1209
1210 if (latest_desc != NULL) {
1211
1212 /* work forwards to clear finished descriptors */
1213 for (desc = to_ioat_desc(ioat_chan->used_desc.prev);
1214 &desc->node != latest_desc->node.next &&
1215 &desc->node != ioat_chan->used_desc.next;
1216 desc = to_ioat_desc(desc->node.next)) {
1217 if (desc->async_tx.cookie) {
1218 cookie = desc->async_tx.cookie;
1219 desc->async_tx.cookie = 0;
Dan Williamse1d181e2008-07-04 00:13:40 -07001220 ioat_dma_unmap(ioat_chan, desc);
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001221 if (desc->async_tx.callback) {
1222 desc->async_tx.callback(desc->async_tx.callback_param);
1223 desc->async_tx.callback = NULL;
1224 }
1225 }
1226 }
1227
1228 /* move used.prev up beyond those that are finished */
1229 if (&desc->node == ioat_chan->used_desc.next)
1230 ioat_chan->used_desc.prev = NULL;
1231 else
1232 ioat_chan->used_desc.prev = &desc->node;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001233 }
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001234 break;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001235 }
1236
Shannon Nelson43d6e362007-10-16 01:27:39 -07001237 spin_unlock_bh(&ioat_chan->desc_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001238
Shannon Nelson43d6e362007-10-16 01:27:39 -07001239 ioat_chan->last_completion = phys_complete;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001240 if (cookie != 0)
Shannon Nelson43d6e362007-10-16 01:27:39 -07001241 ioat_chan->completed_cookie = cookie;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001242
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001243 spin_unlock_bh(&ioat_chan->cleanup_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001244}
1245
1246/**
1247 * ioat_dma_is_complete - poll the status of a IOAT DMA transaction
1248 * @chan: IOAT DMA channel handle
1249 * @cookie: DMA transaction identifier
Randy Dunlap65088712006-07-03 19:45:31 -07001250 * @done: if not %NULL, updated with last completed transaction
1251 * @used: if not %NULL, updated with last used transaction
Chris Leech0bbd5f42006-05-23 17:35:34 -07001252 */
Chris Leech0bbd5f42006-05-23 17:35:34 -07001253static enum dma_status ioat_dma_is_complete(struct dma_chan *chan,
Shannon Nelson43d6e362007-10-16 01:27:39 -07001254 dma_cookie_t cookie,
1255 dma_cookie_t *done,
1256 dma_cookie_t *used)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001257{
1258 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
1259 dma_cookie_t last_used;
1260 dma_cookie_t last_complete;
1261 enum dma_status ret;
1262
1263 last_used = chan->cookie;
1264 last_complete = ioat_chan->completed_cookie;
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001265 ioat_chan->watchdog_tcp_cookie = cookie;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001266
1267 if (done)
Shannon Nelson43d6e362007-10-16 01:27:39 -07001268 *done = last_complete;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001269 if (used)
1270 *used = last_used;
1271
1272 ret = dma_async_is_complete(cookie, last_complete, last_used);
1273 if (ret == DMA_SUCCESS)
1274 return ret;
1275
1276 ioat_dma_memcpy_cleanup(ioat_chan);
1277
1278 last_used = chan->cookie;
1279 last_complete = ioat_chan->completed_cookie;
1280
1281 if (done)
Shannon Nelson43d6e362007-10-16 01:27:39 -07001282 *done = last_complete;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001283 if (used)
1284 *used = last_used;
1285
1286 return dma_async_is_complete(cookie, last_complete, last_used);
1287}
1288
Shannon Nelson43d6e362007-10-16 01:27:39 -07001289static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001290{
1291 struct ioat_desc_sw *desc;
1292
1293 spin_lock_bh(&ioat_chan->desc_lock);
1294
Shannon Nelson3e037452007-10-16 01:27:40 -07001295 desc = ioat_dma_get_next_descriptor(ioat_chan);
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -07001296
1297 if (!desc) {
1298 dev_err(&ioat_chan->device->pdev->dev,
1299 "Unable to start null desc - get next desc failed\n");
1300 spin_unlock_bh(&ioat_chan->desc_lock);
1301 return;
1302 }
1303
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001304 desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL
1305 | IOAT_DMA_DESCRIPTOR_CTL_INT_GN
1306 | IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -07001307 /* set size to non-zero value (channel returns error when size is 0) */
1308 desc->hw->size = NULL_DESC_BUFFER_SIZE;
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001309 desc->hw->src_addr = 0;
1310 desc->hw->dst_addr = 0;
Dan Williams636bdea2008-04-17 20:17:26 -07001311 async_tx_ack(&desc->async_tx);
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001312 switch (ioat_chan->device->version) {
1313 case IOAT_VER_1_2:
1314 desc->hw->next = 0;
1315 list_add_tail(&desc->node, &ioat_chan->used_desc);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001316
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001317 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
1318 ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
1319 writel(((u64) desc->async_tx.phys) >> 32,
1320 ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
1321
1322 writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
1323 + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
1324 break;
1325 case IOAT_VER_2_0:
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -07001326 case IOAT_VER_3_0:
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001327 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
1328 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
1329 writel(((u64) desc->async_tx.phys) >> 32,
1330 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
1331
1332 ioat_chan->dmacount++;
1333 __ioat2_dma_memcpy_issue_pending(ioat_chan);
1334 break;
1335 }
Chris Leech0bbd5f42006-05-23 17:35:34 -07001336 spin_unlock_bh(&ioat_chan->desc_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001337}
1338
1339/*
1340 * Perform a IOAT transaction to verify the HW works.
1341 */
1342#define IOAT_TEST_SIZE 2000
1343
Shannon Nelson95218432007-10-18 03:07:15 -07001344static void ioat_dma_test_callback(void *dma_async_param)
1345{
Dan Williamsb9bdcbb2009-01-06 11:38:22 -07001346 struct completion *cmp = dma_async_param;
1347
1348 complete(cmp);
Shannon Nelson95218432007-10-18 03:07:15 -07001349}
1350
Shannon Nelson3e037452007-10-16 01:27:40 -07001351/**
1352 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
1353 * @device: device to be tested
1354 */
1355static int ioat_dma_self_test(struct ioatdma_device *device)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001356{
1357 int i;
1358 u8 *src;
1359 u8 *dest;
1360 struct dma_chan *dma_chan;
Shannon Nelson711924b2007-12-17 16:20:08 -08001361 struct dma_async_tx_descriptor *tx;
Dan Williams00367312008-02-02 19:49:57 -07001362 dma_addr_t dma_dest, dma_src;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001363 dma_cookie_t cookie;
1364 int err = 0;
Dan Williamsb9bdcbb2009-01-06 11:38:22 -07001365 struct completion cmp;
Dan Williams0c33e1c2009-03-02 13:31:35 -07001366 unsigned long tmo;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001367
Christoph Lametere94b1762006-12-06 20:33:17 -08001368 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001369 if (!src)
1370 return -ENOMEM;
Christoph Lametere94b1762006-12-06 20:33:17 -08001371 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001372 if (!dest) {
1373 kfree(src);
1374 return -ENOMEM;
1375 }
1376
1377 /* Fill in src buffer */
1378 for (i = 0; i < IOAT_TEST_SIZE; i++)
1379 src[i] = (u8)i;
1380
1381 /* Start copy, using first DMA channel */
1382 dma_chan = container_of(device->common.channels.next,
Shannon Nelson43d6e362007-10-16 01:27:39 -07001383 struct dma_chan,
1384 device_node);
Dan Williamsaa1e6f12009-01-06 11:38:17 -07001385 if (device->common.device_alloc_chan_resources(dma_chan) < 1) {
Shannon Nelson43d6e362007-10-16 01:27:39 -07001386 dev_err(&device->pdev->dev,
1387 "selftest cannot allocate chan resource\n");
Chris Leech0bbd5f42006-05-23 17:35:34 -07001388 err = -ENODEV;
1389 goto out;
1390 }
1391
Dan Williams00367312008-02-02 19:49:57 -07001392 dma_src = dma_map_single(dma_chan->device->dev, src, IOAT_TEST_SIZE,
1393 DMA_TO_DEVICE);
1394 dma_dest = dma_map_single(dma_chan->device->dev, dest, IOAT_TEST_SIZE,
1395 DMA_FROM_DEVICE);
1396 tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
1397 IOAT_TEST_SIZE, 0);
Shannon Nelson5149fd02007-10-18 03:07:13 -07001398 if (!tx) {
1399 dev_err(&device->pdev->dev,
1400 "Self-test prep failed, disabling\n");
1401 err = -ENODEV;
1402 goto free_resources;
1403 }
1404
Dan Williams7405f742007-01-02 11:10:43 -07001405 async_tx_ack(tx);
Dan Williamsb9bdcbb2009-01-06 11:38:22 -07001406 init_completion(&cmp);
Shannon Nelson95218432007-10-18 03:07:15 -07001407 tx->callback = ioat_dma_test_callback;
Dan Williamsb9bdcbb2009-01-06 11:38:22 -07001408 tx->callback_param = &cmp;
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001409 cookie = tx->tx_submit(tx);
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001410 if (cookie < 0) {
1411 dev_err(&device->pdev->dev,
1412 "Self-test setup failed, disabling\n");
1413 err = -ENODEV;
1414 goto free_resources;
1415 }
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001416 device->common.device_issue_pending(dma_chan);
Dan Williams532d3b12008-12-03 17:16:55 -07001417
Dan Williams0c33e1c2009-03-02 13:31:35 -07001418 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
Chris Leech0bbd5f42006-05-23 17:35:34 -07001419
Dan Williams0c33e1c2009-03-02 13:31:35 -07001420 if (tmo == 0 ||
1421 device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL)
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001422 != DMA_SUCCESS) {
Shannon Nelson43d6e362007-10-16 01:27:39 -07001423 dev_err(&device->pdev->dev,
Shannon Nelson5149fd02007-10-18 03:07:13 -07001424 "Self-test copy timed out, disabling\n");
Chris Leech0bbd5f42006-05-23 17:35:34 -07001425 err = -ENODEV;
1426 goto free_resources;
1427 }
1428 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
Shannon Nelson43d6e362007-10-16 01:27:39 -07001429 dev_err(&device->pdev->dev,
Shannon Nelson5149fd02007-10-18 03:07:13 -07001430 "Self-test copy failed compare, disabling\n");
Chris Leech0bbd5f42006-05-23 17:35:34 -07001431 err = -ENODEV;
1432 goto free_resources;
1433 }
1434
1435free_resources:
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001436 device->common.device_free_chan_resources(dma_chan);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001437out:
1438 kfree(src);
1439 kfree(dest);
1440 return err;
1441}
1442
Shannon Nelson3e037452007-10-16 01:27:40 -07001443static char ioat_interrupt_style[32] = "msix";
1444module_param_string(ioat_interrupt_style, ioat_interrupt_style,
1445 sizeof(ioat_interrupt_style), 0644);
1446MODULE_PARM_DESC(ioat_interrupt_style,
1447 "set ioat interrupt style: msix (default), "
1448 "msix-single-vector, msi, intx)");
1449
1450/**
1451 * ioat_dma_setup_interrupts - setup interrupt handler
1452 * @device: ioat device
1453 */
1454static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
1455{
1456 struct ioat_dma_chan *ioat_chan;
1457 int err, i, j, msixcnt;
1458 u8 intrctrl = 0;
1459
1460 if (!strcmp(ioat_interrupt_style, "msix"))
1461 goto msix;
1462 if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
1463 goto msix_single_vector;
1464 if (!strcmp(ioat_interrupt_style, "msi"))
1465 goto msi;
1466 if (!strcmp(ioat_interrupt_style, "intx"))
1467 goto intx;
Shannon Nelson5149fd02007-10-18 03:07:13 -07001468 dev_err(&device->pdev->dev, "invalid ioat_interrupt_style %s\n",
1469 ioat_interrupt_style);
1470 goto err_no_irq;
Shannon Nelson3e037452007-10-16 01:27:40 -07001471
1472msix:
1473 /* The number of MSI-X vectors should equal the number of channels */
1474 msixcnt = device->common.chancnt;
1475 for (i = 0; i < msixcnt; i++)
1476 device->msix_entries[i].entry = i;
1477
1478 err = pci_enable_msix(device->pdev, device->msix_entries, msixcnt);
1479 if (err < 0)
1480 goto msi;
1481 if (err > 0)
1482 goto msix_single_vector;
1483
1484 for (i = 0; i < msixcnt; i++) {
1485 ioat_chan = ioat_lookup_chan_by_index(device, i);
1486 err = request_irq(device->msix_entries[i].vector,
1487 ioat_dma_do_interrupt_msix,
1488 0, "ioat-msix", ioat_chan);
1489 if (err) {
1490 for (j = 0; j < i; j++) {
1491 ioat_chan =
1492 ioat_lookup_chan_by_index(device, j);
1493 free_irq(device->msix_entries[j].vector,
1494 ioat_chan);
1495 }
1496 goto msix_single_vector;
1497 }
1498 }
1499 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
1500 device->irq_mode = msix_multi_vector;
1501 goto done;
1502
1503msix_single_vector:
1504 device->msix_entries[0].entry = 0;
1505 err = pci_enable_msix(device->pdev, device->msix_entries, 1);
1506 if (err)
1507 goto msi;
1508
1509 err = request_irq(device->msix_entries[0].vector, ioat_dma_do_interrupt,
1510 0, "ioat-msix", device);
1511 if (err) {
1512 pci_disable_msix(device->pdev);
1513 goto msi;
1514 }
1515 device->irq_mode = msix_single_vector;
1516 goto done;
1517
1518msi:
1519 err = pci_enable_msi(device->pdev);
1520 if (err)
1521 goto intx;
1522
1523 err = request_irq(device->pdev->irq, ioat_dma_do_interrupt,
1524 0, "ioat-msi", device);
1525 if (err) {
1526 pci_disable_msi(device->pdev);
1527 goto intx;
1528 }
1529 /*
1530 * CB 1.2 devices need a bit set in configuration space to enable MSI
1531 */
1532 if (device->version == IOAT_VER_1_2) {
1533 u32 dmactrl;
1534 pci_read_config_dword(device->pdev,
1535 IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1536 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1537 pci_write_config_dword(device->pdev,
1538 IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1539 }
1540 device->irq_mode = msi;
1541 goto done;
1542
1543intx:
1544 err = request_irq(device->pdev->irq, ioat_dma_do_interrupt,
1545 IRQF_SHARED, "ioat-intx", device);
1546 if (err)
1547 goto err_no_irq;
1548 device->irq_mode = intx;
1549
1550done:
1551 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
1552 writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
1553 return 0;
1554
1555err_no_irq:
1556 /* Disable all interrupt generation */
1557 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1558 dev_err(&device->pdev->dev, "no usable interrupts\n");
1559 device->irq_mode = none;
1560 return -1;
1561}
1562
1563/**
1564 * ioat_dma_remove_interrupts - remove whatever interrupts were set
1565 * @device: ioat device
1566 */
1567static void ioat_dma_remove_interrupts(struct ioatdma_device *device)
1568{
1569 struct ioat_dma_chan *ioat_chan;
1570 int i;
1571
1572 /* Disable all interrupt generation */
1573 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1574
1575 switch (device->irq_mode) {
1576 case msix_multi_vector:
1577 for (i = 0; i < device->common.chancnt; i++) {
1578 ioat_chan = ioat_lookup_chan_by_index(device, i);
1579 free_irq(device->msix_entries[i].vector, ioat_chan);
1580 }
1581 pci_disable_msix(device->pdev);
1582 break;
1583 case msix_single_vector:
1584 free_irq(device->msix_entries[0].vector, device);
1585 pci_disable_msix(device->pdev);
1586 break;
1587 case msi:
1588 free_irq(device->pdev->irq, device);
1589 pci_disable_msi(device->pdev);
1590 break;
1591 case intx:
1592 free_irq(device->pdev->irq, device);
1593 break;
1594 case none:
1595 dev_warn(&device->pdev->dev,
1596 "call to %s without interrupts setup\n", __func__);
1597 }
1598 device->irq_mode = none;
1599}
1600
Shannon Nelson8ab89562007-10-16 01:27:39 -07001601struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
1602 void __iomem *iobase)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001603{
1604 int err;
Shannon Nelson8ab89562007-10-16 01:27:39 -07001605 struct ioatdma_device *device;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001606
1607 device = kzalloc(sizeof(*device), GFP_KERNEL);
1608 if (!device) {
1609 err = -ENOMEM;
1610 goto err_kzalloc;
1611 }
Shannon Nelson8ab89562007-10-16 01:27:39 -07001612 device->pdev = pdev;
1613 device->reg_base = iobase;
1614 device->version = readb(device->reg_base + IOAT_VER_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001615
1616 /* DMA coherent memory pool for DMA descriptor allocations */
1617 device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
Shannon Nelson8ab89562007-10-16 01:27:39 -07001618 sizeof(struct ioat_dma_descriptor),
1619 64, 0);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001620 if (!device->dma_pool) {
1621 err = -ENOMEM;
1622 goto err_dma_pool;
1623 }
1624
Shannon Nelson43d6e362007-10-16 01:27:39 -07001625 device->completion_pool = pci_pool_create("completion_pool", pdev,
1626 sizeof(u64), SMP_CACHE_BYTES,
1627 SMP_CACHE_BYTES);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001628 if (!device->completion_pool) {
1629 err = -ENOMEM;
1630 goto err_completion_pool;
1631 }
1632
Chris Leech0bbd5f42006-05-23 17:35:34 -07001633 INIT_LIST_HEAD(&device->common.channels);
Shannon Nelson43d6e362007-10-16 01:27:39 -07001634 ioat_dma_enumerate_channels(device);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001635
Shannon Nelson43d6e362007-10-16 01:27:39 -07001636 device->common.device_alloc_chan_resources =
1637 ioat_dma_alloc_chan_resources;
1638 device->common.device_free_chan_resources =
1639 ioat_dma_free_chan_resources;
Dan Williams7405f742007-01-02 11:10:43 -07001640 device->common.dev = &pdev->dev;
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001641
1642 dma_cap_set(DMA_MEMCPY, device->common.cap_mask);
1643 device->common.device_is_tx_complete = ioat_dma_is_complete;
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001644 switch (device->version) {
1645 case IOAT_VER_1_2:
1646 device->common.device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1647 device->common.device_issue_pending =
1648 ioat1_dma_memcpy_issue_pending;
1649 break;
1650 case IOAT_VER_2_0:
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -07001651 case IOAT_VER_3_0:
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001652 device->common.device_prep_dma_memcpy = ioat2_dma_prep_memcpy;
1653 device->common.device_issue_pending =
1654 ioat2_dma_memcpy_issue_pending;
1655 break;
1656 }
1657
Shannon Nelson3e037452007-10-16 01:27:40 -07001658 dev_err(&device->pdev->dev,
Shannon Nelson5149fd02007-10-18 03:07:13 -07001659 "Intel(R) I/OAT DMA Engine found,"
1660 " %d channels, device version 0x%02x, driver version %s\n",
1661 device->common.chancnt, device->version, IOAT_DMA_VERSION);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001662
Maciej Sosnowski8b794b12009-02-26 11:04:54 +01001663 if (!device->common.chancnt) {
1664 dev_err(&device->pdev->dev,
1665 "Intel(R) I/OAT DMA Engine problem found: "
1666 "zero channels detected\n");
1667 goto err_setup_interrupts;
1668 }
1669
Shannon Nelson3e037452007-10-16 01:27:40 -07001670 err = ioat_dma_setup_interrupts(device);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001671 if (err)
Shannon Nelson3e037452007-10-16 01:27:40 -07001672 goto err_setup_interrupts;
Shannon Nelson8ab89562007-10-16 01:27:39 -07001673
Shannon Nelson3e037452007-10-16 01:27:40 -07001674 err = ioat_dma_self_test(device);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001675 if (err)
1676 goto err_self_test;
1677
Maciej Sosnowski16a37ac2008-07-22 17:30:57 -07001678 ioat_set_tcp_copy_break(device);
1679
Chris Leech0bbd5f42006-05-23 17:35:34 -07001680 dma_async_device_register(&device->common);
1681
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -07001682 if (device->version != IOAT_VER_3_0) {
1683 INIT_DELAYED_WORK(&device->work, ioat_dma_chan_watchdog);
1684 schedule_delayed_work(&device->work,
1685 WATCHDOG_DELAY);
1686 }
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001687
Shannon Nelson8ab89562007-10-16 01:27:39 -07001688 return device;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001689
1690err_self_test:
Shannon Nelson3e037452007-10-16 01:27:40 -07001691 ioat_dma_remove_interrupts(device);
1692err_setup_interrupts:
Chris Leech0bbd5f42006-05-23 17:35:34 -07001693 pci_pool_destroy(device->completion_pool);
1694err_completion_pool:
1695 pci_pool_destroy(device->dma_pool);
1696err_dma_pool:
1697 kfree(device);
1698err_kzalloc:
Shannon Nelsonbb8e8bc2007-12-17 16:20:08 -08001699 dev_err(&pdev->dev,
Shannon Nelson5149fd02007-10-18 03:07:13 -07001700 "Intel(R) I/OAT DMA Engine initialization failed\n");
Shannon Nelson8ab89562007-10-16 01:27:39 -07001701 return NULL;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001702}
1703
Shannon Nelson8ab89562007-10-16 01:27:39 -07001704void ioat_dma_remove(struct ioatdma_device *device)
Dan Aloni428ed602007-03-08 09:57:36 -08001705{
Chris Leech0bbd5f42006-05-23 17:35:34 -07001706 struct dma_chan *chan, *_chan;
1707 struct ioat_dma_chan *ioat_chan;
1708
Maciej Sosnowski2b8a6bf2009-02-26 11:05:07 +01001709 if (device->version != IOAT_VER_3_0)
1710 cancel_delayed_work(&device->work);
1711
Shannon Nelson3e037452007-10-16 01:27:40 -07001712 ioat_dma_remove_interrupts(device);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001713
Shannon Nelsondfe22992007-10-18 03:07:13 -07001714 dma_async_device_unregister(&device->common);
1715
Chris Leech0bbd5f42006-05-23 17:35:34 -07001716 pci_pool_destroy(device->dma_pool);
1717 pci_pool_destroy(device->completion_pool);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001718
Shannon Nelson7df7cf02007-10-18 03:07:12 -07001719 iounmap(device->reg_base);
1720 pci_release_regions(device->pdev);
1721 pci_disable_device(device->pdev);
1722
Shannon Nelson43d6e362007-10-16 01:27:39 -07001723 list_for_each_entry_safe(chan, _chan,
1724 &device->common.channels, device_node) {
Chris Leech0bbd5f42006-05-23 17:35:34 -07001725 ioat_chan = to_ioat_chan(chan);
1726 list_del(&chan->device_node);
1727 kfree(ioat_chan);
1728 }
1729 kfree(device);
1730}
1731