Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Samsung SoC DP (Display Port) interface driver. |
| 3 | * |
| 4 | * Copyright (C) 2012 Samsung Electronics Co., Ltd. |
| 5 | * Author: Jingoo Han <jg1.han@samsung.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your |
| 10 | * option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/slab.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/clk.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/delay.h> |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 21 | #include <linux/of.h> |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 22 | |
| 23 | #include <video/exynos_dp.h> |
| 24 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 25 | #include "exynos_dp_core.h" |
| 26 | |
| 27 | static int exynos_dp_init_dp(struct exynos_dp_device *dp) |
| 28 | { |
| 29 | exynos_dp_reset(dp); |
| 30 | |
Jingoo Han | 24db03a | 2012-05-25 16:21:08 +0900 | [diff] [blame] | 31 | exynos_dp_swreset(dp); |
| 32 | |
Jingoo Han | 75435c7 | 2012-08-23 19:55:13 +0900 | [diff] [blame] | 33 | exynos_dp_init_analog_param(dp); |
| 34 | exynos_dp_init_interrupt(dp); |
| 35 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 36 | /* SW defined function Normal operation */ |
| 37 | exynos_dp_enable_sw_function(dp); |
| 38 | |
| 39 | exynos_dp_config_interrupt(dp); |
| 40 | exynos_dp_init_analog_func(dp); |
| 41 | |
| 42 | exynos_dp_init_hpd(dp); |
| 43 | exynos_dp_init_aux(dp); |
| 44 | |
| 45 | return 0; |
| 46 | } |
| 47 | |
| 48 | static int exynos_dp_detect_hpd(struct exynos_dp_device *dp) |
| 49 | { |
| 50 | int timeout_loop = 0; |
| 51 | |
| 52 | exynos_dp_init_hpd(dp); |
| 53 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 54 | usleep_range(200, 210); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 55 | |
| 56 | while (exynos_dp_get_plug_in_status(dp) != 0) { |
| 57 | timeout_loop++; |
| 58 | if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { |
| 59 | dev_err(dp->dev, "failed to get hpd plug status\n"); |
| 60 | return -ETIMEDOUT; |
| 61 | } |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 62 | usleep_range(10, 11); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 63 | } |
| 64 | |
| 65 | return 0; |
| 66 | } |
| 67 | |
| 68 | static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data) |
| 69 | { |
| 70 | int i; |
| 71 | unsigned char sum = 0; |
| 72 | |
| 73 | for (i = 0; i < EDID_BLOCK_LENGTH; i++) |
| 74 | sum = sum + edid_data[i]; |
| 75 | |
| 76 | return sum; |
| 77 | } |
| 78 | |
| 79 | static int exynos_dp_read_edid(struct exynos_dp_device *dp) |
| 80 | { |
| 81 | unsigned char edid[EDID_BLOCK_LENGTH * 2]; |
| 82 | unsigned int extend_block = 0; |
| 83 | unsigned char sum; |
| 84 | unsigned char test_vector; |
| 85 | int retval; |
| 86 | |
| 87 | /* |
| 88 | * EDID device address is 0x50. |
| 89 | * However, if necessary, you must have set upper address |
| 90 | * into E-EDID in I2C device, 0x30. |
| 91 | */ |
| 92 | |
| 93 | /* Read Extension Flag, Number of 128-byte EDID extension blocks */ |
| 94 | exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, |
| 95 | EDID_EXTENSION_FLAG, |
| 96 | &extend_block); |
| 97 | |
| 98 | if (extend_block > 0) { |
| 99 | dev_dbg(dp->dev, "EDID data includes a single extension!\n"); |
| 100 | |
| 101 | /* Read EDID data */ |
| 102 | retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR, |
| 103 | EDID_HEADER_PATTERN, |
| 104 | EDID_BLOCK_LENGTH, |
| 105 | &edid[EDID_HEADER_PATTERN]); |
| 106 | if (retval != 0) { |
| 107 | dev_err(dp->dev, "EDID Read failed!\n"); |
| 108 | return -EIO; |
| 109 | } |
| 110 | sum = exynos_dp_calc_edid_check_sum(edid); |
| 111 | if (sum != 0) { |
| 112 | dev_err(dp->dev, "EDID bad checksum!\n"); |
| 113 | return -EIO; |
| 114 | } |
| 115 | |
| 116 | /* Read additional EDID data */ |
| 117 | retval = exynos_dp_read_bytes_from_i2c(dp, |
| 118 | I2C_EDID_DEVICE_ADDR, |
| 119 | EDID_BLOCK_LENGTH, |
| 120 | EDID_BLOCK_LENGTH, |
| 121 | &edid[EDID_BLOCK_LENGTH]); |
| 122 | if (retval != 0) { |
| 123 | dev_err(dp->dev, "EDID Read failed!\n"); |
| 124 | return -EIO; |
| 125 | } |
| 126 | sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]); |
| 127 | if (sum != 0) { |
| 128 | dev_err(dp->dev, "EDID bad checksum!\n"); |
| 129 | return -EIO; |
| 130 | } |
| 131 | |
| 132 | exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST, |
| 133 | &test_vector); |
| 134 | if (test_vector & DPCD_TEST_EDID_READ) { |
| 135 | exynos_dp_write_byte_to_dpcd(dp, |
| 136 | DPCD_ADDR_TEST_EDID_CHECKSUM, |
| 137 | edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); |
| 138 | exynos_dp_write_byte_to_dpcd(dp, |
| 139 | DPCD_ADDR_TEST_RESPONSE, |
| 140 | DPCD_TEST_EDID_CHECKSUM_WRITE); |
| 141 | } |
| 142 | } else { |
| 143 | dev_info(dp->dev, "EDID data does not include any extensions.\n"); |
| 144 | |
| 145 | /* Read EDID data */ |
| 146 | retval = exynos_dp_read_bytes_from_i2c(dp, |
| 147 | I2C_EDID_DEVICE_ADDR, |
| 148 | EDID_HEADER_PATTERN, |
| 149 | EDID_BLOCK_LENGTH, |
| 150 | &edid[EDID_HEADER_PATTERN]); |
| 151 | if (retval != 0) { |
| 152 | dev_err(dp->dev, "EDID Read failed!\n"); |
| 153 | return -EIO; |
| 154 | } |
| 155 | sum = exynos_dp_calc_edid_check_sum(edid); |
| 156 | if (sum != 0) { |
| 157 | dev_err(dp->dev, "EDID bad checksum!\n"); |
| 158 | return -EIO; |
| 159 | } |
| 160 | |
| 161 | exynos_dp_read_byte_from_dpcd(dp, |
| 162 | DPCD_ADDR_TEST_REQUEST, |
| 163 | &test_vector); |
| 164 | if (test_vector & DPCD_TEST_EDID_READ) { |
| 165 | exynos_dp_write_byte_to_dpcd(dp, |
| 166 | DPCD_ADDR_TEST_EDID_CHECKSUM, |
| 167 | edid[EDID_CHECKSUM]); |
| 168 | exynos_dp_write_byte_to_dpcd(dp, |
| 169 | DPCD_ADDR_TEST_RESPONSE, |
| 170 | DPCD_TEST_EDID_CHECKSUM_WRITE); |
| 171 | } |
| 172 | } |
| 173 | |
| 174 | dev_err(dp->dev, "EDID Read success!\n"); |
| 175 | return 0; |
| 176 | } |
| 177 | |
| 178 | static int exynos_dp_handle_edid(struct exynos_dp_device *dp) |
| 179 | { |
| 180 | u8 buf[12]; |
| 181 | int i; |
| 182 | int retval; |
| 183 | |
| 184 | /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */ |
| 185 | exynos_dp_read_bytes_from_dpcd(dp, |
| 186 | DPCD_ADDR_DPCD_REV, |
| 187 | 12, buf); |
| 188 | |
| 189 | /* Read EDID */ |
| 190 | for (i = 0; i < 3; i++) { |
| 191 | retval = exynos_dp_read_edid(dp); |
| 192 | if (retval == 0) |
| 193 | break; |
| 194 | } |
| 195 | |
| 196 | return retval; |
| 197 | } |
| 198 | |
| 199 | static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp, |
| 200 | bool enable) |
| 201 | { |
| 202 | u8 data; |
| 203 | |
| 204 | exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data); |
| 205 | |
| 206 | if (enable) |
| 207 | exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, |
| 208 | DPCD_ENHANCED_FRAME_EN | |
| 209 | DPCD_LANE_COUNT_SET(data)); |
| 210 | else |
| 211 | exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, |
| 212 | DPCD_LANE_COUNT_SET(data)); |
| 213 | } |
| 214 | |
| 215 | static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp) |
| 216 | { |
| 217 | u8 data; |
| 218 | int retval; |
| 219 | |
| 220 | exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data); |
| 221 | retval = DPCD_ENHANCED_FRAME_CAP(data); |
| 222 | |
| 223 | return retval; |
| 224 | } |
| 225 | |
| 226 | static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp) |
| 227 | { |
| 228 | u8 data; |
| 229 | |
| 230 | data = exynos_dp_is_enhanced_mode_available(dp); |
| 231 | exynos_dp_enable_rx_to_enhanced_mode(dp, data); |
| 232 | exynos_dp_enable_enhanced_mode(dp, data); |
| 233 | } |
| 234 | |
| 235 | static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp) |
| 236 | { |
| 237 | exynos_dp_set_training_pattern(dp, DP_NONE); |
| 238 | |
| 239 | exynos_dp_write_byte_to_dpcd(dp, |
| 240 | DPCD_ADDR_TRAINING_PATTERN_SET, |
| 241 | DPCD_TRAINING_PATTERN_DISABLED); |
| 242 | } |
| 243 | |
| 244 | static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, |
| 245 | int pre_emphasis, int lane) |
| 246 | { |
| 247 | switch (lane) { |
| 248 | case 0: |
| 249 | exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis); |
| 250 | break; |
| 251 | case 1: |
| 252 | exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis); |
| 253 | break; |
| 254 | |
| 255 | case 2: |
| 256 | exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis); |
| 257 | break; |
| 258 | |
| 259 | case 3: |
| 260 | exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis); |
| 261 | break; |
| 262 | } |
| 263 | } |
| 264 | |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 265 | static int exynos_dp_link_start(struct exynos_dp_device *dp) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 266 | { |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 267 | u8 buf[4]; |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 268 | int lane, lane_count, retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 269 | |
| 270 | lane_count = dp->link_train.lane_count; |
| 271 | |
| 272 | dp->link_train.lt_state = CLOCK_RECOVERY; |
| 273 | dp->link_train.eq_loop = 0; |
| 274 | |
| 275 | for (lane = 0; lane < lane_count; lane++) |
| 276 | dp->link_train.cr_loop[lane] = 0; |
| 277 | |
| 278 | /* Set sink to D0 (Sink Not Ready) mode. */ |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 279 | retval = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 280 | DPCD_SET_POWER_STATE_D0); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 281 | if (retval) |
| 282 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 283 | |
| 284 | /* Set link rate and count as you want to establish*/ |
| 285 | exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate); |
| 286 | exynos_dp_set_lane_count(dp, dp->link_train.lane_count); |
| 287 | |
| 288 | /* Setup RX configuration */ |
| 289 | buf[0] = dp->link_train.link_rate; |
| 290 | buf[1] = dp->link_train.lane_count; |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 291 | retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 292 | 2, buf); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 293 | if (retval) |
| 294 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 295 | |
| 296 | /* Set TX pre-emphasis to minimum */ |
| 297 | for (lane = 0; lane < lane_count; lane++) |
| 298 | exynos_dp_set_lane_lane_pre_emphasis(dp, |
| 299 | PRE_EMPHASIS_LEVEL_0, lane); |
| 300 | |
| 301 | /* Set training pattern 1 */ |
| 302 | exynos_dp_set_training_pattern(dp, TRAINING_PTN1); |
| 303 | |
| 304 | /* Set RX training pattern */ |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 305 | exynos_dp_write_byte_to_dpcd(dp, |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 306 | DPCD_ADDR_TRAINING_PATTERN_SET, |
| 307 | DPCD_SCRAMBLING_DISABLED | |
| 308 | DPCD_TRAINING_PATTERN_1); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 309 | |
| 310 | for (lane = 0; lane < lane_count; lane++) |
| 311 | buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 | |
| 312 | DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0; |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 313 | retval = exynos_dp_write_bytes_to_dpcd(dp, |
Jingoo Han | 123267a | 2012-07-12 15:10:03 +0900 | [diff] [blame] | 314 | DPCD_ADDR_TRAINING_LANE0_SET, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 315 | lane_count, buf); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 316 | |
| 317 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 318 | } |
| 319 | |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 320 | static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 321 | { |
| 322 | int shift = (lane & 1) * 4; |
| 323 | u8 link_value = link_status[lane>>1]; |
| 324 | |
| 325 | return (link_value >> shift) & 0xf; |
| 326 | } |
| 327 | |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 328 | static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 329 | { |
| 330 | int lane; |
| 331 | u8 lane_status; |
| 332 | |
| 333 | for (lane = 0; lane < lane_count; lane++) { |
| 334 | lane_status = exynos_dp_get_lane_status(link_status, lane); |
| 335 | if ((lane_status & DPCD_LANE_CR_DONE) == 0) |
| 336 | return -EINVAL; |
| 337 | } |
| 338 | return 0; |
| 339 | } |
| 340 | |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 341 | static int exynos_dp_channel_eq_ok(u8 link_align[3], int lane_count) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 342 | { |
| 343 | int lane; |
| 344 | u8 lane_align; |
| 345 | u8 lane_status; |
| 346 | |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 347 | lane_align = link_align[2]; |
Jingoo Han | 1f61ce5 | 2012-07-17 17:44:13 +0900 | [diff] [blame] | 348 | if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 349 | return -EINVAL; |
| 350 | |
| 351 | for (lane = 0; lane < lane_count; lane++) { |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 352 | lane_status = exynos_dp_get_lane_status(link_align, lane); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 353 | lane_status &= DPCD_CHANNEL_EQ_BITS; |
| 354 | if (lane_status != DPCD_CHANNEL_EQ_BITS) |
| 355 | return -EINVAL; |
| 356 | } |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 357 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 358 | return 0; |
| 359 | } |
| 360 | |
| 361 | static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2], |
| 362 | int lane) |
| 363 | { |
| 364 | int shift = (lane & 1) * 4; |
| 365 | u8 link_value = adjust_request[lane>>1]; |
| 366 | |
| 367 | return (link_value >> shift) & 0x3; |
| 368 | } |
| 369 | |
| 370 | static unsigned char exynos_dp_get_adjust_request_pre_emphasis( |
| 371 | u8 adjust_request[2], |
| 372 | int lane) |
| 373 | { |
| 374 | int shift = (lane & 1) * 4; |
| 375 | u8 link_value = adjust_request[lane>>1]; |
| 376 | |
| 377 | return ((link_value >> shift) & 0xc) >> 2; |
| 378 | } |
| 379 | |
| 380 | static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp, |
| 381 | u8 training_lane_set, int lane) |
| 382 | { |
| 383 | switch (lane) { |
| 384 | case 0: |
| 385 | exynos_dp_set_lane0_link_training(dp, training_lane_set); |
| 386 | break; |
| 387 | case 1: |
| 388 | exynos_dp_set_lane1_link_training(dp, training_lane_set); |
| 389 | break; |
| 390 | |
| 391 | case 2: |
| 392 | exynos_dp_set_lane2_link_training(dp, training_lane_set); |
| 393 | break; |
| 394 | |
| 395 | case 3: |
| 396 | exynos_dp_set_lane3_link_training(dp, training_lane_set); |
| 397 | break; |
| 398 | } |
| 399 | } |
| 400 | |
| 401 | static unsigned int exynos_dp_get_lane_link_training( |
| 402 | struct exynos_dp_device *dp, |
| 403 | int lane) |
| 404 | { |
| 405 | u32 reg; |
| 406 | |
| 407 | switch (lane) { |
| 408 | case 0: |
| 409 | reg = exynos_dp_get_lane0_link_training(dp); |
| 410 | break; |
| 411 | case 1: |
| 412 | reg = exynos_dp_get_lane1_link_training(dp); |
| 413 | break; |
| 414 | case 2: |
| 415 | reg = exynos_dp_get_lane2_link_training(dp); |
| 416 | break; |
| 417 | case 3: |
| 418 | reg = exynos_dp_get_lane3_link_training(dp); |
| 419 | break; |
Jingoo Han | 64c43df | 2012-06-20 10:25:48 +0900 | [diff] [blame] | 420 | default: |
| 421 | WARN_ON(1); |
| 422 | return 0; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 423 | } |
| 424 | |
| 425 | return reg; |
| 426 | } |
| 427 | |
| 428 | static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp) |
| 429 | { |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 430 | exynos_dp_training_pattern_dis(dp); |
| 431 | exynos_dp_set_enhanced_mode(dp); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 432 | |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 433 | dp->link_train.lt_state = FAILED; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 434 | } |
| 435 | |
| 436 | static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) |
| 437 | { |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 438 | u8 link_status[2]; |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 439 | int lane, lane_count, retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 440 | |
Jingoo Han | 8f802da | 2012-04-04 16:00:00 +0900 | [diff] [blame] | 441 | u8 adjust_request[2]; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 442 | u8 voltage_swing; |
| 443 | u8 pre_emphasis; |
| 444 | u8 training_lane; |
| 445 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 446 | usleep_range(100, 101); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 447 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 448 | lane_count = dp->link_train.lane_count; |
| 449 | |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 450 | retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 451 | 2, link_status); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 452 | if (retval) |
| 453 | return retval; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 454 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 455 | if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { |
| 456 | /* set training pattern 2 for EQ */ |
| 457 | exynos_dp_set_training_pattern(dp, TRAINING_PTN2); |
| 458 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 459 | for (lane = 0; lane < lane_count; lane++) { |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 460 | retval = exynos_dp_read_bytes_from_dpcd(dp, |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 461 | DPCD_ADDR_ADJUST_REQUEST_LANE0_1, |
| 462 | 2, adjust_request); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 463 | if (retval) |
| 464 | return retval; |
| 465 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 466 | voltage_swing = exynos_dp_get_adjust_request_voltage( |
| 467 | adjust_request, lane); |
| 468 | pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( |
| 469 | adjust_request, lane); |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 470 | training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | |
| 471 | DPCD_PRE_EMPHASIS_SET(pre_emphasis); |
| 472 | |
| 473 | if (voltage_swing == VOLTAGE_LEVEL_3) |
| 474 | training_lane |= DPCD_MAX_SWING_REACHED; |
| 475 | if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) |
| 476 | training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; |
| 477 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 478 | dp->link_train.training_lane[lane] = training_lane; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 479 | |
| 480 | exynos_dp_set_lane_link_training(dp, |
| 481 | dp->link_train.training_lane[lane], |
| 482 | lane); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 483 | } |
| 484 | |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 485 | retval = exynos_dp_write_byte_to_dpcd(dp, |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 486 | DPCD_ADDR_TRAINING_PATTERN_SET, |
| 487 | DPCD_SCRAMBLING_DISABLED | |
| 488 | DPCD_TRAINING_PATTERN_2); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 489 | if (retval) |
| 490 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 491 | |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 492 | retval = exynos_dp_write_bytes_to_dpcd(dp, |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 493 | DPCD_ADDR_TRAINING_LANE0_SET, |
| 494 | lane_count, |
| 495 | dp->link_train.training_lane); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 496 | if (retval) |
| 497 | return retval; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 498 | |
| 499 | dev_info(dp->dev, "Link Training Clock Recovery success\n"); |
| 500 | dp->link_train.lt_state = EQUALIZER_TRAINING; |
| 501 | } else { |
| 502 | for (lane = 0; lane < lane_count; lane++) { |
| 503 | training_lane = exynos_dp_get_lane_link_training( |
| 504 | dp, lane); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 505 | retval = exynos_dp_read_bytes_from_dpcd(dp, |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 506 | DPCD_ADDR_ADJUST_REQUEST_LANE0_1, |
| 507 | 2, adjust_request); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 508 | if (retval) |
| 509 | return retval; |
| 510 | |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 511 | voltage_swing = exynos_dp_get_adjust_request_voltage( |
| 512 | adjust_request, lane); |
| 513 | pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( |
| 514 | adjust_request, lane); |
| 515 | |
| 516 | if (voltage_swing == VOLTAGE_LEVEL_3 || |
| 517 | pre_emphasis == PRE_EMPHASIS_LEVEL_3) { |
| 518 | dev_err(dp->dev, "voltage or pre emphasis reached max level\n"); |
| 519 | goto reduce_link_rate; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 520 | } |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 521 | |
| 522 | if ((DPCD_VOLTAGE_SWING_GET(training_lane) == |
| 523 | voltage_swing) && |
| 524 | (DPCD_PRE_EMPHASIS_GET(training_lane) == |
| 525 | pre_emphasis)) { |
| 526 | dp->link_train.cr_loop[lane]++; |
| 527 | if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP) { |
| 528 | dev_err(dp->dev, "CR Max loop\n"); |
| 529 | goto reduce_link_rate; |
| 530 | } |
| 531 | } |
| 532 | |
| 533 | training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | |
| 534 | DPCD_PRE_EMPHASIS_SET(pre_emphasis); |
| 535 | |
| 536 | if (voltage_swing == VOLTAGE_LEVEL_3) |
| 537 | training_lane |= DPCD_MAX_SWING_REACHED; |
| 538 | if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) |
| 539 | training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; |
| 540 | |
| 541 | dp->link_train.training_lane[lane] = training_lane; |
| 542 | |
| 543 | exynos_dp_set_lane_link_training(dp, |
| 544 | dp->link_train.training_lane[lane], lane); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 545 | } |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 546 | |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 547 | retval = exynos_dp_write_bytes_to_dpcd(dp, |
| 548 | DPCD_ADDR_TRAINING_LANE0_SET, lane_count, |
| 549 | dp->link_train.training_lane); |
| 550 | if (retval) |
| 551 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 552 | } |
| 553 | |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 554 | return retval; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 555 | |
| 556 | reduce_link_rate: |
| 557 | exynos_dp_reduce_link_rate(dp); |
| 558 | return -EIO; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 559 | } |
| 560 | |
| 561 | static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) |
| 562 | { |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 563 | u8 link_status[2]; |
| 564 | u8 link_align[3]; |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 565 | int lane, lane_count, retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 566 | u32 reg; |
| 567 | |
Jingoo Han | 8f802da | 2012-04-04 16:00:00 +0900 | [diff] [blame] | 568 | u8 adjust_request[2]; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 569 | u8 voltage_swing; |
| 570 | u8 pre_emphasis; |
| 571 | u8 training_lane; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 572 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 573 | usleep_range(400, 401); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 574 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 575 | lane_count = dp->link_train.lane_count; |
| 576 | |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 577 | retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 578 | 2, link_status); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 579 | if (retval) |
| 580 | return retval; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 581 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 582 | if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 583 | link_align[0] = link_status[0]; |
| 584 | link_align[1] = link_status[1]; |
| 585 | |
| 586 | exynos_dp_read_byte_from_dpcd(dp, |
| 587 | DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED, |
| 588 | &link_align[2]); |
| 589 | |
| 590 | for (lane = 0; lane < lane_count; lane++) { |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 591 | retval = exynos_dp_read_bytes_from_dpcd(dp, |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 592 | DPCD_ADDR_ADJUST_REQUEST_LANE0_1, |
| 593 | 2, adjust_request); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 594 | if (retval) |
| 595 | return retval; |
| 596 | |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 597 | voltage_swing = exynos_dp_get_adjust_request_voltage( |
| 598 | adjust_request, lane); |
| 599 | pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( |
| 600 | adjust_request, lane); |
| 601 | training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | |
| 602 | DPCD_PRE_EMPHASIS_SET(pre_emphasis); |
| 603 | |
| 604 | if (voltage_swing == VOLTAGE_LEVEL_3) |
| 605 | training_lane |= DPCD_MAX_SWING_REACHED; |
| 606 | if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) |
| 607 | training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; |
| 608 | |
| 609 | dp->link_train.training_lane[lane] = training_lane; |
| 610 | } |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 611 | |
Jingoo Han | e75478b | 2012-09-03 17:50:24 +0900 | [diff] [blame] | 612 | if (exynos_dp_channel_eq_ok(link_align, lane_count) == 0) { |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 613 | /* traing pattern Set to Normal */ |
| 614 | exynos_dp_training_pattern_dis(dp); |
| 615 | |
| 616 | dev_info(dp->dev, "Link Training success!\n"); |
| 617 | |
| 618 | exynos_dp_get_link_bandwidth(dp, ®); |
| 619 | dp->link_train.link_rate = reg; |
| 620 | dev_dbg(dp->dev, "final bandwidth = %.2x\n", |
| 621 | dp->link_train.link_rate); |
| 622 | |
| 623 | exynos_dp_get_lane_count(dp, ®); |
| 624 | dp->link_train.lane_count = reg; |
| 625 | dev_dbg(dp->dev, "final lane count = %.2x\n", |
| 626 | dp->link_train.lane_count); |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 627 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 628 | /* set enhanced mode if available */ |
| 629 | exynos_dp_set_enhanced_mode(dp); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 630 | dp->link_train.lt_state = FINISHED; |
| 631 | } else { |
| 632 | /* not all locked */ |
| 633 | dp->link_train.eq_loop++; |
| 634 | |
| 635 | if (dp->link_train.eq_loop > MAX_EQ_LOOP) { |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 636 | dev_err(dp->dev, "EQ Max loop\n"); |
| 637 | goto reduce_link_rate; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 638 | } |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 639 | |
| 640 | for (lane = 0; lane < lane_count; lane++) |
| 641 | exynos_dp_set_lane_link_training(dp, |
| 642 | dp->link_train.training_lane[lane], |
| 643 | lane); |
| 644 | |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 645 | retval = exynos_dp_write_bytes_to_dpcd(dp, |
| 646 | DPCD_ADDR_TRAINING_LANE0_SET, |
| 647 | lane_count, |
| 648 | dp->link_train.training_lane); |
| 649 | if (retval) |
| 650 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 651 | } |
| 652 | } else { |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 653 | goto reduce_link_rate; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 654 | } |
| 655 | |
| 656 | return 0; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 657 | |
| 658 | reduce_link_rate: |
| 659 | exynos_dp_reduce_link_rate(dp); |
| 660 | return -EIO; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 661 | } |
| 662 | |
| 663 | static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp, |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 664 | u8 *bandwidth) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 665 | { |
| 666 | u8 data; |
| 667 | |
| 668 | /* |
| 669 | * For DP rev.1.1, Maximum link rate of Main Link lanes |
| 670 | * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps |
| 671 | */ |
| 672 | exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data); |
| 673 | *bandwidth = data; |
| 674 | } |
| 675 | |
| 676 | static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp, |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 677 | u8 *lane_count) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 678 | { |
| 679 | u8 data; |
| 680 | |
| 681 | /* |
| 682 | * For DP rev.1.1, Maximum number of Main Link lanes |
| 683 | * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes |
| 684 | */ |
| 685 | exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data); |
| 686 | *lane_count = DPCD_MAX_LANE_COUNT(data); |
| 687 | } |
| 688 | |
| 689 | static void exynos_dp_init_training(struct exynos_dp_device *dp, |
| 690 | enum link_lane_count_type max_lane, |
| 691 | enum link_rate_type max_rate) |
| 692 | { |
| 693 | /* |
| 694 | * MACRO_RST must be applied after the PLL_LOCK to avoid |
| 695 | * the DP inter pair skew issue for at least 10 us |
| 696 | */ |
| 697 | exynos_dp_reset_macro(dp); |
| 698 | |
| 699 | /* Initialize by reading RX's DPCD */ |
| 700 | exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); |
| 701 | exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); |
| 702 | |
| 703 | if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && |
| 704 | (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { |
| 705 | dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", |
| 706 | dp->link_train.link_rate); |
| 707 | dp->link_train.link_rate = LINK_RATE_1_62GBPS; |
| 708 | } |
| 709 | |
| 710 | if (dp->link_train.lane_count == 0) { |
| 711 | dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n", |
| 712 | dp->link_train.lane_count); |
| 713 | dp->link_train.lane_count = (u8)LANE_COUNT1; |
| 714 | } |
| 715 | |
| 716 | /* Setup TX lane count & rate */ |
| 717 | if (dp->link_train.lane_count > max_lane) |
| 718 | dp->link_train.lane_count = max_lane; |
| 719 | if (dp->link_train.link_rate > max_rate) |
| 720 | dp->link_train.link_rate = max_rate; |
| 721 | |
| 722 | /* All DP analog module power up */ |
| 723 | exynos_dp_set_analog_power_down(dp, POWER_ALL, 0); |
| 724 | } |
| 725 | |
| 726 | static int exynos_dp_sw_link_training(struct exynos_dp_device *dp) |
| 727 | { |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 728 | int retval = 0, training_finished = 0; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 729 | |
| 730 | dp->link_train.lt_state = START; |
| 731 | |
| 732 | /* Process here */ |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 733 | while (!retval && !training_finished) { |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 734 | switch (dp->link_train.lt_state) { |
| 735 | case START: |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 736 | retval = exynos_dp_link_start(dp); |
| 737 | if (retval) |
| 738 | dev_err(dp->dev, "LT link start failed!\n"); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 739 | break; |
| 740 | case CLOCK_RECOVERY: |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 741 | retval = exynos_dp_process_clock_recovery(dp); |
| 742 | if (retval) |
| 743 | dev_err(dp->dev, "LT CR failed!\n"); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 744 | break; |
| 745 | case EQUALIZER_TRAINING: |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 746 | retval = exynos_dp_process_equalizer_training(dp); |
| 747 | if (retval) |
| 748 | dev_err(dp->dev, "LT EQ failed!\n"); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 749 | break; |
| 750 | case FINISHED: |
| 751 | training_finished = 1; |
| 752 | break; |
| 753 | case FAILED: |
| 754 | return -EREMOTEIO; |
| 755 | } |
| 756 | } |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame^] | 757 | if (retval) |
| 758 | dev_err(dp->dev, "eDP link training failed (%d)\n", retval); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 759 | |
| 760 | return retval; |
| 761 | } |
| 762 | |
| 763 | static int exynos_dp_set_link_train(struct exynos_dp_device *dp, |
| 764 | u32 count, |
| 765 | u32 bwtype) |
| 766 | { |
| 767 | int i; |
| 768 | int retval; |
| 769 | |
| 770 | for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) { |
| 771 | exynos_dp_init_training(dp, count, bwtype); |
| 772 | retval = exynos_dp_sw_link_training(dp); |
| 773 | if (retval == 0) |
| 774 | break; |
| 775 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 776 | usleep_range(100, 110); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 777 | } |
| 778 | |
| 779 | return retval; |
| 780 | } |
| 781 | |
| 782 | static int exynos_dp_config_video(struct exynos_dp_device *dp, |
| 783 | struct video_info *video_info) |
| 784 | { |
| 785 | int retval = 0; |
| 786 | int timeout_loop = 0; |
| 787 | int done_count = 0; |
| 788 | |
| 789 | exynos_dp_config_video_slave_mode(dp, video_info); |
| 790 | |
| 791 | exynos_dp_set_video_color_format(dp, video_info->color_depth, |
| 792 | video_info->color_space, |
| 793 | video_info->dynamic_range, |
| 794 | video_info->ycbcr_coeff); |
| 795 | |
| 796 | if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { |
| 797 | dev_err(dp->dev, "PLL is not locked yet.\n"); |
| 798 | return -EINVAL; |
| 799 | } |
| 800 | |
| 801 | for (;;) { |
| 802 | timeout_loop++; |
| 803 | if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0) |
| 804 | break; |
| 805 | if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { |
| 806 | dev_err(dp->dev, "Timeout of video streamclk ok\n"); |
| 807 | return -ETIMEDOUT; |
| 808 | } |
| 809 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 810 | usleep_range(1, 2); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 811 | } |
| 812 | |
| 813 | /* Set to use the register calculated M/N video */ |
| 814 | exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); |
| 815 | |
| 816 | /* For video bist, Video timing must be generated by register */ |
| 817 | exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); |
| 818 | |
| 819 | /* Disable video mute */ |
| 820 | exynos_dp_enable_video_mute(dp, 0); |
| 821 | |
| 822 | /* Configure video slave mode */ |
| 823 | exynos_dp_enable_video_master(dp, 0); |
| 824 | |
| 825 | /* Enable video */ |
| 826 | exynos_dp_start_video(dp); |
| 827 | |
| 828 | timeout_loop = 0; |
| 829 | |
| 830 | for (;;) { |
| 831 | timeout_loop++; |
| 832 | if (exynos_dp_is_video_stream_on(dp) == 0) { |
| 833 | done_count++; |
| 834 | if (done_count > 10) |
| 835 | break; |
| 836 | } else if (done_count) { |
| 837 | done_count = 0; |
| 838 | } |
| 839 | if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { |
| 840 | dev_err(dp->dev, "Timeout of video streamclk ok\n"); |
| 841 | return -ETIMEDOUT; |
| 842 | } |
| 843 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 844 | usleep_range(1000, 1001); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 845 | } |
| 846 | |
| 847 | if (retval != 0) |
| 848 | dev_err(dp->dev, "Video stream is not detected!\n"); |
| 849 | |
| 850 | return retval; |
| 851 | } |
| 852 | |
| 853 | static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable) |
| 854 | { |
| 855 | u8 data; |
| 856 | |
| 857 | if (enable) { |
| 858 | exynos_dp_enable_scrambling(dp); |
| 859 | |
| 860 | exynos_dp_read_byte_from_dpcd(dp, |
| 861 | DPCD_ADDR_TRAINING_PATTERN_SET, |
| 862 | &data); |
| 863 | exynos_dp_write_byte_to_dpcd(dp, |
| 864 | DPCD_ADDR_TRAINING_PATTERN_SET, |
| 865 | (u8)(data & ~DPCD_SCRAMBLING_DISABLED)); |
| 866 | } else { |
| 867 | exynos_dp_disable_scrambling(dp); |
| 868 | |
| 869 | exynos_dp_read_byte_from_dpcd(dp, |
| 870 | DPCD_ADDR_TRAINING_PATTERN_SET, |
| 871 | &data); |
| 872 | exynos_dp_write_byte_to_dpcd(dp, |
| 873 | DPCD_ADDR_TRAINING_PATTERN_SET, |
| 874 | (u8)(data | DPCD_SCRAMBLING_DISABLED)); |
| 875 | } |
| 876 | } |
| 877 | |
| 878 | static irqreturn_t exynos_dp_irq_handler(int irq, void *arg) |
| 879 | { |
| 880 | struct exynos_dp_device *dp = arg; |
| 881 | |
| 882 | dev_err(dp->dev, "exynos_dp_irq_handler\n"); |
| 883 | return IRQ_HANDLED; |
| 884 | } |
| 885 | |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 886 | #ifdef CONFIG_OF |
| 887 | static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev) |
| 888 | { |
| 889 | struct device_node *dp_node = dev->of_node; |
| 890 | struct exynos_dp_platdata *pd; |
| 891 | struct video_info *dp_video_config; |
| 892 | |
| 893 | pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); |
| 894 | if (!pd) { |
| 895 | dev_err(dev, "memory allocation for pdata failed\n"); |
| 896 | return ERR_PTR(-ENOMEM); |
| 897 | } |
| 898 | dp_video_config = devm_kzalloc(dev, |
| 899 | sizeof(*dp_video_config), GFP_KERNEL); |
| 900 | |
| 901 | if (!dp_video_config) { |
| 902 | dev_err(dev, "memory allocation for video config failed\n"); |
| 903 | return ERR_PTR(-ENOMEM); |
| 904 | } |
| 905 | pd->video_info = dp_video_config; |
| 906 | |
| 907 | dp_video_config->h_sync_polarity = |
| 908 | of_property_read_bool(dp_node, "hsync-active-high"); |
| 909 | |
| 910 | dp_video_config->v_sync_polarity = |
| 911 | of_property_read_bool(dp_node, "vsync-active-high"); |
| 912 | |
| 913 | dp_video_config->interlaced = |
| 914 | of_property_read_bool(dp_node, "interlaced"); |
| 915 | |
| 916 | if (of_property_read_u32(dp_node, "samsung,color-space", |
| 917 | &dp_video_config->color_space)) { |
| 918 | dev_err(dev, "failed to get color-space\n"); |
| 919 | return ERR_PTR(-EINVAL); |
| 920 | } |
| 921 | |
| 922 | if (of_property_read_u32(dp_node, "samsung,dynamic-range", |
| 923 | &dp_video_config->dynamic_range)) { |
| 924 | dev_err(dev, "failed to get dynamic-range\n"); |
| 925 | return ERR_PTR(-EINVAL); |
| 926 | } |
| 927 | |
| 928 | if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff", |
| 929 | &dp_video_config->ycbcr_coeff)) { |
| 930 | dev_err(dev, "failed to get ycbcr-coeff\n"); |
| 931 | return ERR_PTR(-EINVAL); |
| 932 | } |
| 933 | |
| 934 | if (of_property_read_u32(dp_node, "samsung,color-depth", |
| 935 | &dp_video_config->color_depth)) { |
| 936 | dev_err(dev, "failed to get color-depth\n"); |
| 937 | return ERR_PTR(-EINVAL); |
| 938 | } |
| 939 | |
| 940 | if (of_property_read_u32(dp_node, "samsung,link-rate", |
| 941 | &dp_video_config->link_rate)) { |
| 942 | dev_err(dev, "failed to get link-rate\n"); |
| 943 | return ERR_PTR(-EINVAL); |
| 944 | } |
| 945 | |
| 946 | if (of_property_read_u32(dp_node, "samsung,lane-count", |
| 947 | &dp_video_config->lane_count)) { |
| 948 | dev_err(dev, "failed to get lane-count\n"); |
| 949 | return ERR_PTR(-EINVAL); |
| 950 | } |
| 951 | |
| 952 | return pd; |
| 953 | } |
| 954 | |
| 955 | static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp) |
| 956 | { |
| 957 | struct device_node *dp_phy_node; |
| 958 | u32 phy_base; |
| 959 | |
| 960 | dp_phy_node = of_find_node_by_name(dp->dev->of_node, "dptx-phy"); |
| 961 | if (!dp_phy_node) { |
| 962 | dev_err(dp->dev, "could not find dptx-phy node\n"); |
| 963 | return -ENODEV; |
| 964 | } |
| 965 | |
| 966 | if (of_property_read_u32(dp_phy_node, "reg", &phy_base)) { |
| 967 | dev_err(dp->dev, "faild to get reg for dptx-phy\n"); |
| 968 | return -EINVAL; |
| 969 | } |
| 970 | |
| 971 | if (of_property_read_u32(dp_phy_node, "samsung,enable-mask", |
| 972 | &dp->enable_mask)) { |
| 973 | dev_err(dp->dev, "faild to get enable-mask for dptx-phy\n"); |
| 974 | return -EINVAL; |
| 975 | } |
| 976 | |
| 977 | dp->phy_addr = ioremap(phy_base, SZ_4); |
| 978 | if (!dp->phy_addr) { |
| 979 | dev_err(dp->dev, "failed to ioremap dp-phy\n"); |
| 980 | return -ENOMEM; |
| 981 | } |
| 982 | |
| 983 | return 0; |
| 984 | } |
| 985 | |
| 986 | static void exynos_dp_phy_init(struct exynos_dp_device *dp) |
| 987 | { |
| 988 | u32 reg; |
| 989 | |
| 990 | reg = __raw_readl(dp->phy_addr); |
| 991 | reg |= dp->enable_mask; |
| 992 | __raw_writel(reg, dp->phy_addr); |
| 993 | } |
| 994 | |
| 995 | static void exynos_dp_phy_exit(struct exynos_dp_device *dp) |
| 996 | { |
| 997 | u32 reg; |
| 998 | |
| 999 | reg = __raw_readl(dp->phy_addr); |
| 1000 | reg &= ~(dp->enable_mask); |
| 1001 | __raw_writel(reg, dp->phy_addr); |
| 1002 | } |
| 1003 | #else |
| 1004 | static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev) |
| 1005 | { |
| 1006 | return NULL; |
| 1007 | } |
| 1008 | |
| 1009 | static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp) |
| 1010 | { |
| 1011 | return -EINVAL; |
| 1012 | } |
| 1013 | |
| 1014 | static void exynos_dp_phy_init(struct exynos_dp_device *dp) |
| 1015 | { |
| 1016 | return; |
| 1017 | } |
| 1018 | |
| 1019 | static void exynos_dp_phy_exit(struct exynos_dp_device *dp) |
| 1020 | { |
| 1021 | return; |
| 1022 | } |
| 1023 | #endif /* CONFIG_OF */ |
| 1024 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1025 | static int __devinit exynos_dp_probe(struct platform_device *pdev) |
| 1026 | { |
| 1027 | struct resource *res; |
| 1028 | struct exynos_dp_device *dp; |
| 1029 | struct exynos_dp_platdata *pdata; |
| 1030 | |
| 1031 | int ret = 0; |
| 1032 | |
Jingoo Han | 4d10ecf8 | 2012-05-25 16:20:45 +0900 | [diff] [blame] | 1033 | dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device), |
| 1034 | GFP_KERNEL); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1035 | if (!dp) { |
| 1036 | dev_err(&pdev->dev, "no memory for device data\n"); |
| 1037 | return -ENOMEM; |
| 1038 | } |
| 1039 | |
| 1040 | dp->dev = &pdev->dev; |
| 1041 | |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1042 | if (pdev->dev.of_node) { |
| 1043 | pdata = exynos_dp_dt_parse_pdata(&pdev->dev); |
| 1044 | if (IS_ERR(pdata)) |
| 1045 | return PTR_ERR(pdata); |
| 1046 | |
| 1047 | ret = exynos_dp_dt_parse_phydata(dp); |
| 1048 | if (ret) |
| 1049 | return ret; |
| 1050 | } else { |
| 1051 | pdata = pdev->dev.platform_data; |
| 1052 | if (!pdata) { |
| 1053 | dev_err(&pdev->dev, "no platform data\n"); |
| 1054 | return -EINVAL; |
| 1055 | } |
| 1056 | } |
| 1057 | |
Damien Cassou | d913f36 | 2012-08-01 18:20:39 +0200 | [diff] [blame] | 1058 | dp->clock = devm_clk_get(&pdev->dev, "dp"); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1059 | if (IS_ERR(dp->clock)) { |
| 1060 | dev_err(&pdev->dev, "failed to get clock\n"); |
Jingoo Han | 4d10ecf8 | 2012-05-25 16:20:45 +0900 | [diff] [blame] | 1061 | return PTR_ERR(dp->clock); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1062 | } |
| 1063 | |
Jingoo Han | 37414fb | 2012-10-04 15:45:14 +0900 | [diff] [blame] | 1064 | clk_prepare_enable(dp->clock); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1065 | |
| 1066 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1067 | |
Jingoo Han | 4d10ecf8 | 2012-05-25 16:20:45 +0900 | [diff] [blame] | 1068 | dp->reg_base = devm_request_and_ioremap(&pdev->dev, res); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1069 | if (!dp->reg_base) { |
| 1070 | dev_err(&pdev->dev, "failed to ioremap\n"); |
Damien Cassou | d913f36 | 2012-08-01 18:20:39 +0200 | [diff] [blame] | 1071 | return -ENOMEM; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1072 | } |
| 1073 | |
| 1074 | dp->irq = platform_get_irq(pdev, 0); |
| 1075 | if (!dp->irq) { |
| 1076 | dev_err(&pdev->dev, "failed to get irq\n"); |
Damien Cassou | d913f36 | 2012-08-01 18:20:39 +0200 | [diff] [blame] | 1077 | return -ENODEV; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1078 | } |
| 1079 | |
Jingoo Han | 4d10ecf8 | 2012-05-25 16:20:45 +0900 | [diff] [blame] | 1080 | ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler, 0, |
| 1081 | "exynos-dp", dp); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1082 | if (ret) { |
| 1083 | dev_err(&pdev->dev, "failed to request irq\n"); |
Damien Cassou | d913f36 | 2012-08-01 18:20:39 +0200 | [diff] [blame] | 1084 | return ret; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1085 | } |
| 1086 | |
| 1087 | dp->video_info = pdata->video_info; |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1088 | |
| 1089 | if (pdev->dev.of_node) { |
| 1090 | if (dp->phy_addr) |
| 1091 | exynos_dp_phy_init(dp); |
| 1092 | } else { |
| 1093 | if (pdata->phy_init) |
| 1094 | pdata->phy_init(); |
| 1095 | } |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1096 | |
| 1097 | exynos_dp_init_dp(dp); |
| 1098 | |
| 1099 | ret = exynos_dp_detect_hpd(dp); |
| 1100 | if (ret) { |
| 1101 | dev_err(&pdev->dev, "unable to detect hpd\n"); |
Damien Cassou | d913f36 | 2012-08-01 18:20:39 +0200 | [diff] [blame] | 1102 | return ret; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1103 | } |
| 1104 | |
| 1105 | exynos_dp_handle_edid(dp); |
| 1106 | |
| 1107 | ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count, |
| 1108 | dp->video_info->link_rate); |
| 1109 | if (ret) { |
| 1110 | dev_err(&pdev->dev, "unable to do link train\n"); |
Damien Cassou | d913f36 | 2012-08-01 18:20:39 +0200 | [diff] [blame] | 1111 | return ret; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1112 | } |
| 1113 | |
| 1114 | exynos_dp_enable_scramble(dp, 1); |
| 1115 | exynos_dp_enable_rx_to_enhanced_mode(dp, 1); |
| 1116 | exynos_dp_enable_enhanced_mode(dp, 1); |
| 1117 | |
| 1118 | exynos_dp_set_lane_count(dp, dp->video_info->lane_count); |
| 1119 | exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate); |
| 1120 | |
| 1121 | exynos_dp_init_video(dp); |
| 1122 | ret = exynos_dp_config_video(dp, dp->video_info); |
| 1123 | if (ret) { |
| 1124 | dev_err(&pdev->dev, "unable to config video\n"); |
Damien Cassou | d913f36 | 2012-08-01 18:20:39 +0200 | [diff] [blame] | 1125 | return ret; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1126 | } |
| 1127 | |
| 1128 | platform_set_drvdata(pdev, dp); |
| 1129 | |
| 1130 | return 0; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1131 | } |
| 1132 | |
| 1133 | static int __devexit exynos_dp_remove(struct platform_device *pdev) |
| 1134 | { |
| 1135 | struct exynos_dp_platdata *pdata = pdev->dev.platform_data; |
| 1136 | struct exynos_dp_device *dp = platform_get_drvdata(pdev); |
| 1137 | |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1138 | if (pdev->dev.of_node) { |
| 1139 | if (dp->phy_addr) |
| 1140 | exynos_dp_phy_exit(dp); |
| 1141 | } else { |
| 1142 | if (pdata->phy_exit) |
| 1143 | pdata->phy_exit(); |
| 1144 | } |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1145 | |
Jingoo Han | 37414fb | 2012-10-04 15:45:14 +0900 | [diff] [blame] | 1146 | clk_disable_unprepare(dp->clock); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1147 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1148 | return 0; |
| 1149 | } |
| 1150 | |
| 1151 | #ifdef CONFIG_PM_SLEEP |
| 1152 | static int exynos_dp_suspend(struct device *dev) |
| 1153 | { |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1154 | struct exynos_dp_platdata *pdata = dev->platform_data; |
| 1155 | struct exynos_dp_device *dp = dev_get_drvdata(dev); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1156 | |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1157 | if (dev->of_node) { |
| 1158 | if (dp->phy_addr) |
| 1159 | exynos_dp_phy_exit(dp); |
| 1160 | } else { |
| 1161 | if (pdata->phy_exit) |
| 1162 | pdata->phy_exit(); |
| 1163 | } |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1164 | |
Jingoo Han | 37414fb | 2012-10-04 15:45:14 +0900 | [diff] [blame] | 1165 | clk_disable_unprepare(dp->clock); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1166 | |
| 1167 | return 0; |
| 1168 | } |
| 1169 | |
| 1170 | static int exynos_dp_resume(struct device *dev) |
| 1171 | { |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1172 | struct exynos_dp_platdata *pdata = dev->platform_data; |
| 1173 | struct exynos_dp_device *dp = dev_get_drvdata(dev); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1174 | |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1175 | if (dev->of_node) { |
| 1176 | if (dp->phy_addr) |
| 1177 | exynos_dp_phy_init(dp); |
| 1178 | } else { |
| 1179 | if (pdata->phy_init) |
| 1180 | pdata->phy_init(); |
| 1181 | } |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1182 | |
Jingoo Han | 37414fb | 2012-10-04 15:45:14 +0900 | [diff] [blame] | 1183 | clk_prepare_enable(dp->clock); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1184 | |
| 1185 | exynos_dp_init_dp(dp); |
| 1186 | |
| 1187 | exynos_dp_detect_hpd(dp); |
| 1188 | exynos_dp_handle_edid(dp); |
| 1189 | |
| 1190 | exynos_dp_set_link_train(dp, dp->video_info->lane_count, |
| 1191 | dp->video_info->link_rate); |
| 1192 | |
| 1193 | exynos_dp_enable_scramble(dp, 1); |
| 1194 | exynos_dp_enable_rx_to_enhanced_mode(dp, 1); |
| 1195 | exynos_dp_enable_enhanced_mode(dp, 1); |
| 1196 | |
| 1197 | exynos_dp_set_lane_count(dp, dp->video_info->lane_count); |
| 1198 | exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate); |
| 1199 | |
| 1200 | exynos_dp_init_video(dp); |
| 1201 | exynos_dp_config_video(dp, dp->video_info); |
| 1202 | |
| 1203 | return 0; |
| 1204 | } |
| 1205 | #endif |
| 1206 | |
| 1207 | static const struct dev_pm_ops exynos_dp_pm_ops = { |
| 1208 | SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume) |
| 1209 | }; |
| 1210 | |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1211 | static const struct of_device_id exynos_dp_match[] = { |
| 1212 | { .compatible = "samsung,exynos5-dp" }, |
| 1213 | {}, |
| 1214 | }; |
| 1215 | MODULE_DEVICE_TABLE(of, exynos_dp_match); |
| 1216 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1217 | static struct platform_driver exynos_dp_driver = { |
| 1218 | .probe = exynos_dp_probe, |
| 1219 | .remove = __devexit_p(exynos_dp_remove), |
| 1220 | .driver = { |
| 1221 | .name = "exynos-dp", |
| 1222 | .owner = THIS_MODULE, |
| 1223 | .pm = &exynos_dp_pm_ops, |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1224 | .of_match_table = of_match_ptr(exynos_dp_match), |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1225 | }, |
| 1226 | }; |
| 1227 | |
| 1228 | module_platform_driver(exynos_dp_driver); |
| 1229 | |
| 1230 | MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); |
| 1231 | MODULE_DESCRIPTION("Samsung SoC DP Driver"); |
| 1232 | MODULE_LICENSE("GPL"); |