Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2003 Digi International (www.digi.com) |
| 3 | * Scott H Kilau <Scott_Kilau at digi dot com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2, or (at your option) |
| 8 | * any later version. |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 9 | * |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 10 | * This program is distributed in the hope that it will be useful, |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 11 | * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the |
| 12 | * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 13 | * PURPOSE. See the GNU General Public License for more details. |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <linux/kernel.h> |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 17 | #include <linux/sched.h> /* For jiffies, task states */ |
| 18 | #include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */ |
| 19 | #include <linux/delay.h> /* For udelay */ |
Archana kumari | 4a75ffa | 2013-10-16 08:08:54 +0530 | [diff] [blame] | 20 | #include <linux/io.h> /* For read[bwl]/write[bwl] */ |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 21 | #include <linux/serial.h> /* For struct async_serial */ |
| 22 | #include <linux/serial_reg.h> /* For the various UART offsets */ |
| 23 | #include <linux/pci.h> |
| 24 | |
| 25 | #include "dgnc_driver.h" /* Driver main header file */ |
| 26 | #include "dgnc_cls.h" |
| 27 | #include "dgnc_tty.h" |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 28 | |
Lidza Louina | 03425f5 | 2013-09-09 15:01:22 -0400 | [diff] [blame] | 29 | static inline void cls_parse_isr(struct dgnc_board *brd, uint port); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 30 | static inline void cls_clear_break(struct channel_t *ch, int force); |
| 31 | static inline void cls_set_cts_flow_control(struct channel_t *ch); |
| 32 | static inline void cls_set_rts_flow_control(struct channel_t *ch); |
| 33 | static inline void cls_set_ixon_flow_control(struct channel_t *ch); |
| 34 | static inline void cls_set_ixoff_flow_control(struct channel_t *ch); |
| 35 | static inline void cls_set_no_output_flow_control(struct channel_t *ch); |
| 36 | static inline void cls_set_no_input_flow_control(struct channel_t *ch); |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 37 | static void cls_parse_modem(struct channel_t *ch, unsigned char signals); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 38 | static void cls_tasklet(unsigned long data); |
Lidza Louina | 03425f5 | 2013-09-09 15:01:22 -0400 | [diff] [blame] | 39 | static void cls_vpd(struct dgnc_board *brd); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 40 | static void cls_uart_init(struct channel_t *ch); |
| 41 | static void cls_uart_off(struct channel_t *ch); |
| 42 | static int cls_drain(struct tty_struct *tty, uint seconds); |
| 43 | static void cls_param(struct tty_struct *tty); |
| 44 | static void cls_assert_modem_signals(struct channel_t *ch); |
| 45 | static void cls_flush_uart_write(struct channel_t *ch); |
| 46 | static void cls_flush_uart_read(struct channel_t *ch); |
| 47 | static void cls_disable_receiver(struct channel_t *ch); |
| 48 | static void cls_enable_receiver(struct channel_t *ch); |
| 49 | static void cls_send_break(struct channel_t *ch, int msecs); |
| 50 | static void cls_send_start_character(struct channel_t *ch); |
| 51 | static void cls_send_stop_character(struct channel_t *ch); |
| 52 | static void cls_copy_data_from_uart_to_queue(struct channel_t *ch); |
| 53 | static void cls_copy_data_from_queue_to_uart(struct channel_t *ch); |
| 54 | static uint cls_get_uart_bytes_left(struct channel_t *ch); |
| 55 | static void cls_send_immediate_char(struct channel_t *ch, unsigned char); |
| 56 | static irqreturn_t cls_intr(int irq, void *voidbrd); |
| 57 | |
| 58 | struct board_ops dgnc_cls_ops = { |
| 59 | .tasklet = cls_tasklet, |
| 60 | .intr = cls_intr, |
| 61 | .uart_init = cls_uart_init, |
| 62 | .uart_off = cls_uart_off, |
| 63 | .drain = cls_drain, |
| 64 | .param = cls_param, |
| 65 | .vpd = cls_vpd, |
| 66 | .assert_modem_signals = cls_assert_modem_signals, |
| 67 | .flush_uart_write = cls_flush_uart_write, |
| 68 | .flush_uart_read = cls_flush_uart_read, |
| 69 | .disable_receiver = cls_disable_receiver, |
| 70 | .enable_receiver = cls_enable_receiver, |
| 71 | .send_break = cls_send_break, |
| 72 | .send_start_character = cls_send_start_character, |
| 73 | .send_stop_character = cls_send_stop_character, |
| 74 | .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart, |
| 75 | .get_uart_bytes_left = cls_get_uart_bytes_left, |
| 76 | .send_immediate_char = cls_send_immediate_char |
| 77 | }; |
| 78 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 79 | static inline void cls_set_cts_flow_control(struct channel_t *ch) |
| 80 | { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 81 | unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); |
| 82 | unsigned char ier = readb(&ch->ch_cls_uart->ier); |
| 83 | unsigned char isr_fcr = 0; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 84 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 85 | /* |
| 86 | * The Enhanced Register Set may only be accessed when |
| 87 | * the Line Control Register is set to 0xBFh. |
| 88 | */ |
| 89 | writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); |
| 90 | |
| 91 | isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 92 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 93 | /* Turn on CTS flow control, turn off IXON flow control */ |
| 94 | isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR); |
| 95 | isr_fcr &= ~(UART_EXAR654_EFR_IXON); |
| 96 | |
| 97 | writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); |
| 98 | |
| 99 | /* Write old LCR value back out, which turns enhanced access off */ |
| 100 | writeb(lcrb, &ch->ch_cls_uart->lcr); |
| 101 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 102 | /* |
| 103 | * Enable interrupts for CTS flow, turn off interrupts for |
| 104 | * received XOFF chars |
| 105 | */ |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 106 | ier |= (UART_EXAR654_IER_CTSDSR); |
| 107 | ier &= ~(UART_EXAR654_IER_XOFF); |
| 108 | writeb(ier, &ch->ch_cls_uart->ier); |
| 109 | |
| 110 | /* Set the usual FIFO values */ |
| 111 | writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); |
| 112 | |
| 113 | writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 | |
| 114 | UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), |
| 115 | &ch->ch_cls_uart->isr_fcr); |
| 116 | |
| 117 | ch->ch_t_tlevel = 16; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 118 | } |
| 119 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 120 | static inline void cls_set_ixon_flow_control(struct channel_t *ch) |
| 121 | { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 122 | unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); |
| 123 | unsigned char ier = readb(&ch->ch_cls_uart->ier); |
| 124 | unsigned char isr_fcr = 0; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 125 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 126 | /* |
| 127 | * The Enhanced Register Set may only be accessed when |
| 128 | * the Line Control Register is set to 0xBFh. |
| 129 | */ |
| 130 | writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); |
| 131 | |
| 132 | isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 133 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 134 | /* Turn on IXON flow control, turn off CTS flow control */ |
| 135 | isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON); |
| 136 | isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR); |
| 137 | |
| 138 | writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); |
| 139 | |
| 140 | /* Now set our current start/stop chars while in enhanced mode */ |
| 141 | writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); |
| 142 | writeb(0, &ch->ch_cls_uart->lsr); |
| 143 | writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); |
| 144 | writeb(0, &ch->ch_cls_uart->spr); |
| 145 | |
| 146 | /* Write old LCR value back out, which turns enhanced access off */ |
| 147 | writeb(lcrb, &ch->ch_cls_uart->lcr); |
| 148 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 149 | /* |
| 150 | * Disable interrupts for CTS flow, turn on interrupts for |
| 151 | * received XOFF chars |
| 152 | */ |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 153 | ier &= ~(UART_EXAR654_IER_CTSDSR); |
| 154 | ier |= (UART_EXAR654_IER_XOFF); |
| 155 | writeb(ier, &ch->ch_cls_uart->ier); |
| 156 | |
| 157 | /* Set the usual FIFO values */ |
| 158 | writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); |
| 159 | |
| 160 | writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | |
| 161 | UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), |
| 162 | &ch->ch_cls_uart->isr_fcr); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 163 | } |
| 164 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 165 | static inline void cls_set_no_output_flow_control(struct channel_t *ch) |
| 166 | { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 167 | unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); |
| 168 | unsigned char ier = readb(&ch->ch_cls_uart->ier); |
| 169 | unsigned char isr_fcr = 0; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 170 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 171 | /* |
| 172 | * The Enhanced Register Set may only be accessed when |
| 173 | * the Line Control Register is set to 0xBFh. |
| 174 | */ |
| 175 | writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); |
| 176 | |
| 177 | isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 178 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 179 | /* Turn off IXON flow control, turn off CTS flow control */ |
| 180 | isr_fcr |= (UART_EXAR654_EFR_ECB); |
| 181 | isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON); |
| 182 | |
| 183 | writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); |
| 184 | |
| 185 | /* Write old LCR value back out, which turns enhanced access off */ |
| 186 | writeb(lcrb, &ch->ch_cls_uart->lcr); |
| 187 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 188 | /* |
| 189 | * Disable interrupts for CTS flow, turn off interrupts for |
| 190 | * received XOFF chars |
| 191 | */ |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 192 | ier &= ~(UART_EXAR654_IER_CTSDSR); |
| 193 | ier &= ~(UART_EXAR654_IER_XOFF); |
| 194 | writeb(ier, &ch->ch_cls_uart->ier); |
| 195 | |
| 196 | /* Set the usual FIFO values */ |
| 197 | writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); |
| 198 | |
| 199 | writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | |
| 200 | UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), |
| 201 | &ch->ch_cls_uart->isr_fcr); |
| 202 | |
| 203 | ch->ch_r_watermark = 0; |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 204 | ch->ch_t_tlevel = 16; |
| 205 | ch->ch_r_tlevel = 16; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 206 | } |
| 207 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 208 | static inline void cls_set_rts_flow_control(struct channel_t *ch) |
| 209 | { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 210 | unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); |
| 211 | unsigned char ier = readb(&ch->ch_cls_uart->ier); |
| 212 | unsigned char isr_fcr = 0; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 213 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 214 | /* |
| 215 | * The Enhanced Register Set may only be accessed when |
| 216 | * the Line Control Register is set to 0xBFh. |
| 217 | */ |
| 218 | writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); |
| 219 | |
| 220 | isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 221 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 222 | /* Turn on RTS flow control, turn off IXOFF flow control */ |
| 223 | isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR); |
| 224 | isr_fcr &= ~(UART_EXAR654_EFR_IXOFF); |
| 225 | |
| 226 | writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); |
| 227 | |
| 228 | /* Write old LCR value back out, which turns enhanced access off */ |
| 229 | writeb(lcrb, &ch->ch_cls_uart->lcr); |
| 230 | |
| 231 | /* Enable interrupts for RTS flow */ |
| 232 | ier |= (UART_EXAR654_IER_RTSDTR); |
| 233 | writeb(ier, &ch->ch_cls_uart->ier); |
| 234 | |
| 235 | /* Set the usual FIFO values */ |
| 236 | writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); |
| 237 | |
| 238 | writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 | |
| 239 | UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), |
| 240 | &ch->ch_cls_uart->isr_fcr); |
| 241 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 242 | ch->ch_r_watermark = 4; |
| 243 | ch->ch_r_tlevel = 8; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 244 | } |
| 245 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 246 | static inline void cls_set_ixoff_flow_control(struct channel_t *ch) |
| 247 | { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 248 | unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); |
| 249 | unsigned char ier = readb(&ch->ch_cls_uart->ier); |
| 250 | unsigned char isr_fcr = 0; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 251 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 252 | /* |
| 253 | * The Enhanced Register Set may only be accessed when |
| 254 | * the Line Control Register is set to 0xBFh. |
| 255 | */ |
| 256 | writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); |
| 257 | |
| 258 | isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 259 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 260 | /* Turn on IXOFF flow control, turn off RTS flow control */ |
| 261 | isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF); |
| 262 | isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR); |
| 263 | |
| 264 | writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); |
| 265 | |
| 266 | /* Now set our current start/stop chars while in enhanced mode */ |
| 267 | writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); |
| 268 | writeb(0, &ch->ch_cls_uart->lsr); |
| 269 | writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); |
| 270 | writeb(0, &ch->ch_cls_uart->spr); |
| 271 | |
| 272 | /* Write old LCR value back out, which turns enhanced access off */ |
| 273 | writeb(lcrb, &ch->ch_cls_uart->lcr); |
| 274 | |
| 275 | /* Disable interrupts for RTS flow */ |
| 276 | ier &= ~(UART_EXAR654_IER_RTSDTR); |
| 277 | writeb(ier, &ch->ch_cls_uart->ier); |
| 278 | |
| 279 | /* Set the usual FIFO values */ |
| 280 | writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); |
| 281 | |
| 282 | writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | |
| 283 | UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), |
| 284 | &ch->ch_cls_uart->isr_fcr); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 285 | } |
| 286 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 287 | static inline void cls_set_no_input_flow_control(struct channel_t *ch) |
| 288 | { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 289 | unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); |
| 290 | unsigned char ier = readb(&ch->ch_cls_uart->ier); |
| 291 | unsigned char isr_fcr = 0; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 292 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 293 | /* |
| 294 | * The Enhanced Register Set may only be accessed when |
| 295 | * the Line Control Register is set to 0xBFh. |
| 296 | */ |
| 297 | writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); |
| 298 | |
| 299 | isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 300 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 301 | /* Turn off IXOFF flow control, turn off RTS flow control */ |
| 302 | isr_fcr |= (UART_EXAR654_EFR_ECB); |
| 303 | isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF); |
| 304 | |
| 305 | writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); |
| 306 | |
| 307 | /* Write old LCR value back out, which turns enhanced access off */ |
| 308 | writeb(lcrb, &ch->ch_cls_uart->lcr); |
| 309 | |
| 310 | /* Disable interrupts for RTS flow */ |
| 311 | ier &= ~(UART_EXAR654_IER_RTSDTR); |
| 312 | writeb(ier, &ch->ch_cls_uart->ier); |
| 313 | |
| 314 | /* Set the usual FIFO values */ |
| 315 | writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); |
| 316 | |
| 317 | writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | |
| 318 | UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), |
| 319 | &ch->ch_cls_uart->isr_fcr); |
| 320 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 321 | ch->ch_t_tlevel = 16; |
| 322 | ch->ch_r_tlevel = 16; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 323 | } |
| 324 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 325 | /* |
| 326 | * cls_clear_break. |
| 327 | * Determines whether its time to shut off break condition. |
| 328 | * |
| 329 | * No locks are assumed to be held when calling this function. |
| 330 | * channel lock is held and released in this function. |
| 331 | */ |
| 332 | static inline void cls_clear_break(struct channel_t *ch, int force) |
| 333 | { |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 334 | unsigned long flags; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 335 | |
| 336 | if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) |
| 337 | return; |
| 338 | |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 339 | spin_lock_irqsave(&ch->ch_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 340 | |
| 341 | /* Bail if we aren't currently sending a break. */ |
| 342 | if (!ch->ch_stop_sending_break) { |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 343 | spin_unlock_irqrestore(&ch->ch_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 344 | return; |
| 345 | } |
| 346 | |
| 347 | /* Turn break off, and unset some variables */ |
| 348 | if (ch->ch_flags & CH_BREAK_SENDING) { |
stalinsrinivasan.s | f0dcc9f | 2013-12-20 22:03:27 +0530 | [diff] [blame] | 349 | if (time_after(jiffies, ch->ch_stop_sending_break) || force) { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 350 | unsigned char temp = readb(&ch->ch_cls_uart->lcr); |
Konrad Zapalowicz | 8aa5d0d | 2014-08-06 22:17:09 +0200 | [diff] [blame] | 351 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 352 | writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 353 | ch->ch_flags &= ~(CH_BREAK_SENDING); |
| 354 | ch->ch_stop_sending_break = 0; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 355 | } |
| 356 | } |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 357 | spin_unlock_irqrestore(&ch->ch_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 358 | } |
| 359 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 360 | /* Parse the ISR register for the specific port */ |
Lidza Louina | 03425f5 | 2013-09-09 15:01:22 -0400 | [diff] [blame] | 361 | static inline void cls_parse_isr(struct dgnc_board *brd, uint port) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 362 | { |
| 363 | struct channel_t *ch; |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 364 | unsigned char isr = 0; |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 365 | unsigned long flags; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 366 | |
| 367 | /* |
| 368 | * No need to verify board pointer, it was already |
| 369 | * verified in the interrupt routine. |
| 370 | */ |
| 371 | |
Dan Carpenter | 4bef52f | 2015-03-12 20:24:31 +0300 | [diff] [blame] | 372 | if (port >= brd->nasync) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 373 | return; |
| 374 | |
| 375 | ch = brd->channels[port]; |
Giedrius Statkevičius | 071494d | 2015-04-10 02:42:31 +0300 | [diff] [blame] | 376 | if (ch->magic != DGNC_CHANNEL_MAGIC) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 377 | return; |
| 378 | |
| 379 | /* Here we try to figure out what caused the interrupt to happen */ |
| 380 | while (1) { |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 381 | isr = readb(&ch->ch_cls_uart->isr_fcr); |
| 382 | |
| 383 | /* Bail if no pending interrupt on port */ |
Archana kumari | 3d47910 | 2013-10-17 18:45:16 +0530 | [diff] [blame] | 384 | if (isr & UART_IIR_NO_INT) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 385 | break; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 386 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 387 | /* Receive Interrupt pending */ |
| 388 | if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) { |
| 389 | /* Read data from uart -> queue */ |
| 390 | brd->intr_rx++; |
| 391 | ch->ch_intr_rx++; |
| 392 | cls_copy_data_from_uart_to_queue(ch); |
| 393 | dgnc_check_queue_flow_control(ch); |
| 394 | } |
| 395 | |
| 396 | /* Transmit Hold register empty pending */ |
| 397 | if (isr & UART_IIR_THRI) { |
| 398 | /* Transfer data (if any) from Write Queue -> UART. */ |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 399 | spin_lock_irqsave(&ch->ch_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 400 | ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); |
| 401 | brd->intr_tx++; |
| 402 | ch->ch_intr_tx++; |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 403 | spin_unlock_irqrestore(&ch->ch_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 404 | cls_copy_data_from_queue_to_uart(ch); |
| 405 | } |
| 406 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 407 | /* CTS/RTS change of state */ |
| 408 | if (isr & UART_IIR_CTSRTS) { |
| 409 | brd->intr_modem++; |
| 410 | ch->ch_intr_modem++; |
| 411 | /* |
| 412 | * Don't need to do anything, the cls_parse_modem |
| 413 | * below will grab the updated modem signals. |
| 414 | */ |
| 415 | } |
| 416 | |
| 417 | /* Parse any modem signal changes */ |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 418 | cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); |
| 419 | } |
| 420 | } |
| 421 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 422 | /* |
| 423 | * cls_param() |
| 424 | * Send any/all changes to the line to the UART. |
| 425 | */ |
| 426 | static void cls_param(struct tty_struct *tty) |
| 427 | { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 428 | unsigned char lcr = 0; |
| 429 | unsigned char uart_lcr = 0; |
| 430 | unsigned char ier = 0; |
| 431 | unsigned char uart_ier = 0; |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 432 | uint baud = 9600; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 433 | int quot = 0; |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 434 | struct dgnc_board *bd; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 435 | struct channel_t *ch; |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 436 | struct un_t *un; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 437 | |
Archana kumari | 3d47910 | 2013-10-17 18:45:16 +0530 | [diff] [blame] | 438 | if (!tty || tty->magic != TTY_MAGIC) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 439 | return; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 440 | |
Sudip Mukherjee | 6f41825 | 2015-10-04 19:50:13 +0530 | [diff] [blame] | 441 | un = (struct un_t *)tty->driver_data; |
Archana kumari | 3d47910 | 2013-10-17 18:45:16 +0530 | [diff] [blame] | 442 | if (!un || un->magic != DGNC_UNIT_MAGIC) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 443 | return; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 444 | |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 445 | ch = un->un_ch; |
Archana kumari | 3d47910 | 2013-10-17 18:45:16 +0530 | [diff] [blame] | 446 | if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 447 | return; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 448 | |
| 449 | bd = ch->ch_bd; |
Archana kumari | 3d47910 | 2013-10-17 18:45:16 +0530 | [diff] [blame] | 450 | if (!bd || bd->magic != DGNC_BOARD_MAGIC) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 451 | return; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 452 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 453 | /* |
| 454 | * If baud rate is zero, flush queues, and set mval to drop DTR. |
| 455 | */ |
| 456 | if ((ch->ch_c_cflag & (CBAUD)) == 0) { |
Seunghun Lee | 587abd7 | 2014-09-01 22:46:59 +0900 | [diff] [blame] | 457 | ch->ch_r_head = 0; |
| 458 | ch->ch_r_tail = 0; |
| 459 | ch->ch_e_head = 0; |
| 460 | ch->ch_e_tail = 0; |
| 461 | ch->ch_w_head = 0; |
| 462 | ch->ch_w_tail = 0; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 463 | |
| 464 | cls_flush_uart_write(ch); |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 465 | cls_flush_uart_read(ch); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 466 | |
| 467 | /* The baudrate is B0 so all modem lines are to be dropped. */ |
| 468 | ch->ch_flags |= (CH_BAUD0); |
| 469 | ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); |
| 470 | cls_assert_modem_signals(ch); |
| 471 | ch->ch_old_baud = 0; |
| 472 | return; |
| 473 | } else if (ch->ch_custom_speed) { |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 474 | baud = ch->ch_custom_speed; |
| 475 | /* Handle transition from B0 */ |
| 476 | if (ch->ch_flags & CH_BAUD0) { |
| 477 | ch->ch_flags &= ~(CH_BAUD0); |
| 478 | |
| 479 | /* |
| 480 | * Bring back up RTS and DTR... |
| 481 | * Also handle RTS or DTR toggle if set. |
| 482 | */ |
| 483 | if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE)) |
| 484 | ch->ch_mostat |= (UART_MCR_RTS); |
| 485 | if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE)) |
| 486 | ch->ch_mostat |= (UART_MCR_DTR); |
| 487 | } |
| 488 | |
| 489 | } else { |
| 490 | int iindex = 0; |
| 491 | int jindex = 0; |
| 492 | |
| 493 | ulong bauds[4][16] = { |
| 494 | { /* slowbaud */ |
| 495 | 0, 50, 75, 110, |
| 496 | 134, 150, 200, 300, |
| 497 | 600, 1200, 1800, 2400, |
| 498 | 4800, 9600, 19200, 38400 }, |
| 499 | { /* slowbaud & CBAUDEX */ |
| 500 | 0, 57600, 115200, 230400, |
| 501 | 460800, 150, 200, 921600, |
| 502 | 600, 1200, 1800, 2400, |
| 503 | 4800, 9600, 19200, 38400 }, |
| 504 | { /* fastbaud */ |
| 505 | 0, 57600, 76800, 115200, |
| 506 | 131657, 153600, 230400, 460800, |
| 507 | 921600, 1200, 1800, 2400, |
| 508 | 4800, 9600, 19200, 38400 }, |
| 509 | { /* fastbaud & CBAUDEX */ |
| 510 | 0, 57600, 115200, 230400, |
| 511 | 460800, 150, 200, 921600, |
| 512 | 600, 1200, 1800, 2400, |
| 513 | 4800, 9600, 19200, 38400 } |
| 514 | }; |
| 515 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 516 | /* |
| 517 | * Only use the TXPrint baud rate if the terminal |
| 518 | * unit is NOT open |
| 519 | */ |
| 520 | if (!(ch->ch_tun.un_flags & UN_ISOPEN) && |
Sudip Mukherjee | e352d3f | 2015-10-04 19:50:14 +0530 | [diff] [blame] | 521 | (un->un_type == DGNC_PRINT)) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 522 | baud = C_BAUD(ch->ch_pun.un_tty) & 0xff; |
| 523 | else |
| 524 | baud = C_BAUD(ch->ch_tun.un_tty) & 0xff; |
| 525 | |
| 526 | if (ch->ch_c_cflag & CBAUDEX) |
| 527 | iindex = 1; |
| 528 | |
| 529 | if (ch->ch_digi.digi_flags & DIGI_FAST) |
| 530 | iindex += 2; |
| 531 | |
| 532 | jindex = baud; |
| 533 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 534 | if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && |
Sudip Mukherjee | e352d3f | 2015-10-04 19:50:14 +0530 | [diff] [blame] | 535 | (jindex < 16)) { |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 536 | baud = bauds[iindex][jindex]; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 537 | } else { |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 538 | baud = 0; |
| 539 | } |
| 540 | |
| 541 | if (baud == 0) |
| 542 | baud = 9600; |
| 543 | |
| 544 | /* Handle transition from B0 */ |
| 545 | if (ch->ch_flags & CH_BAUD0) { |
| 546 | ch->ch_flags &= ~(CH_BAUD0); |
| 547 | |
| 548 | /* |
| 549 | * Bring back up RTS and DTR... |
| 550 | * Also handle RTS or DTR toggle if set. |
| 551 | */ |
| 552 | if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE)) |
| 553 | ch->ch_mostat |= (UART_MCR_RTS); |
| 554 | if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE)) |
| 555 | ch->ch_mostat |= (UART_MCR_DTR); |
| 556 | } |
| 557 | } |
| 558 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 559 | if (ch->ch_c_cflag & PARENB) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 560 | lcr |= UART_LCR_PARITY; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 561 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 562 | if (!(ch->ch_c_cflag & PARODD)) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 563 | lcr |= UART_LCR_EPAR; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 564 | |
| 565 | /* |
| 566 | * Not all platforms support mark/space parity, |
| 567 | * so this will hide behind an ifdef. |
| 568 | */ |
| 569 | #ifdef CMSPAR |
| 570 | if (ch->ch_c_cflag & CMSPAR) |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 571 | lcr |= UART_LCR_SPAR; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 572 | #endif |
| 573 | |
| 574 | if (ch->ch_c_cflag & CSTOPB) |
| 575 | lcr |= UART_LCR_STOP; |
| 576 | |
| 577 | switch (ch->ch_c_cflag & CSIZE) { |
| 578 | case CS5: |
| 579 | lcr |= UART_LCR_WLEN5; |
| 580 | break; |
| 581 | case CS6: |
| 582 | lcr |= UART_LCR_WLEN6; |
| 583 | break; |
| 584 | case CS7: |
| 585 | lcr |= UART_LCR_WLEN7; |
| 586 | break; |
| 587 | case CS8: |
| 588 | default: |
| 589 | lcr |= UART_LCR_WLEN8; |
| 590 | break; |
| 591 | } |
| 592 | |
Seunghun Lee | 587abd7 | 2014-09-01 22:46:59 +0900 | [diff] [blame] | 593 | uart_ier = readb(&ch->ch_cls_uart->ier); |
| 594 | ier = uart_ier; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 595 | uart_lcr = readb(&ch->ch_cls_uart->lcr); |
| 596 | |
| 597 | if (baud == 0) |
| 598 | baud = 9600; |
| 599 | |
| 600 | quot = ch->ch_bd->bd_dividend / baud; |
| 601 | |
| 602 | if (quot != 0 && ch->ch_old_baud != baud) { |
| 603 | ch->ch_old_baud = baud; |
| 604 | writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr); |
| 605 | writeb((quot & 0xff), &ch->ch_cls_uart->txrx); |
| 606 | writeb((quot >> 8), &ch->ch_cls_uart->ier); |
| 607 | writeb(lcr, &ch->ch_cls_uart->lcr); |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 608 | } |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 609 | |
| 610 | if (uart_lcr != lcr) |
| 611 | writeb(lcr, &ch->ch_cls_uart->lcr); |
| 612 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 613 | if (ch->ch_c_cflag & CREAD) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 614 | ier |= (UART_IER_RDI | UART_IER_RLSI); |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 615 | else |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 616 | ier &= ~(UART_IER_RDI | UART_IER_RLSI); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 617 | |
| 618 | /* |
| 619 | * Have the UART interrupt on modem signal changes ONLY when |
| 620 | * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set. |
| 621 | */ |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 622 | if ((ch->ch_digi.digi_flags & CTSPACE) || |
Cristina Moraru | c76d294 | 2015-10-01 21:43:57 +0300 | [diff] [blame] | 623 | (ch->ch_digi.digi_flags & RTSPACE) || |
| 624 | (ch->ch_c_cflag & CRTSCTS) || |
| 625 | !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) || |
| 626 | !(ch->ch_c_cflag & CLOCAL)) |
| 627 | ier |= UART_IER_MSI; |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 628 | else |
Cristina Moraru | c76d294 | 2015-10-01 21:43:57 +0300 | [diff] [blame] | 629 | ier &= ~UART_IER_MSI; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 630 | |
| 631 | ier |= UART_IER_THRI; |
| 632 | |
| 633 | if (ier != uart_ier) |
| 634 | writeb(ier, &ch->ch_cls_uart->ier); |
| 635 | |
| 636 | if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) { |
| 637 | cls_set_cts_flow_control(ch); |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 638 | } else if (ch->ch_c_iflag & IXON) { |
| 639 | /* |
| 640 | * If start/stop is set to disable, then we should |
| 641 | * disable flow control |
| 642 | */ |
| 643 | if ((ch->ch_startc == _POSIX_VDISABLE) || |
Sudip Mukherjee | e352d3f | 2015-10-04 19:50:14 +0530 | [diff] [blame] | 644 | (ch->ch_stopc == _POSIX_VDISABLE)) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 645 | cls_set_no_output_flow_control(ch); |
| 646 | else |
| 647 | cls_set_ixon_flow_control(ch); |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 648 | } else { |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 649 | cls_set_no_output_flow_control(ch); |
| 650 | } |
| 651 | |
| 652 | if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) { |
| 653 | cls_set_rts_flow_control(ch); |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 654 | } else if (ch->ch_c_iflag & IXOFF) { |
| 655 | /* |
| 656 | * If start/stop is set to disable, then we should disable |
| 657 | * flow control |
| 658 | */ |
| 659 | if ((ch->ch_startc == _POSIX_VDISABLE) || |
Sudip Mukherjee | e352d3f | 2015-10-04 19:50:14 +0530 | [diff] [blame] | 660 | (ch->ch_stopc == _POSIX_VDISABLE)) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 661 | cls_set_no_input_flow_control(ch); |
| 662 | else |
| 663 | cls_set_ixoff_flow_control(ch); |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 664 | } else { |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 665 | cls_set_no_input_flow_control(ch); |
| 666 | } |
| 667 | |
| 668 | cls_assert_modem_signals(ch); |
| 669 | |
| 670 | /* Get current status of the modem signals now */ |
| 671 | cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); |
| 672 | } |
| 673 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 674 | /* |
| 675 | * Our board poller function. |
| 676 | */ |
| 677 | static void cls_tasklet(unsigned long data) |
| 678 | { |
Sudip Mukherjee | 6f41825 | 2015-10-04 19:50:13 +0530 | [diff] [blame] | 679 | struct dgnc_board *bd = (struct dgnc_board *)data; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 680 | struct channel_t *ch; |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 681 | unsigned long flags; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 682 | int i; |
| 683 | int state = 0; |
| 684 | int ports = 0; |
| 685 | |
Roberta Dobrescu | 1f26adc | 2014-10-07 13:08:12 +0300 | [diff] [blame] | 686 | if (!bd || bd->magic != DGNC_BOARD_MAGIC) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 687 | return; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 688 | |
| 689 | /* Cache a couple board values */ |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 690 | spin_lock_irqsave(&bd->bd_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 691 | state = bd->state; |
| 692 | ports = bd->nasync; |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 693 | spin_unlock_irqrestore(&bd->bd_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 694 | |
| 695 | /* |
| 696 | * Do NOT allow the interrupt routine to read the intr registers |
| 697 | * Until we release this lock. |
| 698 | */ |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 699 | spin_lock_irqsave(&bd->bd_intr_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 700 | |
| 701 | /* |
| 702 | * If board is ready, parse deeper to see if there is anything to do. |
| 703 | */ |
| 704 | if ((state == BOARD_READY) && (ports > 0)) { |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 705 | /* Loop on each port */ |
| 706 | for (i = 0; i < ports; i++) { |
| 707 | ch = bd->channels[i]; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 708 | |
| 709 | /* |
| 710 | * NOTE: Remember you CANNOT hold any channel |
| 711 | * locks when calling input. |
| 712 | * During input processing, its possible we |
| 713 | * will call ld, which might do callbacks back |
| 714 | * into us. |
| 715 | */ |
| 716 | dgnc_input(ch); |
| 717 | |
| 718 | /* |
| 719 | * Channel lock is grabbed and then released |
| 720 | * inside this routine. |
| 721 | */ |
| 722 | cls_copy_data_from_queue_to_uart(ch); |
| 723 | dgnc_wakeup_writes(ch); |
| 724 | |
| 725 | /* |
| 726 | * Check carrier function. |
| 727 | */ |
| 728 | dgnc_carrier(ch); |
| 729 | |
| 730 | /* |
| 731 | * The timing check of turning off the break is done |
| 732 | * inside clear_break() |
| 733 | */ |
| 734 | if (ch->ch_stop_sending_break) |
| 735 | cls_clear_break(ch, 0); |
| 736 | } |
| 737 | } |
| 738 | |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 739 | spin_unlock_irqrestore(&bd->bd_intr_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 740 | } |
| 741 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 742 | /* |
| 743 | * cls_intr() |
| 744 | * |
| 745 | * Classic specific interrupt handler. |
| 746 | */ |
| 747 | static irqreturn_t cls_intr(int irq, void *voidbrd) |
| 748 | { |
Tapasweni Pathak | fc33bd2 | 2014-10-30 17:02:04 +0530 | [diff] [blame] | 749 | struct dgnc_board *brd = voidbrd; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 750 | uint i = 0; |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 751 | unsigned char poll_reg; |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 752 | unsigned long flags; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 753 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 754 | /* |
Roberta Dobrescu | 1f26adc | 2014-10-07 13:08:12 +0300 | [diff] [blame] | 755 | * Check to make sure it didn't receive interrupt with a null board |
| 756 | * associated or a board pointer that wasn't ours. |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 757 | */ |
Roberta Dobrescu | 1f26adc | 2014-10-07 13:08:12 +0300 | [diff] [blame] | 758 | if (!brd || brd->magic != DGNC_BOARD_MAGIC) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 759 | return IRQ_NONE; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 760 | |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 761 | spin_lock_irqsave(&brd->bd_intr_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 762 | |
| 763 | brd->intr_count++; |
| 764 | |
| 765 | /* |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 766 | * Check the board's global interrupt offset to see if we |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 767 | * we actually do have an interrupt pending for us. |
| 768 | */ |
| 769 | poll_reg = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET); |
| 770 | |
| 771 | /* If 0, no interrupts pending */ |
| 772 | if (!poll_reg) { |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 773 | spin_unlock_irqrestore(&brd->bd_intr_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 774 | return IRQ_NONE; |
| 775 | } |
| 776 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 777 | /* Parse each port to find out what caused the interrupt */ |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 778 | for (i = 0; i < brd->nasync; i++) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 779 | cls_parse_isr(brd, i); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 780 | |
| 781 | /* |
| 782 | * Schedule tasklet to more in-depth servicing at a better time. |
| 783 | */ |
| 784 | tasklet_schedule(&brd->helper_tasklet); |
| 785 | |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 786 | spin_unlock_irqrestore(&brd->bd_intr_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 787 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 788 | return IRQ_HANDLED; |
| 789 | } |
| 790 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 791 | static void cls_disable_receiver(struct channel_t *ch) |
| 792 | { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 793 | unsigned char tmp = readb(&ch->ch_cls_uart->ier); |
Konrad Zapalowicz | 8aa5d0d | 2014-08-06 22:17:09 +0200 | [diff] [blame] | 794 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 795 | tmp &= ~(UART_IER_RDI); |
| 796 | writeb(tmp, &ch->ch_cls_uart->ier); |
| 797 | } |
| 798 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 799 | static void cls_enable_receiver(struct channel_t *ch) |
| 800 | { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 801 | unsigned char tmp = readb(&ch->ch_cls_uart->ier); |
Konrad Zapalowicz | 8aa5d0d | 2014-08-06 22:17:09 +0200 | [diff] [blame] | 802 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 803 | tmp |= (UART_IER_RDI); |
| 804 | writeb(tmp, &ch->ch_cls_uart->ier); |
| 805 | } |
| 806 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 807 | static void cls_copy_data_from_uart_to_queue(struct channel_t *ch) |
| 808 | { |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 809 | int qleft = 0; |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 810 | unsigned char linestatus = 0; |
| 811 | unsigned char error_mask = 0; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 812 | ushort head; |
| 813 | ushort tail; |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 814 | unsigned long flags; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 815 | |
| 816 | if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) |
| 817 | return; |
| 818 | |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 819 | spin_lock_irqsave(&ch->ch_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 820 | |
| 821 | /* cache head and tail of queue */ |
| 822 | head = ch->ch_r_head; |
| 823 | tail = ch->ch_r_tail; |
| 824 | |
| 825 | /* Store how much space we have left in the queue */ |
Eva Rachel Retuya | 0b7ceaa | 2016-02-24 00:34:56 +0800 | [diff] [blame] | 826 | qleft = tail - head - 1; |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 827 | if (qleft < 0) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 828 | qleft += RQUEUEMASK + 1; |
| 829 | |
| 830 | /* |
| 831 | * Create a mask to determine whether we should |
| 832 | * insert the character (if any) into our queue. |
| 833 | */ |
| 834 | if (ch->ch_c_iflag & IGNBRK) |
| 835 | error_mask |= UART_LSR_BI; |
| 836 | |
| 837 | while (1) { |
| 838 | linestatus = readb(&ch->ch_cls_uart->lsr); |
| 839 | |
| 840 | if (!(linestatus & (UART_LSR_DR))) |
| 841 | break; |
| 842 | |
| 843 | /* |
| 844 | * Discard character if we are ignoring the error mask. |
| 845 | */ |
| 846 | if (linestatus & error_mask) { |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 847 | linestatus = 0; |
Sudip Mukherjee | 2d9920e | 2015-10-03 20:52:39 +0530 | [diff] [blame] | 848 | readb(&ch->ch_cls_uart->txrx); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 849 | continue; |
| 850 | } |
| 851 | |
| 852 | /* |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 853 | * If our queue is full, we have no choice but to drop some |
| 854 | * data. The assumption is that HWFLOW or SWFLOW should have |
| 855 | * stopped things way way before we got to this point. |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 856 | * |
| 857 | * I decided that I wanted to ditch the oldest data first, |
| 858 | * I hope thats okay with everyone? Yes? Good. |
| 859 | */ |
| 860 | while (qleft < 1) { |
Seunghun Lee | 587abd7 | 2014-09-01 22:46:59 +0900 | [diff] [blame] | 861 | tail = (tail + 1) & RQUEUEMASK; |
| 862 | ch->ch_r_tail = tail; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 863 | ch->ch_err_overrun++; |
| 864 | qleft++; |
| 865 | } |
| 866 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 867 | ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE |
| 868 | | UART_LSR_FE); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 869 | ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 870 | |
| 871 | qleft--; |
| 872 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 873 | if (ch->ch_equeue[head] & UART_LSR_PE) |
| 874 | ch->ch_err_parity++; |
| 875 | if (ch->ch_equeue[head] & UART_LSR_BI) |
| 876 | ch->ch_err_break++; |
| 877 | if (ch->ch_equeue[head] & UART_LSR_FE) |
| 878 | ch->ch_err_frame++; |
| 879 | |
| 880 | /* Add to, and flip head if needed */ |
| 881 | head = (head + 1) & RQUEUEMASK; |
| 882 | ch->ch_rxcount++; |
| 883 | } |
| 884 | |
| 885 | /* |
| 886 | * Write new final heads to channel structure. |
| 887 | */ |
| 888 | ch->ch_r_head = head & RQUEUEMASK; |
| 889 | ch->ch_e_head = head & EQUEUEMASK; |
| 890 | |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 891 | spin_unlock_irqrestore(&ch->ch_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 892 | } |
| 893 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 894 | /* |
| 895 | * This function basically goes to sleep for secs, or until |
| 896 | * it gets signalled that the port has fully drained. |
| 897 | */ |
| 898 | static int cls_drain(struct tty_struct *tty, uint seconds) |
| 899 | { |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 900 | unsigned long flags; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 901 | struct channel_t *ch; |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 902 | struct un_t *un; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 903 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 904 | if (!tty || tty->magic != TTY_MAGIC) |
Lidza Louina | 8f90ef8 | 2013-09-09 15:01:23 -0400 | [diff] [blame] | 905 | return -ENXIO; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 906 | |
Sudip Mukherjee | 6f41825 | 2015-10-04 19:50:13 +0530 | [diff] [blame] | 907 | un = (struct un_t *)tty->driver_data; |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 908 | if (!un || un->magic != DGNC_UNIT_MAGIC) |
Lidza Louina | 8f90ef8 | 2013-09-09 15:01:23 -0400 | [diff] [blame] | 909 | return -ENXIO; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 910 | |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 911 | ch = un->un_ch; |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 912 | if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) |
Lidza Louina | 8f90ef8 | 2013-09-09 15:01:23 -0400 | [diff] [blame] | 913 | return -ENXIO; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 914 | |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 915 | spin_lock_irqsave(&ch->ch_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 916 | un->un_flags |= UN_EMPTY; |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 917 | spin_unlock_irqrestore(&ch->ch_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 918 | |
| 919 | /* |
| 920 | * NOTE: Do something with time passed in. |
| 921 | */ |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 922 | |
| 923 | /* If ret is non-zero, user ctrl-c'ed us */ |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 924 | |
Heena Sirwani | ca5dd0b | 2014-10-06 10:19:09 +0530 | [diff] [blame] | 925 | return wait_event_interruptible(un->un_flags_wait, |
| 926 | ((un->un_flags & UN_EMPTY) == 0)); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 927 | } |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 928 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 929 | /* Channel lock MUST be held before calling this function! */ |
| 930 | static void cls_flush_uart_write(struct channel_t *ch) |
| 931 | { |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 932 | if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 933 | return; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 934 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 935 | writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), |
Sudip Mukherjee | e352d3f | 2015-10-04 19:50:14 +0530 | [diff] [blame] | 936 | &ch->ch_cls_uart->isr_fcr); |
Jitendra Kumar Khasdev | 6e41175 | 2015-11-24 23:01:13 +0530 | [diff] [blame] | 937 | usleep_range(10, 20); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 938 | |
| 939 | ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); |
| 940 | } |
| 941 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 942 | /* Channel lock MUST be held before calling this function! */ |
| 943 | static void cls_flush_uart_read(struct channel_t *ch) |
| 944 | { |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 945 | if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 946 | return; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 947 | |
| 948 | /* |
| 949 | * For complete POSIX compatibility, we should be purging the |
| 950 | * read FIFO in the UART here. |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 951 | * |
Seunghun Lee | 83f053d | 2014-07-31 22:30:32 +0900 | [diff] [blame] | 952 | * However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also |
| 953 | * incorrectly flushes write data as well as just basically trashing the |
| 954 | * FIFO. |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 955 | * |
Seunghun Lee | 83f053d | 2014-07-31 22:30:32 +0900 | [diff] [blame] | 956 | * Presumably, this is a bug in this UART. |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 957 | */ |
Seunghun Lee | 645b031 | 2014-07-26 01:49:01 +0900 | [diff] [blame] | 958 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 959 | udelay(10); |
| 960 | } |
| 961 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 962 | static void cls_copy_data_from_queue_to_uart(struct channel_t *ch) |
| 963 | { |
| 964 | ushort head; |
| 965 | ushort tail; |
| 966 | int n; |
| 967 | int qlen; |
| 968 | uint len_written = 0; |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 969 | unsigned long flags; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 970 | |
| 971 | if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) |
| 972 | return; |
| 973 | |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 974 | spin_lock_irqsave(&ch->ch_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 975 | |
| 976 | /* No data to write to the UART */ |
Quentin Lambert | f6a14cf | 2015-03-11 15:22:00 +0100 | [diff] [blame] | 977 | if (ch->ch_w_tail == ch->ch_w_head) |
| 978 | goto exit_unlock; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 979 | |
| 980 | /* If port is "stopped", don't send any data to the UART */ |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 981 | if ((ch->ch_flags & CH_FORCED_STOP) || |
Sudip Mukherjee | e352d3f | 2015-10-04 19:50:14 +0530 | [diff] [blame] | 982 | (ch->ch_flags & CH_BREAK_SENDING)) |
Quentin Lambert | f6a14cf | 2015-03-11 15:22:00 +0100 | [diff] [blame] | 983 | goto exit_unlock; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 984 | |
Quentin Lambert | f6a14cf | 2015-03-11 15:22:00 +0100 | [diff] [blame] | 985 | if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) |
| 986 | goto exit_unlock; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 987 | |
| 988 | n = 32; |
| 989 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 990 | /* cache head and tail of queue */ |
| 991 | head = ch->ch_w_head & WQUEUEMASK; |
| 992 | tail = ch->ch_w_tail & WQUEUEMASK; |
| 993 | qlen = (head - tail) & WQUEUEMASK; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 994 | |
| 995 | /* Find minimum of the FIFO space, versus queue length */ |
| 996 | n = min(n, qlen); |
| 997 | |
| 998 | while (n > 0) { |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 999 | /* |
| 1000 | * If RTS Toggle mode is on, turn on RTS now if not already set, |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 1001 | * and make sure we get an event when the data transfer has |
| 1002 | * completed. |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1003 | */ |
| 1004 | if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) { |
| 1005 | if (!(ch->ch_mostat & UART_MCR_RTS)) { |
| 1006 | ch->ch_mostat |= (UART_MCR_RTS); |
| 1007 | cls_assert_modem_signals(ch); |
| 1008 | } |
| 1009 | ch->ch_tun.un_flags |= (UN_EMPTY); |
| 1010 | } |
| 1011 | |
| 1012 | /* |
| 1013 | * If DTR Toggle mode is on, turn on DTR now if not already set, |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 1014 | * and make sure we get an event when the data transfer has |
| 1015 | * completed. |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1016 | */ |
| 1017 | if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) { |
| 1018 | if (!(ch->ch_mostat & UART_MCR_DTR)) { |
| 1019 | ch->ch_mostat |= (UART_MCR_DTR); |
| 1020 | cls_assert_modem_signals(ch); |
| 1021 | } |
| 1022 | ch->ch_tun.un_flags |= (UN_EMPTY); |
| 1023 | } |
| 1024 | writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1025 | ch->ch_w_tail++; |
| 1026 | ch->ch_w_tail &= WQUEUEMASK; |
| 1027 | ch->ch_txcount++; |
| 1028 | len_written++; |
| 1029 | n--; |
| 1030 | } |
| 1031 | |
| 1032 | if (len_written > 0) |
| 1033 | ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); |
| 1034 | |
Quentin Lambert | f6a14cf | 2015-03-11 15:22:00 +0100 | [diff] [blame] | 1035 | exit_unlock: |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 1036 | spin_unlock_irqrestore(&ch->ch_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1037 | } |
| 1038 | |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 1039 | static void cls_parse_modem(struct channel_t *ch, unsigned char signals) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1040 | { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 1041 | unsigned char msignals = signals; |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 1042 | unsigned long flags; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1043 | |
| 1044 | if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) |
| 1045 | return; |
| 1046 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1047 | /* |
| 1048 | * Do altpin switching. Altpin switches DCD and DSR. |
| 1049 | * This prolly breaks DSRPACE, so we should be more clever here. |
| 1050 | */ |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 1051 | spin_lock_irqsave(&ch->ch_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1052 | if (ch->ch_digi.digi_flags & DIGI_ALTPIN) { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 1053 | unsigned char mswap = signals; |
Konrad Zapalowicz | 8aa5d0d | 2014-08-06 22:17:09 +0200 | [diff] [blame] | 1054 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1055 | if (mswap & UART_MSR_DDCD) { |
| 1056 | msignals &= ~UART_MSR_DDCD; |
| 1057 | msignals |= UART_MSR_DDSR; |
| 1058 | } |
| 1059 | if (mswap & UART_MSR_DDSR) { |
| 1060 | msignals &= ~UART_MSR_DDSR; |
| 1061 | msignals |= UART_MSR_DDCD; |
| 1062 | } |
| 1063 | if (mswap & UART_MSR_DCD) { |
| 1064 | msignals &= ~UART_MSR_DCD; |
| 1065 | msignals |= UART_MSR_DSR; |
| 1066 | } |
| 1067 | if (mswap & UART_MSR_DSR) { |
| 1068 | msignals &= ~UART_MSR_DSR; |
| 1069 | msignals |= UART_MSR_DCD; |
| 1070 | } |
| 1071 | } |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 1072 | spin_unlock_irqrestore(&ch->ch_lock, flags); |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 1073 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 1074 | /* |
| 1075 | * Scrub off lower bits. They signify delta's, which I don't |
| 1076 | * care about |
| 1077 | */ |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1078 | signals &= 0xf0; |
| 1079 | |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 1080 | spin_lock_irqsave(&ch->ch_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1081 | if (msignals & UART_MSR_DCD) |
| 1082 | ch->ch_mistat |= UART_MSR_DCD; |
| 1083 | else |
| 1084 | ch->ch_mistat &= ~UART_MSR_DCD; |
| 1085 | |
| 1086 | if (msignals & UART_MSR_DSR) |
| 1087 | ch->ch_mistat |= UART_MSR_DSR; |
| 1088 | else |
| 1089 | ch->ch_mistat &= ~UART_MSR_DSR; |
| 1090 | |
| 1091 | if (msignals & UART_MSR_RI) |
| 1092 | ch->ch_mistat |= UART_MSR_RI; |
| 1093 | else |
| 1094 | ch->ch_mistat &= ~UART_MSR_RI; |
| 1095 | |
| 1096 | if (msignals & UART_MSR_CTS) |
| 1097 | ch->ch_mistat |= UART_MSR_CTS; |
| 1098 | else |
| 1099 | ch->ch_mistat &= ~UART_MSR_CTS; |
Roberta Dobrescu | 707505b | 2014-09-23 01:55:55 +0300 | [diff] [blame] | 1100 | spin_unlock_irqrestore(&ch->ch_lock, flags); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1101 | } |
| 1102 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1103 | /* Make the UART raise any of the output signals we want up */ |
| 1104 | static void cls_assert_modem_signals(struct channel_t *ch) |
| 1105 | { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 1106 | unsigned char out; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1107 | |
| 1108 | if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) |
| 1109 | return; |
| 1110 | |
| 1111 | out = ch->ch_mostat; |
| 1112 | |
| 1113 | if (ch->ch_flags & CH_LOOPBACK) |
| 1114 | out |= UART_MCR_LOOP; |
| 1115 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 1116 | writeb(out, &ch->ch_cls_uart->mcr); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1117 | |
| 1118 | /* Give time for the UART to actually drop the signals */ |
| 1119 | udelay(10); |
| 1120 | } |
| 1121 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1122 | static void cls_send_start_character(struct channel_t *ch) |
| 1123 | { |
| 1124 | if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) |
| 1125 | return; |
| 1126 | |
| 1127 | if (ch->ch_startc != _POSIX_VDISABLE) { |
| 1128 | ch->ch_xon_sends++; |
| 1129 | writeb(ch->ch_startc, &ch->ch_cls_uart->txrx); |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 1130 | } |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1131 | } |
| 1132 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1133 | static void cls_send_stop_character(struct channel_t *ch) |
| 1134 | { |
| 1135 | if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) |
| 1136 | return; |
| 1137 | |
| 1138 | if (ch->ch_stopc != _POSIX_VDISABLE) { |
| 1139 | ch->ch_xoff_sends++; |
| 1140 | writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx); |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 1141 | } |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1142 | } |
| 1143 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1144 | /* Inits UART */ |
| 1145 | static void cls_uart_init(struct channel_t *ch) |
| 1146 | { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 1147 | unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); |
| 1148 | unsigned char isr_fcr = 0; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1149 | |
| 1150 | writeb(0, &ch->ch_cls_uart->ier); |
| 1151 | |
| 1152 | /* |
| 1153 | * The Enhanced Register Set may only be accessed when |
| 1154 | * the Line Control Register is set to 0xBFh. |
| 1155 | */ |
| 1156 | writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); |
| 1157 | |
| 1158 | isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); |
Lidza Louina | 5ca46fd | 2013-08-21 11:08:00 -0400 | [diff] [blame] | 1159 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1160 | /* Turn on Enhanced/Extended controls */ |
| 1161 | isr_fcr |= (UART_EXAR654_EFR_ECB); |
| 1162 | |
| 1163 | writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); |
| 1164 | |
| 1165 | /* Write old LCR value back out, which turns enhanced access off */ |
| 1166 | writeb(lcrb, &ch->ch_cls_uart->lcr); |
| 1167 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 1168 | /* Clear out UART and FIFO */ |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1169 | readb(&ch->ch_cls_uart->txrx); |
| 1170 | |
Daeseok Youn | ea753f2 | 2016-04-04 18:52:03 +0900 | [diff] [blame] | 1171 | writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, |
Sudip Mukherjee | e352d3f | 2015-10-04 19:50:14 +0530 | [diff] [blame] | 1172 | &ch->ch_cls_uart->isr_fcr); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1173 | udelay(10); |
| 1174 | |
| 1175 | ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); |
| 1176 | |
| 1177 | readb(&ch->ch_cls_uart->lsr); |
| 1178 | readb(&ch->ch_cls_uart->msr); |
| 1179 | } |
| 1180 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1181 | /* |
| 1182 | * Turns off UART. |
| 1183 | */ |
| 1184 | static void cls_uart_off(struct channel_t *ch) |
| 1185 | { |
| 1186 | writeb(0, &ch->ch_cls_uart->ier); |
| 1187 | } |
| 1188 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1189 | /* |
| 1190 | * cls_get_uarts_bytes_left. |
| 1191 | * Returns 0 is nothing left in the FIFO, returns 1 otherwise. |
| 1192 | * |
| 1193 | * The channel lock MUST be held by the calling function. |
| 1194 | */ |
| 1195 | static uint cls_get_uart_bytes_left(struct channel_t *ch) |
| 1196 | { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 1197 | unsigned char left = 0; |
| 1198 | unsigned char lsr = 0; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1199 | |
| 1200 | if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) |
| 1201 | return 0; |
| 1202 | |
| 1203 | lsr = readb(&ch->ch_cls_uart->lsr); |
| 1204 | |
| 1205 | /* Determine whether the Transmitter is empty or not */ |
| 1206 | if (!(lsr & UART_LSR_TEMT)) { |
Archana kumari | 3d47910 | 2013-10-17 18:45:16 +0530 | [diff] [blame] | 1207 | if (ch->ch_flags & CH_TX_FIFO_EMPTY) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1208 | tasklet_schedule(&ch->ch_bd->helper_tasklet); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1209 | left = 1; |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 1210 | } else { |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1211 | ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); |
| 1212 | left = 0; |
| 1213 | } |
| 1214 | |
| 1215 | return left; |
| 1216 | } |
| 1217 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1218 | /* |
| 1219 | * cls_send_break. |
| 1220 | * Starts sending a break thru the UART. |
| 1221 | * |
| 1222 | * The channel lock MUST be held by the calling function. |
| 1223 | */ |
| 1224 | static void cls_send_break(struct channel_t *ch, int msecs) |
| 1225 | { |
| 1226 | if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) |
| 1227 | return; |
| 1228 | |
| 1229 | /* |
| 1230 | * If we receive a time of 0, this means turn off the break. |
| 1231 | */ |
| 1232 | if (msecs == 0) { |
| 1233 | /* Turn break off, and unset some variables */ |
| 1234 | if (ch->ch_flags & CH_BREAK_SENDING) { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 1235 | unsigned char temp = readb(&ch->ch_cls_uart->lcr); |
Konrad Zapalowicz | 8aa5d0d | 2014-08-06 22:17:09 +0200 | [diff] [blame] | 1236 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1237 | writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr); |
| 1238 | ch->ch_flags &= ~(CH_BREAK_SENDING); |
| 1239 | ch->ch_stop_sending_break = 0; |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1240 | } |
| 1241 | return; |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 1242 | } |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1243 | |
| 1244 | /* |
| 1245 | * Set the time we should stop sending the break. |
| 1246 | * If we are already sending a break, toss away the existing |
| 1247 | * time to stop, and use this new value instead. |
| 1248 | */ |
| 1249 | ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs); |
| 1250 | |
| 1251 | /* Tell the UART to start sending the break */ |
| 1252 | if (!(ch->ch_flags & CH_BREAK_SENDING)) { |
Ebru Akagunduz | 446393e | 2014-10-01 23:04:48 +0300 | [diff] [blame] | 1253 | unsigned char temp = readb(&ch->ch_cls_uart->lcr); |
Konrad Zapalowicz | 8aa5d0d | 2014-08-06 22:17:09 +0200 | [diff] [blame] | 1254 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1255 | writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr); |
| 1256 | ch->ch_flags |= (CH_BREAK_SENDING); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1257 | } |
| 1258 | } |
| 1259 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1260 | /* |
| 1261 | * cls_send_immediate_char. |
| 1262 | * Sends a specific character as soon as possible to the UART, |
| 1263 | * jumping over any bytes that might be in the write queue. |
| 1264 | * |
| 1265 | * The channel lock MUST be held by the calling function. |
| 1266 | */ |
| 1267 | static void cls_send_immediate_char(struct channel_t *ch, unsigned char c) |
| 1268 | { |
| 1269 | if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) |
| 1270 | return; |
| 1271 | |
| 1272 | writeb(c, &ch->ch_cls_uart->txrx); |
| 1273 | } |
| 1274 | |
Lidza Louina | 03425f5 | 2013-09-09 15:01:22 -0400 | [diff] [blame] | 1275 | static void cls_vpd(struct dgnc_board *brd) |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1276 | { |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 1277 | ulong vpdbase; /* Start of io base of the card */ |
| 1278 | u8 __iomem *re_map_vpdbase;/* Remapped memory of the card */ |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1279 | int i = 0; |
| 1280 | |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1281 | vpdbase = pci_resource_start(brd->pdev, 3); |
| 1282 | |
| 1283 | /* No VPD */ |
| 1284 | if (!vpdbase) |
| 1285 | return; |
| 1286 | |
| 1287 | re_map_vpdbase = ioremap(vpdbase, 0x400); |
| 1288 | |
| 1289 | if (!re_map_vpdbase) |
| 1290 | return; |
| 1291 | |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 1292 | /* Store the VPD into our buffer */ |
| 1293 | for (i = 0; i < 0x40; i++) { |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1294 | brd->vpd[i] = readb(re_map_vpdbase + i); |
stalinsrinivasan.s | cb3714a | 2013-12-20 22:03:25 +0530 | [diff] [blame] | 1295 | pr_info("%x ", brd->vpd[i]); |
| 1296 | } |
| 1297 | pr_info("\n"); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1298 | |
Sudip Mukherjee | e24bb0e | 2015-10-03 20:52:46 +0530 | [diff] [blame] | 1299 | iounmap(re_map_vpdbase); |
Lidza Louina | 0b99d58 | 2013-08-01 17:00:20 -0400 | [diff] [blame] | 1300 | } |