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gerrit-public.fairphone.software / kernel / msm-4.9 / ad83665b4687f5a4456009487af1ea640b9b1b1b / . / drivers / i2c / busses / i2c-octeon-core.h
blob: 81c6a81cd308745b9452fb99a70125522d21118e [file] [log] [blame]
Jan Glauberad836652016-08-24 23:25:43 +0200[diff] [blame^]1#include <linux/atomic.h>
2#include <linux/clk.h>
3#include <linux/delay.h>
4#include <linux/device.h>
5#include <linux/i2c.h>
6#include <linux/io.h>
7#include <linux/kernel.h>
8#include <linux/pci.h>
9
10/* Register offsets */
11#define SW_TWSI 0x00
12#define TWSI_INT 0x10
13#define SW_TWSI_EXT 0x18
14
15/* Controller command patterns */
16#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
17#define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */
18#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
19#define SW_TWSI_SOVR BIT_ULL(55) /* Size override */
20#define SW_TWSI_SIZE_SHIFT 52
21#define SW_TWSI_ADDR_SHIFT 40
22#define SW_TWSI_IA_SHIFT 32 /* Internal address */
23
24/* Controller opcode word (bits 60:57) */
25#define SW_TWSI_OP_SHIFT 57
26#define SW_TWSI_OP_7 (0ULL << SW_TWSI_OP_SHIFT)
27#define SW_TWSI_OP_7_IA (1ULL << SW_TWSI_OP_SHIFT)
28#define SW_TWSI_OP_10 (2ULL << SW_TWSI_OP_SHIFT)
29#define SW_TWSI_OP_10_IA (3ULL << SW_TWSI_OP_SHIFT)
30#define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
31#define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
32
33/* Controller extended opcode word (bits 34:32) */
34#define SW_TWSI_EOP_SHIFT 32
35#define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
36#define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
37#define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
38#define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
39#define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
40
41/* Controller command and status bits */
42#define TWSI_CTL_CE 0x80 /* High level controller enable */
43#define TWSI_CTL_ENAB 0x40 /* Bus enable */
44#define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
45#define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
46#define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
47#define TWSI_CTL_AAK 0x04 /* Assert ACK */
48
49/* Status values */
50#define STAT_ERROR 0x00
51#define STAT_START 0x08
52#define STAT_REP_START 0x10
53#define STAT_TXADDR_ACK 0x18
54#define STAT_TXADDR_NAK 0x20
55#define STAT_TXDATA_ACK 0x28
56#define STAT_TXDATA_NAK 0x30
57#define STAT_LOST_ARB_38 0x38
58#define STAT_RXADDR_ACK 0x40
59#define STAT_RXADDR_NAK 0x48
60#define STAT_RXDATA_ACK 0x50
61#define STAT_RXDATA_NAK 0x58
62#define STAT_SLAVE_60 0x60
63#define STAT_LOST_ARB_68 0x68
64#define STAT_SLAVE_70 0x70
65#define STAT_LOST_ARB_78 0x78
66#define STAT_SLAVE_80 0x80
67#define STAT_SLAVE_88 0x88
68#define STAT_GENDATA_ACK 0x90
69#define STAT_GENDATA_NAK 0x98
70#define STAT_SLAVE_A0 0xA0
71#define STAT_SLAVE_A8 0xA8
72#define STAT_LOST_ARB_B0 0xB0
73#define STAT_SLAVE_LOST 0xB8
74#define STAT_SLAVE_NAK 0xC0
75#define STAT_SLAVE_ACK 0xC8
76#define STAT_AD2W_ACK 0xD0
77#define STAT_AD2W_NAK 0xD8
78#define STAT_IDLE 0xF8
79
80/* TWSI_INT values */
81#define TWSI_INT_ST_INT BIT_ULL(0)
82#define TWSI_INT_TS_INT BIT_ULL(1)
83#define TWSI_INT_CORE_INT BIT_ULL(2)
84#define TWSI_INT_ST_EN BIT_ULL(4)
85#define TWSI_INT_TS_EN BIT_ULL(5)
86#define TWSI_INT_CORE_EN BIT_ULL(6)
87#define TWSI_INT_SDA_OVR BIT_ULL(8)
88#define TWSI_INT_SCL_OVR BIT_ULL(9)
89#define TWSI_INT_SDA BIT_ULL(10)
90#define TWSI_INT_SCL BIT_ULL(11)
91
92#define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */
93
94struct octeon_i2c {
95 wait_queue_head_t queue;
96 struct i2c_adapter adap;
97 int irq;
98 int hlc_irq; /* For cn7890 only */
99 u32 twsi_freq;
100 int sys_freq;
101 void __iomem *twsi_base;
102 struct device *dev;
103 bool hlc_enabled;
104 bool broken_irq_mode;
105 bool broken_irq_check;
106 void (*int_enable)(struct octeon_i2c *);
107 void (*int_disable)(struct octeon_i2c *);
108 void (*hlc_int_enable)(struct octeon_i2c *);
109 void (*hlc_int_disable)(struct octeon_i2c *);
110 atomic_t int_enable_cnt;
111 atomic_t hlc_int_enable_cnt;
112};
113
114static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
115{
116 __raw_writeq(val, addr);
117 __raw_readq(addr); /* wait for write to land */
118}
119
120/**
121 * octeon_i2c_reg_write - write an I2C core register
122 * @i2c: The struct octeon_i2c
123 * @eop_reg: Register selector
124 * @data: Value to be written
125 *
126 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
127 */
128static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
129{
130 u64 tmp;
131
132 __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
133 do {
134 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
135 } while ((tmp & SW_TWSI_V) != 0);
136}
137
138#define octeon_i2c_ctl_write(i2c, val) \
139 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val)
140#define octeon_i2c_data_write(i2c, val) \
141 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val)
142
143/**
144 * octeon_i2c_reg_read - read lower bits of an I2C core register
145 * @i2c: The struct octeon_i2c
146 * @eop_reg: Register selector
147 *
148 * Returns the data.
149 *
150 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
151 */
152static inline u8 octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg)
153{
154 u64 tmp;
155
156 __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
157 do {
158 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
159 } while ((tmp & SW_TWSI_V) != 0);
160
161 return tmp & 0xFF;
162}
163
164#define octeon_i2c_ctl_read(i2c) \
165 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL)
166#define octeon_i2c_data_read(i2c) \
167 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA)
168#define octeon_i2c_stat_read(i2c) \
169 octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT)
170
171/**
172 * octeon_i2c_read_int - read the TWSI_INT register
173 * @i2c: The struct octeon_i2c
174 *
175 * Returns the value of the register.
176 */
177static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c)
178{
179 return __raw_readq(i2c->twsi_base + TWSI_INT);
180}
181
182/**
183 * octeon_i2c_write_int - write the TWSI_INT register
184 * @i2c: The struct octeon_i2c
185 * @data: Value to be written
186 */
187static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
188{
189 octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT);
190}
191
192/* Prototypes */
193irqreturn_t octeon_i2c_isr(int irq, void *dev_id);
194int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
195int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c);
196void octeon_i2c_set_clock(struct octeon_i2c *i2c);
197extern struct i2c_bus_recovery_info octeon_i2c_recovery_info;