Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 1 | /* |
| 2 | * cxd2099.c: Driver for the CXD2099AR Common Interface Controller |
| 3 | * |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 4 | * Copyright (C) 2010-2011 Digital Devices GmbH |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 5 | * |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License |
| 9 | * version 2 only, as published by the Free Software Foundation. |
| 10 | * |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
| 21 | * 02110-1301, USA |
| 22 | * Or, point your browser to http://www.gnu.org/copyleft/gpl.html |
| 23 | */ |
| 24 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 25 | #include <linux/slab.h> |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/moduleparam.h> |
| 29 | #include <linux/init.h> |
| 30 | #include <linux/i2c.h> |
| 31 | #include <linux/wait.h> |
| 32 | #include <linux/delay.h> |
| 33 | #include <linux/mutex.h> |
| 34 | #include <linux/io.h> |
| 35 | |
| 36 | #include "cxd2099.h" |
| 37 | |
| 38 | #define MAX_BUFFER_SIZE 248 |
| 39 | |
| 40 | struct cxd { |
| 41 | struct dvb_ca_en50221 en; |
| 42 | |
| 43 | struct i2c_adapter *i2c; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 44 | struct cxd2099_cfg cfg; |
| 45 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 46 | u8 regs[0x23]; |
| 47 | u8 lastaddress; |
| 48 | u8 clk_reg_f; |
| 49 | u8 clk_reg_b; |
| 50 | int mode; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 51 | int ready; |
| 52 | int dr; |
| 53 | int slot_stat; |
| 54 | |
| 55 | u8 amem[1024]; |
| 56 | int amem_read; |
| 57 | |
| 58 | int cammode; |
| 59 | struct mutex lock; |
| 60 | }; |
| 61 | |
| 62 | static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr, |
| 63 | u8 reg, u8 data) |
| 64 | { |
| 65 | u8 m[2] = {reg, data}; |
| 66 | struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2}; |
| 67 | |
| 68 | if (i2c_transfer(adapter, &msg, 1) != 1) { |
| 69 | printk(KERN_ERR "Failed to write to I2C register %02x@%02x!\n", |
| 70 | reg, adr); |
| 71 | return -1; |
| 72 | } |
| 73 | return 0; |
| 74 | } |
| 75 | |
| 76 | static int i2c_write(struct i2c_adapter *adapter, u8 adr, |
| 77 | u8 *data, u8 len) |
| 78 | { |
| 79 | struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len}; |
| 80 | |
| 81 | if (i2c_transfer(adapter, &msg, 1) != 1) { |
| 82 | printk(KERN_ERR "Failed to write to I2C!\n"); |
| 83 | return -1; |
| 84 | } |
| 85 | return 0; |
| 86 | } |
| 87 | |
| 88 | static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, |
| 89 | u8 reg, u8 *val) |
| 90 | { |
| 91 | struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 92 | .buf = ®, .len = 1}, |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 93 | {.addr = adr, .flags = I2C_M_RD, |
Oliver Endriss | 9daf9bc | 2011-07-03 14:02:24 -0300 | [diff] [blame] | 94 | .buf = val, .len = 1} }; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 95 | |
| 96 | if (i2c_transfer(adapter, msgs, 2) != 2) { |
| 97 | printk(KERN_ERR "error in i2c_read_reg\n"); |
| 98 | return -1; |
| 99 | } |
| 100 | return 0; |
| 101 | } |
| 102 | |
| 103 | static int i2c_read(struct i2c_adapter *adapter, u8 adr, |
| 104 | u8 reg, u8 *data, u8 n) |
| 105 | { |
| 106 | struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 107 | .buf = ®, .len = 1}, |
| 108 | {.addr = adr, .flags = I2C_M_RD, |
Oliver Endriss | 9daf9bc | 2011-07-03 14:02:24 -0300 | [diff] [blame] | 109 | .buf = data, .len = n} }; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 110 | |
| 111 | if (i2c_transfer(adapter, msgs, 2) != 2) { |
| 112 | printk(KERN_ERR "error in i2c_read\n"); |
| 113 | return -1; |
| 114 | } |
| 115 | return 0; |
| 116 | } |
| 117 | |
| 118 | static int read_block(struct cxd *ci, u8 adr, u8 *data, u8 n) |
| 119 | { |
| 120 | int status; |
| 121 | |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 122 | status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 123 | if (!status) { |
| 124 | ci->lastaddress = adr; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 125 | status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, n); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 126 | } |
| 127 | return status; |
| 128 | } |
| 129 | |
| 130 | static int read_reg(struct cxd *ci, u8 reg, u8 *val) |
| 131 | { |
| 132 | return read_block(ci, reg, val, 1); |
| 133 | } |
| 134 | |
| 135 | |
| 136 | static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n) |
| 137 | { |
| 138 | int status; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 139 | u8 addr[3] = {2, address & 0xff, address >> 8}; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 140 | |
Oliver Endriss | 9daf9bc | 2011-07-03 14:02:24 -0300 | [diff] [blame] | 141 | status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 142 | if (!status) |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 143 | status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 144 | return status; |
| 145 | } |
| 146 | |
| 147 | static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n) |
| 148 | { |
| 149 | int status; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 150 | u8 addr[3] = {2, address & 0xff, address >> 8}; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 151 | |
Oliver Endriss | 9daf9bc | 2011-07-03 14:02:24 -0300 | [diff] [blame] | 152 | status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 153 | if (!status) { |
| 154 | u8 buf[256] = {3}; |
| 155 | memcpy(buf+1, data, n); |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 156 | status = i2c_write(ci->i2c, ci->cfg.adr, buf, n+1); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 157 | } |
| 158 | return status; |
| 159 | } |
| 160 | |
| 161 | static int read_io(struct cxd *ci, u16 address, u8 *val) |
| 162 | { |
| 163 | int status; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 164 | u8 addr[3] = {2, address & 0xff, address >> 8}; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 165 | |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 166 | status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 167 | if (!status) |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 168 | status = i2c_read(ci->i2c, ci->cfg.adr, 3, val, 1); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 169 | return status; |
| 170 | } |
| 171 | |
| 172 | static int write_io(struct cxd *ci, u16 address, u8 val) |
| 173 | { |
| 174 | int status; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 175 | u8 addr[3] = {2, address & 0xff, address >> 8}; |
| 176 | u8 buf[2] = {3, val}; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 177 | |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 178 | status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 179 | if (!status) |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 180 | status = i2c_write(ci->i2c, ci->cfg.adr, buf, 2); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 181 | return status; |
| 182 | } |
| 183 | |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 184 | #if 0 |
| 185 | static int read_io_data(struct cxd *ci, u8 *data, u8 n) |
| 186 | { |
| 187 | int status; |
| 188 | u8 addr[3] = { 2, 0, 0 }; |
| 189 | |
| 190 | status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); |
| 191 | if (!status) |
| 192 | status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n); |
| 193 | return 0; |
| 194 | } |
| 195 | |
| 196 | static int write_io_data(struct cxd *ci, u8 *data, u8 n) |
| 197 | { |
| 198 | int status; |
| 199 | u8 addr[3] = {2, 0, 0}; |
| 200 | |
| 201 | status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); |
| 202 | if (!status) { |
| 203 | u8 buf[256] = {3}; |
| 204 | memcpy(buf+1, data, n); |
| 205 | status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1); |
| 206 | } |
| 207 | return 0; |
| 208 | } |
| 209 | #endif |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 210 | |
| 211 | static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask) |
| 212 | { |
| 213 | int status; |
| 214 | |
Oliver Endriss | 9daf9bc | 2011-07-03 14:02:24 -0300 | [diff] [blame] | 215 | status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 216 | if (!status && reg >= 6 && reg <= 8 && mask != 0xff) |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 217 | status = i2c_read_reg(ci->i2c, ci->cfg.adr, 1, &ci->regs[reg]); |
| 218 | ci->regs[reg] = (ci->regs[reg] & (~mask)) | val; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 219 | if (!status) { |
| 220 | ci->lastaddress = reg; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 221 | status = i2c_write_reg(ci->i2c, ci->cfg.adr, 1, ci->regs[reg]); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 222 | } |
| 223 | if (reg == 0x20) |
| 224 | ci->regs[reg] &= 0x7f; |
| 225 | return status; |
| 226 | } |
| 227 | |
| 228 | static int write_reg(struct cxd *ci, u8 reg, u8 val) |
| 229 | { |
| 230 | return write_regm(ci, reg, val, 0xff); |
| 231 | } |
| 232 | |
| 233 | #ifdef BUFFER_MODE |
| 234 | static int write_block(struct cxd *ci, u8 adr, u8 *data, int n) |
| 235 | { |
| 236 | int status; |
| 237 | u8 buf[256] = {1}; |
| 238 | |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 239 | status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 240 | if (!status) { |
| 241 | ci->lastaddress = adr; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 242 | memcpy(buf + 1, data, n); |
| 243 | status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 244 | } |
| 245 | return status; |
| 246 | } |
| 247 | #endif |
| 248 | |
| 249 | static void set_mode(struct cxd *ci, int mode) |
| 250 | { |
| 251 | if (mode == ci->mode) |
| 252 | return; |
| 253 | |
| 254 | switch (mode) { |
| 255 | case 0x00: /* IO mem */ |
| 256 | write_regm(ci, 0x06, 0x00, 0x07); |
| 257 | break; |
| 258 | case 0x01: /* ATT mem */ |
| 259 | write_regm(ci, 0x06, 0x02, 0x07); |
| 260 | break; |
| 261 | default: |
| 262 | break; |
| 263 | } |
| 264 | ci->mode = mode; |
| 265 | } |
| 266 | |
| 267 | static void cam_mode(struct cxd *ci, int mode) |
| 268 | { |
| 269 | if (mode == ci->cammode) |
| 270 | return; |
| 271 | |
| 272 | switch (mode) { |
| 273 | case 0x00: |
| 274 | write_regm(ci, 0x20, 0x80, 0x80); |
| 275 | break; |
| 276 | case 0x01: |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 277 | #ifdef BUFFER_MODE |
| 278 | if (!ci->en.read_data) |
| 279 | return; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 280 | printk(KERN_INFO "enable cam buffer mode\n"); |
| 281 | /* write_reg(ci, 0x0d, 0x00); */ |
| 282 | /* write_reg(ci, 0x0e, 0x01); */ |
| 283 | write_regm(ci, 0x08, 0x40, 0x40); |
| 284 | /* read_reg(ci, 0x12, &dummy); */ |
| 285 | write_regm(ci, 0x08, 0x80, 0x80); |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 286 | #endif |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 287 | break; |
| 288 | default: |
| 289 | break; |
| 290 | } |
| 291 | ci->cammode = mode; |
| 292 | } |
| 293 | |
| 294 | |
| 295 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 296 | static int init(struct cxd *ci) |
| 297 | { |
| 298 | int status; |
| 299 | |
| 300 | mutex_lock(&ci->lock); |
| 301 | ci->mode = -1; |
| 302 | do { |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 303 | status = write_reg(ci, 0x00, 0x00); |
| 304 | if (status < 0) |
| 305 | break; |
| 306 | status = write_reg(ci, 0x01, 0x00); |
| 307 | if (status < 0) |
| 308 | break; |
| 309 | status = write_reg(ci, 0x02, 0x10); |
| 310 | if (status < 0) |
| 311 | break; |
| 312 | status = write_reg(ci, 0x03, 0x00); |
| 313 | if (status < 0) |
| 314 | break; |
| 315 | status = write_reg(ci, 0x05, 0xFF); |
| 316 | if (status < 0) |
| 317 | break; |
| 318 | status = write_reg(ci, 0x06, 0x1F); |
| 319 | if (status < 0) |
| 320 | break; |
| 321 | status = write_reg(ci, 0x07, 0x1F); |
| 322 | if (status < 0) |
| 323 | break; |
| 324 | status = write_reg(ci, 0x08, 0x28); |
| 325 | if (status < 0) |
| 326 | break; |
| 327 | status = write_reg(ci, 0x14, 0x20); |
| 328 | if (status < 0) |
| 329 | break; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 330 | |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 331 | #if 0 |
| 332 | status = write_reg(ci, 0x09, 0x4D); /* Input Mode C, BYPass Serial, TIVAL = low, MSB */ |
| 333 | if (status < 0) |
| 334 | break; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 335 | #endif |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 336 | status = write_reg(ci, 0x0A, 0xA7); /* TOSTRT = 8, Mode B (gated clock), falling Edge, Serial, POL=HIGH, MSB */ |
| 337 | if (status < 0) |
| 338 | break; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 339 | |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 340 | status = write_reg(ci, 0x0B, 0x33); |
| 341 | if (status < 0) |
| 342 | break; |
| 343 | status = write_reg(ci, 0x0C, 0x33); |
| 344 | if (status < 0) |
| 345 | break; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 346 | |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 347 | status = write_regm(ci, 0x14, 0x00, 0x0F); |
| 348 | if (status < 0) |
| 349 | break; |
| 350 | status = write_reg(ci, 0x15, ci->clk_reg_b); |
| 351 | if (status < 0) |
| 352 | break; |
| 353 | status = write_regm(ci, 0x16, 0x00, 0x0F); |
| 354 | if (status < 0) |
| 355 | break; |
| 356 | status = write_reg(ci, 0x17, ci->clk_reg_f); |
| 357 | if (status < 0) |
| 358 | break; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 359 | |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 360 | if (ci->cfg.clock_mode) { |
| 361 | if (ci->cfg.polarity) { |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 362 | status = write_reg(ci, 0x09, 0x6f); |
| 363 | if (status < 0) |
| 364 | break; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 365 | } else { |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 366 | status = write_reg(ci, 0x09, 0x6d); |
| 367 | if (status < 0) |
| 368 | break; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 369 | } |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 370 | status = write_reg(ci, 0x20, 0x68); |
| 371 | if (status < 0) |
| 372 | break; |
| 373 | status = write_reg(ci, 0x21, 0x00); |
| 374 | if (status < 0) |
| 375 | break; |
| 376 | status = write_reg(ci, 0x22, 0x02); |
| 377 | if (status < 0) |
| 378 | break; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 379 | } else { |
| 380 | if (ci->cfg.polarity) { |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 381 | status = write_reg(ci, 0x09, 0x4f); |
| 382 | if (status < 0) |
| 383 | break; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 384 | } else { |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 385 | status = write_reg(ci, 0x09, 0x4d); |
| 386 | if (status < 0) |
| 387 | break; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 388 | } |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 389 | |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 390 | status = write_reg(ci, 0x20, 0x28); |
| 391 | if (status < 0) |
| 392 | break; |
| 393 | status = write_reg(ci, 0x21, 0x00); |
| 394 | if (status < 0) |
| 395 | break; |
| 396 | status = write_reg(ci, 0x22, 0x07); |
| 397 | if (status < 0) |
| 398 | break; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 399 | } |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 400 | |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 401 | status = write_regm(ci, 0x20, 0x80, 0x80); |
| 402 | if (status < 0) |
| 403 | break; |
| 404 | status = write_regm(ci, 0x03, 0x02, 0x02); |
| 405 | if (status < 0) |
| 406 | break; |
| 407 | status = write_reg(ci, 0x01, 0x04); |
| 408 | if (status < 0) |
| 409 | break; |
| 410 | status = write_reg(ci, 0x00, 0x31); |
| 411 | if (status < 0) |
| 412 | break; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 413 | |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 414 | /* Put TS in bypass */ |
Mauro Carvalho Chehab | af070bd | 2011-07-03 18:45:37 -0300 | [diff] [blame] | 415 | status = write_regm(ci, 0x09, 0x08, 0x08); |
| 416 | if (status < 0) |
| 417 | break; |
Oliver Endriss | 9daf9bc | 2011-07-03 14:02:24 -0300 | [diff] [blame] | 418 | ci->cammode = -1; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 419 | cam_mode(ci, 0); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 420 | } while (0); |
| 421 | mutex_unlock(&ci->lock); |
| 422 | |
| 423 | return 0; |
| 424 | } |
| 425 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 426 | static int read_attribute_mem(struct dvb_ca_en50221 *ca, |
| 427 | int slot, int address) |
| 428 | { |
| 429 | struct cxd *ci = ca->data; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 430 | #if 0 |
| 431 | if (ci->amem_read) { |
Oliver Endriss | 9daf9bc | 2011-07-03 14:02:24 -0300 | [diff] [blame] | 432 | if (address <= 0 || address > 1024) |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 433 | return -EIO; |
| 434 | return ci->amem[address]; |
| 435 | } |
| 436 | |
| 437 | mutex_lock(&ci->lock); |
| 438 | write_regm(ci, 0x06, 0x00, 0x05); |
| 439 | read_pccard(ci, 0, &ci->amem[0], 128); |
| 440 | read_pccard(ci, 128, &ci->amem[0], 128); |
| 441 | read_pccard(ci, 256, &ci->amem[0], 128); |
| 442 | read_pccard(ci, 384, &ci->amem[0], 128); |
| 443 | write_regm(ci, 0x06, 0x05, 0x05); |
| 444 | mutex_unlock(&ci->lock); |
| 445 | return ci->amem[address]; |
| 446 | #else |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 447 | u8 val; |
| 448 | mutex_lock(&ci->lock); |
| 449 | set_mode(ci, 1); |
| 450 | read_pccard(ci, address, &val, 1); |
| 451 | mutex_unlock(&ci->lock); |
Oliver Endriss | 9daf9bc | 2011-07-03 14:02:24 -0300 | [diff] [blame] | 452 | /* printk(KERN_INFO "%02x:%02x\n", address,val); */ |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 453 | return val; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 454 | #endif |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 455 | } |
| 456 | |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 457 | static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, |
| 458 | int address, u8 value) |
| 459 | { |
| 460 | struct cxd *ci = ca->data; |
| 461 | |
| 462 | mutex_lock(&ci->lock); |
| 463 | set_mode(ci, 1); |
| 464 | write_pccard(ci, address, &value, 1); |
| 465 | mutex_unlock(&ci->lock); |
| 466 | return 0; |
| 467 | } |
| 468 | |
| 469 | static int read_cam_control(struct dvb_ca_en50221 *ca, |
| 470 | int slot, u8 address) |
| 471 | { |
| 472 | struct cxd *ci = ca->data; |
| 473 | u8 val; |
| 474 | |
| 475 | mutex_lock(&ci->lock); |
| 476 | set_mode(ci, 0); |
| 477 | read_io(ci, address, &val); |
| 478 | mutex_unlock(&ci->lock); |
| 479 | return val; |
| 480 | } |
| 481 | |
| 482 | static int write_cam_control(struct dvb_ca_en50221 *ca, int slot, |
| 483 | u8 address, u8 value) |
| 484 | { |
| 485 | struct cxd *ci = ca->data; |
| 486 | |
| 487 | mutex_lock(&ci->lock); |
| 488 | set_mode(ci, 0); |
| 489 | write_io(ci, address, value); |
| 490 | mutex_unlock(&ci->lock); |
| 491 | return 0; |
| 492 | } |
| 493 | |
| 494 | static int slot_reset(struct dvb_ca_en50221 *ca, int slot) |
| 495 | { |
| 496 | struct cxd *ci = ca->data; |
| 497 | |
| 498 | mutex_lock(&ci->lock); |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 499 | #if 0 |
| 500 | write_reg(ci, 0x00, 0x21); |
| 501 | write_reg(ci, 0x06, 0x1F); |
| 502 | write_reg(ci, 0x00, 0x31); |
| 503 | #else |
| 504 | #if 0 |
| 505 | write_reg(ci, 0x06, 0x1F); |
| 506 | write_reg(ci, 0x06, 0x2F); |
| 507 | #else |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 508 | cam_mode(ci, 0); |
| 509 | write_reg(ci, 0x00, 0x21); |
| 510 | write_reg(ci, 0x06, 0x1F); |
| 511 | write_reg(ci, 0x00, 0x31); |
| 512 | write_regm(ci, 0x20, 0x80, 0x80); |
| 513 | write_reg(ci, 0x03, 0x02); |
| 514 | ci->ready = 0; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 515 | #endif |
| 516 | #endif |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 517 | ci->mode = -1; |
| 518 | { |
| 519 | int i; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 520 | #if 0 |
| 521 | u8 val; |
| 522 | #endif |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 523 | for (i = 0; i < 100; i++) { |
| 524 | msleep(10); |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 525 | #if 0 |
Oliver Endriss | 9daf9bc | 2011-07-03 14:02:24 -0300 | [diff] [blame] | 526 | read_reg(ci, 0x06, &val); |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 527 | printk(KERN_INFO "%d:%02x\n", i, val); |
| 528 | if (!(val&0x10)) |
| 529 | break; |
| 530 | #else |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 531 | if (ci->ready) |
| 532 | break; |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 533 | #endif |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 534 | } |
| 535 | } |
| 536 | mutex_unlock(&ci->lock); |
| 537 | /* msleep(500); */ |
| 538 | return 0; |
| 539 | } |
| 540 | |
| 541 | static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot) |
| 542 | { |
| 543 | struct cxd *ci = ca->data; |
| 544 | |
| 545 | printk(KERN_INFO "slot_shutdown\n"); |
| 546 | mutex_lock(&ci->lock); |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 547 | write_regm(ci, 0x09, 0x08, 0x08); |
| 548 | write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */ |
| 549 | write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */ |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 550 | ci->mode = -1; |
| 551 | mutex_unlock(&ci->lock); |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 552 | return 0; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 553 | } |
| 554 | |
| 555 | static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot) |
| 556 | { |
| 557 | struct cxd *ci = ca->data; |
| 558 | |
| 559 | mutex_lock(&ci->lock); |
| 560 | write_regm(ci, 0x09, 0x00, 0x08); |
| 561 | set_mode(ci, 0); |
| 562 | #ifdef BUFFER_MODE |
| 563 | cam_mode(ci, 1); |
| 564 | #endif |
| 565 | mutex_unlock(&ci->lock); |
| 566 | return 0; |
| 567 | } |
| 568 | |
| 569 | |
| 570 | static int campoll(struct cxd *ci) |
| 571 | { |
| 572 | u8 istat; |
| 573 | |
| 574 | read_reg(ci, 0x04, &istat); |
| 575 | if (!istat) |
| 576 | return 0; |
| 577 | write_reg(ci, 0x05, istat); |
| 578 | |
| 579 | if (istat&0x40) { |
| 580 | ci->dr = 1; |
| 581 | printk(KERN_INFO "DR\n"); |
| 582 | } |
| 583 | if (istat&0x20) |
| 584 | printk(KERN_INFO "WC\n"); |
| 585 | |
| 586 | if (istat&2) { |
| 587 | u8 slotstat; |
| 588 | |
| 589 | read_reg(ci, 0x01, &slotstat); |
| 590 | if (!(2&slotstat)) { |
| 591 | if (!ci->slot_stat) { |
| 592 | ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_PRESENT; |
| 593 | write_regm(ci, 0x03, 0x08, 0x08); |
| 594 | } |
| 595 | |
| 596 | } else { |
| 597 | if (ci->slot_stat) { |
| 598 | ci->slot_stat = 0; |
| 599 | write_regm(ci, 0x03, 0x00, 0x08); |
| 600 | printk(KERN_INFO "NO CAM\n"); |
| 601 | ci->ready = 0; |
| 602 | } |
| 603 | } |
| 604 | if (istat&8 && ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) { |
| 605 | ci->ready = 1; |
| 606 | ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 607 | } |
| 608 | } |
| 609 | return 0; |
| 610 | } |
| 611 | |
| 612 | |
| 613 | static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open) |
| 614 | { |
| 615 | struct cxd *ci = ca->data; |
| 616 | u8 slotstat; |
| 617 | |
| 618 | mutex_lock(&ci->lock); |
| 619 | campoll(ci); |
| 620 | read_reg(ci, 0x01, &slotstat); |
| 621 | mutex_unlock(&ci->lock); |
| 622 | |
| 623 | return ci->slot_stat; |
| 624 | } |
| 625 | |
| 626 | #ifdef BUFFER_MODE |
| 627 | static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount) |
| 628 | { |
| 629 | struct cxd *ci = ca->data; |
| 630 | u8 msb, lsb; |
| 631 | u16 len; |
| 632 | |
| 633 | mutex_lock(&ci->lock); |
| 634 | campoll(ci); |
| 635 | mutex_unlock(&ci->lock); |
| 636 | |
| 637 | printk(KERN_INFO "read_data\n"); |
| 638 | if (!ci->dr) |
| 639 | return 0; |
| 640 | |
| 641 | mutex_lock(&ci->lock); |
| 642 | read_reg(ci, 0x0f, &msb); |
| 643 | read_reg(ci, 0x10, &lsb); |
| 644 | len = (msb<<8)|lsb; |
| 645 | read_block(ci, 0x12, ebuf, len); |
| 646 | ci->dr = 0; |
| 647 | mutex_unlock(&ci->lock); |
| 648 | |
| 649 | return len; |
| 650 | } |
| 651 | |
| 652 | static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount) |
| 653 | { |
| 654 | struct cxd *ci = ca->data; |
| 655 | |
| 656 | mutex_lock(&ci->lock); |
Oliver Endriss | 9daf9bc | 2011-07-03 14:02:24 -0300 | [diff] [blame] | 657 | printk(kern_INFO "write_data %d\n", ecount); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 658 | write_reg(ci, 0x0d, ecount>>8); |
| 659 | write_reg(ci, 0x0e, ecount&0xff); |
| 660 | write_block(ci, 0x11, ebuf, ecount); |
| 661 | mutex_unlock(&ci->lock); |
| 662 | return ecount; |
| 663 | } |
| 664 | #endif |
| 665 | |
| 666 | static struct dvb_ca_en50221 en_templ = { |
| 667 | .read_attribute_mem = read_attribute_mem, |
| 668 | .write_attribute_mem = write_attribute_mem, |
| 669 | .read_cam_control = read_cam_control, |
| 670 | .write_cam_control = write_cam_control, |
| 671 | .slot_reset = slot_reset, |
| 672 | .slot_shutdown = slot_shutdown, |
| 673 | .slot_ts_enable = slot_ts_enable, |
| 674 | .poll_slot_status = poll_slot_status, |
| 675 | #ifdef BUFFER_MODE |
| 676 | .read_data = read_data, |
| 677 | .write_data = write_data, |
| 678 | #endif |
| 679 | |
| 680 | }; |
| 681 | |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 682 | struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg, |
| 683 | void *priv, |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 684 | struct i2c_adapter *i2c) |
| 685 | { |
Devendra Naga | 4aff355 | 2012-08-04 14:12:03 -0300 | [diff] [blame] | 686 | struct cxd *ci; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 687 | u8 val; |
| 688 | |
Oliver Endriss | 9daf9bc | 2011-07-03 14:02:24 -0300 | [diff] [blame] | 689 | if (i2c_read_reg(i2c, cfg->adr, 0, &val) < 0) { |
| 690 | printk(KERN_INFO "No CXD2099 detected at %02x\n", cfg->adr); |
Devendra Naga | 4aff355 | 2012-08-04 14:12:03 -0300 | [diff] [blame] | 691 | return NULL; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 692 | } |
| 693 | |
Devendra Naga | ada3678 | 2012-08-04 14:12:21 -0300 | [diff] [blame^] | 694 | ci = kzalloc(sizeof(struct cxd), GFP_KERNEL); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 695 | if (!ci) |
Devendra Naga | 4aff355 | 2012-08-04 14:12:03 -0300 | [diff] [blame] | 696 | return NULL; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 697 | |
| 698 | mutex_init(&ci->lock); |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 699 | memcpy(&ci->cfg, cfg, sizeof(struct cxd2099_cfg)); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 700 | ci->i2c = i2c; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 701 | ci->lastaddress = 0xff; |
| 702 | ci->clk_reg_b = 0x4a; |
| 703 | ci->clk_reg_f = 0x1b; |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 704 | |
| 705 | memcpy(&ci->en, &en_templ, sizeof(en_templ)); |
| 706 | ci->en.data = ci; |
| 707 | init(ci); |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 708 | printk(KERN_INFO "Attached CXD2099AR at %02x\n", ci->cfg.adr); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 709 | return &ci->en; |
| 710 | } |
| 711 | EXPORT_SYMBOL(cxd2099_attach); |
| 712 | |
| 713 | MODULE_DESCRIPTION("cxd2099"); |
Ralph Metzler | 6eb9419 | 2011-07-03 14:00:57 -0300 | [diff] [blame] | 714 | MODULE_AUTHOR("Ralph Metzler"); |
Ralph Metzler | 0f0b270 | 2011-01-10 06:36:15 -0300 | [diff] [blame] | 715 | MODULE_LICENSE("GPL"); |