blob: 945887d3fdb35a6588155590474479901a45671f [file] [log] [blame]
Shawn Guo117ccd552013-05-03 11:28:42 +08001/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
Fabio Estevam33106702014-02-06 13:08:08 -020011#include <dt-bindings/gpio/gpio.h>
Anson Huang4291b642014-01-14 17:30:28 +080012#include <dt-bindings/input/input.h>
Shawn Guo117ccd552013-05-03 11:28:42 +080013#include "imx6sl.dtsi"
14
15/ {
16 model = "Freescale i.MX6 SoloLite EVK Board";
17 compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
18
19 memory {
20 reg = <0x80000000 0x40000000>;
21 };
Peter Chen60222322013-09-10 10:23:16 +080022
Fabio Estevame99b0772014-08-19 15:21:14 -030023 backlight {
24 compatible = "pwm-backlight";
25 pwms = <&pwm1 0 5000000>;
26 brightness-levels = <0 4 8 16 32 64 128 255>;
27 default-brightness-level = <6>;
28 };
29
Fabio Estevam33106702014-02-06 13:08:08 -020030 leds {
31 compatible = "gpio-leds";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_led>;
34
35 user {
36 label = "debug";
37 gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
38 linux,default-trigger = "heartbeat";
39 };
40 };
41
Peter Chen60222322013-09-10 10:23:16 +080042 regulators {
43 compatible = "simple-bus";
Shawn Guo56160e32014-02-07 23:22:50 +080044 #address-cells = <1>;
45 #size-cells = <0>;
Peter Chen60222322013-09-10 10:23:16 +080046
Shawn Guo56160e32014-02-07 23:22:50 +080047 reg_usb_otg1_vbus: regulator@0 {
Peter Chen60222322013-09-10 10:23:16 +080048 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080049 reg = <0>;
Peter Chen60222322013-09-10 10:23:16 +080050 regulator-name = "usb_otg1_vbus";
51 regulator-min-microvolt = <5000000>;
52 regulator-max-microvolt = <5000000>;
53 gpio = <&gpio4 0 0>;
54 enable-active-high;
Peter Chen2de9dd02015-03-06 16:04:21 +080055 vin-supply = <&swbst_reg>;
Peter Chen60222322013-09-10 10:23:16 +080056 };
57
Shawn Guo56160e32014-02-07 23:22:50 +080058 reg_usb_otg2_vbus: regulator@1 {
Peter Chen60222322013-09-10 10:23:16 +080059 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080060 reg = <1>;
Peter Chen60222322013-09-10 10:23:16 +080061 regulator-name = "usb_otg2_vbus";
62 regulator-min-microvolt = <5000000>;
63 regulator-max-microvolt = <5000000>;
64 gpio = <&gpio4 2 0>;
65 enable-active-high;
Peter Chen2de9dd02015-03-06 16:04:21 +080066 vin-supply = <&swbst_reg>;
Peter Chen60222322013-09-10 10:23:16 +080067 };
Fabio Estevam032de432014-02-06 08:57:51 -020068
69 reg_aud3v: regulator@2 {
70 compatible = "regulator-fixed";
71 reg = <2>;
72 regulator-name = "wm8962-supply-3v15";
73 regulator-min-microvolt = <3150000>;
74 regulator-max-microvolt = <3150000>;
75 regulator-boot-on;
76 };
77
78 reg_aud4v: regulator@3 {
79 compatible = "regulator-fixed";
80 reg = <3>;
81 regulator-name = "wm8962-supply-4v2";
82 regulator-min-microvolt = <4325000>;
83 regulator-max-microvolt = <4325000>;
84 regulator-boot-on;
85 };
Fabio Estevame99b0772014-08-19 15:21:14 -030086
87 reg_lcd_3v3: regulator@4 {
88 compatible = "regulator-fixed";
89 reg = <4>;
90 regulator-name = "lcd-3v3";
91 gpio = <&gpio4 3 0>;
92 enable-active-high;
93 };
Peter Chen60222322013-09-10 10:23:16 +080094 };
Fabio Estevam032de432014-02-06 08:57:51 -020095
96 sound {
97 compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
98 model = "wm8962-audio";
99 ssi-controller = <&ssi2>;
100 audio-codec = <&codec>;
101 audio-routing =
102 "Headphone Jack", "HPOUTL",
103 "Headphone Jack", "HPOUTR",
104 "Ext Spk", "SPKOUTL",
105 "Ext Spk", "SPKOUTR",
106 "AMIC", "MICBIAS",
107 "IN3R", "AMIC";
108 mux-int-port = <2>;
109 mux-ext-port = <3>;
110 };
111};
112
113&audmux {
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_audmux3>;
116 status = "okay";
Shawn Guo117ccd552013-05-03 11:28:42 +0800117};
118
Huang Shijied1b53972013-10-18 10:32:53 +0800119&ecspi1 {
120 fsl,spi-num-chipselects = <1>;
121 cs-gpios = <&gpio4 11 0>;
122 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +0800123 pinctrl-0 = <&pinctrl_ecspi1>;
Huang Shijied1b53972013-10-18 10:32:53 +0800124 status = "okay";
125
126 flash: m25p80@0 {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "st,m25p32";
130 spi-max-frequency = <20000000>;
131 reg = <0>;
132 };
133};
134
Shawn Guo117ccd552013-05-03 11:28:42 +0800135&fec {
Fugang Duan01d41c92014-05-20 14:50:44 +0800136 pinctrl-names = "default", "sleep";
Shawn Guofffaa652013-11-04 10:49:04 +0800137 pinctrl-0 = <&pinctrl_fec>;
Fugang Duan01d41c92014-05-20 14:50:44 +0800138 pinctrl-1 = <&pinctrl_fec_sleep>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800139 phy-mode = "rmii";
140 status = "okay";
141};
142
Fabio Estevam56df2682014-02-06 08:57:50 -0200143&i2c1 {
144 clock-frequency = <100000>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_i2c1>;
147 status = "okay";
148
149 pmic: pfuze100@08 {
150 compatible = "fsl,pfuze100";
151 reg = <0x08>;
152
153 regulators {
154 sw1a_reg: sw1ab {
155 regulator-min-microvolt = <300000>;
156 regulator-max-microvolt = <1875000>;
157 regulator-boot-on;
158 regulator-always-on;
159 regulator-ramp-delay = <6250>;
160 };
161
162 sw1c_reg: sw1c {
163 regulator-min-microvolt = <300000>;
164 regulator-max-microvolt = <1875000>;
165 regulator-boot-on;
166 regulator-always-on;
167 regulator-ramp-delay = <6250>;
168 };
169
170 sw2_reg: sw2 {
171 regulator-min-microvolt = <800000>;
172 regulator-max-microvolt = <3300000>;
173 regulator-boot-on;
174 regulator-always-on;
175 };
176
177 sw3a_reg: sw3a {
178 regulator-min-microvolt = <400000>;
179 regulator-max-microvolt = <1975000>;
180 regulator-boot-on;
181 regulator-always-on;
182 };
183
184 sw3b_reg: sw3b {
185 regulator-min-microvolt = <400000>;
186 regulator-max-microvolt = <1975000>;
187 regulator-boot-on;
188 regulator-always-on;
189 };
190
191 sw4_reg: sw4 {
192 regulator-min-microvolt = <800000>;
193 regulator-max-microvolt = <3300000>;
194 };
195
196 swbst_reg: swbst {
197 regulator-min-microvolt = <5000000>;
198 regulator-max-microvolt = <5150000>;
199 };
200
201 snvs_reg: vsnvs {
202 regulator-min-microvolt = <1000000>;
203 regulator-max-microvolt = <3000000>;
204 regulator-boot-on;
205 regulator-always-on;
206 };
207
208 vref_reg: vrefddr {
209 regulator-boot-on;
210 regulator-always-on;
211 };
212
213 vgen1_reg: vgen1 {
214 regulator-min-microvolt = <800000>;
215 regulator-max-microvolt = <1550000>;
Fabio Estevamd2c39362014-02-19 08:13:48 -0300216 regulator-always-on;
Fabio Estevam56df2682014-02-06 08:57:50 -0200217 };
218
219 vgen2_reg: vgen2 {
220 regulator-min-microvolt = <800000>;
221 regulator-max-microvolt = <1550000>;
222 };
223
224 vgen3_reg: vgen3 {
225 regulator-min-microvolt = <1800000>;
226 regulator-max-microvolt = <3300000>;
227 };
228
229 vgen4_reg: vgen4 {
230 regulator-min-microvolt = <1800000>;
231 regulator-max-microvolt = <3300000>;
232 regulator-always-on;
233 };
234
235 vgen5_reg: vgen5 {
236 regulator-min-microvolt = <1800000>;
237 regulator-max-microvolt = <3300000>;
238 regulator-always-on;
239 };
240
241 vgen6_reg: vgen6 {
242 regulator-min-microvolt = <1800000>;
243 regulator-max-microvolt = <3300000>;
244 regulator-always-on;
245 };
246 };
247 };
248};
249
Fabio Estevam032de432014-02-06 08:57:51 -0200250&i2c2 {
251 clock-frequency = <100000>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_i2c2>;
254 status = "okay";
255
256 codec: wm8962@1a {
257 compatible = "wlf,wm8962";
258 reg = <0x1a>;
259 clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
260 DCVDD-supply = <&vgen3_reg>;
261 DBVDD-supply = <&reg_aud3v>;
262 AVDD-supply = <&vgen3_reg>;
263 CPVDD-supply = <&vgen3_reg>;
264 MICVDD-supply = <&reg_aud3v>;
265 PLLVDD-supply = <&vgen3_reg>;
266 SPKVDD1-supply = <&reg_aud4v>;
267 SPKVDD2-supply = <&reg_aud4v>;
268 };
269};
270
Shawn Guo117ccd552013-05-03 11:28:42 +0800271&iomuxc {
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_hog>;
274
Shawn Guofffaa652013-11-04 10:49:04 +0800275 imx6sl-evk {
Shawn Guo117ccd552013-05-03 11:28:42 +0800276 pinctrl_hog: hoggrp {
277 fsl,pins = <
278 MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
279 MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
280 MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
281 MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
282 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
Peter Chen60222322013-09-10 10:23:16 +0800283 MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
284 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
Fabio Estevam032de432014-02-06 08:57:51 -0200285 MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
286 >;
287 };
288
289 pinctrl_audmux3: audmux3grp {
290 fsl,pins = <
291 MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
292 MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
293 MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
294 MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
Shawn Guo117ccd552013-05-03 11:28:42 +0800295 >;
296 };
Shawn Guofffaa652013-11-04 10:49:04 +0800297
298 pinctrl_ecspi1: ecspi1grp {
299 fsl,pins = <
300 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
301 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
302 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
Fabio Estevam2cd36712014-04-11 09:09:39 -0300303 MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000
Shawn Guofffaa652013-11-04 10:49:04 +0800304 >;
305 };
306
307 pinctrl_fec: fecgrp {
308 fsl,pins = <
309 MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
310 MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
311 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
312 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
313 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
314 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
315 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
316 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
317 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
318 >;
319 };
320
Fugang Duan01d41c92014-05-20 14:50:44 +0800321 pinctrl_fec_sleep: fecgrp-sleep {
322 fsl,pins = <
323 MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080
324 MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080
325 MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080
326 MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080
327 MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080
328 MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080
329 MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080
330 MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080
331 >;
332 };
333
Fabio Estevam56df2682014-02-06 08:57:50 -0200334 pinctrl_i2c1: i2c1grp {
335 fsl,pins = <
336 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
337 MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
338 >;
339 };
340
Fabio Estevam032de432014-02-06 08:57:51 -0200341
342 pinctrl_i2c2: i2c2grp {
343 fsl,pins = <
344 MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
345 MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
346 >;
347 };
348
Anson Huang4291b642014-01-14 17:30:28 +0800349 pinctrl_kpp: kppgrp {
350 fsl,pins = <
351 MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
352 MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010
353 MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0
354 MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0
355 MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0
356 MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0
357 >;
358 };
359
Fabio Estevame99b0772014-08-19 15:21:14 -0300360 pinctrl_lcd: lcdgrp {
361 fsl,pins = <
362 MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
363 MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
364 MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
365 MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
366 MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
367 MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
368 MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
369 MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
370 MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
371 MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
372 MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
373 MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
374 MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
375 MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
376 MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
377 MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
378 MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
379 MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
380 MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
381 MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
382 MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
383 MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
384 MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
385 MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
386 MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
387 MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
388 MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
389 MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
390 >;
391 };
392
Fabio Estevam1bb9dae52014-08-19 15:21:13 -0300393 pinctrl_led: ledgrp {
394 fsl,pins = <
395 MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
396 >;
397 };
398
Fabio Estevame99b0772014-08-19 15:21:14 -0300399 pinctrl_pwm1: pwmgrp {
400 fsl,pins = <
401 MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
402 >;
403 };
404
Shawn Guofffaa652013-11-04 10:49:04 +0800405 pinctrl_uart1: uart1grp {
406 fsl,pins = <
407 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
408 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
409 >;
410 };
411
412 pinctrl_usbotg1: usbotg1grp {
413 fsl,pins = <
414 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
415 >;
416 };
417
418 pinctrl_usdhc1: usdhc1grp {
419 fsl,pins = <
420 MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
421 MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
422 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
423 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
424 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
425 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
426 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
427 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
428 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
429 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
430 >;
431 };
432
433 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
434 fsl,pins = <
435 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
436 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
437 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
438 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
439 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
440 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
441 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
442 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
443 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
444 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
445 >;
446 };
447
448 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
449 fsl,pins = <
450 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
451 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
452 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
453 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
454 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
455 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
456 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
457 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
458 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
459 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
460 >;
461 };
462
463 pinctrl_usdhc2: usdhc2grp {
464 fsl,pins = <
465 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
466 MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
467 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
468 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
469 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
470 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
471 >;
472 };
473
474 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
475 fsl,pins = <
476 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
477 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
478 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
479 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
480 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
481 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
482 >;
483 };
484
485 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
486 fsl,pins = <
487 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
488 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
489 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
490 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
491 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
492 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
493 >;
494 };
495
496 pinctrl_usdhc3: usdhc3grp {
497 fsl,pins = <
498 MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
499 MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
500 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
501 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
502 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
503 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
504 >;
505 };
506
507 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
508 fsl,pins = <
509 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
510 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
511 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
512 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
513 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
514 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
515 >;
516 };
517
518 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
519 fsl,pins = <
520 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
521 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
522 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
523 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
524 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
525 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
526 >;
527 };
Shawn Guo117ccd552013-05-03 11:28:42 +0800528 };
529};
530
Anson Huang4291b642014-01-14 17:30:28 +0800531&kpp {
532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_kpp>;
534 linux,keymap = <
535 MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */
536 MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */
537 MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */
538 MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */
539 MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */
540 MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */
541 MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
542 MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */
543 >;
544 status = "okay";
545};
546
Fabio Estevame99b0772014-08-19 15:21:14 -0300547&lcdif {
548 pinctrl-names = "default";
549 pinctrl-0 = <&pinctrl_lcd>;
550 lcd-supply = <&reg_lcd_3v3>;
Fabio Estevam3f50a612014-09-02 22:45:14 -0300551 display = <&display0>;
Fabio Estevame99b0772014-08-19 15:21:14 -0300552 status = "okay";
553
Fabio Estevam3f50a612014-09-02 22:45:14 -0300554 display0: display0 {
Fabio Estevame99b0772014-08-19 15:21:14 -0300555 bits-per-pixel = <32>;
556 bus-width = <24>;
557
558 display-timings {
559 native-mode = <&timing0>;
560 timing0: timing0 {
561 clock-frequency = <33500000>;
562 hactive = <800>;
563 vactive = <480>;
564 hback-porch = <89>;
565 hfront-porch = <164>;
566 vback-porch = <23>;
567 vfront-porch = <10>;
568 hsync-len = <10>;
569 vsync-len = <10>;
570 hsync-active = <0>;
571 vsync-active = <0>;
572 de-active = <1>;
573 pixelclk-active = <0>;
574 };
575 };
576 };
577};
578
579&pwm1 {
580 pinctrl-names = "default";
581 pinctrl-0 = <&pinctrl_pwm1>;
582 status = "okay";
583};
584
Robin Gong422b0672014-11-12 16:20:37 +0800585&snvs_poweroff {
586 status = "okay";
587};
588
Fabio Estevam032de432014-02-06 08:57:51 -0200589&ssi2 {
Fabio Estevam032de432014-02-06 08:57:51 -0200590 status = "okay";
591};
592
Shawn Guo117ccd552013-05-03 11:28:42 +0800593&uart1 {
594 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +0800595 pinctrl-0 = <&pinctrl_uart1>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800596 status = "okay";
597};
598
Peter Chen60222322013-09-10 10:23:16 +0800599&usbotg1 {
600 vbus-supply = <&reg_usb_otg1_vbus>;
601 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +0800602 pinctrl-0 = <&pinctrl_usbotg1>;
Peter Chen60222322013-09-10 10:23:16 +0800603 disable-over-current;
604 status = "okay";
605};
606
607&usbotg2 {
608 vbus-supply = <&reg_usb_otg2_vbus>;
609 dr_mode = "host";
610 disable-over-current;
611 status = "okay";
612};
613
Shawn Guo117ccd552013-05-03 11:28:42 +0800614&usdhc1 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800615 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800616 pinctrl-0 = <&pinctrl_usdhc1>;
617 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
618 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800619 bus-width = <8>;
620 cd-gpios = <&gpio4 7 0>;
621 wp-gpios = <&gpio4 6 0>;
622 status = "okay";
623};
624
625&usdhc2 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800626 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800627 pinctrl-0 = <&pinctrl_usdhc2>;
628 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
629 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800630 cd-gpios = <&gpio5 0 0>;
631 wp-gpios = <&gpio4 29 0>;
632 status = "okay";
633};
634
635&usdhc3 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800636 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800637 pinctrl-0 = <&pinctrl_usdhc3>;
638 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
639 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800640 cd-gpios = <&gpio3 22 0>;
641 status = "okay";
642};