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Ben Hutchings8ceee662008-04-27 12:55:59 +01001/****************************************************************************
Ben Hutchings177dfcd2008-12-12 21:50:08 -08002 * Driver for Solarflare Solarstorm network controllers and boards
Ben Hutchings906bb262009-11-29 15:16:19 +00003 * Copyright 2007-2009 Solarflare Communications Inc.
Ben Hutchings8ceee662008-04-27 12:55:59 +01004 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include <linux/delay.h>
Herbert Xuda3bc072009-01-18 21:50:16 -080011#include <linux/rtnetlink.h>
Ben Hutchings8ceee662008-04-27 12:55:59 +010012#include <linux/seq_file.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090013#include <linux/slab.h>
Ben Hutchings8ceee662008-04-27 12:55:59 +010014#include "efx.h"
Ben Hutchings8ceee662008-04-27 12:55:59 +010015#include "mdio_10g.h"
Ben Hutchings744093c2009-11-29 15:12:08 +000016#include "nic.h"
Ben Hutchings8ceee662008-04-27 12:55:59 +010017#include "phy.h"
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -080018#include "workarounds.h"
Ben Hutchings8ceee662008-04-27 12:55:59 +010019
Ben Hutchings8fbca792010-09-22 10:00:11 +000020/* We expect these MMDs to be in the package. */
Ben Hutchings68e7f452009-04-29 08:05:08 +000021#define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \
22 MDIO_DEVS_PCS | \
23 MDIO_DEVS_PHYXS | \
24 MDIO_DEVS_AN)
Ben Hutchings8ceee662008-04-27 12:55:59 +010025
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -080026#define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
27 (1 << LOOPBACK_PCS) | \
28 (1 << LOOPBACK_PMAPMD) | \
Ben Hutchingse58f69f2009-11-29 15:08:41 +000029 (1 << LOOPBACK_PHYXS_WS))
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -080030
Ben Hutchings8ceee662008-04-27 12:55:59 +010031/* We complain if we fail to see the link partner as 10G capable this many
32 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
33 */
34#define MAX_BAD_LP_TRIES (5)
35
36/* Extended control register */
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -080037#define PMA_PMD_XCONTROL_REG 49152
38#define PMA_PMD_EXT_GMII_EN_LBN 1
39#define PMA_PMD_EXT_GMII_EN_WIDTH 1
40#define PMA_PMD_EXT_CLK_OUT_LBN 2
41#define PMA_PMD_EXT_CLK_OUT_WIDTH 1
Ben Hutchings8fbca792010-09-22 10:00:11 +000042#define PMA_PMD_LNPGA_POWERDOWN_LBN 8
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -080043#define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -080044#define PMA_PMD_EXT_CLK312_WIDTH 1
45#define PMA_PMD_EXT_LPOWER_LBN 12
46#define PMA_PMD_EXT_LPOWER_WIDTH 1
Steve Hodgson869b5b32009-01-29 17:48:10 +000047#define PMA_PMD_EXT_ROBUST_LBN 14
48#define PMA_PMD_EXT_ROBUST_WIDTH 1
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -080049#define PMA_PMD_EXT_SSR_LBN 15
50#define PMA_PMD_EXT_SSR_WIDTH 1
Ben Hutchings8ceee662008-04-27 12:55:59 +010051
52/* extended status register */
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -080053#define PMA_PMD_XSTATUS_REG 49153
Ben Hutchingse762cd72009-06-10 05:30:05 +000054#define PMA_PMD_XSTAT_MDIX_LBN 14
Ben Hutchings8ceee662008-04-27 12:55:59 +010055#define PMA_PMD_XSTAT_FLP_LBN (12)
56
57/* LED control register */
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -080058#define PMA_PMD_LED_CTRL_REG 49159
Ben Hutchings8ceee662008-04-27 12:55:59 +010059#define PMA_PMA_LED_ACTIVITY_LBN (3)
60
61/* LED function override register */
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -080062#define PMA_PMD_LED_OVERR_REG 49161
Ben Hutchings8ceee662008-04-27 12:55:59 +010063/* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
64#define PMA_PMD_LED_LINK_LBN (0)
65#define PMA_PMD_LED_SPEED_LBN (2)
66#define PMA_PMD_LED_TX_LBN (4)
67#define PMA_PMD_LED_RX_LBN (6)
68/* Override settings */
69#define PMA_PMD_LED_AUTO (0) /* H/W control */
70#define PMA_PMD_LED_ON (1)
71#define PMA_PMD_LED_OFF (2)
72#define PMA_PMD_LED_FLASH (3)
Ben Hutchings04cc8ca2008-12-12 21:50:46 -080073#define PMA_PMD_LED_MASK 3
Ben Hutchings8ceee662008-04-27 12:55:59 +010074/* All LEDs under hardware control */
Ben Hutchings8ceee662008-04-27 12:55:59 +010075/* Green and Amber under hardware control, Red off */
Ben Hutchingsdcf477b2009-11-23 16:02:49 +000076#define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
Ben Hutchings8ceee662008-04-27 12:55:59 +010077
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -080078#define PMA_PMD_SPEED_ENABLE_REG 49192
79#define PMA_PMD_100TX_ADV_LBN 1
80#define PMA_PMD_100TX_ADV_WIDTH 1
81#define PMA_PMD_1000T_ADV_LBN 2
82#define PMA_PMD_1000T_ADV_WIDTH 1
83#define PMA_PMD_10000T_ADV_LBN 3
84#define PMA_PMD_10000T_ADV_WIDTH 1
85#define PMA_PMD_SPEED_LBN 4
86#define PMA_PMD_SPEED_WIDTH 4
Ben Hutchings8ceee662008-04-27 12:55:59 +010087
Ben Hutchings8fbca792010-09-22 10:00:11 +000088/* Misc register defines */
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -080089#define PCS_CLOCK_CTRL_REG 55297
Ben Hutchings8ceee662008-04-27 12:55:59 +010090#define PLL312_RST_N_LBN 2
91
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -080092#define PCS_SOFT_RST2_REG 55302
Ben Hutchings8ceee662008-04-27 12:55:59 +010093#define SERDES_RST_N_LBN 13
94#define XGXS_RST_N_LBN 12
95
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -080096#define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
Ben Hutchings8ceee662008-04-27 12:55:59 +010097#define CLK312_EN_LBN 3
98
Ben Hutchings3273c2e2008-05-07 13:36:19 +010099/* PHYXS registers */
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800100#define PHYXS_XCONTROL_REG 49152
101#define PHYXS_RESET_LBN 15
102#define PHYXS_RESET_WIDTH 1
103
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100104#define PHYXS_TEST1 (49162)
105#define LOOPBACK_NEAR_LBN (8)
106#define LOOPBACK_NEAR_WIDTH (1)
107
Ben Hutchings8ceee662008-04-27 12:55:59 +0100108/* Boot status register */
Ben Hutchings190dbcf2009-02-27 13:06:45 +0000109#define PCS_BOOT_STATUS_REG 53248
110#define PCS_BOOT_FATAL_ERROR_LBN 0
111#define PCS_BOOT_PROGRESS_LBN 1
112#define PCS_BOOT_PROGRESS_WIDTH 2
113#define PCS_BOOT_PROGRESS_INIT 0
114#define PCS_BOOT_PROGRESS_WAIT_MDIO 1
115#define PCS_BOOT_PROGRESS_CHECKSUM 2
116#define PCS_BOOT_PROGRESS_JUMP 3
117#define PCS_BOOT_DOWNLOAD_WAIT_LBN 3
118#define PCS_BOOT_CODE_STARTED_LBN 4
Ben Hutchings8ceee662008-04-27 12:55:59 +0100119
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800120/* 100M/1G PHY registers */
121#define GPHY_XCONTROL_REG 49152
122#define GPHY_ISOLATE_LBN 10
123#define GPHY_ISOLATE_WIDTH 1
124#define GPHY_DUPLEX_LBN 8
125#define GPHY_DUPLEX_WIDTH 1
126#define GPHY_LOOPBACK_NEAR_LBN 14
127#define GPHY_LOOPBACK_NEAR_WIDTH 1
128
129#define C22EXT_STATUS_REG 49153
130#define C22EXT_STATUS_LINK_LBN 2
131#define C22EXT_STATUS_LINK_WIDTH 1
132
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000133#define C22EXT_MSTSLV_CTRL 49161
134#define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8
135#define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9
136
137#define C22EXT_MSTSLV_STATUS 49162
138#define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10
139#define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800140
Ben Hutchings8ceee662008-04-27 12:55:59 +0100141/* Time to wait between powering down the LNPGA and turning off the power
142 * rails */
143#define LNPGA_PDOWN_WAIT (HZ / 5)
144
Ben Hutchings8ceee662008-04-27 12:55:59 +0100145struct tenxpress_phy_data {
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100146 enum efx_loopback_mode loopback_mode;
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100147 enum efx_phy_mode phy_mode;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100148 int bad_lp_tries;
149};
150
Ben Hutchings8ceee662008-04-27 12:55:59 +0100151static int tenxpress_init(struct efx_nic *efx)
152{
Ben Hutchings8fbca792010-09-22 10:00:11 +0000153 /* Enable 312.5 MHz clock */
154 efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
155 1 << CLK312_EN_LBN);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100156
Ben Hutchings8ceee662008-04-27 12:55:59 +0100157 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
Ben Hutchings8fbca792010-09-22 10:00:11 +0000158 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG,
159 1 << PMA_PMA_LED_ACTIVITY_LBN, true);
160 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG,
161 SFX7101_PMA_PMD_LED_DEFAULT);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100162
Ben Hutchings190dbcf2009-02-27 13:06:45 +0000163 return 0;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100164}
165
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000166static int tenxpress_phy_probe(struct efx_nic *efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100167{
168 struct tenxpress_phy_data *phy_data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100169
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000170 /* Allocate phy private storage */
Ben Hutchings8ceee662008-04-27 12:55:59 +0100171 phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
Ben Hutchings9b7bfc42008-05-16 21:20:20 +0100172 if (!phy_data)
173 return -ENOMEM;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100174 efx->phy_data = phy_data;
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100175 phy_data->phy_mode = efx->phy_mode;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100176
Ben Hutchings8fbca792010-09-22 10:00:11 +0000177 efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS;
178 efx->mdio.mode_support = MDIO_SUPPORTS_C45;
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000179
Ben Hutchings8fbca792010-09-22 10:00:11 +0000180 efx->loopback_modes = SFX7101_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000181
Ben Hutchings8fbca792010-09-22 10:00:11 +0000182 efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg |
183 ADVERTISED_10000baseT_Full);
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000184
185 return 0;
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000186}
187
188static int tenxpress_phy_init(struct efx_nic *efx)
189{
190 int rc;
191
192 falcon_board(efx)->type->init_phy(efx);
193
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800194 if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
Ben Hutchings68e7f452009-04-29 08:05:08 +0000195 rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800196 if (rc < 0)
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000197 return rc;
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800198
Ben Hutchings68e7f452009-04-29 08:05:08 +0000199 rc = efx_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800200 if (rc < 0)
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000201 return rc;
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800202 }
Ben Hutchings8ceee662008-04-27 12:55:59 +0100203
204 rc = tenxpress_init(efx);
205 if (rc < 0)
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000206 return rc;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100207
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000208 /* Reinitialise flow control settings */
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000209 efx_link_set_wanted_fc(efx, efx->wanted_fc);
210 efx_mdio_an_reconfigure(efx);
Ben Hutchingsc6342632009-10-12 09:27:07 +0000211
Ben Hutchings8ceee662008-04-27 12:55:59 +0100212 schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
213
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800214 /* Let XGXS and SerDes out of reset */
Ben Hutchings8ceee662008-04-27 12:55:59 +0100215 falcon_reset_xaui(efx);
216
217 return 0;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100218}
219
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800220/* Perform a "special software reset" on the PHY. The caller is
221 * responsible for saving and restoring the PHY hardware registers
222 * properly, and masking/unmasking LASI */
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100223static int tenxpress_special_reset(struct efx_nic *efx)
224{
225 int rc, reg;
226
Ben Hutchings8fbca792010-09-22 10:00:11 +0000227 /* The XGMAC clock is driven from the SFX7101 312MHz clock, so
Ben Hutchingsc8fcc492008-09-01 12:49:25 +0100228 * a special software reset can glitch the XGMAC sufficiently for stats
Ben Hutchings1974cc22009-01-29 18:00:07 +0000229 * requests to fail. */
Ben Hutchings55edc6e2009-11-25 16:11:35 +0000230 falcon_stop_nic_stats(efx);
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100231
232 /* Initiate reset */
Ben Hutchings68e7f452009-04-29 08:05:08 +0000233 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100234 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
Ben Hutchings68e7f452009-04-29 08:05:08 +0000235 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100236
Ben Hutchingsc8fcc492008-09-01 12:49:25 +0100237 mdelay(200);
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100238
239 /* Wait for the blocks to come out of reset */
Ben Hutchings68e7f452009-04-29 08:05:08 +0000240 rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100241 if (rc < 0)
Ben Hutchings1974cc22009-01-29 18:00:07 +0000242 goto out;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100243
244 /* Try and reconfigure the device */
245 rc = tenxpress_init(efx);
246 if (rc < 0)
Ben Hutchings1974cc22009-01-29 18:00:07 +0000247 goto out;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100248
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800249 /* Wait for the XGXS state machine to churn */
250 mdelay(10);
Ben Hutchings1974cc22009-01-29 18:00:07 +0000251out:
Ben Hutchings55edc6e2009-11-25 16:11:35 +0000252 falcon_start_nic_stats(efx);
Ben Hutchingsc8fcc492008-09-01 12:49:25 +0100253 return rc;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100254}
255
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800256static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100257{
258 struct tenxpress_phy_data *pd = efx->phy_data;
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800259 bool bad_lp;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100260 int reg;
261
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800262 if (link_ok) {
263 bad_lp = false;
264 } else {
265 /* Check that AN has started but not completed. */
Ben Hutchings68e7f452009-04-29 08:05:08 +0000266 reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1);
267 if (!(reg & MDIO_AN_STAT1_LPABLE))
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800268 return; /* LP status is unknown */
Ben Hutchings68e7f452009-04-29 08:05:08 +0000269 bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE);
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800270 if (bad_lp)
271 pd->bad_lp_tries++;
272 }
273
Ben Hutchings8ceee662008-04-27 12:55:59 +0100274 /* Nothing to do if all is well and was previously so. */
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800275 if (!pd->bad_lp_tries)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100276 return;
277
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800278 /* Use the RX (red) LED as an error indicator once we've seen AN
279 * failure several times in a row, and also log a message. */
280 if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
Ben Hutchings68e7f452009-04-29 08:05:08 +0000281 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
282 PMA_PMD_LED_OVERR_REG);
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800283 reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
284 if (!bad_lp) {
285 reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
286 } else {
287 reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
Ben Hutchings62776d02010-06-23 11:30:07 +0000288 netif_err(efx, link, efx->net_dev,
289 "appears to be plugged into a port"
290 " that is not 10GBASE-T capable. The PHY"
291 " supports 10GBASE-T ONLY, so no link can"
292 " be established\n");
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800293 }
Ben Hutchings68e7f452009-04-29 08:05:08 +0000294 efx_mdio_write(efx, MDIO_MMD_PMAPMD,
295 PMA_PMD_LED_OVERR_REG, reg);
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800296 pd->bad_lp_tries = bad_lp;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100297 }
Ben Hutchings8ceee662008-04-27 12:55:59 +0100298}
299
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800300static bool sfx7101_link_ok(struct efx_nic *efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100301{
Ben Hutchings68e7f452009-04-29 08:05:08 +0000302 return efx_mdio_links_ok(efx,
303 MDIO_DEVS_PMAPMD |
304 MDIO_DEVS_PCS |
305 MDIO_DEVS_PHYXS);
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800306}
307
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800308static void tenxpress_ext_loopback(struct efx_nic *efx)
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100309{
Ben Hutchings68e7f452009-04-29 08:05:08 +0000310 efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1,
311 1 << LOOPBACK_NEAR_LBN,
312 efx->loopback_mode == LOOPBACK_PHYXS);
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800313}
314
315static void tenxpress_low_power(struct efx_nic *efx)
316{
Ben Hutchings8fbca792010-09-22 10:00:11 +0000317 efx_mdio_set_mmds_lpower(
318 efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
319 TENXPRESS_REQUIRED_DEVS);
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100320}
321
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000322static int tenxpress_phy_reconfigure(struct efx_nic *efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100323{
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100324 struct tenxpress_phy_data *phy_data = efx->phy_data;
Steve Hodgson8b9dc8d2009-01-29 17:49:09 +0000325 bool phy_mode_change, loop_reset;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100326
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800327 if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) {
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100328 phy_data->phy_mode = efx->phy_mode;
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000329 return 0;
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100330 }
Ben Hutchings8ceee662008-04-27 12:55:59 +0100331
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800332 phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
333 phy_data->phy_mode != PHY_MODE_NORMAL);
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000334 loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, LOOPBACKS_EXTERNAL(efx)) ||
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800335 LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));
336
Steve Hodgson8b9dc8d2009-01-29 17:49:09 +0000337 if (loop_reset || phy_mode_change) {
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000338 tenxpress_special_reset(efx);
Ben Hutchings8fbca792010-09-22 10:00:11 +0000339 falcon_reset_xaui(efx);
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100340 }
341
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000342 tenxpress_low_power(efx);
Ben Hutchings68e7f452009-04-29 08:05:08 +0000343 efx_mdio_transmit_disable(efx);
344 efx_mdio_phy_reconfigure(efx);
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800345 tenxpress_ext_loopback(efx);
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000346 efx_mdio_an_reconfigure(efx);
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100347
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100348 phy_data->loopback_mode = efx->loopback_mode;
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100349 phy_data->phy_mode = efx->phy_mode;
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000350
351 return 0;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100352}
353
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000354static void
355tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd);
356
357/* Poll for link state changes */
358static bool tenxpress_phy_poll(struct efx_nic *efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100359{
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000360 struct efx_link_state old_state = efx->link_state;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100361
Ben Hutchings8fbca792010-09-22 10:00:11 +0000362 efx->link_state.up = sfx7101_link_ok(efx);
363 efx->link_state.speed = 10000;
364 efx->link_state.fd = true;
365 efx->link_state.fc = efx_mdio_get_pause(efx);
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000366
Ben Hutchings8fbca792010-09-22 10:00:11 +0000367 sfx7101_check_bad_lp(efx, efx->link_state.up);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100368
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000369 return !efx_link_state_equal(&efx->link_state, &old_state);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100370}
371
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000372static void sfx7101_phy_fini(struct efx_nic *efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100373{
374 int reg;
375
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000376 /* Power down the LNPGA */
377 reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
378 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
379
380 /* Waiting here ensures that the board fini, which can turn
381 * off the power to the PHY, won't get run until the LNPGA
382 * powerdown has been given long enough to complete. */
383 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
384}
385
386static void tenxpress_phy_remove(struct efx_nic *efx)
387{
Ben Hutchings8ceee662008-04-27 12:55:59 +0100388 kfree(efx->phy_data);
389 efx->phy_data = NULL;
390}
391
392
Ben Hutchings398468e2009-11-23 16:03:45 +0000393/* Override the RX, TX and link LEDs */
394void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100395{
396 int reg;
397
Ben Hutchings398468e2009-11-23 16:03:45 +0000398 switch (mode) {
399 case EFX_LED_OFF:
400 reg = (PMA_PMD_LED_OFF << PMA_PMD_LED_TX_LBN) |
401 (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) |
402 (PMA_PMD_LED_OFF << PMA_PMD_LED_LINK_LBN);
403 break;
404 case EFX_LED_ON:
405 reg = (PMA_PMD_LED_ON << PMA_PMD_LED_TX_LBN) |
406 (PMA_PMD_LED_ON << PMA_PMD_LED_RX_LBN) |
407 (PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN);
408 break;
409 default:
Ben Hutchings8fbca792010-09-22 10:00:11 +0000410 reg = SFX7101_PMA_PMD_LED_DEFAULT;
Ben Hutchings398468e2009-11-23 16:03:45 +0000411 break;
412 }
Ben Hutchings8ceee662008-04-27 12:55:59 +0100413
Ben Hutchings68e7f452009-04-29 08:05:08 +0000414 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100415}
416
Ben Hutchings307505e2008-12-26 13:48:00 -0800417static const char *const sfx7101_test_names[] = {
Ben Hutchings17967212008-12-26 13:47:25 -0800418 "bist"
419};
420
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000421static const char *sfx7101_test_name(struct efx_nic *efx, unsigned int index)
422{
423 if (index < ARRAY_SIZE(sfx7101_test_names))
424 return sfx7101_test_names[index];
425 return NULL;
426}
427
Ben Hutchings17967212008-12-26 13:47:25 -0800428static int
Ben Hutchings307505e2008-12-26 13:48:00 -0800429sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags)
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100430{
Ben Hutchings17967212008-12-26 13:47:25 -0800431 int rc;
432
433 if (!(flags & ETH_TEST_FL_OFFLINE))
434 return 0;
435
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100436 /* BIST is automatically run after a special software reset */
Ben Hutchings17967212008-12-26 13:47:25 -0800437 rc = tenxpress_special_reset(efx);
438 results[0] = rc ? -1 : 1;
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000439
440 efx_mdio_an_reconfigure(efx);
441
Ben Hutchings17967212008-12-26 13:47:25 -0800442 return rc;
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100443}
444
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000445static void
446tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800447{
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000448 u32 adv = 0, lpa = 0;
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800449 int reg;
450
Ben Hutchings68e7f452009-04-29 08:05:08 +0000451 reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
452 if (reg & MDIO_AN_10GBT_CTRL_ADV10G)
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000453 adv |= ADVERTISED_10000baseT_Full;
Ben Hutchings68e7f452009-04-29 08:05:08 +0000454 reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
455 if (reg & MDIO_AN_10GBT_STAT_LP10G)
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800456 lpa |= ADVERTISED_10000baseT_Full;
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800457
Ben Hutchings68e7f452009-04-29 08:05:08 +0000458 mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa);
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800459
Steve Hodgson8b9dc8d2009-01-29 17:49:09 +0000460 /* In loopback, the PHY automatically brings up the correct interface,
461 * but doesn't advertise the correct speed. So override it */
Ben Hutchings8fbca792010-09-22 10:00:11 +0000462 if (LOOPBACK_EXTERNAL(efx))
Steve Hodgson8b9dc8d2009-01-29 17:49:09 +0000463 ecmd->speed = SPEED_10000;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100464}
465
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000466static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100467{
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000468 if (!ecmd->autoneg)
469 return -EINVAL;
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800470
Ben Hutchings68e7f452009-04-29 08:05:08 +0000471 return efx_mdio_set_settings(efx, ecmd);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100472}
473
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000474static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising)
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800475{
Ben Hutchings68e7f452009-04-29 08:05:08 +0000476 efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
477 MDIO_AN_10GBT_CTRL_ADV10G,
478 advertising & ADVERTISED_10000baseT_Full);
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000479}
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800480
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800481struct efx_phy_operations falcon_sfx7101_phy_ops = {
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000482 .probe = tenxpress_phy_probe,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100483 .init = tenxpress_phy_init,
484 .reconfigure = tenxpress_phy_reconfigure,
Ben Hutchings766ca0f2008-12-12 21:59:24 -0800485 .poll = tenxpress_phy_poll,
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000486 .fini = sfx7101_phy_fini,
487 .remove = tenxpress_phy_remove,
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000488 .get_settings = tenxpress_get_settings,
489 .set_settings = tenxpress_set_settings,
490 .set_npage_adv = sfx7101_set_npage_adv,
Ben Hutchings4f16c072010-02-03 09:30:50 +0000491 .test_alive = efx_mdio_test_alive,
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000492 .test_name = sfx7101_test_name,
Ben Hutchings307505e2008-12-26 13:48:00 -0800493 .run_tests = sfx7101_run_tests,
Ben Hutchingse6fa2eb2008-12-12 22:00:17 -0800494};