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Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -07001/*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23#ifndef __SH_ETH_H__
24#define __SH_ETH_H__
25
26#include <linux/module.h>
27#include <linux/kernel.h>
28#include <linux/spinlock.h>
29#include <linux/workqueue.h>
30#include <linux/netdevice.h>
31#include <linux/phy.h>
32
Yoshinori Sato71557a32008-08-06 19:49:00 -040033#include <asm/sh_eth.h>
34
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -070035#define CARDNAME "sh-eth"
36#define TX_TIMEOUT (5*HZ)
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +090037#define TX_RING_SIZE 64 /* Tx ring size */
38#define RX_RING_SIZE 64 /* Rx ring size */
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -070039#define ETHERSMALL 60
40#define PKT_BUF_SZ 1538
41
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +090042#ifdef CONFIG_CPU_SUBTYPE_SH7763
43
44#define SH7763_SKB_ALIGN 32
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -070045/* Chip Base Address */
Nobuhiro Iwamatsu2e2a6a92009-03-16 19:52:23 +000046# define SH_TSU_ADDR 0xFEE01800
47# define ARSTR SH_TSU_ADDR
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -070048
49/* Chip Registers */
50/* E-DMAC */
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +090051# define EDSR 0x000
52# define EDMR 0x400
53# define EDTRR 0x408
54# define EDRRR 0x410
55# define EESR 0x428
56# define EESIPR 0x430
57# define TDLAR 0x010
58# define TDFAR 0x014
59# define TDFXR 0x018
60# define TDFFR 0x01C
61# define RDLAR 0x030
62# define RDFAR 0x034
63# define RDFXR 0x038
64# define RDFFR 0x03C
65# define TRSCER 0x438
66# define RMFCR 0x440
67# define TFTR 0x448
68# define FDR 0x450
69# define RMCR 0x458
70# define RPADIR 0x460
71# define FCFTR 0x468
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -070072
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +090073/* Ether Register */
74# define ECMR 0x500
75# define ECSR 0x510
76# define ECSIPR 0x518
77# define PIR 0x520
78# define PSR 0x528
79# define PIPR 0x52C
80# define RFLR 0x508
81# define APR 0x554
82# define MPR 0x558
83# define PFTCR 0x55C
84# define PFRCR 0x560
85# define TPAUSER 0x564
86# define GECMR 0x5B0
87# define BCULR 0x5B4
88# define MAHR 0x5C0
89# define MALR 0x5C8
90# define TROCR 0x700
91# define CDCR 0x708
92# define LCCR 0x710
93# define CEFCR 0x740
94# define FRECR 0x748
95# define TSFRCR 0x750
96# define TLFRCR 0x758
97# define RFCR 0x760
98# define CERCR 0x768
99# define CEECR 0x770
100# define MAFCR 0x778
101
102/* TSU Absolute Address */
103# define TSU_CTRST 0x004
104# define TSU_FWEN0 0x010
105# define TSU_FWEN1 0x014
106# define TSU_FCM 0x18
107# define TSU_BSYSL0 0x20
108# define TSU_BSYSL1 0x24
109# define TSU_PRISL0 0x28
110# define TSU_PRISL1 0x2C
111# define TSU_FWSL0 0x30
112# define TSU_FWSL1 0x34
113# define TSU_FWSLC 0x38
114# define TSU_QTAG0 0x40
115# define TSU_QTAG1 0x44
116# define TSU_FWSR 0x50
117# define TSU_FWINMK 0x54
118# define TSU_ADQT0 0x48
119# define TSU_ADQT1 0x4C
120# define TSU_VTAG0 0x58
121# define TSU_VTAG1 0x5C
122# define TSU_ADSBSY 0x60
123# define TSU_TEN 0x64
124# define TSU_POST1 0x70
125# define TSU_POST2 0x74
126# define TSU_POST3 0x78
127# define TSU_POST4 0x7C
128# define TSU_ADRH0 0x100
129# define TSU_ADRL0 0x104
130# define TSU_ADRH31 0x1F8
131# define TSU_ADRL31 0x1FC
132
133# define TXNLCR0 0x80
134# define TXALCR0 0x84
135# define RXNLCR0 0x88
136# define RXALCR0 0x8C
137# define FWNLCR0 0x90
138# define FWALCR0 0x94
139# define TXNLCR1 0xA0
140# define TXALCR1 0xA4
141# define RXNLCR1 0xA8
142# define RXALCR1 0xAC
143# define FWNLCR1 0xB0
144# define FWALCR1 0x40
145
146#else /* CONFIG_CPU_SUBTYPE_SH7763 */
147# define RX_OFFSET 2 /* skb offset */
Yoshinori Sato71557a32008-08-06 19:49:00 -0400148#ifndef CONFIG_CPU_SUBTYPE_SH7619
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900149/* Chip base address */
150# define SH_TSU_ADDR 0xA7000804
151# define ARSTR 0xA7000800
Yoshinori Sato71557a32008-08-06 19:49:00 -0400152#endif
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900153/* Chip Registers */
154/* E-DMAC */
155# define EDMR 0x0000
156# define EDTRR 0x0004
157# define EDRRR 0x0008
158# define TDLAR 0x000C
159# define RDLAR 0x0010
160# define EESR 0x0014
161# define EESIPR 0x0018
162# define TRSCER 0x001C
163# define RMFCR 0x0020
164# define TFTR 0x0024
165# define FDR 0x0028
166# define RMCR 0x002C
167# define EDOCR 0x0030
168# define FCFTR 0x0034
169# define RPADIR 0x0038
170# define TRIMD 0x003C
171# define RBWAR 0x0040
172# define RDFAR 0x0044
173# define TBRAR 0x004C
174# define TDFAR 0x0050
175
176/* Ether Register */
177# define ECMR 0x0160
178# define ECSR 0x0164
179# define ECSIPR 0x0168
180# define PIR 0x016C
181# define MAHR 0x0170
182# define MALR 0x0174
183# define RFLR 0x0178
184# define PSR 0x017C
185# define TROCR 0x0180
186# define CDCR 0x0184
187# define LCCR 0x0188
188# define CNDCR 0x018C
189# define CEFCR 0x0194
190# define FRECR 0x0198
191# define TSFRCR 0x019C
192# define TLFRCR 0x01A0
193# define RFCR 0x01A4
194# define MAFCR 0x01A8
195# define IPGR 0x01B4
196# if defined(CONFIG_CPU_SUBTYPE_SH7710)
197# define APR 0x01B8
198# define MPR 0x01BC
199# define TPAUSER 0x1C4
200# define BCFR 0x1CC
201# endif /* CONFIG_CPU_SH7710 */
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700202
203/* TSU */
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900204# define TSU_CTRST 0x004
205# define TSU_FWEN0 0x010
206# define TSU_FWEN1 0x014
207# define TSU_FCM 0x018
208# define TSU_BSYSL0 0x020
209# define TSU_BSYSL1 0x024
210# define TSU_PRISL0 0x028
211# define TSU_PRISL1 0x02C
212# define TSU_FWSL0 0x030
213# define TSU_FWSL1 0x034
214# define TSU_FWSLC 0x038
215# define TSU_QTAGM0 0x040
216# define TSU_QTAGM1 0x044
217# define TSU_ADQT0 0x048
218# define TSU_ADQT1 0x04C
219# define TSU_FWSR 0x050
220# define TSU_FWINMK 0x054
221# define TSU_ADSBSY 0x060
222# define TSU_TEN 0x064
223# define TSU_POST1 0x070
224# define TSU_POST2 0x074
225# define TSU_POST3 0x078
226# define TSU_POST4 0x07C
227# define TXNLCR0 0x080
228# define TXALCR0 0x084
229# define RXNLCR0 0x088
230# define RXALCR0 0x08C
231# define FWNLCR0 0x090
232# define FWALCR0 0x094
233# define TXNLCR1 0x0A0
234# define TXALCR1 0x0A4
235# define RXNLCR1 0x0A8
236# define RXALCR1 0x0AC
237# define FWNLCR1 0x0B0
238# define FWALCR1 0x0B4
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700239
240#define TSU_ADRH0 0x0100
241#define TSU_ADRL0 0x0104
242#define TSU_ADRL31 0x01FC
243
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900244#endif /* CONFIG_CPU_SUBTYPE_SH7763 */
245
246/*
247 * Register's bits
248 */
249#ifdef CONFIG_CPU_SUBTYPE_SH7763
250/* EDSR */
251enum EDSR_BIT {
252 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
253};
254#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
255
256/* GECMR */
257enum GECMR_BIT {
258 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
259};
260#endif
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700261
262/* EDMR */
263enum DMAC_M_BIT {
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900264 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
265#ifdef CONFIG_CPU_SUBTYPE_SH7763
266 EDMR_SRST = 0x03,
267 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
268 EDMR_EL = 0x40, /* Litte endian */
269#else /* CONFIG_CPU_SUBTYPE_SH7763 */
270 EDMR_SRST = 0x01,
271#endif
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700272};
273
274/* EDTRR */
275enum DMAC_T_BIT {
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900276#ifdef CONFIG_CPU_SUBTYPE_SH7763
277 EDTRR_TRNS = 0x03,
278#else
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700279 EDTRR_TRNS = 0x01,
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900280#endif
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700281};
282
283/* EDRRR*/
284enum EDRRR_R_BIT {
285 EDRRR_R = 0x01,
286};
287
288/* TPAUSER */
289enum TPAUSER_BIT {
290 TPAUSER_TPAUSE = 0x0000ffff,
291 TPAUSER_UNLIMITED = 0,
292};
293
294/* BCFR */
295enum BCFR_BIT {
296 BCFR_RPAUSE = 0x0000ffff,
297 BCFR_UNLIMITED = 0,
298};
299
300/* PIR */
301enum PIR_BIT {
302 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
303};
304
305/* PSR */
306enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
307
308/* EESR */
309enum EESR_BIT {
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900310#ifndef CONFIG_CPU_SUBTYPE_SH7763
311 EESR_TWB = 0x40000000,
312#else
313 EESR_TWB = 0xC0000000,
314 EESR_TC1 = 0x20000000,
315 EESR_TUC = 0x10000000,
316 EESR_ROC = 0x80000000,
317#endif
318 EESR_TABT = 0x04000000,
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700319 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900320#ifndef CONFIG_CPU_SUBTYPE_SH7763
321 EESR_ADE = 0x00800000,
322#endif
323 EESR_ECI = 0x00400000,
324 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
325 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
326 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
327#ifndef CONFIG_CPU_SUBTYPE_SH7763
328 EESR_CND = 0x00000800,
329#endif
330 EESR_DLC = 0x00000400,
331 EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
332 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
333 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
334 EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
335 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700336};
337
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900338
339#ifdef CONFIG_CPU_SUBTYPE_SH7763
340# define TX_CHECK (EESR_TC1 | EESR_FTC)
341# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
342 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
343# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
344
345#else
346# define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
347# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700348 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900349# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
350#endif
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700351
352/* EESIPR */
353enum DMAC_IM_BIT {
354 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
355 DMAC_M_RABT = 0x02000000,
356 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
357 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
358 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
359 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
360 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
361 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
362 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
363 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
364 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
365 DMAC_M_RINT1 = 0x00000001,
366};
367
368/* Receive descriptor bit */
369enum RD_STS_BIT {
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900370 RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
371 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700372 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
373 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
374 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
375 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
376 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
377 RD_RFS1 = 0x00000001,
378};
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900379#define RDF1ST RD_RFP1
380#define RDFEND RD_RFP0
381#define RD_RFP (RD_RFP1|RD_RFP0)
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700382
383/* FCFTR */
384enum FCFTR_BIT {
385 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
386 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
387 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
388};
389#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
Yoshinori Sato71557a32008-08-06 19:49:00 -0400390#ifndef CONFIG_CPU_SUBTYPE_SH7619
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700391#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
Yoshinori Sato71557a32008-08-06 19:49:00 -0400392#else
393#define FIFO_F_D_RFD (FCFTR_RFD0)
394#endif
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700395
396/* Transfer descriptor bit */
397enum TD_STS_BIT {
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900398 TD_TACT = 0x80000000,
399 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700400 TD_TFP0 = 0x10000000,
401};
402#define TDF1ST TD_TFP1
403#define TDFEND TD_TFP0
404#define TD_TFP (TD_TFP1|TD_TFP0)
405
406/* RMCR */
407enum RECV_RST_BIT { RMCR_RST = 0x01, };
408/* ECMR */
409enum FELIC_MODE_BIT {
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900410#ifdef CONFIG_CPU_SUBTYPE_SH7763
411 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
412 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
413#endif
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700414 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
415 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
416 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
417 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
418 ECMR_PRM = 0x00000001,
419};
420
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900421#ifdef CONFIG_CPU_SUBTYPE_SH7763
422#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF |\
423 ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
Yoshinori Sato71557a32008-08-06 19:49:00 -0400424#elif CONFIG_CPU_SUBTYPE_SH7619
425#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900426#else
Yoshinori Sato71557a32008-08-06 19:49:00 -0400427#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900428#endif
429
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700430/* ECSR */
431enum ECSR_STATUS_BIT {
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900432#ifndef CONFIG_CPU_SUBTYPE_SH7763
433 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
434#endif
435 ECSR_LCHNG = 0x04,
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700436 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
437};
438
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900439#ifdef CONFIG_CPU_SUBTYPE_SH7763
440# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
441#else
442# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
443 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
444#endif
445
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700446/* ECSIPR */
447enum ECSIPR_STATUS_MASK_BIT {
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900448#ifndef CONFIG_CPU_SUBTYPE_SH7763
449 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
450#endif
451 ECSIPR_LCHNGIP = 0x04,
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700452 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
453};
454
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900455#ifdef CONFIG_CPU_SUBTYPE_SH7763
456# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
457#else
458# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
459 ECSIPR_ICDIP | ECSIPR_MPDIP)
460#endif
461
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700462/* APR */
463enum APR_BIT {
464 APR_AP = 0x00000001,
465};
466
467/* MPR */
468enum MPR_BIT {
469 MPR_MP = 0x00000001,
470};
471
472/* TRSCER */
473enum DESC_I_BIT {
474 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
475 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
476 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
477 DESC_I_RINT1 = 0x0001,
478};
479
480/* RPADIR */
481enum RPADIR_BIT {
482 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
483 RPADIR_PADR = 0x0003f,
484};
485
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900486#if defined(CONFIG_CPU_SUBTYPE_SH7763)
487# define RPADIR_INIT (0x00)
488#else
489# define RPADIR_INIT (RPADIR_PADS1)
490#endif
491
492/* RFLR */
493#define RFLR_VALUE 0x1000
494
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700495/* FDR */
496enum FIFO_SIZE_BIT {
Yoshinori Sato71557a32008-08-06 19:49:00 -0400497#ifndef CONFIG_CPU_SUBTYPE_SH7619
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700498 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
Yoshinori Sato71557a32008-08-06 19:49:00 -0400499#else
500 FIFO_SIZE_T = 0x00000100, FIFO_SIZE_R = 0x00000001,
501#endif
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700502};
503enum phy_offsets {
504 PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
505 PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
506 PHY_16 = 16,
507};
508
509/* PHY_CTRL */
510enum PHY_CTRL_BIT {
511 PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
512 PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
513 PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
514};
515#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
516
517/* PHY_STAT */
518enum PHY_STAT_BIT {
519 PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
520 PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
521 PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
522 PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
523};
524
525/* PHY_ANA */
526enum PHY_ANA_BIT {
527 PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
528 PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
529 PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900530 PHY_A_SEL = 0x001e,
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700531};
532/* PHY_ANL */
533enum PHY_ANL_BIT {
534 PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
535 PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
536 PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
537 PHY_L_SEL = 0x001f,
538};
539
540/* PHY_ANE */
541enum PHY_ANE_BIT {
542 PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
543 PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
544};
545
546/* DM9161 */
547enum PHY_16_BIT {
548 PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
549 PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
550 PHY_16_TXselect = 0x0400,
551 PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
552 PHY_16_Force100LNK = 0x0080,
553 PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
554 PHY_16_RPDCTR_EN = 0x0010,
555 PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
556 PHY_16_Sleepmode = 0x0002,
557 PHY_16_RemoteLoopOut = 0x0001,
558};
559
560#define POST_RX 0x08
561#define POST_FW 0x04
562#define POST0_RX (POST_RX)
563#define POST0_FW (POST_FW)
564#define POST1_RX (POST_RX >> 2)
565#define POST1_FW (POST_FW >> 2)
566#define POST_ALL (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
567
568/* ARSTR */
569enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
570
571/* TSU_FWEN0 */
572enum TSU_FWEN0_BIT {
573 TSU_FWEN0_0 = 0x00000001,
574};
575
576/* TSU_ADSBSY */
577enum TSU_ADSBSY_BIT {
578 TSU_ADSBSY_0 = 0x00000001,
579};
580
581/* TSU_TEN */
582enum TSU_TEN_BIT {
583 TSU_TEN_0 = 0x80000000,
584};
585
586/* TSU_FWSL0 */
587enum TSU_FWSL0_BIT {
588 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
589 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
590 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
591};
592
593/* TSU_FWSLC */
594enum TSU_FWSLC_BIT {
595 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
596 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
597 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
598 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
599 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
600};
601
602/*
603 * The sh ether Tx buffer descriptors.
604 * This structure should be 20 bytes.
605 */
606struct sh_eth_txdesc {
607 u32 status; /* TD0 */
608#if defined(CONFIG_CPU_LITTLE_ENDIAN)
609 u16 pad0; /* TD1 */
610 u16 buffer_length; /* TD1 */
611#else
612 u16 buffer_length; /* TD1 */
613 u16 pad0; /* TD1 */
614#endif
615 u32 addr; /* TD2 */
616 u32 pad1; /* padding data */
Yoshinori Sato71557a32008-08-06 19:49:00 -0400617} __attribute__((aligned(2), packed));
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700618
619/*
620 * The sh ether Rx buffer descriptors.
621 * This structure should be 20 bytes.
622 */
623struct sh_eth_rxdesc {
624 u32 status; /* RD0 */
625#if defined(CONFIG_CPU_LITTLE_ENDIAN)
626 u16 frame_length; /* RD1 */
627 u16 buffer_length; /* RD1 */
628#else
629 u16 buffer_length; /* RD1 */
630 u16 frame_length; /* RD1 */
631#endif
632 u32 addr; /* RD2 */
633 u32 pad0; /* padding data */
Yoshinori Sato71557a32008-08-06 19:49:00 -0400634} __attribute__((aligned(2), packed));
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700635
636struct sh_eth_private {
637 dma_addr_t rx_desc_dma;
638 dma_addr_t tx_desc_dma;
639 struct sh_eth_rxdesc *rx_ring;
640 struct sh_eth_txdesc *tx_ring;
641 struct sk_buff **rx_skbuff;
642 struct sk_buff **tx_skbuff;
643 struct net_device_stats stats;
644 struct timer_list timer;
645 spinlock_t lock;
646 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
647 u32 cur_tx, dirty_tx;
648 u32 rx_buf_sz; /* Based on MTU+slack. */
Yoshinori Sato71557a32008-08-06 19:49:00 -0400649 int edmac_endian;
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700650 /* MII transceiver section. */
651 u32 phy_id; /* PHY ID */
652 struct mii_bus *mii_bus; /* MDIO bus control */
653 struct phy_device *phydev; /* PHY device control */
654 enum phy_state link;
655 int msg_enable;
656 int speed;
657 int duplex;
658 u32 rx_int_var, tx_int_var; /* interrupt control variables */
659 char post_rx; /* POST receive */
660 char post_fw; /* POST forward */
661 struct net_device_stats tsu_stats; /* TSU forward status */
662};
663
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900664#ifdef CONFIG_CPU_SUBTYPE_SH7763
665/* SH7763 has endian control register */
666#define swaps(x, y)
667#else
Nobuhiro Iwamatsu86a74ff2008-06-09 16:33:56 -0700668static void swaps(char *src, int len)
669{
670#ifdef __LITTLE_ENDIAN__
671 u32 *p = (u32 *)src;
672 u32 *maxp;
673 maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
674
675 for (; p < maxp; p++)
676 *p = swab32(*p);
677#endif
678}
Nobuhiro Iwamatsub0ca2a22008-06-30 11:08:17 +0900679#endif /* CONFIG_CPU_SUBTYPE_SH7763 */
Nobuhiro Iwamatsu0caa1162008-06-18 18:32:09 +0900680#endif