Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | #include <linux/firmware.h> |
| 24 | #include "drmP.h" |
| 25 | #include "amdgpu.h" |
| 26 | #include "amdgpu_gfx.h" |
| 27 | #include "vi.h" |
| 28 | #include "vid.h" |
| 29 | #include "amdgpu_ucode.h" |
| 30 | #include "clearstate_vi.h" |
| 31 | |
| 32 | #include "gmc/gmc_8_2_d.h" |
| 33 | #include "gmc/gmc_8_2_sh_mask.h" |
| 34 | |
| 35 | #include "oss/oss_3_0_d.h" |
| 36 | #include "oss/oss_3_0_sh_mask.h" |
| 37 | |
| 38 | #include "bif/bif_5_0_d.h" |
| 39 | #include "bif/bif_5_0_sh_mask.h" |
| 40 | |
| 41 | #include "gca/gfx_8_0_d.h" |
| 42 | #include "gca/gfx_8_0_enum.h" |
| 43 | #include "gca/gfx_8_0_sh_mask.h" |
| 44 | #include "gca/gfx_8_0_enum.h" |
| 45 | |
| 46 | #include "uvd/uvd_5_0_d.h" |
| 47 | #include "uvd/uvd_5_0_sh_mask.h" |
| 48 | |
| 49 | #include "dce/dce_10_0_d.h" |
| 50 | #include "dce/dce_10_0_sh_mask.h" |
| 51 | |
| 52 | #define GFX8_NUM_GFX_RINGS 1 |
| 53 | #define GFX8_NUM_COMPUTE_RINGS 8 |
| 54 | |
| 55 | #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 |
| 56 | #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 |
| 57 | #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003 |
| 58 | |
| 59 | #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) |
| 60 | #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) |
| 61 | #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) |
| 62 | #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT) |
| 63 | #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) |
| 64 | #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT) |
| 65 | #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT) |
| 66 | #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT) |
| 67 | #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT) |
| 68 | |
Jammy Zhou | c65444f | 2015-05-13 22:49:04 +0800 | [diff] [blame] | 69 | MODULE_FIRMWARE("amdgpu/carrizo_ce.bin"); |
| 70 | MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin"); |
| 71 | MODULE_FIRMWARE("amdgpu/carrizo_me.bin"); |
| 72 | MODULE_FIRMWARE("amdgpu/carrizo_mec.bin"); |
| 73 | MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin"); |
| 74 | MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin"); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 75 | |
Jammy Zhou | c65444f | 2015-05-13 22:49:04 +0800 | [diff] [blame] | 76 | MODULE_FIRMWARE("amdgpu/tonga_ce.bin"); |
| 77 | MODULE_FIRMWARE("amdgpu/tonga_pfp.bin"); |
| 78 | MODULE_FIRMWARE("amdgpu/tonga_me.bin"); |
| 79 | MODULE_FIRMWARE("amdgpu/tonga_mec.bin"); |
| 80 | MODULE_FIRMWARE("amdgpu/tonga_mec2.bin"); |
| 81 | MODULE_FIRMWARE("amdgpu/tonga_rlc.bin"); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 82 | |
Jammy Zhou | c65444f | 2015-05-13 22:49:04 +0800 | [diff] [blame] | 83 | MODULE_FIRMWARE("amdgpu/topaz_ce.bin"); |
| 84 | MODULE_FIRMWARE("amdgpu/topaz_pfp.bin"); |
| 85 | MODULE_FIRMWARE("amdgpu/topaz_me.bin"); |
| 86 | MODULE_FIRMWARE("amdgpu/topaz_mec.bin"); |
| 87 | MODULE_FIRMWARE("amdgpu/topaz_mec2.bin"); |
| 88 | MODULE_FIRMWARE("amdgpu/topaz_rlc.bin"); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 89 | |
David Zhang | af15a2d | 2015-07-30 19:42:11 -0400 | [diff] [blame^] | 90 | MODULE_FIRMWARE("amdgpu/fiji_ce.bin"); |
| 91 | MODULE_FIRMWARE("amdgpu/fiji_pfp.bin"); |
| 92 | MODULE_FIRMWARE("amdgpu/fiji_me.bin"); |
| 93 | MODULE_FIRMWARE("amdgpu/fiji_mec.bin"); |
| 94 | MODULE_FIRMWARE("amdgpu/fiji_mec2.bin"); |
| 95 | MODULE_FIRMWARE("amdgpu/fiji_rlc.bin"); |
| 96 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 97 | static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = |
| 98 | { |
| 99 | {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, |
| 100 | {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, |
| 101 | {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, |
| 102 | {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, |
| 103 | {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, |
| 104 | {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, |
| 105 | {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, |
| 106 | {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, |
| 107 | {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, |
| 108 | {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, |
| 109 | {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, |
| 110 | {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, |
| 111 | {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, |
| 112 | {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, |
| 113 | {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, |
| 114 | {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} |
| 115 | }; |
| 116 | |
| 117 | static const u32 golden_settings_tonga_a11[] = |
| 118 | { |
| 119 | mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208, |
| 120 | mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, |
| 121 | mmDB_DEBUG2, 0xf00fffff, 0x00000400, |
| 122 | mmGB_GPU_ID, 0x0000000f, 0x00000000, |
| 123 | mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, |
| 124 | mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc, |
| 125 | mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, |
Alex Deucher | 6a00a09 | 2015-06-09 14:33:03 -0400 | [diff] [blame] | 126 | mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 127 | mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, |
| 128 | mmTCC_CTRL, 0x00100000, 0xf31fff7f, |
Alex Deucher | 6a00a09 | 2015-06-09 14:33:03 -0400 | [diff] [blame] | 129 | mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 130 | mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb, |
| 131 | mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, |
| 132 | mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, |
Alex Deucher | 6a00a09 | 2015-06-09 14:33:03 -0400 | [diff] [blame] | 133 | mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 134 | }; |
| 135 | |
| 136 | static const u32 tonga_golden_common_all[] = |
| 137 | { |
| 138 | mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| 139 | mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, |
| 140 | mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A, |
| 141 | mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, |
| 142 | mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, |
| 143 | mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, |
| 144 | mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, |
| 145 | mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF |
| 146 | }; |
| 147 | |
| 148 | static const u32 tonga_mgcg_cgcg_init[] = |
| 149 | { |
| 150 | mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, |
| 151 | mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| 152 | mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| 153 | mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, |
| 154 | mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, |
| 155 | mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 156 | mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, |
| 157 | mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, |
| 158 | mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, |
| 159 | mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, |
| 160 | mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, |
| 161 | mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 162 | mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 163 | mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 164 | mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, |
| 165 | mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, |
| 166 | mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, |
| 167 | mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, |
| 168 | mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, |
| 169 | mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, |
| 170 | mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, |
| 171 | mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, |
| 172 | mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, |
| 173 | mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, |
| 174 | mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, |
| 175 | mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, |
| 176 | mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, |
| 177 | mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| 178 | mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| 179 | mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, |
| 180 | mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| 181 | mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 182 | mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 183 | mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, |
| 184 | mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 185 | mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 186 | mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 187 | mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 188 | mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 189 | mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 190 | mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 191 | mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 192 | mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 193 | mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 194 | mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 195 | mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 196 | mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 197 | mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 198 | mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 199 | mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 200 | mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 201 | mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 202 | mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 203 | mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, |
| 204 | mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 205 | mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 206 | mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 207 | mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 208 | mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 209 | mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 210 | mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 211 | mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 212 | mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 213 | mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 214 | mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 215 | mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 216 | mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 217 | mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 218 | mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 219 | mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 220 | mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 221 | mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, |
| 222 | mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, |
| 223 | mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, |
| 224 | mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, |
| 225 | }; |
| 226 | |
David Zhang | af15a2d | 2015-07-30 19:42:11 -0400 | [diff] [blame^] | 227 | static const u32 fiji_golden_common_all[] = |
| 228 | { |
| 229 | mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| 230 | mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a, |
| 231 | mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e, |
| 232 | mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003, |
| 233 | mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, |
| 234 | mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, |
| 235 | mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, |
| 236 | mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF |
| 237 | }; |
| 238 | |
| 239 | static const u32 golden_settings_fiji_a10[] = |
| 240 | { |
| 241 | mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, |
| 242 | mmDB_DEBUG2, 0xf00fffff, 0x00000400, |
| 243 | mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, |
| 244 | mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x00000100, |
| 245 | mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, |
| 246 | mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, |
| 247 | mmTCC_CTRL, 0x00100000, 0xf30fff7f, |
| 248 | mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff, |
| 249 | mmTCP_CHAN_STEER_HI, 0xffffffff, 0x7d6cf5e4, |
| 250 | mmTCP_CHAN_STEER_LO, 0xffffffff, 0x3928b1a0, |
| 251 | }; |
| 252 | |
| 253 | static const u32 fiji_mgcg_cgcg_init[] = |
| 254 | { |
| 255 | mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffc0, |
| 256 | mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| 257 | mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| 258 | mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, |
| 259 | mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, |
| 260 | mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 261 | mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, |
| 262 | mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, |
| 263 | mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, |
| 264 | mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, |
| 265 | mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, |
| 266 | mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 267 | mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 268 | mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 269 | mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, |
| 270 | mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, |
| 271 | mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, |
| 272 | mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, |
| 273 | mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, |
| 274 | mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, |
| 275 | mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, |
| 276 | mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, |
| 277 | mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, |
| 278 | mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, |
| 279 | mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, |
| 280 | mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, |
| 281 | mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, |
| 282 | mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| 283 | mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| 284 | mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, |
| 285 | mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| 286 | mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, |
| 287 | mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, |
| 288 | mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, |
| 289 | mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, |
| 290 | }; |
| 291 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 292 | static const u32 golden_settings_iceland_a11[] = |
| 293 | { |
| 294 | mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, |
| 295 | mmDB_DEBUG2, 0xf00fffff, 0x00000400, |
| 296 | mmDB_DEBUG3, 0xc0000000, 0xc0000000, |
| 297 | mmGB_GPU_ID, 0x0000000f, 0x00000000, |
| 298 | mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, |
| 299 | mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, |
| 300 | mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002, |
| 301 | mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000, |
Alex Deucher | 6a00a09 | 2015-06-09 14:33:03 -0400 | [diff] [blame] | 302 | mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 303 | mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, |
| 304 | mmTCC_CTRL, 0x00100000, 0xf31fff7f, |
Alex Deucher | 6a00a09 | 2015-06-09 14:33:03 -0400 | [diff] [blame] | 305 | mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 306 | mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1, |
| 307 | mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, |
| 308 | mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010, |
| 309 | }; |
| 310 | |
| 311 | static const u32 iceland_golden_common_all[] = |
| 312 | { |
| 313 | mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| 314 | mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002, |
| 315 | mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, |
| 316 | mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001, |
| 317 | mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, |
| 318 | mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, |
| 319 | mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, |
| 320 | mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF |
| 321 | }; |
| 322 | |
| 323 | static const u32 iceland_mgcg_cgcg_init[] = |
| 324 | { |
| 325 | mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, |
| 326 | mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| 327 | mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| 328 | mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, |
| 329 | mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100, |
| 330 | mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100, |
| 331 | mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100, |
| 332 | mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, |
| 333 | mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, |
| 334 | mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, |
| 335 | mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, |
| 336 | mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 337 | mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 338 | mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 339 | mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, |
| 340 | mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, |
| 341 | mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, |
| 342 | mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, |
| 343 | mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, |
| 344 | mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, |
| 345 | mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, |
| 346 | mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, |
| 347 | mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100, |
| 348 | mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, |
| 349 | mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, |
| 350 | mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, |
| 351 | mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, |
| 352 | mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| 353 | mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| 354 | mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, |
| 355 | mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| 356 | mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 357 | mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 358 | mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, |
| 359 | mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 360 | mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 361 | mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 362 | mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 363 | mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 364 | mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 365 | mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 366 | mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 367 | mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 368 | mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 369 | mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 370 | mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 371 | mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 372 | mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 373 | mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 374 | mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 375 | mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 376 | mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 377 | mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 378 | mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, |
| 379 | mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 380 | mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 381 | mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 382 | mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 383 | mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 384 | mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 385 | mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 386 | mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, |
| 387 | mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, |
| 388 | mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, |
| 389 | }; |
| 390 | |
| 391 | static const u32 cz_golden_settings_a11[] = |
| 392 | { |
| 393 | mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, |
| 394 | mmDB_DEBUG2, 0xf00fffff, 0x00000400, |
| 395 | mmGB_GPU_ID, 0x0000000f, 0x00000000, |
| 396 | mmPA_SC_ENHANCE, 0xffffffff, 0x00000001, |
| 397 | mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, |
Alex Deucher | 6a00a09 | 2015-06-09 14:33:03 -0400 | [diff] [blame] | 398 | mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 399 | mmTA_CNTL_AUX, 0x000f000f, 0x00010000, |
Alex Deucher | 6a00a09 | 2015-06-09 14:33:03 -0400 | [diff] [blame] | 400 | mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 401 | mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3, |
| 402 | mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302 |
| 403 | }; |
| 404 | |
| 405 | static const u32 cz_golden_common_all[] = |
| 406 | { |
| 407 | mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| 408 | mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002, |
| 409 | mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, |
| 410 | mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001, |
| 411 | mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, |
| 412 | mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, |
| 413 | mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, |
| 414 | mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF |
| 415 | }; |
| 416 | |
| 417 | static const u32 cz_mgcg_cgcg_init[] = |
| 418 | { |
| 419 | mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, |
| 420 | mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| 421 | mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| 422 | mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, |
| 423 | mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, |
| 424 | mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 425 | mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100, |
| 426 | mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, |
| 427 | mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, |
| 428 | mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, |
| 429 | mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, |
| 430 | mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 431 | mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 432 | mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, |
| 433 | mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, |
| 434 | mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, |
| 435 | mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, |
| 436 | mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, |
| 437 | mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, |
| 438 | mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, |
| 439 | mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, |
| 440 | mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, |
| 441 | mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, |
| 442 | mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, |
| 443 | mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, |
| 444 | mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, |
| 445 | mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, |
| 446 | mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| 447 | mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, |
| 448 | mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, |
| 449 | mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, |
| 450 | mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 451 | mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 452 | mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, |
| 453 | mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 454 | mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 455 | mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 456 | mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 457 | mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 458 | mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 459 | mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 460 | mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 461 | mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 462 | mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 463 | mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 464 | mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 465 | mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 466 | mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 467 | mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 468 | mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 469 | mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 470 | mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 471 | mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 472 | mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, |
| 473 | mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 474 | mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 475 | mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 476 | mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 477 | mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 478 | mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 479 | mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 480 | mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 481 | mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 482 | mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 483 | mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 484 | mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 485 | mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, |
| 486 | mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, |
| 487 | mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, |
| 488 | mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, |
| 489 | mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, |
| 490 | mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, |
| 491 | mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, |
| 492 | mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, |
| 493 | mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, |
| 494 | }; |
| 495 | |
| 496 | static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev); |
| 497 | static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev); |
| 498 | static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev); |
| 499 | |
| 500 | static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) |
| 501 | { |
| 502 | switch (adev->asic_type) { |
| 503 | case CHIP_TOPAZ: |
| 504 | amdgpu_program_register_sequence(adev, |
| 505 | iceland_mgcg_cgcg_init, |
| 506 | (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); |
| 507 | amdgpu_program_register_sequence(adev, |
| 508 | golden_settings_iceland_a11, |
| 509 | (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); |
| 510 | amdgpu_program_register_sequence(adev, |
| 511 | iceland_golden_common_all, |
| 512 | (const u32)ARRAY_SIZE(iceland_golden_common_all)); |
| 513 | break; |
David Zhang | af15a2d | 2015-07-30 19:42:11 -0400 | [diff] [blame^] | 514 | case CHIP_FIJI: |
| 515 | amdgpu_program_register_sequence(adev, |
| 516 | fiji_mgcg_cgcg_init, |
| 517 | (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); |
| 518 | amdgpu_program_register_sequence(adev, |
| 519 | golden_settings_fiji_a10, |
| 520 | (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); |
| 521 | amdgpu_program_register_sequence(adev, |
| 522 | fiji_golden_common_all, |
| 523 | (const u32)ARRAY_SIZE(fiji_golden_common_all)); |
| 524 | break; |
| 525 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 526 | case CHIP_TONGA: |
| 527 | amdgpu_program_register_sequence(adev, |
| 528 | tonga_mgcg_cgcg_init, |
| 529 | (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); |
| 530 | amdgpu_program_register_sequence(adev, |
| 531 | golden_settings_tonga_a11, |
| 532 | (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); |
| 533 | amdgpu_program_register_sequence(adev, |
| 534 | tonga_golden_common_all, |
| 535 | (const u32)ARRAY_SIZE(tonga_golden_common_all)); |
| 536 | break; |
| 537 | case CHIP_CARRIZO: |
| 538 | amdgpu_program_register_sequence(adev, |
| 539 | cz_mgcg_cgcg_init, |
| 540 | (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); |
| 541 | amdgpu_program_register_sequence(adev, |
| 542 | cz_golden_settings_a11, |
| 543 | (const u32)ARRAY_SIZE(cz_golden_settings_a11)); |
| 544 | amdgpu_program_register_sequence(adev, |
| 545 | cz_golden_common_all, |
| 546 | (const u32)ARRAY_SIZE(cz_golden_common_all)); |
| 547 | break; |
| 548 | default: |
| 549 | break; |
| 550 | } |
| 551 | } |
| 552 | |
| 553 | static void gfx_v8_0_scratch_init(struct amdgpu_device *adev) |
| 554 | { |
| 555 | int i; |
| 556 | |
| 557 | adev->gfx.scratch.num_reg = 7; |
| 558 | adev->gfx.scratch.reg_base = mmSCRATCH_REG0; |
| 559 | for (i = 0; i < adev->gfx.scratch.num_reg; i++) { |
| 560 | adev->gfx.scratch.free[i] = true; |
| 561 | adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; |
| 562 | } |
| 563 | } |
| 564 | |
| 565 | static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring) |
| 566 | { |
| 567 | struct amdgpu_device *adev = ring->adev; |
| 568 | uint32_t scratch; |
| 569 | uint32_t tmp = 0; |
| 570 | unsigned i; |
| 571 | int r; |
| 572 | |
| 573 | r = amdgpu_gfx_scratch_get(adev, &scratch); |
| 574 | if (r) { |
| 575 | DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); |
| 576 | return r; |
| 577 | } |
| 578 | WREG32(scratch, 0xCAFEDEAD); |
| 579 | r = amdgpu_ring_lock(ring, 3); |
| 580 | if (r) { |
| 581 | DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", |
| 582 | ring->idx, r); |
| 583 | amdgpu_gfx_scratch_free(adev, scratch); |
| 584 | return r; |
| 585 | } |
| 586 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); |
| 587 | amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); |
| 588 | amdgpu_ring_write(ring, 0xDEADBEEF); |
| 589 | amdgpu_ring_unlock_commit(ring); |
| 590 | |
| 591 | for (i = 0; i < adev->usec_timeout; i++) { |
| 592 | tmp = RREG32(scratch); |
| 593 | if (tmp == 0xDEADBEEF) |
| 594 | break; |
| 595 | DRM_UDELAY(1); |
| 596 | } |
| 597 | if (i < adev->usec_timeout) { |
| 598 | DRM_INFO("ring test on %d succeeded in %d usecs\n", |
| 599 | ring->idx, i); |
| 600 | } else { |
| 601 | DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", |
| 602 | ring->idx, scratch, tmp); |
| 603 | r = -EINVAL; |
| 604 | } |
| 605 | amdgpu_gfx_scratch_free(adev, scratch); |
| 606 | return r; |
| 607 | } |
| 608 | |
| 609 | static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring) |
| 610 | { |
| 611 | struct amdgpu_device *adev = ring->adev; |
| 612 | struct amdgpu_ib ib; |
| 613 | uint32_t scratch; |
| 614 | uint32_t tmp = 0; |
| 615 | unsigned i; |
| 616 | int r; |
| 617 | |
| 618 | r = amdgpu_gfx_scratch_get(adev, &scratch); |
| 619 | if (r) { |
| 620 | DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r); |
| 621 | return r; |
| 622 | } |
| 623 | WREG32(scratch, 0xCAFEDEAD); |
| 624 | r = amdgpu_ib_get(ring, NULL, 256, &ib); |
| 625 | if (r) { |
| 626 | DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); |
| 627 | amdgpu_gfx_scratch_free(adev, scratch); |
| 628 | return r; |
| 629 | } |
| 630 | ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); |
| 631 | ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); |
| 632 | ib.ptr[2] = 0xDEADBEEF; |
| 633 | ib.length_dw = 3; |
| 634 | r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); |
| 635 | if (r) { |
| 636 | amdgpu_gfx_scratch_free(adev, scratch); |
| 637 | amdgpu_ib_free(adev, &ib); |
| 638 | DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); |
| 639 | return r; |
| 640 | } |
| 641 | r = amdgpu_fence_wait(ib.fence, false); |
| 642 | if (r) { |
| 643 | DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); |
| 644 | amdgpu_gfx_scratch_free(adev, scratch); |
| 645 | amdgpu_ib_free(adev, &ib); |
| 646 | return r; |
| 647 | } |
| 648 | for (i = 0; i < adev->usec_timeout; i++) { |
| 649 | tmp = RREG32(scratch); |
| 650 | if (tmp == 0xDEADBEEF) |
| 651 | break; |
| 652 | DRM_UDELAY(1); |
| 653 | } |
| 654 | if (i < adev->usec_timeout) { |
| 655 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", |
| 656 | ib.fence->ring->idx, i); |
| 657 | } else { |
| 658 | DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", |
| 659 | scratch, tmp); |
| 660 | r = -EINVAL; |
| 661 | } |
| 662 | amdgpu_gfx_scratch_free(adev, scratch); |
| 663 | amdgpu_ib_free(adev, &ib); |
| 664 | return r; |
| 665 | } |
| 666 | |
| 667 | static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) |
| 668 | { |
| 669 | const char *chip_name; |
| 670 | char fw_name[30]; |
| 671 | int err; |
| 672 | struct amdgpu_firmware_info *info = NULL; |
| 673 | const struct common_firmware_header *header = NULL; |
Jammy Zhou | 595fd01 | 2015-08-04 11:44:19 +0800 | [diff] [blame] | 674 | const struct gfx_firmware_header_v1_0 *cp_hdr; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 675 | |
| 676 | DRM_DEBUG("\n"); |
| 677 | |
| 678 | switch (adev->asic_type) { |
| 679 | case CHIP_TOPAZ: |
| 680 | chip_name = "topaz"; |
| 681 | break; |
| 682 | case CHIP_TONGA: |
| 683 | chip_name = "tonga"; |
| 684 | break; |
| 685 | case CHIP_CARRIZO: |
| 686 | chip_name = "carrizo"; |
| 687 | break; |
David Zhang | af15a2d | 2015-07-30 19:42:11 -0400 | [diff] [blame^] | 688 | case CHIP_FIJI: |
| 689 | chip_name = "fiji"; |
| 690 | break; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 691 | default: |
| 692 | BUG(); |
| 693 | } |
| 694 | |
Jammy Zhou | c65444f | 2015-05-13 22:49:04 +0800 | [diff] [blame] | 695 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 696 | err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); |
| 697 | if (err) |
| 698 | goto out; |
| 699 | err = amdgpu_ucode_validate(adev->gfx.pfp_fw); |
| 700 | if (err) |
| 701 | goto out; |
Jammy Zhou | 595fd01 | 2015-08-04 11:44:19 +0800 | [diff] [blame] | 702 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; |
| 703 | adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); |
| 704 | adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 705 | |
Jammy Zhou | c65444f | 2015-05-13 22:49:04 +0800 | [diff] [blame] | 706 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 707 | err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); |
| 708 | if (err) |
| 709 | goto out; |
| 710 | err = amdgpu_ucode_validate(adev->gfx.me_fw); |
| 711 | if (err) |
| 712 | goto out; |
Jammy Zhou | 595fd01 | 2015-08-04 11:44:19 +0800 | [diff] [blame] | 713 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; |
| 714 | adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); |
| 715 | adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 716 | |
Jammy Zhou | c65444f | 2015-05-13 22:49:04 +0800 | [diff] [blame] | 717 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 718 | err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); |
| 719 | if (err) |
| 720 | goto out; |
| 721 | err = amdgpu_ucode_validate(adev->gfx.ce_fw); |
| 722 | if (err) |
| 723 | goto out; |
Jammy Zhou | 595fd01 | 2015-08-04 11:44:19 +0800 | [diff] [blame] | 724 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; |
| 725 | adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); |
| 726 | adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 727 | |
Jammy Zhou | c65444f | 2015-05-13 22:49:04 +0800 | [diff] [blame] | 728 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 729 | err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); |
| 730 | if (err) |
| 731 | goto out; |
| 732 | err = amdgpu_ucode_validate(adev->gfx.rlc_fw); |
Jammy Zhou | 595fd01 | 2015-08-04 11:44:19 +0800 | [diff] [blame] | 733 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; |
| 734 | adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); |
| 735 | adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 736 | |
Jammy Zhou | c65444f | 2015-05-13 22:49:04 +0800 | [diff] [blame] | 737 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 738 | err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); |
| 739 | if (err) |
| 740 | goto out; |
| 741 | err = amdgpu_ucode_validate(adev->gfx.mec_fw); |
| 742 | if (err) |
| 743 | goto out; |
Jammy Zhou | 595fd01 | 2015-08-04 11:44:19 +0800 | [diff] [blame] | 744 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; |
| 745 | adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); |
| 746 | adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 747 | |
Jammy Zhou | c65444f | 2015-05-13 22:49:04 +0800 | [diff] [blame] | 748 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 749 | err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); |
| 750 | if (!err) { |
| 751 | err = amdgpu_ucode_validate(adev->gfx.mec2_fw); |
| 752 | if (err) |
| 753 | goto out; |
Jammy Zhou | 595fd01 | 2015-08-04 11:44:19 +0800 | [diff] [blame] | 754 | cp_hdr = (const struct gfx_firmware_header_v1_0 *) |
| 755 | adev->gfx.mec2_fw->data; |
| 756 | adev->gfx.mec2_fw_version = le32_to_cpu( |
| 757 | cp_hdr->header.ucode_version); |
| 758 | adev->gfx.mec2_feature_version = le32_to_cpu( |
| 759 | cp_hdr->ucode_feature_version); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 760 | } else { |
| 761 | err = 0; |
| 762 | adev->gfx.mec2_fw = NULL; |
| 763 | } |
| 764 | |
| 765 | if (adev->firmware.smu_load) { |
| 766 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; |
| 767 | info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; |
| 768 | info->fw = adev->gfx.pfp_fw; |
| 769 | header = (const struct common_firmware_header *)info->fw->data; |
| 770 | adev->firmware.fw_size += |
| 771 | ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); |
| 772 | |
| 773 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; |
| 774 | info->ucode_id = AMDGPU_UCODE_ID_CP_ME; |
| 775 | info->fw = adev->gfx.me_fw; |
| 776 | header = (const struct common_firmware_header *)info->fw->data; |
| 777 | adev->firmware.fw_size += |
| 778 | ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); |
| 779 | |
| 780 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; |
| 781 | info->ucode_id = AMDGPU_UCODE_ID_CP_CE; |
| 782 | info->fw = adev->gfx.ce_fw; |
| 783 | header = (const struct common_firmware_header *)info->fw->data; |
| 784 | adev->firmware.fw_size += |
| 785 | ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); |
| 786 | |
| 787 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; |
| 788 | info->ucode_id = AMDGPU_UCODE_ID_RLC_G; |
| 789 | info->fw = adev->gfx.rlc_fw; |
| 790 | header = (const struct common_firmware_header *)info->fw->data; |
| 791 | adev->firmware.fw_size += |
| 792 | ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); |
| 793 | |
| 794 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; |
| 795 | info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; |
| 796 | info->fw = adev->gfx.mec_fw; |
| 797 | header = (const struct common_firmware_header *)info->fw->data; |
| 798 | adev->firmware.fw_size += |
| 799 | ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); |
| 800 | |
| 801 | if (adev->gfx.mec2_fw) { |
| 802 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; |
| 803 | info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; |
| 804 | info->fw = adev->gfx.mec2_fw; |
| 805 | header = (const struct common_firmware_header *)info->fw->data; |
| 806 | adev->firmware.fw_size += |
| 807 | ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); |
| 808 | } |
| 809 | |
| 810 | } |
| 811 | |
| 812 | out: |
| 813 | if (err) { |
| 814 | dev_err(adev->dev, |
| 815 | "gfx8: Failed to load firmware \"%s\"\n", |
| 816 | fw_name); |
| 817 | release_firmware(adev->gfx.pfp_fw); |
| 818 | adev->gfx.pfp_fw = NULL; |
| 819 | release_firmware(adev->gfx.me_fw); |
| 820 | adev->gfx.me_fw = NULL; |
| 821 | release_firmware(adev->gfx.ce_fw); |
| 822 | adev->gfx.ce_fw = NULL; |
| 823 | release_firmware(adev->gfx.rlc_fw); |
| 824 | adev->gfx.rlc_fw = NULL; |
| 825 | release_firmware(adev->gfx.mec_fw); |
| 826 | adev->gfx.mec_fw = NULL; |
| 827 | release_firmware(adev->gfx.mec2_fw); |
| 828 | adev->gfx.mec2_fw = NULL; |
| 829 | } |
| 830 | return err; |
| 831 | } |
| 832 | |
| 833 | static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) |
| 834 | { |
| 835 | int r; |
| 836 | |
| 837 | if (adev->gfx.mec.hpd_eop_obj) { |
| 838 | r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); |
| 839 | if (unlikely(r != 0)) |
| 840 | dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); |
| 841 | amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); |
| 842 | amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); |
| 843 | |
| 844 | amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); |
| 845 | adev->gfx.mec.hpd_eop_obj = NULL; |
| 846 | } |
| 847 | } |
| 848 | |
| 849 | #define MEC_HPD_SIZE 2048 |
| 850 | |
| 851 | static int gfx_v8_0_mec_init(struct amdgpu_device *adev) |
| 852 | { |
| 853 | int r; |
| 854 | u32 *hpd; |
| 855 | |
| 856 | /* |
| 857 | * we assign only 1 pipe because all other pipes will |
| 858 | * be handled by KFD |
| 859 | */ |
| 860 | adev->gfx.mec.num_mec = 1; |
| 861 | adev->gfx.mec.num_pipe = 1; |
| 862 | adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; |
| 863 | |
| 864 | if (adev->gfx.mec.hpd_eop_obj == NULL) { |
| 865 | r = amdgpu_bo_create(adev, |
| 866 | adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, |
| 867 | PAGE_SIZE, true, |
| 868 | AMDGPU_GEM_DOMAIN_GTT, 0, NULL, |
| 869 | &adev->gfx.mec.hpd_eop_obj); |
| 870 | if (r) { |
| 871 | dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); |
| 872 | return r; |
| 873 | } |
| 874 | } |
| 875 | |
| 876 | r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); |
| 877 | if (unlikely(r != 0)) { |
| 878 | gfx_v8_0_mec_fini(adev); |
| 879 | return r; |
| 880 | } |
| 881 | r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, |
| 882 | &adev->gfx.mec.hpd_eop_gpu_addr); |
| 883 | if (r) { |
| 884 | dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); |
| 885 | gfx_v8_0_mec_fini(adev); |
| 886 | return r; |
| 887 | } |
| 888 | r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); |
| 889 | if (r) { |
| 890 | dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); |
| 891 | gfx_v8_0_mec_fini(adev); |
| 892 | return r; |
| 893 | } |
| 894 | |
| 895 | memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); |
| 896 | |
| 897 | amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); |
| 898 | amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); |
| 899 | |
| 900 | return 0; |
| 901 | } |
| 902 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 903 | static int gfx_v8_0_sw_init(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 904 | { |
| 905 | int i, r; |
| 906 | struct amdgpu_ring *ring; |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 907 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 908 | |
| 909 | /* EOP Event */ |
| 910 | r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); |
| 911 | if (r) |
| 912 | return r; |
| 913 | |
| 914 | /* Privileged reg */ |
| 915 | r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); |
| 916 | if (r) |
| 917 | return r; |
| 918 | |
| 919 | /* Privileged inst */ |
| 920 | r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); |
| 921 | if (r) |
| 922 | return r; |
| 923 | |
| 924 | adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; |
| 925 | |
| 926 | gfx_v8_0_scratch_init(adev); |
| 927 | |
| 928 | r = gfx_v8_0_init_microcode(adev); |
| 929 | if (r) { |
| 930 | DRM_ERROR("Failed to load gfx firmware!\n"); |
| 931 | return r; |
| 932 | } |
| 933 | |
| 934 | r = gfx_v8_0_mec_init(adev); |
| 935 | if (r) { |
| 936 | DRM_ERROR("Failed to init MEC BOs!\n"); |
| 937 | return r; |
| 938 | } |
| 939 | |
| 940 | r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs); |
| 941 | if (r) { |
| 942 | DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r); |
| 943 | return r; |
| 944 | } |
| 945 | |
| 946 | /* set up the gfx ring */ |
| 947 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) { |
| 948 | ring = &adev->gfx.gfx_ring[i]; |
| 949 | ring->ring_obj = NULL; |
| 950 | sprintf(ring->name, "gfx"); |
| 951 | /* no gfx doorbells on iceland */ |
| 952 | if (adev->asic_type != CHIP_TOPAZ) { |
| 953 | ring->use_doorbell = true; |
| 954 | ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0; |
| 955 | } |
| 956 | |
| 957 | r = amdgpu_ring_init(adev, ring, 1024 * 1024, |
| 958 | PACKET3(PACKET3_NOP, 0x3FFF), 0xf, |
| 959 | &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, |
| 960 | AMDGPU_RING_TYPE_GFX); |
| 961 | if (r) |
| 962 | return r; |
| 963 | } |
| 964 | |
| 965 | /* set up the compute queues */ |
| 966 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
| 967 | unsigned irq_type; |
| 968 | |
| 969 | /* max 32 queues per MEC */ |
| 970 | if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { |
| 971 | DRM_ERROR("Too many (%d) compute rings!\n", i); |
| 972 | break; |
| 973 | } |
| 974 | ring = &adev->gfx.compute_ring[i]; |
| 975 | ring->ring_obj = NULL; |
| 976 | ring->use_doorbell = true; |
| 977 | ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i; |
| 978 | ring->me = 1; /* first MEC */ |
| 979 | ring->pipe = i / 8; |
| 980 | ring->queue = i % 8; |
| 981 | sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); |
| 982 | irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; |
| 983 | /* type-2 packets are deprecated on MEC, use type-3 instead */ |
| 984 | r = amdgpu_ring_init(adev, ring, 1024 * 1024, |
| 985 | PACKET3(PACKET3_NOP, 0x3FFF), 0xf, |
| 986 | &adev->gfx.eop_irq, irq_type, |
| 987 | AMDGPU_RING_TYPE_COMPUTE); |
| 988 | if (r) |
| 989 | return r; |
| 990 | } |
| 991 | |
| 992 | /* reserve GDS, GWS and OA resource for gfx */ |
| 993 | r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size, |
| 994 | PAGE_SIZE, true, |
| 995 | AMDGPU_GEM_DOMAIN_GDS, 0, |
| 996 | NULL, &adev->gds.gds_gfx_bo); |
| 997 | if (r) |
| 998 | return r; |
| 999 | |
| 1000 | r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size, |
| 1001 | PAGE_SIZE, true, |
| 1002 | AMDGPU_GEM_DOMAIN_GWS, 0, |
| 1003 | NULL, &adev->gds.gws_gfx_bo); |
| 1004 | if (r) |
| 1005 | return r; |
| 1006 | |
| 1007 | r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size, |
| 1008 | PAGE_SIZE, true, |
| 1009 | AMDGPU_GEM_DOMAIN_OA, 0, |
| 1010 | NULL, &adev->gds.oa_gfx_bo); |
| 1011 | if (r) |
| 1012 | return r; |
| 1013 | |
Ken Wang | a101a89 | 2015-06-03 17:47:54 +0800 | [diff] [blame] | 1014 | adev->gfx.ce_ram_size = 0x8000; |
| 1015 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 1016 | return 0; |
| 1017 | } |
| 1018 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 1019 | static int gfx_v8_0_sw_fini(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 1020 | { |
| 1021 | int i; |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 1022 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 1023 | |
| 1024 | amdgpu_bo_unref(&adev->gds.oa_gfx_bo); |
| 1025 | amdgpu_bo_unref(&adev->gds.gws_gfx_bo); |
| 1026 | amdgpu_bo_unref(&adev->gds.gds_gfx_bo); |
| 1027 | |
| 1028 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
| 1029 | amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); |
| 1030 | for (i = 0; i < adev->gfx.num_compute_rings; i++) |
| 1031 | amdgpu_ring_fini(&adev->gfx.compute_ring[i]); |
| 1032 | |
| 1033 | amdgpu_wb_free(adev, adev->gfx.ce_sync_offs); |
| 1034 | |
| 1035 | gfx_v8_0_mec_fini(adev); |
| 1036 | |
| 1037 | return 0; |
| 1038 | } |
| 1039 | |
| 1040 | static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) |
| 1041 | { |
| 1042 | const u32 num_tile_mode_states = 32; |
| 1043 | const u32 num_secondary_tile_mode_states = 16; |
| 1044 | u32 reg_offset, gb_tile_moden, split_equal_to_row_size; |
| 1045 | |
| 1046 | switch (adev->gfx.config.mem_row_size_in_kb) { |
| 1047 | case 1: |
| 1048 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; |
| 1049 | break; |
| 1050 | case 2: |
| 1051 | default: |
| 1052 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; |
| 1053 | break; |
| 1054 | case 4: |
| 1055 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; |
| 1056 | break; |
| 1057 | } |
| 1058 | |
| 1059 | switch (adev->asic_type) { |
| 1060 | case CHIP_TOPAZ: |
| 1061 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { |
| 1062 | switch (reg_offset) { |
| 1063 | case 0: |
| 1064 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1065 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1066 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | |
| 1067 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1068 | break; |
| 1069 | case 1: |
| 1070 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1071 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1072 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | |
| 1073 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1074 | break; |
| 1075 | case 2: |
| 1076 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1077 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1078 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| 1079 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1080 | break; |
| 1081 | case 3: |
| 1082 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1083 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1084 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | |
| 1085 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1086 | break; |
| 1087 | case 4: |
| 1088 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1089 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1090 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| 1091 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1092 | break; |
| 1093 | case 5: |
| 1094 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 1095 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1096 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| 1097 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1098 | break; |
| 1099 | case 6: |
| 1100 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1101 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1102 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| 1103 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1104 | break; |
| 1105 | case 8: |
| 1106 | gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | |
| 1107 | PIPE_CONFIG(ADDR_SURF_P2)); |
| 1108 | break; |
| 1109 | case 9: |
| 1110 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 1111 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1112 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 1113 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1114 | break; |
| 1115 | case 10: |
| 1116 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1117 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1118 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 1119 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1120 | break; |
| 1121 | case 11: |
| 1122 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1123 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1124 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 1125 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| 1126 | break; |
| 1127 | case 13: |
| 1128 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 1129 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1130 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1131 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1132 | break; |
| 1133 | case 14: |
| 1134 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1135 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1136 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1137 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1138 | break; |
| 1139 | case 15: |
| 1140 | gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | |
| 1141 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1142 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1143 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1144 | break; |
| 1145 | case 16: |
| 1146 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1147 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1148 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1149 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| 1150 | break; |
| 1151 | case 18: |
| 1152 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | |
| 1153 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1154 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1155 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1156 | break; |
| 1157 | case 19: |
| 1158 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | |
| 1159 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1160 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1161 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1162 | break; |
| 1163 | case 20: |
| 1164 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | |
| 1165 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1166 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1167 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1168 | break; |
| 1169 | case 21: |
| 1170 | gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | |
| 1171 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1172 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1173 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1174 | break; |
| 1175 | case 22: |
| 1176 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | |
| 1177 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1178 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1179 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1180 | break; |
| 1181 | case 24: |
| 1182 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | |
| 1183 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1184 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1185 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1186 | break; |
| 1187 | case 25: |
| 1188 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | |
| 1189 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1190 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1191 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1192 | break; |
| 1193 | case 26: |
| 1194 | gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | |
| 1195 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1196 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1197 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1198 | break; |
| 1199 | case 27: |
| 1200 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 1201 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1202 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 1203 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1204 | break; |
| 1205 | case 28: |
| 1206 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1207 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1208 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 1209 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1210 | break; |
| 1211 | case 29: |
| 1212 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1213 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1214 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 1215 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| 1216 | break; |
| 1217 | case 7: |
| 1218 | case 12: |
| 1219 | case 17: |
| 1220 | case 23: |
| 1221 | /* unused idx */ |
| 1222 | continue; |
| 1223 | default: |
| 1224 | gb_tile_moden = 0; |
| 1225 | break; |
| 1226 | }; |
| 1227 | adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; |
| 1228 | WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); |
| 1229 | } |
| 1230 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { |
| 1231 | switch (reg_offset) { |
| 1232 | case 0: |
| 1233 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | |
| 1234 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1235 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1236 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1237 | break; |
| 1238 | case 1: |
| 1239 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | |
| 1240 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1241 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1242 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1243 | break; |
| 1244 | case 2: |
| 1245 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | |
| 1246 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1247 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1248 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1249 | break; |
| 1250 | case 3: |
| 1251 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1252 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1253 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1254 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1255 | break; |
| 1256 | case 4: |
| 1257 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1258 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 1259 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1260 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1261 | break; |
| 1262 | case 5: |
| 1263 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1264 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1265 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1266 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1267 | break; |
| 1268 | case 6: |
| 1269 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1270 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1271 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1272 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1273 | break; |
| 1274 | case 8: |
| 1275 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | |
| 1276 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | |
| 1277 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1278 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1279 | break; |
| 1280 | case 9: |
| 1281 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | |
| 1282 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1283 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1284 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1285 | break; |
| 1286 | case 10: |
| 1287 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | |
| 1288 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1289 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1290 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1291 | break; |
| 1292 | case 11: |
| 1293 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | |
| 1294 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 1295 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1296 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1297 | break; |
| 1298 | case 12: |
| 1299 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1300 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 1301 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1302 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1303 | break; |
| 1304 | case 13: |
| 1305 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1306 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1307 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1308 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1309 | break; |
| 1310 | case 14: |
| 1311 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1312 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1313 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1314 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1315 | break; |
| 1316 | case 7: |
| 1317 | /* unused idx */ |
| 1318 | continue; |
| 1319 | default: |
| 1320 | gb_tile_moden = 0; |
| 1321 | break; |
| 1322 | }; |
| 1323 | adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; |
| 1324 | WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); |
| 1325 | } |
David Zhang | af15a2d | 2015-07-30 19:42:11 -0400 | [diff] [blame^] | 1326 | case CHIP_FIJI: |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 1327 | case CHIP_TONGA: |
| 1328 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { |
| 1329 | switch (reg_offset) { |
| 1330 | case 0: |
| 1331 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1332 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1333 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | |
| 1334 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1335 | break; |
| 1336 | case 1: |
| 1337 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1338 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1339 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | |
| 1340 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1341 | break; |
| 1342 | case 2: |
| 1343 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1344 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1345 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| 1346 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1347 | break; |
| 1348 | case 3: |
| 1349 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1350 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1351 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | |
| 1352 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1353 | break; |
| 1354 | case 4: |
| 1355 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1356 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1357 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| 1358 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1359 | break; |
| 1360 | case 5: |
| 1361 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 1362 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1363 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| 1364 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1365 | break; |
| 1366 | case 6: |
| 1367 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1368 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1369 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| 1370 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1371 | break; |
| 1372 | case 7: |
| 1373 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1374 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 1375 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| 1376 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1377 | break; |
| 1378 | case 8: |
| 1379 | gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | |
| 1380 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)); |
| 1381 | break; |
| 1382 | case 9: |
| 1383 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 1384 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1385 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 1386 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1387 | break; |
| 1388 | case 10: |
| 1389 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1390 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1391 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 1392 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1393 | break; |
| 1394 | case 11: |
| 1395 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1396 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1397 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 1398 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| 1399 | break; |
| 1400 | case 12: |
| 1401 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1402 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 1403 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 1404 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| 1405 | break; |
| 1406 | case 13: |
| 1407 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 1408 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1409 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1410 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1411 | break; |
| 1412 | case 14: |
| 1413 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1414 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1415 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1416 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1417 | break; |
| 1418 | case 15: |
| 1419 | gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | |
| 1420 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1421 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1422 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1423 | break; |
| 1424 | case 16: |
| 1425 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1426 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1427 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1428 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| 1429 | break; |
| 1430 | case 17: |
| 1431 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1432 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 1433 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1434 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| 1435 | break; |
| 1436 | case 18: |
| 1437 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | |
| 1438 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1439 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1440 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1441 | break; |
| 1442 | case 19: |
| 1443 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | |
| 1444 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1445 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1446 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1447 | break; |
| 1448 | case 20: |
| 1449 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | |
| 1450 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1451 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1452 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1453 | break; |
| 1454 | case 21: |
| 1455 | gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | |
| 1456 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1457 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1458 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1459 | break; |
| 1460 | case 22: |
| 1461 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | |
| 1462 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1463 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1464 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1465 | break; |
| 1466 | case 23: |
| 1467 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | |
| 1468 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 1469 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1470 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1471 | break; |
| 1472 | case 24: |
| 1473 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | |
| 1474 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1475 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1476 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1477 | break; |
| 1478 | case 25: |
| 1479 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | |
| 1480 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1481 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1482 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1483 | break; |
| 1484 | case 26: |
| 1485 | gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | |
| 1486 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1487 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1488 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1489 | break; |
| 1490 | case 27: |
| 1491 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 1492 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1493 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 1494 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1495 | break; |
| 1496 | case 28: |
| 1497 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1498 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1499 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 1500 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1501 | break; |
| 1502 | case 29: |
| 1503 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1504 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | |
| 1505 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 1506 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| 1507 | break; |
| 1508 | case 30: |
| 1509 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1510 | PIPE_CONFIG(ADDR_SURF_P4_16x16) | |
| 1511 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 1512 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| 1513 | break; |
| 1514 | default: |
| 1515 | gb_tile_moden = 0; |
| 1516 | break; |
| 1517 | }; |
| 1518 | adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; |
| 1519 | WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); |
| 1520 | } |
| 1521 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { |
| 1522 | switch (reg_offset) { |
| 1523 | case 0: |
| 1524 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1525 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1526 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1527 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1528 | break; |
| 1529 | case 1: |
| 1530 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1531 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1532 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1533 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1534 | break; |
| 1535 | case 2: |
| 1536 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1537 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1538 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1539 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1540 | break; |
| 1541 | case 3: |
| 1542 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1543 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1544 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1545 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1546 | break; |
| 1547 | case 4: |
| 1548 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1549 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 1550 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1551 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1552 | break; |
| 1553 | case 5: |
| 1554 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1555 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1556 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 1557 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1558 | break; |
| 1559 | case 6: |
| 1560 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1561 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1562 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 1563 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1564 | break; |
| 1565 | case 8: |
| 1566 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1567 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | |
| 1568 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1569 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1570 | break; |
| 1571 | case 9: |
| 1572 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1573 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1574 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1575 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1576 | break; |
| 1577 | case 10: |
| 1578 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1579 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 1580 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1581 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1582 | break; |
| 1583 | case 11: |
| 1584 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1585 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1586 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1587 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1588 | break; |
| 1589 | case 12: |
| 1590 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1591 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1592 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 1593 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1594 | break; |
| 1595 | case 13: |
| 1596 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1597 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1598 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 1599 | NUM_BANKS(ADDR_SURF_4_BANK)); |
| 1600 | break; |
| 1601 | case 14: |
| 1602 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1603 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1604 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | |
| 1605 | NUM_BANKS(ADDR_SURF_4_BANK)); |
| 1606 | break; |
| 1607 | case 7: |
| 1608 | /* unused idx */ |
| 1609 | continue; |
| 1610 | default: |
| 1611 | gb_tile_moden = 0; |
| 1612 | break; |
| 1613 | }; |
| 1614 | adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; |
| 1615 | WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); |
| 1616 | } |
| 1617 | break; |
| 1618 | case CHIP_CARRIZO: |
| 1619 | default: |
| 1620 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { |
| 1621 | switch (reg_offset) { |
| 1622 | case 0: |
| 1623 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1624 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1625 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | |
| 1626 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1627 | break; |
| 1628 | case 1: |
| 1629 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1630 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1631 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | |
| 1632 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1633 | break; |
| 1634 | case 2: |
| 1635 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1636 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1637 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | |
| 1638 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1639 | break; |
| 1640 | case 3: |
| 1641 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1642 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1643 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | |
| 1644 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1645 | break; |
| 1646 | case 4: |
| 1647 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1648 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1649 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| 1650 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1651 | break; |
| 1652 | case 5: |
| 1653 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 1654 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1655 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| 1656 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1657 | break; |
| 1658 | case 6: |
| 1659 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1660 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1661 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | |
| 1662 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); |
| 1663 | break; |
| 1664 | case 8: |
| 1665 | gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | |
| 1666 | PIPE_CONFIG(ADDR_SURF_P2)); |
| 1667 | break; |
| 1668 | case 9: |
| 1669 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 1670 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1671 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 1672 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1673 | break; |
| 1674 | case 10: |
| 1675 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1676 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1677 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 1678 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1679 | break; |
| 1680 | case 11: |
| 1681 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1682 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1683 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | |
| 1684 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| 1685 | break; |
| 1686 | case 13: |
| 1687 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 1688 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1689 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1690 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1691 | break; |
| 1692 | case 14: |
| 1693 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1694 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1695 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1696 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1697 | break; |
| 1698 | case 15: |
| 1699 | gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | |
| 1700 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1701 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1702 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1703 | break; |
| 1704 | case 16: |
| 1705 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1706 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1707 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1708 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| 1709 | break; |
| 1710 | case 18: |
| 1711 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | |
| 1712 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1713 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1714 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1715 | break; |
| 1716 | case 19: |
| 1717 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | |
| 1718 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1719 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1720 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1721 | break; |
| 1722 | case 20: |
| 1723 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | |
| 1724 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1725 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1726 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1727 | break; |
| 1728 | case 21: |
| 1729 | gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | |
| 1730 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1731 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1732 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1733 | break; |
| 1734 | case 22: |
| 1735 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | |
| 1736 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1737 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1738 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1739 | break; |
| 1740 | case 24: |
| 1741 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | |
| 1742 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1743 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | |
| 1744 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1745 | break; |
| 1746 | case 25: |
| 1747 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | |
| 1748 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1749 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1750 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1751 | break; |
| 1752 | case 26: |
| 1753 | gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | |
| 1754 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1755 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | |
| 1756 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); |
| 1757 | break; |
| 1758 | case 27: |
| 1759 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | |
| 1760 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1761 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 1762 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1763 | break; |
| 1764 | case 28: |
| 1765 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | |
| 1766 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1767 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 1768 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); |
| 1769 | break; |
| 1770 | case 29: |
| 1771 | gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | |
| 1772 | PIPE_CONFIG(ADDR_SURF_P2) | |
| 1773 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | |
| 1774 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); |
| 1775 | break; |
| 1776 | case 7: |
| 1777 | case 12: |
| 1778 | case 17: |
| 1779 | case 23: |
| 1780 | /* unused idx */ |
| 1781 | continue; |
| 1782 | default: |
| 1783 | gb_tile_moden = 0; |
| 1784 | break; |
| 1785 | }; |
| 1786 | adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; |
| 1787 | WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); |
| 1788 | } |
| 1789 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { |
| 1790 | switch (reg_offset) { |
| 1791 | case 0: |
| 1792 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1793 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1794 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1795 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1796 | break; |
| 1797 | case 1: |
| 1798 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1799 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 1800 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1801 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1802 | break; |
| 1803 | case 2: |
| 1804 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1805 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1806 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1807 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1808 | break; |
| 1809 | case 3: |
| 1810 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1811 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1812 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1813 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1814 | break; |
| 1815 | case 4: |
| 1816 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1817 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1818 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1819 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1820 | break; |
| 1821 | case 5: |
| 1822 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1823 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1824 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1825 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1826 | break; |
| 1827 | case 6: |
| 1828 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1829 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1830 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1831 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1832 | break; |
| 1833 | case 8: |
| 1834 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | |
| 1835 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | |
| 1836 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1837 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1838 | break; |
| 1839 | case 9: |
| 1840 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | |
| 1841 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1842 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1843 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1844 | break; |
| 1845 | case 10: |
| 1846 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | |
| 1847 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | |
| 1848 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1849 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1850 | break; |
| 1851 | case 11: |
| 1852 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | |
| 1853 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 1854 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1855 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1856 | break; |
| 1857 | case 12: |
| 1858 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1859 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | |
| 1860 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1861 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1862 | break; |
| 1863 | case 13: |
| 1864 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1865 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1866 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | |
| 1867 | NUM_BANKS(ADDR_SURF_16_BANK)); |
| 1868 | break; |
| 1869 | case 14: |
| 1870 | gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | |
| 1871 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | |
| 1872 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | |
| 1873 | NUM_BANKS(ADDR_SURF_8_BANK)); |
| 1874 | break; |
| 1875 | case 7: |
| 1876 | /* unused idx */ |
| 1877 | continue; |
| 1878 | default: |
| 1879 | gb_tile_moden = 0; |
| 1880 | break; |
| 1881 | }; |
| 1882 | adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; |
| 1883 | WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); |
| 1884 | } |
| 1885 | } |
| 1886 | } |
| 1887 | |
| 1888 | static u32 gfx_v8_0_create_bitmask(u32 bit_width) |
| 1889 | { |
| 1890 | u32 i, mask = 0; |
| 1891 | |
| 1892 | for (i = 0; i < bit_width; i++) { |
| 1893 | mask <<= 1; |
| 1894 | mask |= 1; |
| 1895 | } |
| 1896 | return mask; |
| 1897 | } |
| 1898 | |
| 1899 | void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num) |
| 1900 | { |
| 1901 | u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); |
| 1902 | |
| 1903 | if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) { |
| 1904 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); |
| 1905 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); |
| 1906 | } else if (se_num == 0xffffffff) { |
| 1907 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); |
| 1908 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); |
| 1909 | } else if (sh_num == 0xffffffff) { |
| 1910 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); |
| 1911 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); |
| 1912 | } else { |
| 1913 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); |
| 1914 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); |
| 1915 | } |
| 1916 | WREG32(mmGRBM_GFX_INDEX, data); |
| 1917 | } |
| 1918 | |
| 1919 | static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev, |
| 1920 | u32 max_rb_num_per_se, |
| 1921 | u32 sh_per_se) |
| 1922 | { |
| 1923 | u32 data, mask; |
| 1924 | |
| 1925 | data = RREG32(mmCC_RB_BACKEND_DISABLE); |
Alex Deucher | 4f2d3ad | 2015-07-10 17:05:31 -0400 | [diff] [blame] | 1926 | data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 1927 | |
| 1928 | data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); |
| 1929 | |
| 1930 | data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; |
| 1931 | |
| 1932 | mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se); |
| 1933 | |
| 1934 | return data & mask; |
| 1935 | } |
| 1936 | |
| 1937 | static void gfx_v8_0_setup_rb(struct amdgpu_device *adev, |
| 1938 | u32 se_num, u32 sh_per_se, |
| 1939 | u32 max_rb_num_per_se) |
| 1940 | { |
| 1941 | int i, j; |
| 1942 | u32 data, mask; |
| 1943 | u32 disabled_rbs = 0; |
| 1944 | u32 enabled_rbs = 0; |
| 1945 | |
| 1946 | mutex_lock(&adev->grbm_idx_mutex); |
| 1947 | for (i = 0; i < se_num; i++) { |
| 1948 | for (j = 0; j < sh_per_se; j++) { |
| 1949 | gfx_v8_0_select_se_sh(adev, i, j); |
| 1950 | data = gfx_v8_0_get_rb_disabled(adev, |
| 1951 | max_rb_num_per_se, sh_per_se); |
| 1952 | disabled_rbs |= data << ((i * sh_per_se + j) * |
| 1953 | RB_BITMAP_WIDTH_PER_SH); |
| 1954 | } |
| 1955 | } |
| 1956 | gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); |
| 1957 | mutex_unlock(&adev->grbm_idx_mutex); |
| 1958 | |
| 1959 | mask = 1; |
| 1960 | for (i = 0; i < max_rb_num_per_se * se_num; i++) { |
| 1961 | if (!(disabled_rbs & mask)) |
| 1962 | enabled_rbs |= mask; |
| 1963 | mask <<= 1; |
| 1964 | } |
| 1965 | |
| 1966 | adev->gfx.config.backend_enable_mask = enabled_rbs; |
| 1967 | |
| 1968 | mutex_lock(&adev->grbm_idx_mutex); |
| 1969 | for (i = 0; i < se_num; i++) { |
| 1970 | gfx_v8_0_select_se_sh(adev, i, 0xffffffff); |
| 1971 | data = 0; |
| 1972 | for (j = 0; j < sh_per_se; j++) { |
| 1973 | switch (enabled_rbs & 3) { |
| 1974 | case 0: |
| 1975 | if (j == 0) |
| 1976 | data |= (RASTER_CONFIG_RB_MAP_3 << |
| 1977 | PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT); |
| 1978 | else |
| 1979 | data |= (RASTER_CONFIG_RB_MAP_0 << |
| 1980 | PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT); |
| 1981 | break; |
| 1982 | case 1: |
| 1983 | data |= (RASTER_CONFIG_RB_MAP_0 << |
| 1984 | (i * sh_per_se + j) * 2); |
| 1985 | break; |
| 1986 | case 2: |
| 1987 | data |= (RASTER_CONFIG_RB_MAP_3 << |
| 1988 | (i * sh_per_se + j) * 2); |
| 1989 | break; |
| 1990 | case 3: |
| 1991 | default: |
| 1992 | data |= (RASTER_CONFIG_RB_MAP_2 << |
| 1993 | (i * sh_per_se + j) * 2); |
| 1994 | break; |
| 1995 | } |
| 1996 | enabled_rbs >>= 2; |
| 1997 | } |
| 1998 | WREG32(mmPA_SC_RASTER_CONFIG, data); |
| 1999 | } |
| 2000 | gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); |
| 2001 | mutex_unlock(&adev->grbm_idx_mutex); |
| 2002 | } |
| 2003 | |
Ben Goz | cd06bf6 | 2015-06-24 22:39:21 +0300 | [diff] [blame] | 2004 | /** |
| 2005 | * gmc_v8_0_init_compute_vmid - gart enable |
| 2006 | * |
| 2007 | * @rdev: amdgpu_device pointer |
| 2008 | * |
| 2009 | * Initialize compute vmid sh_mem registers |
| 2010 | * |
| 2011 | */ |
| 2012 | #define DEFAULT_SH_MEM_BASES (0x6000) |
| 2013 | #define FIRST_COMPUTE_VMID (8) |
| 2014 | #define LAST_COMPUTE_VMID (16) |
| 2015 | static void gmc_v8_0_init_compute_vmid(struct amdgpu_device *adev) |
| 2016 | { |
| 2017 | int i; |
| 2018 | uint32_t sh_mem_config; |
| 2019 | uint32_t sh_mem_bases; |
| 2020 | |
| 2021 | /* |
| 2022 | * Configure apertures: |
| 2023 | * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) |
| 2024 | * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) |
| 2025 | * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) |
| 2026 | */ |
| 2027 | sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); |
| 2028 | |
| 2029 | sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 << |
| 2030 | SH_MEM_CONFIG__ADDRESS_MODE__SHIFT | |
| 2031 | SH_MEM_ALIGNMENT_MODE_UNALIGNED << |
| 2032 | SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT | |
| 2033 | MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT | |
| 2034 | SH_MEM_CONFIG__PRIVATE_ATC_MASK; |
| 2035 | |
| 2036 | mutex_lock(&adev->srbm_mutex); |
| 2037 | for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { |
| 2038 | vi_srbm_select(adev, 0, 0, 0, i); |
| 2039 | /* CP and shaders */ |
| 2040 | WREG32(mmSH_MEM_CONFIG, sh_mem_config); |
| 2041 | WREG32(mmSH_MEM_APE1_BASE, 1); |
| 2042 | WREG32(mmSH_MEM_APE1_LIMIT, 0); |
| 2043 | WREG32(mmSH_MEM_BASES, sh_mem_bases); |
| 2044 | } |
| 2045 | vi_srbm_select(adev, 0, 0, 0, 0); |
| 2046 | mutex_unlock(&adev->srbm_mutex); |
| 2047 | } |
| 2048 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2049 | static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) |
| 2050 | { |
| 2051 | u32 gb_addr_config; |
| 2052 | u32 mc_shared_chmap, mc_arb_ramcfg; |
| 2053 | u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; |
| 2054 | u32 tmp; |
| 2055 | int i; |
| 2056 | |
| 2057 | switch (adev->asic_type) { |
| 2058 | case CHIP_TOPAZ: |
| 2059 | adev->gfx.config.max_shader_engines = 1; |
| 2060 | adev->gfx.config.max_tile_pipes = 2; |
| 2061 | adev->gfx.config.max_cu_per_sh = 6; |
| 2062 | adev->gfx.config.max_sh_per_se = 1; |
| 2063 | adev->gfx.config.max_backends_per_se = 2; |
| 2064 | adev->gfx.config.max_texture_channel_caches = 2; |
| 2065 | adev->gfx.config.max_gprs = 256; |
| 2066 | adev->gfx.config.max_gs_threads = 32; |
| 2067 | adev->gfx.config.max_hw_contexts = 8; |
| 2068 | |
| 2069 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
| 2070 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
| 2071 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
| 2072 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
| 2073 | gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN; |
| 2074 | break; |
David Zhang | af15a2d | 2015-07-30 19:42:11 -0400 | [diff] [blame^] | 2075 | case CHIP_FIJI: |
| 2076 | adev->gfx.config.max_shader_engines = 4; |
| 2077 | adev->gfx.config.max_tile_pipes = 16; |
| 2078 | adev->gfx.config.max_cu_per_sh = 16; |
| 2079 | adev->gfx.config.max_sh_per_se = 1; |
| 2080 | adev->gfx.config.max_backends_per_se = 4; |
| 2081 | adev->gfx.config.max_texture_channel_caches = 8; |
| 2082 | adev->gfx.config.max_gprs = 256; |
| 2083 | adev->gfx.config.max_gs_threads = 32; |
| 2084 | adev->gfx.config.max_hw_contexts = 8; |
| 2085 | |
| 2086 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
| 2087 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
| 2088 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
| 2089 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
| 2090 | gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; |
| 2091 | break; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2092 | case CHIP_TONGA: |
| 2093 | adev->gfx.config.max_shader_engines = 4; |
| 2094 | adev->gfx.config.max_tile_pipes = 8; |
| 2095 | adev->gfx.config.max_cu_per_sh = 8; |
| 2096 | adev->gfx.config.max_sh_per_se = 1; |
| 2097 | adev->gfx.config.max_backends_per_se = 2; |
| 2098 | adev->gfx.config.max_texture_channel_caches = 8; |
| 2099 | adev->gfx.config.max_gprs = 256; |
| 2100 | adev->gfx.config.max_gs_threads = 32; |
| 2101 | adev->gfx.config.max_hw_contexts = 8; |
| 2102 | |
| 2103 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
| 2104 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
| 2105 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
| 2106 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
| 2107 | gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; |
| 2108 | break; |
| 2109 | case CHIP_CARRIZO: |
| 2110 | adev->gfx.config.max_shader_engines = 1; |
| 2111 | adev->gfx.config.max_tile_pipes = 2; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2112 | adev->gfx.config.max_sh_per_se = 1; |
Alex Deucher | a0e2f50 | 2015-07-08 22:23:38 -0400 | [diff] [blame] | 2113 | adev->gfx.config.max_backends_per_se = 2; |
Alex Deucher | bd5c97b | 2015-06-05 14:34:19 -0400 | [diff] [blame] | 2114 | |
| 2115 | switch (adev->pdev->revision) { |
| 2116 | case 0xc4: |
| 2117 | case 0x84: |
| 2118 | case 0xc8: |
| 2119 | case 0xcc: |
| 2120 | /* B10 */ |
| 2121 | adev->gfx.config.max_cu_per_sh = 8; |
Alex Deucher | bd5c97b | 2015-06-05 14:34:19 -0400 | [diff] [blame] | 2122 | break; |
| 2123 | case 0xc5: |
| 2124 | case 0x81: |
| 2125 | case 0x85: |
| 2126 | case 0xc9: |
| 2127 | case 0xcd: |
| 2128 | /* B8 */ |
| 2129 | adev->gfx.config.max_cu_per_sh = 6; |
Alex Deucher | bd5c97b | 2015-06-05 14:34:19 -0400 | [diff] [blame] | 2130 | break; |
| 2131 | case 0xc6: |
| 2132 | case 0xca: |
| 2133 | case 0xce: |
| 2134 | /* B6 */ |
| 2135 | adev->gfx.config.max_cu_per_sh = 6; |
Alex Deucher | bd5c97b | 2015-06-05 14:34:19 -0400 | [diff] [blame] | 2136 | break; |
| 2137 | case 0xc7: |
| 2138 | case 0x87: |
| 2139 | case 0xcb: |
| 2140 | default: |
| 2141 | /* B4 */ |
| 2142 | adev->gfx.config.max_cu_per_sh = 4; |
Alex Deucher | bd5c97b | 2015-06-05 14:34:19 -0400 | [diff] [blame] | 2143 | break; |
| 2144 | } |
| 2145 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2146 | adev->gfx.config.max_texture_channel_caches = 2; |
| 2147 | adev->gfx.config.max_gprs = 256; |
| 2148 | adev->gfx.config.max_gs_threads = 32; |
| 2149 | adev->gfx.config.max_hw_contexts = 8; |
| 2150 | |
| 2151 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
| 2152 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
| 2153 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
| 2154 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
| 2155 | gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; |
| 2156 | break; |
| 2157 | default: |
| 2158 | adev->gfx.config.max_shader_engines = 2; |
| 2159 | adev->gfx.config.max_tile_pipes = 4; |
| 2160 | adev->gfx.config.max_cu_per_sh = 2; |
| 2161 | adev->gfx.config.max_sh_per_se = 1; |
| 2162 | adev->gfx.config.max_backends_per_se = 2; |
| 2163 | adev->gfx.config.max_texture_channel_caches = 4; |
| 2164 | adev->gfx.config.max_gprs = 256; |
| 2165 | adev->gfx.config.max_gs_threads = 32; |
| 2166 | adev->gfx.config.max_hw_contexts = 8; |
| 2167 | |
| 2168 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
| 2169 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
| 2170 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
| 2171 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
| 2172 | gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; |
| 2173 | break; |
| 2174 | } |
| 2175 | |
| 2176 | tmp = RREG32(mmGRBM_CNTL); |
| 2177 | tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff); |
| 2178 | WREG32(mmGRBM_CNTL, tmp); |
| 2179 | |
| 2180 | mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); |
| 2181 | adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); |
| 2182 | mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; |
| 2183 | |
| 2184 | adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; |
| 2185 | adev->gfx.config.mem_max_burst_length_bytes = 256; |
Jammy Zhou | 2f7d10b | 2015-07-22 11:29:01 +0800 | [diff] [blame] | 2186 | if (adev->flags & AMD_IS_APU) { |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2187 | /* Get memory bank mapping mode. */ |
| 2188 | tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); |
| 2189 | dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); |
| 2190 | dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); |
| 2191 | |
| 2192 | tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); |
| 2193 | dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); |
| 2194 | dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); |
| 2195 | |
| 2196 | /* Validate settings in case only one DIMM installed. */ |
| 2197 | if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) |
| 2198 | dimm00_addr_map = 0; |
| 2199 | if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) |
| 2200 | dimm01_addr_map = 0; |
| 2201 | if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) |
| 2202 | dimm10_addr_map = 0; |
| 2203 | if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) |
| 2204 | dimm11_addr_map = 0; |
| 2205 | |
| 2206 | /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ |
| 2207 | /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ |
| 2208 | if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) |
| 2209 | adev->gfx.config.mem_row_size_in_kb = 2; |
| 2210 | else |
| 2211 | adev->gfx.config.mem_row_size_in_kb = 1; |
| 2212 | } else { |
| 2213 | tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); |
| 2214 | adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; |
| 2215 | if (adev->gfx.config.mem_row_size_in_kb > 4) |
| 2216 | adev->gfx.config.mem_row_size_in_kb = 4; |
| 2217 | } |
| 2218 | |
| 2219 | adev->gfx.config.shader_engine_tile_size = 32; |
| 2220 | adev->gfx.config.num_gpus = 1; |
| 2221 | adev->gfx.config.multi_gpu_tile_size = 64; |
| 2222 | |
| 2223 | /* fix up row size */ |
| 2224 | switch (adev->gfx.config.mem_row_size_in_kb) { |
| 2225 | case 1: |
| 2226 | default: |
| 2227 | gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); |
| 2228 | break; |
| 2229 | case 2: |
| 2230 | gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1); |
| 2231 | break; |
| 2232 | case 4: |
| 2233 | gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2); |
| 2234 | break; |
| 2235 | } |
| 2236 | adev->gfx.config.gb_addr_config = gb_addr_config; |
| 2237 | |
| 2238 | WREG32(mmGB_ADDR_CONFIG, gb_addr_config); |
| 2239 | WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); |
| 2240 | WREG32(mmDMIF_ADDR_CALC, gb_addr_config); |
| 2241 | WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, |
| 2242 | gb_addr_config & 0x70); |
| 2243 | WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, |
| 2244 | gb_addr_config & 0x70); |
| 2245 | WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); |
| 2246 | WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); |
| 2247 | WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); |
| 2248 | |
| 2249 | gfx_v8_0_tiling_mode_table_init(adev); |
| 2250 | |
| 2251 | gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines, |
| 2252 | adev->gfx.config.max_sh_per_se, |
| 2253 | adev->gfx.config.max_backends_per_se); |
| 2254 | |
| 2255 | /* XXX SH_MEM regs */ |
| 2256 | /* where to put LDS, scratch, GPUVM in FSA64 space */ |
| 2257 | mutex_lock(&adev->srbm_mutex); |
| 2258 | for (i = 0; i < 16; i++) { |
| 2259 | vi_srbm_select(adev, 0, 0, 0, i); |
| 2260 | /* CP and shaders */ |
| 2261 | if (i == 0) { |
| 2262 | tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC); |
| 2263 | tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); |
Jack Xiao | 74a5d16 | 2015-05-08 14:46:49 +0800 | [diff] [blame] | 2264 | tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, |
| 2265 | SH_MEM_ALIGNMENT_MODE_UNALIGNED); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2266 | WREG32(mmSH_MEM_CONFIG, tmp); |
| 2267 | } else { |
| 2268 | tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); |
| 2269 | tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC); |
Jack Xiao | 74a5d16 | 2015-05-08 14:46:49 +0800 | [diff] [blame] | 2270 | tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, |
| 2271 | SH_MEM_ALIGNMENT_MODE_UNALIGNED); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2272 | WREG32(mmSH_MEM_CONFIG, tmp); |
| 2273 | } |
| 2274 | |
| 2275 | WREG32(mmSH_MEM_APE1_BASE, 1); |
| 2276 | WREG32(mmSH_MEM_APE1_LIMIT, 0); |
| 2277 | WREG32(mmSH_MEM_BASES, 0); |
| 2278 | } |
| 2279 | vi_srbm_select(adev, 0, 0, 0, 0); |
| 2280 | mutex_unlock(&adev->srbm_mutex); |
| 2281 | |
Ben Goz | cd06bf6 | 2015-06-24 22:39:21 +0300 | [diff] [blame] | 2282 | gmc_v8_0_init_compute_vmid(adev); |
| 2283 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2284 | mutex_lock(&adev->grbm_idx_mutex); |
| 2285 | /* |
| 2286 | * making sure that the following register writes will be broadcasted |
| 2287 | * to all the shaders |
| 2288 | */ |
| 2289 | gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); |
| 2290 | |
| 2291 | WREG32(mmPA_SC_FIFO_SIZE, |
| 2292 | (adev->gfx.config.sc_prim_fifo_size_frontend << |
| 2293 | PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | |
| 2294 | (adev->gfx.config.sc_prim_fifo_size_backend << |
| 2295 | PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | |
| 2296 | (adev->gfx.config.sc_hiz_tile_fifo_size << |
| 2297 | PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | |
| 2298 | (adev->gfx.config.sc_earlyz_tile_fifo_size << |
| 2299 | PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); |
| 2300 | mutex_unlock(&adev->grbm_idx_mutex); |
| 2301 | |
| 2302 | } |
| 2303 | |
| 2304 | static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev) |
| 2305 | { |
| 2306 | u32 i, j, k; |
| 2307 | u32 mask; |
| 2308 | |
| 2309 | mutex_lock(&adev->grbm_idx_mutex); |
| 2310 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { |
| 2311 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { |
| 2312 | gfx_v8_0_select_se_sh(adev, i, j); |
| 2313 | for (k = 0; k < adev->usec_timeout; k++) { |
| 2314 | if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) |
| 2315 | break; |
| 2316 | udelay(1); |
| 2317 | } |
| 2318 | } |
| 2319 | } |
| 2320 | gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); |
| 2321 | mutex_unlock(&adev->grbm_idx_mutex); |
| 2322 | |
| 2323 | mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | |
| 2324 | RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | |
| 2325 | RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | |
| 2326 | RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; |
| 2327 | for (k = 0; k < adev->usec_timeout; k++) { |
| 2328 | if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) |
| 2329 | break; |
| 2330 | udelay(1); |
| 2331 | } |
| 2332 | } |
| 2333 | |
| 2334 | static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, |
| 2335 | bool enable) |
| 2336 | { |
| 2337 | u32 tmp = RREG32(mmCP_INT_CNTL_RING0); |
| 2338 | |
| 2339 | if (enable) { |
| 2340 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1); |
| 2341 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1); |
| 2342 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1); |
| 2343 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1); |
| 2344 | } else { |
| 2345 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0); |
| 2346 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0); |
| 2347 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0); |
| 2348 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0); |
| 2349 | } |
| 2350 | WREG32(mmCP_INT_CNTL_RING0, tmp); |
| 2351 | } |
| 2352 | |
| 2353 | void gfx_v8_0_rlc_stop(struct amdgpu_device *adev) |
| 2354 | { |
| 2355 | u32 tmp = RREG32(mmRLC_CNTL); |
| 2356 | |
| 2357 | tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); |
| 2358 | WREG32(mmRLC_CNTL, tmp); |
| 2359 | |
| 2360 | gfx_v8_0_enable_gui_idle_interrupt(adev, false); |
| 2361 | |
| 2362 | gfx_v8_0_wait_for_rlc_serdes(adev); |
| 2363 | } |
| 2364 | |
| 2365 | static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev) |
| 2366 | { |
| 2367 | u32 tmp = RREG32(mmGRBM_SOFT_RESET); |
| 2368 | |
| 2369 | tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); |
| 2370 | WREG32(mmGRBM_SOFT_RESET, tmp); |
| 2371 | udelay(50); |
| 2372 | tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); |
| 2373 | WREG32(mmGRBM_SOFT_RESET, tmp); |
| 2374 | udelay(50); |
| 2375 | } |
| 2376 | |
| 2377 | static void gfx_v8_0_rlc_start(struct amdgpu_device *adev) |
| 2378 | { |
| 2379 | u32 tmp = RREG32(mmRLC_CNTL); |
| 2380 | |
| 2381 | tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1); |
| 2382 | WREG32(mmRLC_CNTL, tmp); |
| 2383 | |
| 2384 | /* carrizo do enable cp interrupt after cp inited */ |
| 2385 | if (adev->asic_type != CHIP_CARRIZO) |
| 2386 | gfx_v8_0_enable_gui_idle_interrupt(adev, true); |
| 2387 | |
| 2388 | udelay(50); |
| 2389 | } |
| 2390 | |
| 2391 | static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev) |
| 2392 | { |
| 2393 | const struct rlc_firmware_header_v2_0 *hdr; |
| 2394 | const __le32 *fw_data; |
| 2395 | unsigned i, fw_size; |
| 2396 | |
| 2397 | if (!adev->gfx.rlc_fw) |
| 2398 | return -EINVAL; |
| 2399 | |
| 2400 | hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; |
| 2401 | amdgpu_ucode_print_rlc_hdr(&hdr->header); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2402 | |
| 2403 | fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + |
| 2404 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
| 2405 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; |
| 2406 | |
| 2407 | WREG32(mmRLC_GPM_UCODE_ADDR, 0); |
| 2408 | for (i = 0; i < fw_size; i++) |
| 2409 | WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); |
| 2410 | WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); |
| 2411 | |
| 2412 | return 0; |
| 2413 | } |
| 2414 | |
| 2415 | static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) |
| 2416 | { |
| 2417 | int r; |
| 2418 | |
| 2419 | gfx_v8_0_rlc_stop(adev); |
| 2420 | |
| 2421 | /* disable CG */ |
| 2422 | WREG32(mmRLC_CGCG_CGLS_CTRL, 0); |
| 2423 | |
| 2424 | /* disable PG */ |
| 2425 | WREG32(mmRLC_PG_CNTL, 0); |
| 2426 | |
| 2427 | gfx_v8_0_rlc_reset(adev); |
| 2428 | |
| 2429 | if (!adev->firmware.smu_load) { |
| 2430 | /* legacy rlc firmware loading */ |
| 2431 | r = gfx_v8_0_rlc_load_microcode(adev); |
| 2432 | if (r) |
| 2433 | return r; |
| 2434 | } else { |
| 2435 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, |
| 2436 | AMDGPU_UCODE_ID_RLC_G); |
| 2437 | if (r) |
| 2438 | return -EINVAL; |
| 2439 | } |
| 2440 | |
| 2441 | gfx_v8_0_rlc_start(adev); |
| 2442 | |
| 2443 | return 0; |
| 2444 | } |
| 2445 | |
| 2446 | static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) |
| 2447 | { |
| 2448 | int i; |
| 2449 | u32 tmp = RREG32(mmCP_ME_CNTL); |
| 2450 | |
| 2451 | if (enable) { |
| 2452 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); |
| 2453 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); |
| 2454 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); |
| 2455 | } else { |
| 2456 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); |
| 2457 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); |
| 2458 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); |
| 2459 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
| 2460 | adev->gfx.gfx_ring[i].ready = false; |
| 2461 | } |
| 2462 | WREG32(mmCP_ME_CNTL, tmp); |
| 2463 | udelay(50); |
| 2464 | } |
| 2465 | |
| 2466 | static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev) |
| 2467 | { |
| 2468 | const struct gfx_firmware_header_v1_0 *pfp_hdr; |
| 2469 | const struct gfx_firmware_header_v1_0 *ce_hdr; |
| 2470 | const struct gfx_firmware_header_v1_0 *me_hdr; |
| 2471 | const __le32 *fw_data; |
| 2472 | unsigned i, fw_size; |
| 2473 | |
| 2474 | if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) |
| 2475 | return -EINVAL; |
| 2476 | |
| 2477 | pfp_hdr = (const struct gfx_firmware_header_v1_0 *) |
| 2478 | adev->gfx.pfp_fw->data; |
| 2479 | ce_hdr = (const struct gfx_firmware_header_v1_0 *) |
| 2480 | adev->gfx.ce_fw->data; |
| 2481 | me_hdr = (const struct gfx_firmware_header_v1_0 *) |
| 2482 | adev->gfx.me_fw->data; |
| 2483 | |
| 2484 | amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); |
| 2485 | amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); |
| 2486 | amdgpu_ucode_print_gfx_hdr(&me_hdr->header); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2487 | |
| 2488 | gfx_v8_0_cp_gfx_enable(adev, false); |
| 2489 | |
| 2490 | /* PFP */ |
| 2491 | fw_data = (const __le32 *) |
| 2492 | (adev->gfx.pfp_fw->data + |
| 2493 | le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); |
| 2494 | fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; |
| 2495 | WREG32(mmCP_PFP_UCODE_ADDR, 0); |
| 2496 | for (i = 0; i < fw_size; i++) |
| 2497 | WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); |
| 2498 | WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); |
| 2499 | |
| 2500 | /* CE */ |
| 2501 | fw_data = (const __le32 *) |
| 2502 | (adev->gfx.ce_fw->data + |
| 2503 | le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); |
| 2504 | fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; |
| 2505 | WREG32(mmCP_CE_UCODE_ADDR, 0); |
| 2506 | for (i = 0; i < fw_size; i++) |
| 2507 | WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); |
| 2508 | WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); |
| 2509 | |
| 2510 | /* ME */ |
| 2511 | fw_data = (const __le32 *) |
| 2512 | (adev->gfx.me_fw->data + |
| 2513 | le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); |
| 2514 | fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; |
| 2515 | WREG32(mmCP_ME_RAM_WADDR, 0); |
| 2516 | for (i = 0; i < fw_size; i++) |
| 2517 | WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); |
| 2518 | WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); |
| 2519 | |
| 2520 | return 0; |
| 2521 | } |
| 2522 | |
| 2523 | static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev) |
| 2524 | { |
| 2525 | u32 count = 0; |
| 2526 | const struct cs_section_def *sect = NULL; |
| 2527 | const struct cs_extent_def *ext = NULL; |
| 2528 | |
| 2529 | /* begin clear state */ |
| 2530 | count += 2; |
| 2531 | /* context control state */ |
| 2532 | count += 3; |
| 2533 | |
| 2534 | for (sect = vi_cs_data; sect->section != NULL; ++sect) { |
| 2535 | for (ext = sect->section; ext->extent != NULL; ++ext) { |
| 2536 | if (sect->id == SECT_CONTEXT) |
| 2537 | count += 2 + ext->reg_count; |
| 2538 | else |
| 2539 | return 0; |
| 2540 | } |
| 2541 | } |
| 2542 | /* pa_sc_raster_config/pa_sc_raster_config1 */ |
| 2543 | count += 4; |
| 2544 | /* end clear state */ |
| 2545 | count += 2; |
| 2546 | /* clear state */ |
| 2547 | count += 2; |
| 2548 | |
| 2549 | return count; |
| 2550 | } |
| 2551 | |
| 2552 | static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) |
| 2553 | { |
| 2554 | struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; |
| 2555 | const struct cs_section_def *sect = NULL; |
| 2556 | const struct cs_extent_def *ext = NULL; |
| 2557 | int r, i; |
| 2558 | |
| 2559 | /* init the CP */ |
| 2560 | WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); |
| 2561 | WREG32(mmCP_ENDIAN_SWAP, 0); |
| 2562 | WREG32(mmCP_DEVICE_ID, 1); |
| 2563 | |
| 2564 | gfx_v8_0_cp_gfx_enable(adev, true); |
| 2565 | |
| 2566 | r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4); |
| 2567 | if (r) { |
| 2568 | DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); |
| 2569 | return r; |
| 2570 | } |
| 2571 | |
| 2572 | /* clear state buffer */ |
| 2573 | amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
| 2574 | amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); |
| 2575 | |
| 2576 | amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); |
| 2577 | amdgpu_ring_write(ring, 0x80000000); |
| 2578 | amdgpu_ring_write(ring, 0x80000000); |
| 2579 | |
| 2580 | for (sect = vi_cs_data; sect->section != NULL; ++sect) { |
| 2581 | for (ext = sect->section; ext->extent != NULL; ++ext) { |
| 2582 | if (sect->id == SECT_CONTEXT) { |
| 2583 | amdgpu_ring_write(ring, |
| 2584 | PACKET3(PACKET3_SET_CONTEXT_REG, |
| 2585 | ext->reg_count)); |
| 2586 | amdgpu_ring_write(ring, |
| 2587 | ext->reg_index - PACKET3_SET_CONTEXT_REG_START); |
| 2588 | for (i = 0; i < ext->reg_count; i++) |
| 2589 | amdgpu_ring_write(ring, ext->extent[i]); |
| 2590 | } |
| 2591 | } |
| 2592 | } |
| 2593 | |
| 2594 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| 2595 | amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); |
| 2596 | switch (adev->asic_type) { |
| 2597 | case CHIP_TONGA: |
David Zhang | af15a2d | 2015-07-30 19:42:11 -0400 | [diff] [blame^] | 2598 | case CHIP_FIJI: |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2599 | amdgpu_ring_write(ring, 0x16000012); |
| 2600 | amdgpu_ring_write(ring, 0x0000002A); |
| 2601 | break; |
| 2602 | case CHIP_TOPAZ: |
| 2603 | case CHIP_CARRIZO: |
| 2604 | amdgpu_ring_write(ring, 0x00000002); |
| 2605 | amdgpu_ring_write(ring, 0x00000000); |
| 2606 | break; |
| 2607 | default: |
| 2608 | BUG(); |
| 2609 | } |
| 2610 | |
| 2611 | amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
| 2612 | amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); |
| 2613 | |
| 2614 | amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); |
| 2615 | amdgpu_ring_write(ring, 0); |
| 2616 | |
| 2617 | /* init the CE partitions */ |
| 2618 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); |
| 2619 | amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); |
| 2620 | amdgpu_ring_write(ring, 0x8000); |
| 2621 | amdgpu_ring_write(ring, 0x8000); |
| 2622 | |
| 2623 | amdgpu_ring_unlock_commit(ring); |
| 2624 | |
| 2625 | return 0; |
| 2626 | } |
| 2627 | |
| 2628 | static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) |
| 2629 | { |
| 2630 | struct amdgpu_ring *ring; |
| 2631 | u32 tmp; |
| 2632 | u32 rb_bufsz; |
| 2633 | u64 rb_addr, rptr_addr; |
| 2634 | int r; |
| 2635 | |
| 2636 | /* Set the write pointer delay */ |
| 2637 | WREG32(mmCP_RB_WPTR_DELAY, 0); |
| 2638 | |
| 2639 | /* set the RB to use vmid 0 */ |
| 2640 | WREG32(mmCP_RB_VMID, 0); |
| 2641 | |
| 2642 | /* Set ring buffer size */ |
| 2643 | ring = &adev->gfx.gfx_ring[0]; |
| 2644 | rb_bufsz = order_base_2(ring->ring_size / 8); |
| 2645 | tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); |
| 2646 | tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); |
| 2647 | tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); |
| 2648 | tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1); |
| 2649 | #ifdef __BIG_ENDIAN |
| 2650 | tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); |
| 2651 | #endif |
| 2652 | WREG32(mmCP_RB0_CNTL, tmp); |
| 2653 | |
| 2654 | /* Initialize the ring buffer's read and write pointers */ |
| 2655 | WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); |
| 2656 | ring->wptr = 0; |
| 2657 | WREG32(mmCP_RB0_WPTR, ring->wptr); |
| 2658 | |
| 2659 | /* set the wb address wether it's enabled or not */ |
| 2660 | rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); |
| 2661 | WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); |
| 2662 | WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); |
| 2663 | |
| 2664 | mdelay(1); |
| 2665 | WREG32(mmCP_RB0_CNTL, tmp); |
| 2666 | |
| 2667 | rb_addr = ring->gpu_addr >> 8; |
| 2668 | WREG32(mmCP_RB0_BASE, rb_addr); |
| 2669 | WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); |
| 2670 | |
| 2671 | /* no gfx doorbells on iceland */ |
| 2672 | if (adev->asic_type != CHIP_TOPAZ) { |
| 2673 | tmp = RREG32(mmCP_RB_DOORBELL_CONTROL); |
| 2674 | if (ring->use_doorbell) { |
| 2675 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, |
| 2676 | DOORBELL_OFFSET, ring->doorbell_index); |
| 2677 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, |
| 2678 | DOORBELL_EN, 1); |
| 2679 | } else { |
| 2680 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, |
| 2681 | DOORBELL_EN, 0); |
| 2682 | } |
| 2683 | WREG32(mmCP_RB_DOORBELL_CONTROL, tmp); |
| 2684 | |
| 2685 | if (adev->asic_type == CHIP_TONGA) { |
| 2686 | tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, |
| 2687 | DOORBELL_RANGE_LOWER, |
| 2688 | AMDGPU_DOORBELL_GFX_RING0); |
| 2689 | WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp); |
| 2690 | |
| 2691 | WREG32(mmCP_RB_DOORBELL_RANGE_UPPER, |
| 2692 | CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); |
| 2693 | } |
| 2694 | |
| 2695 | } |
| 2696 | |
| 2697 | /* start the ring */ |
| 2698 | gfx_v8_0_cp_gfx_start(adev); |
| 2699 | ring->ready = true; |
| 2700 | r = amdgpu_ring_test_ring(ring); |
| 2701 | if (r) { |
| 2702 | ring->ready = false; |
| 2703 | return r; |
| 2704 | } |
| 2705 | |
| 2706 | return 0; |
| 2707 | } |
| 2708 | |
| 2709 | static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) |
| 2710 | { |
| 2711 | int i; |
| 2712 | |
| 2713 | if (enable) { |
| 2714 | WREG32(mmCP_MEC_CNTL, 0); |
| 2715 | } else { |
| 2716 | WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); |
| 2717 | for (i = 0; i < adev->gfx.num_compute_rings; i++) |
| 2718 | adev->gfx.compute_ring[i].ready = false; |
| 2719 | } |
| 2720 | udelay(50); |
| 2721 | } |
| 2722 | |
| 2723 | static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev) |
| 2724 | { |
| 2725 | gfx_v8_0_cp_compute_enable(adev, true); |
| 2726 | |
| 2727 | return 0; |
| 2728 | } |
| 2729 | |
| 2730 | static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev) |
| 2731 | { |
| 2732 | const struct gfx_firmware_header_v1_0 *mec_hdr; |
| 2733 | const __le32 *fw_data; |
| 2734 | unsigned i, fw_size; |
| 2735 | |
| 2736 | if (!adev->gfx.mec_fw) |
| 2737 | return -EINVAL; |
| 2738 | |
| 2739 | gfx_v8_0_cp_compute_enable(adev, false); |
| 2740 | |
| 2741 | mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; |
| 2742 | amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2743 | |
| 2744 | fw_data = (const __le32 *) |
| 2745 | (adev->gfx.mec_fw->data + |
| 2746 | le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); |
| 2747 | fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; |
| 2748 | |
| 2749 | /* MEC1 */ |
| 2750 | WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); |
| 2751 | for (i = 0; i < fw_size; i++) |
| 2752 | WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i)); |
| 2753 | WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); |
| 2754 | |
| 2755 | /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ |
| 2756 | if (adev->gfx.mec2_fw) { |
| 2757 | const struct gfx_firmware_header_v1_0 *mec2_hdr; |
| 2758 | |
| 2759 | mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; |
| 2760 | amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2761 | |
| 2762 | fw_data = (const __le32 *) |
| 2763 | (adev->gfx.mec2_fw->data + |
| 2764 | le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); |
| 2765 | fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; |
| 2766 | |
| 2767 | WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); |
| 2768 | for (i = 0; i < fw_size; i++) |
| 2769 | WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i)); |
| 2770 | WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version); |
| 2771 | } |
| 2772 | |
| 2773 | return 0; |
| 2774 | } |
| 2775 | |
| 2776 | struct vi_mqd { |
| 2777 | uint32_t header; /* ordinal0 */ |
| 2778 | uint32_t compute_dispatch_initiator; /* ordinal1 */ |
| 2779 | uint32_t compute_dim_x; /* ordinal2 */ |
| 2780 | uint32_t compute_dim_y; /* ordinal3 */ |
| 2781 | uint32_t compute_dim_z; /* ordinal4 */ |
| 2782 | uint32_t compute_start_x; /* ordinal5 */ |
| 2783 | uint32_t compute_start_y; /* ordinal6 */ |
| 2784 | uint32_t compute_start_z; /* ordinal7 */ |
| 2785 | uint32_t compute_num_thread_x; /* ordinal8 */ |
| 2786 | uint32_t compute_num_thread_y; /* ordinal9 */ |
| 2787 | uint32_t compute_num_thread_z; /* ordinal10 */ |
| 2788 | uint32_t compute_pipelinestat_enable; /* ordinal11 */ |
| 2789 | uint32_t compute_perfcount_enable; /* ordinal12 */ |
| 2790 | uint32_t compute_pgm_lo; /* ordinal13 */ |
| 2791 | uint32_t compute_pgm_hi; /* ordinal14 */ |
| 2792 | uint32_t compute_tba_lo; /* ordinal15 */ |
| 2793 | uint32_t compute_tba_hi; /* ordinal16 */ |
| 2794 | uint32_t compute_tma_lo; /* ordinal17 */ |
| 2795 | uint32_t compute_tma_hi; /* ordinal18 */ |
| 2796 | uint32_t compute_pgm_rsrc1; /* ordinal19 */ |
| 2797 | uint32_t compute_pgm_rsrc2; /* ordinal20 */ |
| 2798 | uint32_t compute_vmid; /* ordinal21 */ |
| 2799 | uint32_t compute_resource_limits; /* ordinal22 */ |
| 2800 | uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */ |
| 2801 | uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */ |
| 2802 | uint32_t compute_tmpring_size; /* ordinal25 */ |
| 2803 | uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */ |
| 2804 | uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */ |
| 2805 | uint32_t compute_restart_x; /* ordinal28 */ |
| 2806 | uint32_t compute_restart_y; /* ordinal29 */ |
| 2807 | uint32_t compute_restart_z; /* ordinal30 */ |
| 2808 | uint32_t compute_thread_trace_enable; /* ordinal31 */ |
| 2809 | uint32_t compute_misc_reserved; /* ordinal32 */ |
| 2810 | uint32_t compute_dispatch_id; /* ordinal33 */ |
| 2811 | uint32_t compute_threadgroup_id; /* ordinal34 */ |
| 2812 | uint32_t compute_relaunch; /* ordinal35 */ |
| 2813 | uint32_t compute_wave_restore_addr_lo; /* ordinal36 */ |
| 2814 | uint32_t compute_wave_restore_addr_hi; /* ordinal37 */ |
| 2815 | uint32_t compute_wave_restore_control; /* ordinal38 */ |
| 2816 | uint32_t reserved9; /* ordinal39 */ |
| 2817 | uint32_t reserved10; /* ordinal40 */ |
| 2818 | uint32_t reserved11; /* ordinal41 */ |
| 2819 | uint32_t reserved12; /* ordinal42 */ |
| 2820 | uint32_t reserved13; /* ordinal43 */ |
| 2821 | uint32_t reserved14; /* ordinal44 */ |
| 2822 | uint32_t reserved15; /* ordinal45 */ |
| 2823 | uint32_t reserved16; /* ordinal46 */ |
| 2824 | uint32_t reserved17; /* ordinal47 */ |
| 2825 | uint32_t reserved18; /* ordinal48 */ |
| 2826 | uint32_t reserved19; /* ordinal49 */ |
| 2827 | uint32_t reserved20; /* ordinal50 */ |
| 2828 | uint32_t reserved21; /* ordinal51 */ |
| 2829 | uint32_t reserved22; /* ordinal52 */ |
| 2830 | uint32_t reserved23; /* ordinal53 */ |
| 2831 | uint32_t reserved24; /* ordinal54 */ |
| 2832 | uint32_t reserved25; /* ordinal55 */ |
| 2833 | uint32_t reserved26; /* ordinal56 */ |
| 2834 | uint32_t reserved27; /* ordinal57 */ |
| 2835 | uint32_t reserved28; /* ordinal58 */ |
| 2836 | uint32_t reserved29; /* ordinal59 */ |
| 2837 | uint32_t reserved30; /* ordinal60 */ |
| 2838 | uint32_t reserved31; /* ordinal61 */ |
| 2839 | uint32_t reserved32; /* ordinal62 */ |
| 2840 | uint32_t reserved33; /* ordinal63 */ |
| 2841 | uint32_t reserved34; /* ordinal64 */ |
| 2842 | uint32_t compute_user_data_0; /* ordinal65 */ |
| 2843 | uint32_t compute_user_data_1; /* ordinal66 */ |
| 2844 | uint32_t compute_user_data_2; /* ordinal67 */ |
| 2845 | uint32_t compute_user_data_3; /* ordinal68 */ |
| 2846 | uint32_t compute_user_data_4; /* ordinal69 */ |
| 2847 | uint32_t compute_user_data_5; /* ordinal70 */ |
| 2848 | uint32_t compute_user_data_6; /* ordinal71 */ |
| 2849 | uint32_t compute_user_data_7; /* ordinal72 */ |
| 2850 | uint32_t compute_user_data_8; /* ordinal73 */ |
| 2851 | uint32_t compute_user_data_9; /* ordinal74 */ |
| 2852 | uint32_t compute_user_data_10; /* ordinal75 */ |
| 2853 | uint32_t compute_user_data_11; /* ordinal76 */ |
| 2854 | uint32_t compute_user_data_12; /* ordinal77 */ |
| 2855 | uint32_t compute_user_data_13; /* ordinal78 */ |
| 2856 | uint32_t compute_user_data_14; /* ordinal79 */ |
| 2857 | uint32_t compute_user_data_15; /* ordinal80 */ |
| 2858 | uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */ |
| 2859 | uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */ |
| 2860 | uint32_t reserved35; /* ordinal83 */ |
| 2861 | uint32_t reserved36; /* ordinal84 */ |
| 2862 | uint32_t reserved37; /* ordinal85 */ |
| 2863 | uint32_t cp_mqd_query_time_lo; /* ordinal86 */ |
| 2864 | uint32_t cp_mqd_query_time_hi; /* ordinal87 */ |
| 2865 | uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */ |
| 2866 | uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */ |
| 2867 | uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */ |
| 2868 | uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */ |
| 2869 | uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */ |
| 2870 | uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */ |
| 2871 | uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */ |
| 2872 | uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */ |
| 2873 | uint32_t reserved38; /* ordinal96 */ |
| 2874 | uint32_t reserved39; /* ordinal97 */ |
| 2875 | uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */ |
| 2876 | uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */ |
| 2877 | uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */ |
| 2878 | uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */ |
| 2879 | uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */ |
| 2880 | uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */ |
| 2881 | uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */ |
| 2882 | uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */ |
| 2883 | uint32_t reserved40; /* ordinal106 */ |
| 2884 | uint32_t reserved41; /* ordinal107 */ |
| 2885 | uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */ |
| 2886 | uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */ |
| 2887 | uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */ |
| 2888 | uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */ |
| 2889 | uint32_t reserved42; /* ordinal112 */ |
| 2890 | uint32_t reserved43; /* ordinal113 */ |
| 2891 | uint32_t cp_pq_exe_status_lo; /* ordinal114 */ |
| 2892 | uint32_t cp_pq_exe_status_hi; /* ordinal115 */ |
| 2893 | uint32_t cp_packet_id_lo; /* ordinal116 */ |
| 2894 | uint32_t cp_packet_id_hi; /* ordinal117 */ |
| 2895 | uint32_t cp_packet_exe_status_lo; /* ordinal118 */ |
| 2896 | uint32_t cp_packet_exe_status_hi; /* ordinal119 */ |
| 2897 | uint32_t gds_save_base_addr_lo; /* ordinal120 */ |
| 2898 | uint32_t gds_save_base_addr_hi; /* ordinal121 */ |
| 2899 | uint32_t gds_save_mask_lo; /* ordinal122 */ |
| 2900 | uint32_t gds_save_mask_hi; /* ordinal123 */ |
| 2901 | uint32_t ctx_save_base_addr_lo; /* ordinal124 */ |
| 2902 | uint32_t ctx_save_base_addr_hi; /* ordinal125 */ |
| 2903 | uint32_t reserved44; /* ordinal126 */ |
| 2904 | uint32_t reserved45; /* ordinal127 */ |
| 2905 | uint32_t cp_mqd_base_addr_lo; /* ordinal128 */ |
| 2906 | uint32_t cp_mqd_base_addr_hi; /* ordinal129 */ |
| 2907 | uint32_t cp_hqd_active; /* ordinal130 */ |
| 2908 | uint32_t cp_hqd_vmid; /* ordinal131 */ |
| 2909 | uint32_t cp_hqd_persistent_state; /* ordinal132 */ |
| 2910 | uint32_t cp_hqd_pipe_priority; /* ordinal133 */ |
| 2911 | uint32_t cp_hqd_queue_priority; /* ordinal134 */ |
| 2912 | uint32_t cp_hqd_quantum; /* ordinal135 */ |
| 2913 | uint32_t cp_hqd_pq_base_lo; /* ordinal136 */ |
| 2914 | uint32_t cp_hqd_pq_base_hi; /* ordinal137 */ |
| 2915 | uint32_t cp_hqd_pq_rptr; /* ordinal138 */ |
| 2916 | uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */ |
| 2917 | uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */ |
| 2918 | uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */ |
| 2919 | uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */ |
| 2920 | uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */ |
| 2921 | uint32_t cp_hqd_pq_wptr; /* ordinal144 */ |
| 2922 | uint32_t cp_hqd_pq_control; /* ordinal145 */ |
| 2923 | uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */ |
| 2924 | uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */ |
| 2925 | uint32_t cp_hqd_ib_rptr; /* ordinal148 */ |
| 2926 | uint32_t cp_hqd_ib_control; /* ordinal149 */ |
| 2927 | uint32_t cp_hqd_iq_timer; /* ordinal150 */ |
| 2928 | uint32_t cp_hqd_iq_rptr; /* ordinal151 */ |
| 2929 | uint32_t cp_hqd_dequeue_request; /* ordinal152 */ |
| 2930 | uint32_t cp_hqd_dma_offload; /* ordinal153 */ |
| 2931 | uint32_t cp_hqd_sema_cmd; /* ordinal154 */ |
| 2932 | uint32_t cp_hqd_msg_type; /* ordinal155 */ |
| 2933 | uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */ |
| 2934 | uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */ |
| 2935 | uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */ |
| 2936 | uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */ |
| 2937 | uint32_t cp_hqd_hq_status0; /* ordinal160 */ |
| 2938 | uint32_t cp_hqd_hq_control0; /* ordinal161 */ |
| 2939 | uint32_t cp_mqd_control; /* ordinal162 */ |
| 2940 | uint32_t cp_hqd_hq_status1; /* ordinal163 */ |
| 2941 | uint32_t cp_hqd_hq_control1; /* ordinal164 */ |
| 2942 | uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */ |
| 2943 | uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */ |
| 2944 | uint32_t cp_hqd_eop_control; /* ordinal167 */ |
| 2945 | uint32_t cp_hqd_eop_rptr; /* ordinal168 */ |
| 2946 | uint32_t cp_hqd_eop_wptr; /* ordinal169 */ |
| 2947 | uint32_t cp_hqd_eop_done_events; /* ordinal170 */ |
| 2948 | uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */ |
| 2949 | uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */ |
| 2950 | uint32_t cp_hqd_ctx_save_control; /* ordinal173 */ |
| 2951 | uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */ |
| 2952 | uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */ |
| 2953 | uint32_t cp_hqd_wg_state_offset; /* ordinal176 */ |
| 2954 | uint32_t cp_hqd_ctx_save_size; /* ordinal177 */ |
| 2955 | uint32_t cp_hqd_gds_resource_state; /* ordinal178 */ |
| 2956 | uint32_t cp_hqd_error; /* ordinal179 */ |
| 2957 | uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */ |
| 2958 | uint32_t cp_hqd_eop_dones; /* ordinal181 */ |
| 2959 | uint32_t reserved46; /* ordinal182 */ |
| 2960 | uint32_t reserved47; /* ordinal183 */ |
| 2961 | uint32_t reserved48; /* ordinal184 */ |
| 2962 | uint32_t reserved49; /* ordinal185 */ |
| 2963 | uint32_t reserved50; /* ordinal186 */ |
| 2964 | uint32_t reserved51; /* ordinal187 */ |
| 2965 | uint32_t reserved52; /* ordinal188 */ |
| 2966 | uint32_t reserved53; /* ordinal189 */ |
| 2967 | uint32_t reserved54; /* ordinal190 */ |
| 2968 | uint32_t reserved55; /* ordinal191 */ |
| 2969 | uint32_t iqtimer_pkt_header; /* ordinal192 */ |
| 2970 | uint32_t iqtimer_pkt_dw0; /* ordinal193 */ |
| 2971 | uint32_t iqtimer_pkt_dw1; /* ordinal194 */ |
| 2972 | uint32_t iqtimer_pkt_dw2; /* ordinal195 */ |
| 2973 | uint32_t iqtimer_pkt_dw3; /* ordinal196 */ |
| 2974 | uint32_t iqtimer_pkt_dw4; /* ordinal197 */ |
| 2975 | uint32_t iqtimer_pkt_dw5; /* ordinal198 */ |
| 2976 | uint32_t iqtimer_pkt_dw6; /* ordinal199 */ |
| 2977 | uint32_t iqtimer_pkt_dw7; /* ordinal200 */ |
| 2978 | uint32_t iqtimer_pkt_dw8; /* ordinal201 */ |
| 2979 | uint32_t iqtimer_pkt_dw9; /* ordinal202 */ |
| 2980 | uint32_t iqtimer_pkt_dw10; /* ordinal203 */ |
| 2981 | uint32_t iqtimer_pkt_dw11; /* ordinal204 */ |
| 2982 | uint32_t iqtimer_pkt_dw12; /* ordinal205 */ |
| 2983 | uint32_t iqtimer_pkt_dw13; /* ordinal206 */ |
| 2984 | uint32_t iqtimer_pkt_dw14; /* ordinal207 */ |
| 2985 | uint32_t iqtimer_pkt_dw15; /* ordinal208 */ |
| 2986 | uint32_t iqtimer_pkt_dw16; /* ordinal209 */ |
| 2987 | uint32_t iqtimer_pkt_dw17; /* ordinal210 */ |
| 2988 | uint32_t iqtimer_pkt_dw18; /* ordinal211 */ |
| 2989 | uint32_t iqtimer_pkt_dw19; /* ordinal212 */ |
| 2990 | uint32_t iqtimer_pkt_dw20; /* ordinal213 */ |
| 2991 | uint32_t iqtimer_pkt_dw21; /* ordinal214 */ |
| 2992 | uint32_t iqtimer_pkt_dw22; /* ordinal215 */ |
| 2993 | uint32_t iqtimer_pkt_dw23; /* ordinal216 */ |
| 2994 | uint32_t iqtimer_pkt_dw24; /* ordinal217 */ |
| 2995 | uint32_t iqtimer_pkt_dw25; /* ordinal218 */ |
| 2996 | uint32_t iqtimer_pkt_dw26; /* ordinal219 */ |
| 2997 | uint32_t iqtimer_pkt_dw27; /* ordinal220 */ |
| 2998 | uint32_t iqtimer_pkt_dw28; /* ordinal221 */ |
| 2999 | uint32_t iqtimer_pkt_dw29; /* ordinal222 */ |
| 3000 | uint32_t iqtimer_pkt_dw30; /* ordinal223 */ |
| 3001 | uint32_t iqtimer_pkt_dw31; /* ordinal224 */ |
| 3002 | uint32_t reserved56; /* ordinal225 */ |
| 3003 | uint32_t reserved57; /* ordinal226 */ |
| 3004 | uint32_t reserved58; /* ordinal227 */ |
| 3005 | uint32_t set_resources_header; /* ordinal228 */ |
| 3006 | uint32_t set_resources_dw1; /* ordinal229 */ |
| 3007 | uint32_t set_resources_dw2; /* ordinal230 */ |
| 3008 | uint32_t set_resources_dw3; /* ordinal231 */ |
| 3009 | uint32_t set_resources_dw4; /* ordinal232 */ |
| 3010 | uint32_t set_resources_dw5; /* ordinal233 */ |
| 3011 | uint32_t set_resources_dw6; /* ordinal234 */ |
| 3012 | uint32_t set_resources_dw7; /* ordinal235 */ |
| 3013 | uint32_t reserved59; /* ordinal236 */ |
| 3014 | uint32_t reserved60; /* ordinal237 */ |
| 3015 | uint32_t reserved61; /* ordinal238 */ |
| 3016 | uint32_t reserved62; /* ordinal239 */ |
| 3017 | uint32_t reserved63; /* ordinal240 */ |
| 3018 | uint32_t reserved64; /* ordinal241 */ |
| 3019 | uint32_t reserved65; /* ordinal242 */ |
| 3020 | uint32_t reserved66; /* ordinal243 */ |
| 3021 | uint32_t reserved67; /* ordinal244 */ |
| 3022 | uint32_t reserved68; /* ordinal245 */ |
| 3023 | uint32_t reserved69; /* ordinal246 */ |
| 3024 | uint32_t reserved70; /* ordinal247 */ |
| 3025 | uint32_t reserved71; /* ordinal248 */ |
| 3026 | uint32_t reserved72; /* ordinal249 */ |
| 3027 | uint32_t reserved73; /* ordinal250 */ |
| 3028 | uint32_t reserved74; /* ordinal251 */ |
| 3029 | uint32_t reserved75; /* ordinal252 */ |
| 3030 | uint32_t reserved76; /* ordinal253 */ |
| 3031 | uint32_t reserved77; /* ordinal254 */ |
| 3032 | uint32_t reserved78; /* ordinal255 */ |
| 3033 | |
| 3034 | uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */ |
| 3035 | }; |
| 3036 | |
| 3037 | static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev) |
| 3038 | { |
| 3039 | int i, r; |
| 3040 | |
| 3041 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
| 3042 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; |
| 3043 | |
| 3044 | if (ring->mqd_obj) { |
| 3045 | r = amdgpu_bo_reserve(ring->mqd_obj, false); |
| 3046 | if (unlikely(r != 0)) |
| 3047 | dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); |
| 3048 | |
| 3049 | amdgpu_bo_unpin(ring->mqd_obj); |
| 3050 | amdgpu_bo_unreserve(ring->mqd_obj); |
| 3051 | |
| 3052 | amdgpu_bo_unref(&ring->mqd_obj); |
| 3053 | ring->mqd_obj = NULL; |
| 3054 | } |
| 3055 | } |
| 3056 | } |
| 3057 | |
| 3058 | static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) |
| 3059 | { |
| 3060 | int r, i, j; |
| 3061 | u32 tmp; |
| 3062 | bool use_doorbell = true; |
| 3063 | u64 hqd_gpu_addr; |
| 3064 | u64 mqd_gpu_addr; |
| 3065 | u64 eop_gpu_addr; |
| 3066 | u64 wb_gpu_addr; |
| 3067 | u32 *buf; |
| 3068 | struct vi_mqd *mqd; |
| 3069 | |
| 3070 | /* init the pipes */ |
| 3071 | mutex_lock(&adev->srbm_mutex); |
| 3072 | for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { |
| 3073 | int me = (i < 4) ? 1 : 2; |
| 3074 | int pipe = (i < 4) ? i : (i - 4); |
| 3075 | |
| 3076 | eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); |
| 3077 | eop_gpu_addr >>= 8; |
| 3078 | |
| 3079 | vi_srbm_select(adev, me, pipe, 0, 0); |
| 3080 | |
| 3081 | /* write the EOP addr */ |
| 3082 | WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr); |
| 3083 | WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr)); |
| 3084 | |
| 3085 | /* set the VMID assigned */ |
| 3086 | WREG32(mmCP_HQD_VMID, 0); |
| 3087 | |
| 3088 | /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ |
| 3089 | tmp = RREG32(mmCP_HQD_EOP_CONTROL); |
| 3090 | tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, |
| 3091 | (order_base_2(MEC_HPD_SIZE / 4) - 1)); |
| 3092 | WREG32(mmCP_HQD_EOP_CONTROL, tmp); |
| 3093 | } |
| 3094 | vi_srbm_select(adev, 0, 0, 0, 0); |
| 3095 | mutex_unlock(&adev->srbm_mutex); |
| 3096 | |
| 3097 | /* init the queues. Just two for now. */ |
| 3098 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
| 3099 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; |
| 3100 | |
| 3101 | if (ring->mqd_obj == NULL) { |
| 3102 | r = amdgpu_bo_create(adev, |
| 3103 | sizeof(struct vi_mqd), |
| 3104 | PAGE_SIZE, true, |
| 3105 | AMDGPU_GEM_DOMAIN_GTT, 0, NULL, |
| 3106 | &ring->mqd_obj); |
| 3107 | if (r) { |
| 3108 | dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); |
| 3109 | return r; |
| 3110 | } |
| 3111 | } |
| 3112 | |
| 3113 | r = amdgpu_bo_reserve(ring->mqd_obj, false); |
| 3114 | if (unlikely(r != 0)) { |
| 3115 | gfx_v8_0_cp_compute_fini(adev); |
| 3116 | return r; |
| 3117 | } |
| 3118 | r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, |
| 3119 | &mqd_gpu_addr); |
| 3120 | if (r) { |
| 3121 | dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); |
| 3122 | gfx_v8_0_cp_compute_fini(adev); |
| 3123 | return r; |
| 3124 | } |
| 3125 | r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); |
| 3126 | if (r) { |
| 3127 | dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); |
| 3128 | gfx_v8_0_cp_compute_fini(adev); |
| 3129 | return r; |
| 3130 | } |
| 3131 | |
| 3132 | /* init the mqd struct */ |
| 3133 | memset(buf, 0, sizeof(struct vi_mqd)); |
| 3134 | |
| 3135 | mqd = (struct vi_mqd *)buf; |
| 3136 | mqd->header = 0xC0310800; |
| 3137 | mqd->compute_pipelinestat_enable = 0x00000001; |
| 3138 | mqd->compute_static_thread_mgmt_se0 = 0xffffffff; |
| 3139 | mqd->compute_static_thread_mgmt_se1 = 0xffffffff; |
| 3140 | mqd->compute_static_thread_mgmt_se2 = 0xffffffff; |
| 3141 | mqd->compute_static_thread_mgmt_se3 = 0xffffffff; |
| 3142 | mqd->compute_misc_reserved = 0x00000003; |
| 3143 | |
| 3144 | mutex_lock(&adev->srbm_mutex); |
| 3145 | vi_srbm_select(adev, ring->me, |
| 3146 | ring->pipe, |
| 3147 | ring->queue, 0); |
| 3148 | |
| 3149 | /* disable wptr polling */ |
| 3150 | tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); |
| 3151 | tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); |
| 3152 | WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); |
| 3153 | |
| 3154 | mqd->cp_hqd_eop_base_addr_lo = |
| 3155 | RREG32(mmCP_HQD_EOP_BASE_ADDR); |
| 3156 | mqd->cp_hqd_eop_base_addr_hi = |
| 3157 | RREG32(mmCP_HQD_EOP_BASE_ADDR_HI); |
| 3158 | |
| 3159 | /* enable doorbell? */ |
| 3160 | tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); |
| 3161 | if (use_doorbell) { |
| 3162 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); |
| 3163 | } else { |
| 3164 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0); |
| 3165 | } |
| 3166 | WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp); |
| 3167 | mqd->cp_hqd_pq_doorbell_control = tmp; |
| 3168 | |
| 3169 | /* disable the queue if it's active */ |
| 3170 | mqd->cp_hqd_dequeue_request = 0; |
| 3171 | mqd->cp_hqd_pq_rptr = 0; |
| 3172 | mqd->cp_hqd_pq_wptr= 0; |
| 3173 | if (RREG32(mmCP_HQD_ACTIVE) & 1) { |
| 3174 | WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); |
| 3175 | for (j = 0; j < adev->usec_timeout; j++) { |
| 3176 | if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) |
| 3177 | break; |
| 3178 | udelay(1); |
| 3179 | } |
| 3180 | WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request); |
| 3181 | WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr); |
| 3182 | WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr); |
| 3183 | } |
| 3184 | |
| 3185 | /* set the pointer to the MQD */ |
| 3186 | mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; |
| 3187 | mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); |
| 3188 | WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); |
| 3189 | WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); |
| 3190 | |
| 3191 | /* set MQD vmid to 0 */ |
| 3192 | tmp = RREG32(mmCP_MQD_CONTROL); |
| 3193 | tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); |
| 3194 | WREG32(mmCP_MQD_CONTROL, tmp); |
| 3195 | mqd->cp_mqd_control = tmp; |
| 3196 | |
| 3197 | /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ |
| 3198 | hqd_gpu_addr = ring->gpu_addr >> 8; |
| 3199 | mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; |
| 3200 | mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); |
| 3201 | WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); |
| 3202 | WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); |
| 3203 | |
| 3204 | /* set up the HQD, this is similar to CP_RB0_CNTL */ |
| 3205 | tmp = RREG32(mmCP_HQD_PQ_CONTROL); |
| 3206 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, |
| 3207 | (order_base_2(ring->ring_size / 4) - 1)); |
| 3208 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, |
| 3209 | ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); |
| 3210 | #ifdef __BIG_ENDIAN |
| 3211 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); |
| 3212 | #endif |
| 3213 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); |
| 3214 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); |
| 3215 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); |
| 3216 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); |
| 3217 | WREG32(mmCP_HQD_PQ_CONTROL, tmp); |
| 3218 | mqd->cp_hqd_pq_control = tmp; |
| 3219 | |
| 3220 | /* set the wb address wether it's enabled or not */ |
| 3221 | wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); |
| 3222 | mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; |
| 3223 | mqd->cp_hqd_pq_rptr_report_addr_hi = |
| 3224 | upper_32_bits(wb_gpu_addr) & 0xffff; |
| 3225 | WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, |
| 3226 | mqd->cp_hqd_pq_rptr_report_addr_lo); |
| 3227 | WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, |
| 3228 | mqd->cp_hqd_pq_rptr_report_addr_hi); |
| 3229 | |
| 3230 | /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ |
| 3231 | wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); |
| 3232 | mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc; |
| 3233 | mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; |
| 3234 | WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr); |
| 3235 | WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, |
| 3236 | mqd->cp_hqd_pq_wptr_poll_addr_hi); |
| 3237 | |
| 3238 | /* enable the doorbell if requested */ |
| 3239 | if (use_doorbell) { |
| 3240 | if (adev->asic_type == CHIP_CARRIZO) { |
| 3241 | WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, |
| 3242 | AMDGPU_DOORBELL_KIQ << 2); |
| 3243 | WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, |
Alex Deucher | b8826b0 | 2015-08-10 11:08:31 -0400 | [diff] [blame] | 3244 | AMDGPU_DOORBELL_MEC_RING7 << 2); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3245 | } |
| 3246 | tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); |
| 3247 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, |
| 3248 | DOORBELL_OFFSET, ring->doorbell_index); |
| 3249 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); |
| 3250 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0); |
| 3251 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0); |
| 3252 | mqd->cp_hqd_pq_doorbell_control = tmp; |
| 3253 | |
| 3254 | } else { |
| 3255 | mqd->cp_hqd_pq_doorbell_control = 0; |
| 3256 | } |
| 3257 | WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, |
| 3258 | mqd->cp_hqd_pq_doorbell_control); |
| 3259 | |
Sonny Jiang | 845253e | 2015-06-23 11:59:55 -0400 | [diff] [blame] | 3260 | /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ |
| 3261 | ring->wptr = 0; |
| 3262 | mqd->cp_hqd_pq_wptr = ring->wptr; |
| 3263 | WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr); |
| 3264 | mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); |
| 3265 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3266 | /* set the vmid for the queue */ |
| 3267 | mqd->cp_hqd_vmid = 0; |
| 3268 | WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid); |
| 3269 | |
| 3270 | tmp = RREG32(mmCP_HQD_PERSISTENT_STATE); |
| 3271 | tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); |
| 3272 | WREG32(mmCP_HQD_PERSISTENT_STATE, tmp); |
| 3273 | mqd->cp_hqd_persistent_state = tmp; |
| 3274 | |
| 3275 | /* activate the queue */ |
| 3276 | mqd->cp_hqd_active = 1; |
| 3277 | WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active); |
| 3278 | |
| 3279 | vi_srbm_select(adev, 0, 0, 0, 0); |
| 3280 | mutex_unlock(&adev->srbm_mutex); |
| 3281 | |
| 3282 | amdgpu_bo_kunmap(ring->mqd_obj); |
| 3283 | amdgpu_bo_unreserve(ring->mqd_obj); |
| 3284 | } |
| 3285 | |
| 3286 | if (use_doorbell) { |
| 3287 | tmp = RREG32(mmCP_PQ_STATUS); |
| 3288 | tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1); |
| 3289 | WREG32(mmCP_PQ_STATUS, tmp); |
| 3290 | } |
| 3291 | |
| 3292 | r = gfx_v8_0_cp_compute_start(adev); |
| 3293 | if (r) |
| 3294 | return r; |
| 3295 | |
| 3296 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
| 3297 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; |
| 3298 | |
| 3299 | ring->ready = true; |
| 3300 | r = amdgpu_ring_test_ring(ring); |
| 3301 | if (r) |
| 3302 | ring->ready = false; |
| 3303 | } |
| 3304 | |
| 3305 | return 0; |
| 3306 | } |
| 3307 | |
| 3308 | static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) |
| 3309 | { |
| 3310 | int r; |
| 3311 | |
| 3312 | if (adev->asic_type != CHIP_CARRIZO) |
| 3313 | gfx_v8_0_enable_gui_idle_interrupt(adev, false); |
| 3314 | |
| 3315 | if (!adev->firmware.smu_load) { |
| 3316 | /* legacy firmware loading */ |
| 3317 | r = gfx_v8_0_cp_gfx_load_microcode(adev); |
| 3318 | if (r) |
| 3319 | return r; |
| 3320 | |
| 3321 | r = gfx_v8_0_cp_compute_load_microcode(adev); |
| 3322 | if (r) |
| 3323 | return r; |
| 3324 | } else { |
| 3325 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, |
| 3326 | AMDGPU_UCODE_ID_CP_CE); |
| 3327 | if (r) |
| 3328 | return -EINVAL; |
| 3329 | |
| 3330 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, |
| 3331 | AMDGPU_UCODE_ID_CP_PFP); |
| 3332 | if (r) |
| 3333 | return -EINVAL; |
| 3334 | |
| 3335 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, |
| 3336 | AMDGPU_UCODE_ID_CP_ME); |
| 3337 | if (r) |
| 3338 | return -EINVAL; |
| 3339 | |
| 3340 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, |
| 3341 | AMDGPU_UCODE_ID_CP_MEC1); |
| 3342 | if (r) |
| 3343 | return -EINVAL; |
| 3344 | } |
| 3345 | |
| 3346 | r = gfx_v8_0_cp_gfx_resume(adev); |
| 3347 | if (r) |
| 3348 | return r; |
| 3349 | |
| 3350 | r = gfx_v8_0_cp_compute_resume(adev); |
| 3351 | if (r) |
| 3352 | return r; |
| 3353 | |
| 3354 | gfx_v8_0_enable_gui_idle_interrupt(adev, true); |
| 3355 | |
| 3356 | return 0; |
| 3357 | } |
| 3358 | |
| 3359 | static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable) |
| 3360 | { |
| 3361 | gfx_v8_0_cp_gfx_enable(adev, enable); |
| 3362 | gfx_v8_0_cp_compute_enable(adev, enable); |
| 3363 | } |
| 3364 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3365 | static int gfx_v8_0_hw_init(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3366 | { |
| 3367 | int r; |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3368 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3369 | |
| 3370 | gfx_v8_0_init_golden_registers(adev); |
| 3371 | |
| 3372 | gfx_v8_0_gpu_init(adev); |
| 3373 | |
| 3374 | r = gfx_v8_0_rlc_resume(adev); |
| 3375 | if (r) |
| 3376 | return r; |
| 3377 | |
| 3378 | r = gfx_v8_0_cp_resume(adev); |
| 3379 | if (r) |
| 3380 | return r; |
| 3381 | |
| 3382 | return r; |
| 3383 | } |
| 3384 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3385 | static int gfx_v8_0_hw_fini(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3386 | { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3387 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 3388 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3389 | gfx_v8_0_cp_enable(adev, false); |
| 3390 | gfx_v8_0_rlc_stop(adev); |
| 3391 | gfx_v8_0_cp_compute_fini(adev); |
| 3392 | |
| 3393 | return 0; |
| 3394 | } |
| 3395 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3396 | static int gfx_v8_0_suspend(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3397 | { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3398 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 3399 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3400 | return gfx_v8_0_hw_fini(adev); |
| 3401 | } |
| 3402 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3403 | static int gfx_v8_0_resume(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3404 | { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3405 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 3406 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3407 | return gfx_v8_0_hw_init(adev); |
| 3408 | } |
| 3409 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3410 | static bool gfx_v8_0_is_idle(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3411 | { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3412 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 3413 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3414 | if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)) |
| 3415 | return false; |
| 3416 | else |
| 3417 | return true; |
| 3418 | } |
| 3419 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3420 | static int gfx_v8_0_wait_for_idle(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3421 | { |
| 3422 | unsigned i; |
| 3423 | u32 tmp; |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3424 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3425 | |
| 3426 | for (i = 0; i < adev->usec_timeout; i++) { |
| 3427 | /* read MC_STATUS */ |
| 3428 | tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; |
| 3429 | |
| 3430 | if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) |
| 3431 | return 0; |
| 3432 | udelay(1); |
| 3433 | } |
| 3434 | return -ETIMEDOUT; |
| 3435 | } |
| 3436 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3437 | static void gfx_v8_0_print_status(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3438 | { |
| 3439 | int i; |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3440 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3441 | |
| 3442 | dev_info(adev->dev, "GFX 8.x registers\n"); |
| 3443 | dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", |
| 3444 | RREG32(mmGRBM_STATUS)); |
| 3445 | dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", |
| 3446 | RREG32(mmGRBM_STATUS2)); |
| 3447 | dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", |
| 3448 | RREG32(mmGRBM_STATUS_SE0)); |
| 3449 | dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", |
| 3450 | RREG32(mmGRBM_STATUS_SE1)); |
| 3451 | dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", |
| 3452 | RREG32(mmGRBM_STATUS_SE2)); |
| 3453 | dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", |
| 3454 | RREG32(mmGRBM_STATUS_SE3)); |
| 3455 | dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); |
| 3456 | dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", |
| 3457 | RREG32(mmCP_STALLED_STAT1)); |
| 3458 | dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", |
| 3459 | RREG32(mmCP_STALLED_STAT2)); |
| 3460 | dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", |
| 3461 | RREG32(mmCP_STALLED_STAT3)); |
| 3462 | dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", |
| 3463 | RREG32(mmCP_CPF_BUSY_STAT)); |
| 3464 | dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", |
| 3465 | RREG32(mmCP_CPF_STALLED_STAT1)); |
| 3466 | dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); |
| 3467 | dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); |
| 3468 | dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", |
| 3469 | RREG32(mmCP_CPC_STALLED_STAT1)); |
| 3470 | dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); |
| 3471 | |
| 3472 | for (i = 0; i < 32; i++) { |
| 3473 | dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", |
| 3474 | i, RREG32(mmGB_TILE_MODE0 + (i * 4))); |
| 3475 | } |
| 3476 | for (i = 0; i < 16; i++) { |
| 3477 | dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", |
| 3478 | i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4))); |
| 3479 | } |
| 3480 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { |
| 3481 | dev_info(adev->dev, " se: %d\n", i); |
| 3482 | gfx_v8_0_select_se_sh(adev, i, 0xffffffff); |
| 3483 | dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", |
| 3484 | RREG32(mmPA_SC_RASTER_CONFIG)); |
| 3485 | dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", |
| 3486 | RREG32(mmPA_SC_RASTER_CONFIG_1)); |
| 3487 | } |
| 3488 | gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); |
| 3489 | |
| 3490 | dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", |
| 3491 | RREG32(mmGB_ADDR_CONFIG)); |
| 3492 | dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n", |
| 3493 | RREG32(mmHDP_ADDR_CONFIG)); |
| 3494 | dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", |
| 3495 | RREG32(mmDMIF_ADDR_CALC)); |
| 3496 | dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n", |
| 3497 | RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET)); |
| 3498 | dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n", |
| 3499 | RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET)); |
| 3500 | dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", |
| 3501 | RREG32(mmUVD_UDEC_ADDR_CONFIG)); |
| 3502 | dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", |
| 3503 | RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); |
| 3504 | dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", |
| 3505 | RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); |
| 3506 | |
| 3507 | dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", |
| 3508 | RREG32(mmCP_MEQ_THRESHOLDS)); |
| 3509 | dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", |
| 3510 | RREG32(mmSX_DEBUG_1)); |
| 3511 | dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", |
| 3512 | RREG32(mmTA_CNTL_AUX)); |
| 3513 | dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", |
| 3514 | RREG32(mmSPI_CONFIG_CNTL)); |
| 3515 | dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", |
| 3516 | RREG32(mmSQ_CONFIG)); |
| 3517 | dev_info(adev->dev, " DB_DEBUG=0x%08X\n", |
| 3518 | RREG32(mmDB_DEBUG)); |
| 3519 | dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", |
| 3520 | RREG32(mmDB_DEBUG2)); |
| 3521 | dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", |
| 3522 | RREG32(mmDB_DEBUG3)); |
| 3523 | dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", |
| 3524 | RREG32(mmCB_HW_CONTROL)); |
| 3525 | dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", |
| 3526 | RREG32(mmSPI_CONFIG_CNTL_1)); |
| 3527 | dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", |
| 3528 | RREG32(mmPA_SC_FIFO_SIZE)); |
| 3529 | dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", |
| 3530 | RREG32(mmVGT_NUM_INSTANCES)); |
| 3531 | dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", |
| 3532 | RREG32(mmCP_PERFMON_CNTL)); |
| 3533 | dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", |
| 3534 | RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS)); |
| 3535 | dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", |
| 3536 | RREG32(mmVGT_CACHE_INVALIDATION)); |
| 3537 | dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", |
| 3538 | RREG32(mmVGT_GS_VERTEX_REUSE)); |
| 3539 | dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", |
| 3540 | RREG32(mmPA_SC_LINE_STIPPLE_STATE)); |
| 3541 | dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", |
| 3542 | RREG32(mmPA_CL_ENHANCE)); |
| 3543 | dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", |
| 3544 | RREG32(mmPA_SC_ENHANCE)); |
| 3545 | |
| 3546 | dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", |
| 3547 | RREG32(mmCP_ME_CNTL)); |
| 3548 | dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", |
| 3549 | RREG32(mmCP_MAX_CONTEXT)); |
| 3550 | dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n", |
| 3551 | RREG32(mmCP_ENDIAN_SWAP)); |
| 3552 | dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", |
| 3553 | RREG32(mmCP_DEVICE_ID)); |
| 3554 | |
| 3555 | dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", |
| 3556 | RREG32(mmCP_SEM_WAIT_TIMER)); |
| 3557 | |
| 3558 | dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", |
| 3559 | RREG32(mmCP_RB_WPTR_DELAY)); |
| 3560 | dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", |
| 3561 | RREG32(mmCP_RB_VMID)); |
| 3562 | dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", |
| 3563 | RREG32(mmCP_RB0_CNTL)); |
| 3564 | dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", |
| 3565 | RREG32(mmCP_RB0_WPTR)); |
| 3566 | dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", |
| 3567 | RREG32(mmCP_RB0_RPTR_ADDR)); |
| 3568 | dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", |
| 3569 | RREG32(mmCP_RB0_RPTR_ADDR_HI)); |
| 3570 | dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", |
| 3571 | RREG32(mmCP_RB0_CNTL)); |
| 3572 | dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", |
| 3573 | RREG32(mmCP_RB0_BASE)); |
| 3574 | dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", |
| 3575 | RREG32(mmCP_RB0_BASE_HI)); |
| 3576 | dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", |
| 3577 | RREG32(mmCP_MEC_CNTL)); |
| 3578 | dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n", |
| 3579 | RREG32(mmCP_CPF_DEBUG)); |
| 3580 | |
| 3581 | dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", |
| 3582 | RREG32(mmSCRATCH_ADDR)); |
| 3583 | dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", |
| 3584 | RREG32(mmSCRATCH_UMSK)); |
| 3585 | |
| 3586 | dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", |
| 3587 | RREG32(mmCP_INT_CNTL_RING0)); |
| 3588 | dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", |
| 3589 | RREG32(mmRLC_LB_CNTL)); |
| 3590 | dev_info(adev->dev, " RLC_CNTL=0x%08X\n", |
| 3591 | RREG32(mmRLC_CNTL)); |
| 3592 | dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", |
| 3593 | RREG32(mmRLC_CGCG_CGLS_CTRL)); |
| 3594 | dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", |
| 3595 | RREG32(mmRLC_LB_CNTR_INIT)); |
| 3596 | dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", |
| 3597 | RREG32(mmRLC_LB_CNTR_MAX)); |
| 3598 | dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", |
| 3599 | RREG32(mmRLC_LB_INIT_CU_MASK)); |
| 3600 | dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", |
| 3601 | RREG32(mmRLC_LB_PARAMS)); |
| 3602 | dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", |
| 3603 | RREG32(mmRLC_LB_CNTL)); |
| 3604 | dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n", |
| 3605 | RREG32(mmRLC_MC_CNTL)); |
| 3606 | dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", |
| 3607 | RREG32(mmRLC_UCODE_CNTL)); |
| 3608 | |
| 3609 | mutex_lock(&adev->srbm_mutex); |
| 3610 | for (i = 0; i < 16; i++) { |
| 3611 | vi_srbm_select(adev, 0, 0, 0, i); |
| 3612 | dev_info(adev->dev, " VM %d:\n", i); |
| 3613 | dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", |
| 3614 | RREG32(mmSH_MEM_CONFIG)); |
| 3615 | dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n", |
| 3616 | RREG32(mmSH_MEM_APE1_BASE)); |
| 3617 | dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n", |
| 3618 | RREG32(mmSH_MEM_APE1_LIMIT)); |
| 3619 | dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", |
| 3620 | RREG32(mmSH_MEM_BASES)); |
| 3621 | } |
| 3622 | vi_srbm_select(adev, 0, 0, 0, 0); |
| 3623 | mutex_unlock(&adev->srbm_mutex); |
| 3624 | } |
| 3625 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3626 | static int gfx_v8_0_soft_reset(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3627 | { |
| 3628 | u32 grbm_soft_reset = 0, srbm_soft_reset = 0; |
| 3629 | u32 tmp; |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3630 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3631 | |
| 3632 | /* GRBM_STATUS */ |
| 3633 | tmp = RREG32(mmGRBM_STATUS); |
| 3634 | if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | |
| 3635 | GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | |
| 3636 | GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | |
| 3637 | GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | |
| 3638 | GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | |
| 3639 | GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { |
| 3640 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, |
| 3641 | GRBM_SOFT_RESET, SOFT_RESET_CP, 1); |
| 3642 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, |
| 3643 | GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); |
| 3644 | } |
| 3645 | |
| 3646 | if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { |
| 3647 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, |
| 3648 | GRBM_SOFT_RESET, SOFT_RESET_CP, 1); |
| 3649 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, |
| 3650 | SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); |
| 3651 | } |
| 3652 | |
| 3653 | /* GRBM_STATUS2 */ |
| 3654 | tmp = RREG32(mmGRBM_STATUS2); |
| 3655 | if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) |
| 3656 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, |
| 3657 | GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); |
| 3658 | |
| 3659 | /* SRBM_STATUS */ |
| 3660 | tmp = RREG32(mmSRBM_STATUS); |
| 3661 | if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING)) |
| 3662 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, |
| 3663 | SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); |
| 3664 | |
| 3665 | if (grbm_soft_reset || srbm_soft_reset) { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3666 | gfx_v8_0_print_status((void *)adev); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3667 | /* stop the rlc */ |
| 3668 | gfx_v8_0_rlc_stop(adev); |
| 3669 | |
| 3670 | /* Disable GFX parsing/prefetching */ |
| 3671 | gfx_v8_0_cp_gfx_enable(adev, false); |
| 3672 | |
| 3673 | /* Disable MEC parsing/prefetching */ |
| 3674 | /* XXX todo */ |
| 3675 | |
| 3676 | if (grbm_soft_reset) { |
| 3677 | tmp = RREG32(mmGRBM_SOFT_RESET); |
| 3678 | tmp |= grbm_soft_reset; |
| 3679 | dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); |
| 3680 | WREG32(mmGRBM_SOFT_RESET, tmp); |
| 3681 | tmp = RREG32(mmGRBM_SOFT_RESET); |
| 3682 | |
| 3683 | udelay(50); |
| 3684 | |
| 3685 | tmp &= ~grbm_soft_reset; |
| 3686 | WREG32(mmGRBM_SOFT_RESET, tmp); |
| 3687 | tmp = RREG32(mmGRBM_SOFT_RESET); |
| 3688 | } |
| 3689 | |
| 3690 | if (srbm_soft_reset) { |
| 3691 | tmp = RREG32(mmSRBM_SOFT_RESET); |
| 3692 | tmp |= srbm_soft_reset; |
| 3693 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); |
| 3694 | WREG32(mmSRBM_SOFT_RESET, tmp); |
| 3695 | tmp = RREG32(mmSRBM_SOFT_RESET); |
| 3696 | |
| 3697 | udelay(50); |
| 3698 | |
| 3699 | tmp &= ~srbm_soft_reset; |
| 3700 | WREG32(mmSRBM_SOFT_RESET, tmp); |
| 3701 | tmp = RREG32(mmSRBM_SOFT_RESET); |
| 3702 | } |
| 3703 | /* Wait a little for things to settle down */ |
| 3704 | udelay(50); |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3705 | gfx_v8_0_print_status((void *)adev); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3706 | } |
| 3707 | return 0; |
| 3708 | } |
| 3709 | |
| 3710 | /** |
| 3711 | * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot |
| 3712 | * |
| 3713 | * @adev: amdgpu_device pointer |
| 3714 | * |
| 3715 | * Fetches a GPU clock counter snapshot. |
| 3716 | * Returns the 64 bit clock counter snapshot. |
| 3717 | */ |
| 3718 | uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev) |
| 3719 | { |
| 3720 | uint64_t clock; |
| 3721 | |
| 3722 | mutex_lock(&adev->gfx.gpu_clock_mutex); |
| 3723 | WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); |
| 3724 | clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | |
| 3725 | ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); |
| 3726 | mutex_unlock(&adev->gfx.gpu_clock_mutex); |
| 3727 | return clock; |
| 3728 | } |
| 3729 | |
| 3730 | static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring, |
| 3731 | uint32_t vmid, |
| 3732 | uint32_t gds_base, uint32_t gds_size, |
| 3733 | uint32_t gws_base, uint32_t gws_size, |
| 3734 | uint32_t oa_base, uint32_t oa_size) |
| 3735 | { |
| 3736 | gds_base = gds_base >> AMDGPU_GDS_SHIFT; |
| 3737 | gds_size = gds_size >> AMDGPU_GDS_SHIFT; |
| 3738 | |
| 3739 | gws_base = gws_base >> AMDGPU_GWS_SHIFT; |
| 3740 | gws_size = gws_size >> AMDGPU_GWS_SHIFT; |
| 3741 | |
| 3742 | oa_base = oa_base >> AMDGPU_OA_SHIFT; |
| 3743 | oa_size = oa_size >> AMDGPU_OA_SHIFT; |
| 3744 | |
| 3745 | /* GDS Base */ |
| 3746 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 3747 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | |
| 3748 | WRITE_DATA_DST_SEL(0))); |
| 3749 | amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); |
| 3750 | amdgpu_ring_write(ring, 0); |
| 3751 | amdgpu_ring_write(ring, gds_base); |
| 3752 | |
| 3753 | /* GDS Size */ |
| 3754 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 3755 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | |
| 3756 | WRITE_DATA_DST_SEL(0))); |
| 3757 | amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); |
| 3758 | amdgpu_ring_write(ring, 0); |
| 3759 | amdgpu_ring_write(ring, gds_size); |
| 3760 | |
| 3761 | /* GWS */ |
| 3762 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 3763 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | |
| 3764 | WRITE_DATA_DST_SEL(0))); |
| 3765 | amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); |
| 3766 | amdgpu_ring_write(ring, 0); |
| 3767 | amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); |
| 3768 | |
| 3769 | /* OA */ |
| 3770 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 3771 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | |
| 3772 | WRITE_DATA_DST_SEL(0))); |
| 3773 | amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); |
| 3774 | amdgpu_ring_write(ring, 0); |
| 3775 | amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); |
| 3776 | } |
| 3777 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3778 | static int gfx_v8_0_early_init(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3779 | { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3780 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3781 | |
| 3782 | adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; |
| 3783 | adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS; |
| 3784 | gfx_v8_0_set_ring_funcs(adev); |
| 3785 | gfx_v8_0_set_irq_funcs(adev); |
| 3786 | gfx_v8_0_set_gds_init(adev); |
| 3787 | |
| 3788 | return 0; |
| 3789 | } |
| 3790 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3791 | static int gfx_v8_0_set_powergating_state(void *handle, |
| 3792 | enum amd_powergating_state state) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3793 | { |
| 3794 | return 0; |
| 3795 | } |
| 3796 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3797 | static int gfx_v8_0_set_clockgating_state(void *handle, |
| 3798 | enum amd_clockgating_state state) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3799 | { |
| 3800 | return 0; |
| 3801 | } |
| 3802 | |
| 3803 | static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) |
| 3804 | { |
| 3805 | u32 rptr; |
| 3806 | |
| 3807 | rptr = ring->adev->wb.wb[ring->rptr_offs]; |
| 3808 | |
| 3809 | return rptr; |
| 3810 | } |
| 3811 | |
| 3812 | static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) |
| 3813 | { |
| 3814 | struct amdgpu_device *adev = ring->adev; |
| 3815 | u32 wptr; |
| 3816 | |
| 3817 | if (ring->use_doorbell) |
| 3818 | /* XXX check if swapping is necessary on BE */ |
| 3819 | wptr = ring->adev->wb.wb[ring->wptr_offs]; |
| 3820 | else |
| 3821 | wptr = RREG32(mmCP_RB0_WPTR); |
| 3822 | |
| 3823 | return wptr; |
| 3824 | } |
| 3825 | |
| 3826 | static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) |
| 3827 | { |
| 3828 | struct amdgpu_device *adev = ring->adev; |
| 3829 | |
| 3830 | if (ring->use_doorbell) { |
| 3831 | /* XXX check if swapping is necessary on BE */ |
| 3832 | adev->wb.wb[ring->wptr_offs] = ring->wptr; |
| 3833 | WDOORBELL32(ring->doorbell_index, ring->wptr); |
| 3834 | } else { |
| 3835 | WREG32(mmCP_RB0_WPTR, ring->wptr); |
| 3836 | (void)RREG32(mmCP_RB0_WPTR); |
| 3837 | } |
| 3838 | } |
| 3839 | |
Christian König | d2edb07 | 2015-05-11 14:10:34 +0200 | [diff] [blame] | 3840 | static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3841 | { |
| 3842 | u32 ref_and_mask, reg_mem_engine; |
| 3843 | |
| 3844 | if (ring->type == AMDGPU_RING_TYPE_COMPUTE) { |
| 3845 | switch (ring->me) { |
| 3846 | case 1: |
| 3847 | ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; |
| 3848 | break; |
| 3849 | case 2: |
| 3850 | ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; |
| 3851 | break; |
| 3852 | default: |
| 3853 | return; |
| 3854 | } |
| 3855 | reg_mem_engine = 0; |
| 3856 | } else { |
| 3857 | ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; |
| 3858 | reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */ |
| 3859 | } |
| 3860 | |
| 3861 | amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); |
| 3862 | amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ |
| 3863 | WAIT_REG_MEM_FUNCTION(3) | /* == */ |
| 3864 | reg_mem_engine)); |
| 3865 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); |
| 3866 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); |
| 3867 | amdgpu_ring_write(ring, ref_and_mask); |
| 3868 | amdgpu_ring_write(ring, ref_and_mask); |
| 3869 | amdgpu_ring_write(ring, 0x20); /* poll interval */ |
| 3870 | } |
| 3871 | |
monk.liu | 9332313 | 2015-07-15 17:21:45 +0800 | [diff] [blame] | 3872 | static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3873 | struct amdgpu_ib *ib) |
| 3874 | { |
Christian König | 3cb485f | 2015-05-11 15:34:59 +0200 | [diff] [blame] | 3875 | bool need_ctx_switch = ring->current_ctx != ib->ctx; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3876 | u32 header, control = 0; |
| 3877 | u32 next_rptr = ring->wptr + 5; |
Jammy Zhou | aa2bdb24 | 2015-05-11 23:49:34 +0800 | [diff] [blame] | 3878 | |
| 3879 | /* drop the CE preamble IB for the same context */ |
monk.liu | 9332313 | 2015-07-15 17:21:45 +0800 | [diff] [blame] | 3880 | if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch) |
Jammy Zhou | aa2bdb24 | 2015-05-11 23:49:34 +0800 | [diff] [blame] | 3881 | return; |
| 3882 | |
monk.liu | 9332313 | 2015-07-15 17:21:45 +0800 | [diff] [blame] | 3883 | if (need_ctx_switch) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3884 | next_rptr += 2; |
| 3885 | |
| 3886 | next_rptr += 4; |
| 3887 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 3888 | amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); |
| 3889 | amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); |
| 3890 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); |
| 3891 | amdgpu_ring_write(ring, next_rptr); |
| 3892 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3893 | /* insert SWITCH_BUFFER packet before first IB in the ring frame */ |
monk.liu | 9332313 | 2015-07-15 17:21:45 +0800 | [diff] [blame] | 3894 | if (need_ctx_switch) { |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3895 | amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); |
| 3896 | amdgpu_ring_write(ring, 0); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3897 | } |
| 3898 | |
Jammy Zhou | de807f8 | 2015-05-11 23:41:41 +0800 | [diff] [blame] | 3899 | if (ib->flags & AMDGPU_IB_FLAG_CE) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3900 | header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); |
| 3901 | else |
| 3902 | header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); |
| 3903 | |
| 3904 | control |= ib->length_dw | |
| 3905 | (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0); |
| 3906 | |
| 3907 | amdgpu_ring_write(ring, header); |
| 3908 | amdgpu_ring_write(ring, |
| 3909 | #ifdef __BIG_ENDIAN |
| 3910 | (2 << 0) | |
| 3911 | #endif |
| 3912 | (ib->gpu_addr & 0xFFFFFFFC)); |
| 3913 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); |
| 3914 | amdgpu_ring_write(ring, control); |
| 3915 | } |
| 3916 | |
monk.liu | 9332313 | 2015-07-15 17:21:45 +0800 | [diff] [blame] | 3917 | static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring, |
| 3918 | struct amdgpu_ib *ib) |
| 3919 | { |
| 3920 | u32 header, control = 0; |
| 3921 | u32 next_rptr = ring->wptr + 5; |
| 3922 | |
| 3923 | control |= INDIRECT_BUFFER_VALID; |
| 3924 | |
| 3925 | next_rptr += 4; |
| 3926 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 3927 | amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); |
| 3928 | amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); |
| 3929 | amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); |
| 3930 | amdgpu_ring_write(ring, next_rptr); |
| 3931 | |
| 3932 | header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); |
| 3933 | |
| 3934 | control |= ib->length_dw | |
| 3935 | (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0); |
| 3936 | |
| 3937 | amdgpu_ring_write(ring, header); |
| 3938 | amdgpu_ring_write(ring, |
| 3939 | #ifdef __BIG_ENDIAN |
| 3940 | (2 << 0) | |
| 3941 | #endif |
| 3942 | (ib->gpu_addr & 0xFFFFFFFC)); |
| 3943 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); |
| 3944 | amdgpu_ring_write(ring, control); |
| 3945 | } |
| 3946 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3947 | static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, |
Chunming Zhou | 890ee23 | 2015-06-01 14:35:03 +0800 | [diff] [blame] | 3948 | u64 seq, unsigned flags) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3949 | { |
Chunming Zhou | 890ee23 | 2015-06-01 14:35:03 +0800 | [diff] [blame] | 3950 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
| 3951 | bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; |
| 3952 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3953 | /* EVENT_WRITE_EOP - flush caches, send int */ |
| 3954 | amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
| 3955 | amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | |
| 3956 | EOP_TC_ACTION_EN | |
| 3957 | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | |
| 3958 | EVENT_INDEX(5))); |
| 3959 | amdgpu_ring_write(ring, addr & 0xfffffffc); |
| 3960 | amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | |
Chunming Zhou | 890ee23 | 2015-06-01 14:35:03 +0800 | [diff] [blame] | 3961 | DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3962 | amdgpu_ring_write(ring, lower_32_bits(seq)); |
| 3963 | amdgpu_ring_write(ring, upper_32_bits(seq)); |
| 3964 | } |
| 3965 | |
| 3966 | /** |
| 3967 | * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring |
| 3968 | * |
| 3969 | * @ring: amdgpu ring buffer object |
| 3970 | * @semaphore: amdgpu semaphore object |
| 3971 | * @emit_wait: Is this a sempahore wait? |
| 3972 | * |
| 3973 | * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP |
| 3974 | * from running ahead of semaphore waits. |
| 3975 | */ |
| 3976 | static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring, |
| 3977 | struct amdgpu_semaphore *semaphore, |
| 3978 | bool emit_wait) |
| 3979 | { |
| 3980 | uint64_t addr = semaphore->gpu_addr; |
| 3981 | unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; |
| 3982 | |
| 3983 | if (ring->adev->asic_type == CHIP_TOPAZ || |
David Zhang | af15a2d | 2015-07-30 19:42:11 -0400 | [diff] [blame^] | 3984 | ring->adev->asic_type == CHIP_TONGA || |
| 3985 | ring->adev->asic_type == CHIP_FIJI) |
David Zhang | 147dbfb | 2015-06-11 02:28:56 +0800 | [diff] [blame] | 3986 | /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */ |
| 3987 | return false; |
| 3988 | else { |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3989 | amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2)); |
| 3990 | amdgpu_ring_write(ring, lower_32_bits(addr)); |
| 3991 | amdgpu_ring_write(ring, upper_32_bits(addr)); |
| 3992 | amdgpu_ring_write(ring, sel); |
| 3993 | } |
| 3994 | |
| 3995 | if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) { |
| 3996 | /* Prevent the PFP from running ahead of the semaphore wait */ |
| 3997 | amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); |
| 3998 | amdgpu_ring_write(ring, 0x0); |
| 3999 | } |
| 4000 | |
| 4001 | return true; |
| 4002 | } |
| 4003 | |
| 4004 | static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring) |
| 4005 | { |
| 4006 | struct amdgpu_device *adev = ring->adev; |
| 4007 | u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4; |
| 4008 | |
| 4009 | /* instruct DE to set a magic number */ |
| 4010 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 4011 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | |
| 4012 | WRITE_DATA_DST_SEL(5))); |
| 4013 | amdgpu_ring_write(ring, gpu_addr & 0xfffffffc); |
| 4014 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff); |
| 4015 | amdgpu_ring_write(ring, 1); |
| 4016 | |
| 4017 | /* let CE wait till condition satisfied */ |
| 4018 | amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); |
| 4019 | amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ |
| 4020 | WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ |
| 4021 | WAIT_REG_MEM_FUNCTION(3) | /* == */ |
| 4022 | WAIT_REG_MEM_ENGINE(2))); /* ce */ |
| 4023 | amdgpu_ring_write(ring, gpu_addr & 0xfffffffc); |
| 4024 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff); |
| 4025 | amdgpu_ring_write(ring, 1); |
| 4026 | amdgpu_ring_write(ring, 0xffffffff); |
| 4027 | amdgpu_ring_write(ring, 4); /* poll interval */ |
| 4028 | |
| 4029 | /* instruct CE to reset wb of ce_sync to zero */ |
| 4030 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 4031 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | |
| 4032 | WRITE_DATA_DST_SEL(5) | |
| 4033 | WR_CONFIRM)); |
| 4034 | amdgpu_ring_write(ring, gpu_addr & 0xfffffffc); |
| 4035 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff); |
| 4036 | amdgpu_ring_write(ring, 0); |
| 4037 | } |
| 4038 | |
| 4039 | static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, |
| 4040 | unsigned vm_id, uint64_t pd_addr) |
| 4041 | { |
| 4042 | int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 4043 | |
| 4044 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 4045 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | |
| 4046 | WRITE_DATA_DST_SEL(0))); |
| 4047 | if (vm_id < 8) { |
| 4048 | amdgpu_ring_write(ring, |
| 4049 | (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); |
| 4050 | } else { |
| 4051 | amdgpu_ring_write(ring, |
| 4052 | (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); |
| 4053 | } |
| 4054 | amdgpu_ring_write(ring, 0); |
| 4055 | amdgpu_ring_write(ring, pd_addr >> 12); |
| 4056 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 4057 | /* bits 0-15 are the VM contexts0-15 */ |
| 4058 | /* invalidate the cache */ |
| 4059 | amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); |
| 4060 | amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | |
| 4061 | WRITE_DATA_DST_SEL(0))); |
| 4062 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); |
| 4063 | amdgpu_ring_write(ring, 0); |
| 4064 | amdgpu_ring_write(ring, 1 << vm_id); |
| 4065 | |
| 4066 | /* wait for the invalidate to complete */ |
| 4067 | amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); |
| 4068 | amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ |
| 4069 | WAIT_REG_MEM_FUNCTION(0) | /* always */ |
| 4070 | WAIT_REG_MEM_ENGINE(0))); /* me */ |
| 4071 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); |
| 4072 | amdgpu_ring_write(ring, 0); |
| 4073 | amdgpu_ring_write(ring, 0); /* ref */ |
| 4074 | amdgpu_ring_write(ring, 0); /* mask */ |
| 4075 | amdgpu_ring_write(ring, 0x20); /* poll interval */ |
| 4076 | |
| 4077 | /* compute doesn't have PFP */ |
| 4078 | if (usepfp) { |
| 4079 | /* sync PFP to ME, otherwise we might get invalid PFP reads */ |
| 4080 | amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); |
| 4081 | amdgpu_ring_write(ring, 0x0); |
| 4082 | |
| 4083 | /* synce CE with ME to prevent CE fetch CEIB before context switch done */ |
| 4084 | gfx_v8_0_ce_sync_me(ring); |
| 4085 | } |
| 4086 | } |
| 4087 | |
| 4088 | static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring) |
| 4089 | { |
| 4090 | if (gfx_v8_0_is_idle(ring->adev)) { |
| 4091 | amdgpu_ring_lockup_update(ring); |
| 4092 | return false; |
| 4093 | } |
| 4094 | return amdgpu_ring_test_lockup(ring); |
| 4095 | } |
| 4096 | |
| 4097 | static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring) |
| 4098 | { |
| 4099 | return ring->adev->wb.wb[ring->rptr_offs]; |
| 4100 | } |
| 4101 | |
| 4102 | static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring) |
| 4103 | { |
| 4104 | return ring->adev->wb.wb[ring->wptr_offs]; |
| 4105 | } |
| 4106 | |
| 4107 | static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring) |
| 4108 | { |
| 4109 | struct amdgpu_device *adev = ring->adev; |
| 4110 | |
| 4111 | /* XXX check if swapping is necessary on BE */ |
| 4112 | adev->wb.wb[ring->wptr_offs] = ring->wptr; |
| 4113 | WDOORBELL32(ring->doorbell_index, ring->wptr); |
| 4114 | } |
| 4115 | |
| 4116 | static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring, |
| 4117 | u64 addr, u64 seq, |
Chunming Zhou | 890ee23 | 2015-06-01 14:35:03 +0800 | [diff] [blame] | 4118 | unsigned flags) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 4119 | { |
Chunming Zhou | 890ee23 | 2015-06-01 14:35:03 +0800 | [diff] [blame] | 4120 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
| 4121 | bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; |
| 4122 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 4123 | /* RELEASE_MEM - flush caches, send int */ |
| 4124 | amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); |
| 4125 | amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | |
| 4126 | EOP_TC_ACTION_EN | |
| 4127 | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | |
| 4128 | EVENT_INDEX(5))); |
Chunming Zhou | 890ee23 | 2015-06-01 14:35:03 +0800 | [diff] [blame] | 4129 | amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 4130 | amdgpu_ring_write(ring, addr & 0xfffffffc); |
| 4131 | amdgpu_ring_write(ring, upper_32_bits(addr)); |
| 4132 | amdgpu_ring_write(ring, lower_32_bits(seq)); |
| 4133 | amdgpu_ring_write(ring, upper_32_bits(seq)); |
| 4134 | } |
| 4135 | |
| 4136 | static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, |
| 4137 | enum amdgpu_interrupt_state state) |
| 4138 | { |
| 4139 | u32 cp_int_cntl; |
| 4140 | |
| 4141 | switch (state) { |
| 4142 | case AMDGPU_IRQ_STATE_DISABLE: |
| 4143 | cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); |
| 4144 | cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, |
| 4145 | TIME_STAMP_INT_ENABLE, 0); |
| 4146 | WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); |
| 4147 | break; |
| 4148 | case AMDGPU_IRQ_STATE_ENABLE: |
| 4149 | cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); |
| 4150 | cp_int_cntl = |
| 4151 | REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, |
| 4152 | TIME_STAMP_INT_ENABLE, 1); |
| 4153 | WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); |
| 4154 | break; |
| 4155 | default: |
| 4156 | break; |
| 4157 | } |
| 4158 | } |
| 4159 | |
| 4160 | static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, |
| 4161 | int me, int pipe, |
| 4162 | enum amdgpu_interrupt_state state) |
| 4163 | { |
| 4164 | u32 mec_int_cntl, mec_int_cntl_reg; |
| 4165 | |
| 4166 | /* |
| 4167 | * amdgpu controls only pipe 0 of MEC1. That's why this function only |
| 4168 | * handles the setting of interrupts for this specific pipe. All other |
| 4169 | * pipes' interrupts are set by amdkfd. |
| 4170 | */ |
| 4171 | |
| 4172 | if (me == 1) { |
| 4173 | switch (pipe) { |
| 4174 | case 0: |
| 4175 | mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; |
| 4176 | break; |
| 4177 | default: |
| 4178 | DRM_DEBUG("invalid pipe %d\n", pipe); |
| 4179 | return; |
| 4180 | } |
| 4181 | } else { |
| 4182 | DRM_DEBUG("invalid me %d\n", me); |
| 4183 | return; |
| 4184 | } |
| 4185 | |
| 4186 | switch (state) { |
| 4187 | case AMDGPU_IRQ_STATE_DISABLE: |
| 4188 | mec_int_cntl = RREG32(mec_int_cntl_reg); |
| 4189 | mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, |
| 4190 | TIME_STAMP_INT_ENABLE, 0); |
| 4191 | WREG32(mec_int_cntl_reg, mec_int_cntl); |
| 4192 | break; |
| 4193 | case AMDGPU_IRQ_STATE_ENABLE: |
| 4194 | mec_int_cntl = RREG32(mec_int_cntl_reg); |
| 4195 | mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, |
| 4196 | TIME_STAMP_INT_ENABLE, 1); |
| 4197 | WREG32(mec_int_cntl_reg, mec_int_cntl); |
| 4198 | break; |
| 4199 | default: |
| 4200 | break; |
| 4201 | } |
| 4202 | } |
| 4203 | |
| 4204 | static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev, |
| 4205 | struct amdgpu_irq_src *source, |
| 4206 | unsigned type, |
| 4207 | enum amdgpu_interrupt_state state) |
| 4208 | { |
| 4209 | u32 cp_int_cntl; |
| 4210 | |
| 4211 | switch (state) { |
| 4212 | case AMDGPU_IRQ_STATE_DISABLE: |
| 4213 | cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); |
| 4214 | cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, |
| 4215 | PRIV_REG_INT_ENABLE, 0); |
| 4216 | WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); |
| 4217 | break; |
| 4218 | case AMDGPU_IRQ_STATE_ENABLE: |
| 4219 | cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); |
| 4220 | cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, |
| 4221 | PRIV_REG_INT_ENABLE, 0); |
| 4222 | WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); |
| 4223 | break; |
| 4224 | default: |
| 4225 | break; |
| 4226 | } |
| 4227 | |
| 4228 | return 0; |
| 4229 | } |
| 4230 | |
| 4231 | static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev, |
| 4232 | struct amdgpu_irq_src *source, |
| 4233 | unsigned type, |
| 4234 | enum amdgpu_interrupt_state state) |
| 4235 | { |
| 4236 | u32 cp_int_cntl; |
| 4237 | |
| 4238 | switch (state) { |
| 4239 | case AMDGPU_IRQ_STATE_DISABLE: |
| 4240 | cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); |
| 4241 | cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, |
| 4242 | PRIV_INSTR_INT_ENABLE, 0); |
| 4243 | WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); |
| 4244 | break; |
| 4245 | case AMDGPU_IRQ_STATE_ENABLE: |
| 4246 | cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); |
| 4247 | cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, |
| 4248 | PRIV_INSTR_INT_ENABLE, 1); |
| 4249 | WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); |
| 4250 | break; |
| 4251 | default: |
| 4252 | break; |
| 4253 | } |
| 4254 | |
| 4255 | return 0; |
| 4256 | } |
| 4257 | |
| 4258 | static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev, |
| 4259 | struct amdgpu_irq_src *src, |
| 4260 | unsigned type, |
| 4261 | enum amdgpu_interrupt_state state) |
| 4262 | { |
| 4263 | switch (type) { |
| 4264 | case AMDGPU_CP_IRQ_GFX_EOP: |
| 4265 | gfx_v8_0_set_gfx_eop_interrupt_state(adev, state); |
| 4266 | break; |
| 4267 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: |
| 4268 | gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state); |
| 4269 | break; |
| 4270 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: |
| 4271 | gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state); |
| 4272 | break; |
| 4273 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: |
| 4274 | gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state); |
| 4275 | break; |
| 4276 | case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: |
| 4277 | gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state); |
| 4278 | break; |
| 4279 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: |
| 4280 | gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state); |
| 4281 | break; |
| 4282 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: |
| 4283 | gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state); |
| 4284 | break; |
| 4285 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: |
| 4286 | gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state); |
| 4287 | break; |
| 4288 | case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: |
| 4289 | gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state); |
| 4290 | break; |
| 4291 | default: |
| 4292 | break; |
| 4293 | } |
| 4294 | return 0; |
| 4295 | } |
| 4296 | |
| 4297 | static int gfx_v8_0_eop_irq(struct amdgpu_device *adev, |
| 4298 | struct amdgpu_irq_src *source, |
| 4299 | struct amdgpu_iv_entry *entry) |
| 4300 | { |
| 4301 | int i; |
| 4302 | u8 me_id, pipe_id, queue_id; |
| 4303 | struct amdgpu_ring *ring; |
| 4304 | |
| 4305 | DRM_DEBUG("IH: CP EOP\n"); |
| 4306 | me_id = (entry->ring_id & 0x0c) >> 2; |
| 4307 | pipe_id = (entry->ring_id & 0x03) >> 0; |
| 4308 | queue_id = (entry->ring_id & 0x70) >> 4; |
| 4309 | |
| 4310 | switch (me_id) { |
| 4311 | case 0: |
| 4312 | amdgpu_fence_process(&adev->gfx.gfx_ring[0]); |
| 4313 | break; |
| 4314 | case 1: |
| 4315 | case 2: |
| 4316 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
| 4317 | ring = &adev->gfx.compute_ring[i]; |
| 4318 | /* Per-queue interrupt is supported for MEC starting from VI. |
| 4319 | * The interrupt can only be enabled/disabled per pipe instead of per queue. |
| 4320 | */ |
| 4321 | if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) |
| 4322 | amdgpu_fence_process(ring); |
| 4323 | } |
| 4324 | break; |
| 4325 | } |
| 4326 | return 0; |
| 4327 | } |
| 4328 | |
| 4329 | static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev, |
| 4330 | struct amdgpu_irq_src *source, |
| 4331 | struct amdgpu_iv_entry *entry) |
| 4332 | { |
| 4333 | DRM_ERROR("Illegal register access in command stream\n"); |
| 4334 | schedule_work(&adev->reset_work); |
| 4335 | return 0; |
| 4336 | } |
| 4337 | |
| 4338 | static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev, |
| 4339 | struct amdgpu_irq_src *source, |
| 4340 | struct amdgpu_iv_entry *entry) |
| 4341 | { |
| 4342 | DRM_ERROR("Illegal instruction in command stream\n"); |
| 4343 | schedule_work(&adev->reset_work); |
| 4344 | return 0; |
| 4345 | } |
| 4346 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 4347 | const struct amd_ip_funcs gfx_v8_0_ip_funcs = { |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 4348 | .early_init = gfx_v8_0_early_init, |
| 4349 | .late_init = NULL, |
| 4350 | .sw_init = gfx_v8_0_sw_init, |
| 4351 | .sw_fini = gfx_v8_0_sw_fini, |
| 4352 | .hw_init = gfx_v8_0_hw_init, |
| 4353 | .hw_fini = gfx_v8_0_hw_fini, |
| 4354 | .suspend = gfx_v8_0_suspend, |
| 4355 | .resume = gfx_v8_0_resume, |
| 4356 | .is_idle = gfx_v8_0_is_idle, |
| 4357 | .wait_for_idle = gfx_v8_0_wait_for_idle, |
| 4358 | .soft_reset = gfx_v8_0_soft_reset, |
| 4359 | .print_status = gfx_v8_0_print_status, |
| 4360 | .set_clockgating_state = gfx_v8_0_set_clockgating_state, |
| 4361 | .set_powergating_state = gfx_v8_0_set_powergating_state, |
| 4362 | }; |
| 4363 | |
| 4364 | static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { |
| 4365 | .get_rptr = gfx_v8_0_ring_get_rptr_gfx, |
| 4366 | .get_wptr = gfx_v8_0_ring_get_wptr_gfx, |
| 4367 | .set_wptr = gfx_v8_0_ring_set_wptr_gfx, |
| 4368 | .parse_cs = NULL, |
monk.liu | 9332313 | 2015-07-15 17:21:45 +0800 | [diff] [blame] | 4369 | .emit_ib = gfx_v8_0_ring_emit_ib_gfx, |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 4370 | .emit_fence = gfx_v8_0_ring_emit_fence_gfx, |
| 4371 | .emit_semaphore = gfx_v8_0_ring_emit_semaphore, |
| 4372 | .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, |
| 4373 | .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, |
Christian König | d2edb07 | 2015-05-11 14:10:34 +0200 | [diff] [blame] | 4374 | .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 4375 | .test_ring = gfx_v8_0_ring_test_ring, |
| 4376 | .test_ib = gfx_v8_0_ring_test_ib, |
| 4377 | .is_lockup = gfx_v8_0_ring_is_lockup, |
| 4378 | }; |
| 4379 | |
| 4380 | static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { |
| 4381 | .get_rptr = gfx_v8_0_ring_get_rptr_compute, |
| 4382 | .get_wptr = gfx_v8_0_ring_get_wptr_compute, |
| 4383 | .set_wptr = gfx_v8_0_ring_set_wptr_compute, |
| 4384 | .parse_cs = NULL, |
monk.liu | 9332313 | 2015-07-15 17:21:45 +0800 | [diff] [blame] | 4385 | .emit_ib = gfx_v8_0_ring_emit_ib_compute, |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 4386 | .emit_fence = gfx_v8_0_ring_emit_fence_compute, |
| 4387 | .emit_semaphore = gfx_v8_0_ring_emit_semaphore, |
| 4388 | .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, |
| 4389 | .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, |
monk.liu | 35074d2 | 2015-06-03 16:32:49 +0800 | [diff] [blame] | 4390 | .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 4391 | .test_ring = gfx_v8_0_ring_test_ring, |
| 4392 | .test_ib = gfx_v8_0_ring_test_ib, |
| 4393 | .is_lockup = gfx_v8_0_ring_is_lockup, |
| 4394 | }; |
| 4395 | |
| 4396 | static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev) |
| 4397 | { |
| 4398 | int i; |
| 4399 | |
| 4400 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
| 4401 | adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx; |
| 4402 | |
| 4403 | for (i = 0; i < adev->gfx.num_compute_rings; i++) |
| 4404 | adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute; |
| 4405 | } |
| 4406 | |
| 4407 | static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = { |
| 4408 | .set = gfx_v8_0_set_eop_interrupt_state, |
| 4409 | .process = gfx_v8_0_eop_irq, |
| 4410 | }; |
| 4411 | |
| 4412 | static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = { |
| 4413 | .set = gfx_v8_0_set_priv_reg_fault_state, |
| 4414 | .process = gfx_v8_0_priv_reg_irq, |
| 4415 | }; |
| 4416 | |
| 4417 | static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = { |
| 4418 | .set = gfx_v8_0_set_priv_inst_fault_state, |
| 4419 | .process = gfx_v8_0_priv_inst_irq, |
| 4420 | }; |
| 4421 | |
| 4422 | static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev) |
| 4423 | { |
| 4424 | adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; |
| 4425 | adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; |
| 4426 | |
| 4427 | adev->gfx.priv_reg_irq.num_types = 1; |
| 4428 | adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; |
| 4429 | |
| 4430 | adev->gfx.priv_inst_irq.num_types = 1; |
| 4431 | adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; |
| 4432 | } |
| 4433 | |
| 4434 | static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev) |
| 4435 | { |
| 4436 | /* init asci gds info */ |
| 4437 | adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); |
| 4438 | adev->gds.gws.total_size = 64; |
| 4439 | adev->gds.oa.total_size = 16; |
| 4440 | |
| 4441 | if (adev->gds.mem.total_size == 64 * 1024) { |
| 4442 | adev->gds.mem.gfx_partition_size = 4096; |
| 4443 | adev->gds.mem.cs_partition_size = 4096; |
| 4444 | |
| 4445 | adev->gds.gws.gfx_partition_size = 4; |
| 4446 | adev->gds.gws.cs_partition_size = 4; |
| 4447 | |
| 4448 | adev->gds.oa.gfx_partition_size = 4; |
| 4449 | adev->gds.oa.cs_partition_size = 1; |
| 4450 | } else { |
| 4451 | adev->gds.mem.gfx_partition_size = 1024; |
| 4452 | adev->gds.mem.cs_partition_size = 1024; |
| 4453 | |
| 4454 | adev->gds.gws.gfx_partition_size = 16; |
| 4455 | adev->gds.gws.cs_partition_size = 16; |
| 4456 | |
| 4457 | adev->gds.oa.gfx_partition_size = 4; |
| 4458 | adev->gds.oa.cs_partition_size = 4; |
| 4459 | } |
| 4460 | } |
| 4461 | |
| 4462 | static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev, |
| 4463 | u32 se, u32 sh) |
| 4464 | { |
| 4465 | u32 mask = 0, tmp, tmp1; |
| 4466 | int i; |
| 4467 | |
| 4468 | gfx_v8_0_select_se_sh(adev, se, sh); |
| 4469 | tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); |
| 4470 | tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); |
| 4471 | gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); |
| 4472 | |
| 4473 | tmp &= 0xffff0000; |
| 4474 | |
| 4475 | tmp |= tmp1; |
| 4476 | tmp >>= 16; |
| 4477 | |
| 4478 | for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) { |
| 4479 | mask <<= 1; |
| 4480 | mask |= 1; |
| 4481 | } |
| 4482 | |
| 4483 | return (~tmp) & mask; |
| 4484 | } |
| 4485 | |
| 4486 | int gfx_v8_0_get_cu_info(struct amdgpu_device *adev, |
| 4487 | struct amdgpu_cu_info *cu_info) |
| 4488 | { |
| 4489 | int i, j, k, counter, active_cu_number = 0; |
| 4490 | u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; |
| 4491 | |
| 4492 | if (!adev || !cu_info) |
| 4493 | return -EINVAL; |
| 4494 | |
| 4495 | mutex_lock(&adev->grbm_idx_mutex); |
| 4496 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { |
| 4497 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { |
| 4498 | mask = 1; |
| 4499 | ao_bitmap = 0; |
| 4500 | counter = 0; |
| 4501 | bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j); |
| 4502 | cu_info->bitmap[i][j] = bitmap; |
| 4503 | |
| 4504 | for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { |
| 4505 | if (bitmap & mask) { |
| 4506 | if (counter < 2) |
| 4507 | ao_bitmap |= mask; |
| 4508 | counter ++; |
| 4509 | } |
| 4510 | mask <<= 1; |
| 4511 | } |
| 4512 | active_cu_number += counter; |
| 4513 | ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); |
| 4514 | } |
| 4515 | } |
| 4516 | |
| 4517 | cu_info->number = active_cu_number; |
| 4518 | cu_info->ao_cu_mask = ao_cu_mask; |
| 4519 | mutex_unlock(&adev->grbm_idx_mutex); |
| 4520 | return 0; |
| 4521 | } |