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gerrit-public.fairphone.software / kernel / msm-4.9 / af4dc88c56559c1ebf53628ddcc18dde23924e33 / . / arch / arm / plat-mxc / include / mach / entry-macro.S
blob: 066d464d322d7617025cd0adf6346802ec687a8f [file] [log] [blame]
Quinn Jensen52c543f2007-07-09 22:06:53 +0100[diff] [blame]1/*
2 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
Amit Kucheriaa0037082009-12-03 22:36:41 +0200[diff] [blame]3 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
Quinn Jensen52c543f2007-07-09 22:06:53 +0100[diff] [blame]4 */
5
6/*
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
Sascha Hauera2449092008-12-18 11:51:57 +0100[diff] [blame]12#include <mach/hardware.h>
13
Darius Augulis479c9012008-09-09 11:29:41 +0200[diff] [blame]14#define AVIC_NIMASK 0x04
15
Quinn Jensen52c543f2007-07-09 22:06:53 +0100[diff] [blame]16 @ this macro disables fast irq (not implemented)
17 .macro disable_fiq
18 .endm
19
20 .macro get_irqnr_preamble, base, tmp
Amit Kucheriaa0037082009-12-03 22:36:41 +0200[diff] [blame]21#ifndef CONFIG_MXC_TZIC
Sascha Hauer12b8eb82009-05-25 10:50:52 +0200[diff] [blame]22 ldr \base, =avic_base
23 ldr \base, [\base]
Darius Augulis479c9012008-09-09 11:29:41 +0200[diff] [blame]24#ifdef CONFIG_MXC_IRQ_PRIOR
25 ldr r4, [\base, #AVIC_NIMASK]
26#endif
Amit Kucheriaa0037082009-12-03 22:36:41 +0200[diff] [blame]27#elif defined CONFIG_MXC_TZIC
28 ldr \base, =tzic_base
29 ldr \base, [\base]
30#endif /* CONFIG_MXC_TZIC */
Quinn Jensen52c543f2007-07-09 22:06:53 +0100[diff] [blame]31 .endm
32
33 .macro arch_ret_to_user, tmp1, tmp2
34 .endm
35
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]36 @ this macro checks which interrupt occurred
Quinn Jensen52c543f2007-07-09 22:06:53 +0100[diff] [blame]37 @ and returns its number in irqnr
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]38 @ and returns if an interrupt occurred in irqstat
Quinn Jensen52c543f2007-07-09 22:06:53 +0100[diff] [blame]39 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
Amit Kucheriaa0037082009-12-03 22:36:41 +0200[diff] [blame]40#ifndef CONFIG_MXC_TZIC
Quinn Jensen52c543f2007-07-09 22:06:53 +0100[diff] [blame]41 @ Load offset & priority of the highest priority
42 @ interrupt pending from AVIC_NIVECSR
43 ldr \irqstat, [\base, #0x40]
44 @ Shift to get the decoded IRQ number, using ASR so
45 @ 'no interrupt pending' becomes 0xffffffff
46 mov \irqnr, \irqstat, asr #16
47 @ set zero flag if IRQ + 1 == 0
48 adds \tmp, \irqnr, #1
Darius Augulis479c9012008-09-09 11:29:41 +0200[diff] [blame]49#ifdef CONFIG_MXC_IRQ_PRIOR
50 bicne \tmp, \irqstat, #0xFFFFFFE0
51 strne \tmp, [\base, #AVIC_NIMASK]
52 streq r4, [\base, #AVIC_NIMASK]
53#endif
Amit Kucheriaa0037082009-12-03 22:36:41 +0200[diff] [blame]54#elif defined CONFIG_MXC_TZIC
55 @ Load offset & priority of the highest priority
56 @ interrupt pending.
Peter Hortoncdc3f102010-12-06 11:37:38 +0000[diff] [blame]57 @ 0x080 is INTSEC0 register
Amit Kucheriaa0037082009-12-03 22:36:41 +0200[diff] [blame]58 @ 0xD80 is HIPND0 register
59 mov \irqnr, #0
Peter Hortoncdc3f102010-12-06 11:37:38 +0000[diff] [blame]601000: add \irqstat, \base, \irqnr, lsr #3
61 ldr \tmp, [\irqstat, #0xd80]
62 ldr \irqstat, [\irqstat, #0x080]
63 ands \tmp, \tmp, \irqstat
64 bne 1001f
65 add \irqnr, \irqnr, #32
Amit Kucheriaa0037082009-12-03 22:36:41 +0200[diff] [blame]66 cmp \irqnr, #128
67 blo 1000b
68 b 2001f
691001: mov \irqstat, #1
701002: tst \tmp, \irqstat
71 bne 2002f
72 movs \tmp, \tmp, lsr #1
73 addne \irqnr, \irqnr, #1
74 bne 1002b
752001:
76 mov \irqnr, #0
772002:
78 movs \irqnr, \irqnr
79#endif
Quinn Jensen52c543f2007-07-09 22:06:53 +0100[diff] [blame]80 .endm