Linus Walleij | fa59440 | 2009-04-23 10:19:58 +0100 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * arch/arm/mach-u300/include/mach/irqs.h |
| 4 | * |
| 5 | * |
| 6 | * Copyright (C) 2006-2009 ST-Ericsson AB |
| 7 | * License terms: GNU General Public License (GPL) version 2 |
| 8 | * IRQ channel definitions for the U300 platforms. |
| 9 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
| 10 | */ |
| 11 | |
| 12 | #ifndef __MACH_IRQS_H |
| 13 | #define __MACH_IRQS_H |
| 14 | |
| 15 | #define IRQ_U300_INTCON0_START 0 |
| 16 | #define IRQ_U300_INTCON1_START 32 |
| 17 | /* These are on INTCON0 - 30 lines */ |
| 18 | #define IRQ_U300_IRQ0_EXT 0 |
| 19 | #define IRQ_U300_IRQ1_EXT 1 |
| 20 | #define IRQ_U300_DMA 2 |
| 21 | #define IRQ_U300_VIDEO_ENC_0 3 |
| 22 | #define IRQ_U300_VIDEO_ENC_1 4 |
| 23 | #define IRQ_U300_AAIF_RX 5 |
| 24 | #define IRQ_U300_AAIF_TX 6 |
| 25 | #define IRQ_U300_AAIF_VGPIO 7 |
| 26 | #define IRQ_U300_AAIF_WAKEUP 8 |
| 27 | #define IRQ_U300_PCM_I2S0_FRAME 9 |
| 28 | #define IRQ_U300_PCM_I2S0_FIFO 10 |
| 29 | #define IRQ_U300_PCM_I2S1_FRAME 11 |
| 30 | #define IRQ_U300_PCM_I2S1_FIFO 12 |
| 31 | #define IRQ_U300_XGAM_GAMCON 13 |
| 32 | #define IRQ_U300_XGAM_CDI 14 |
| 33 | #define IRQ_U300_XGAM_CDICON 15 |
| 34 | #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) |
| 35 | /* MMIACC not used on the DB3210 or DB3350 chips */ |
| 36 | #define IRQ_U300_XGAM_MMIACC 16 |
| 37 | #endif |
| 38 | #define IRQ_U300_XGAM_PDI 17 |
| 39 | #define IRQ_U300_XGAM_PDICON 18 |
| 40 | #define IRQ_U300_XGAM_GAMEACC 19 |
| 41 | #define IRQ_U300_XGAM_MCIDCT 20 |
| 42 | #define IRQ_U300_APEX 21 |
| 43 | #define IRQ_U300_UART0 22 |
| 44 | #define IRQ_U300_SPI 23 |
| 45 | #define IRQ_U300_TIMER_APP_OS 24 |
| 46 | #define IRQ_U300_TIMER_APP_DD 25 |
| 47 | #define IRQ_U300_TIMER_APP_GP1 26 |
| 48 | #define IRQ_U300_TIMER_APP_GP2 27 |
| 49 | #define IRQ_U300_TIMER_OS 28 |
| 50 | #define IRQ_U300_TIMER_MS 29 |
| 51 | #define IRQ_U300_KEYPAD_KEYBF 30 |
| 52 | #define IRQ_U300_KEYPAD_KEYBR 31 |
| 53 | /* These are on INTCON1 - 32 lines */ |
| 54 | #define IRQ_U300_GPIO_PORT0 32 |
| 55 | #define IRQ_U300_GPIO_PORT1 33 |
| 56 | #define IRQ_U300_GPIO_PORT2 34 |
| 57 | |
| 58 | #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \ |
| 59 | defined(CONFIG_MACH_U300_BS335) |
| 60 | /* These are for DB3150, DB3200 and DB3350 */ |
| 61 | #define IRQ_U300_WDOG 35 |
| 62 | #define IRQ_U300_EVHIST 36 |
| 63 | #define IRQ_U300_MSPRO 37 |
| 64 | #define IRQ_U300_MMCSD_MCIINTR0 38 |
| 65 | #define IRQ_U300_MMCSD_MCIINTR1 39 |
| 66 | #define IRQ_U300_I2C0 40 |
| 67 | #define IRQ_U300_I2C1 41 |
| 68 | #define IRQ_U300_RTC 42 |
| 69 | #define IRQ_U300_NFIF 43 |
| 70 | #define IRQ_U300_NFIF2 44 |
| 71 | #endif |
| 72 | |
| 73 | /* DB3150 and DB3200 have only 45 IRQs */ |
| 74 | #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 75 | #define U300_VIC_IRQS_END 45 |
Linus Walleij | fa59440 | 2009-04-23 10:19:58 +0100 | [diff] [blame] | 76 | #endif |
| 77 | |
| 78 | /* The DB3350-specific interrupt lines */ |
| 79 | #ifdef CONFIG_MACH_U300_BS335 |
| 80 | #define IRQ_U300_ISP_F0 45 |
| 81 | #define IRQ_U300_ISP_F1 46 |
| 82 | #define IRQ_U300_ISP_F2 47 |
| 83 | #define IRQ_U300_ISP_F3 48 |
| 84 | #define IRQ_U300_ISP_F4 49 |
| 85 | #define IRQ_U300_GPIO_PORT3 50 |
| 86 | #define IRQ_U300_SYSCON_PLL_LOCK 51 |
| 87 | #define IRQ_U300_UART1 52 |
| 88 | #define IRQ_U300_GPIO_PORT4 53 |
| 89 | #define IRQ_U300_GPIO_PORT5 54 |
| 90 | #define IRQ_U300_GPIO_PORT6 55 |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 91 | #define U300_VIC_IRQS_END 56 |
Linus Walleij | fa59440 | 2009-04-23 10:19:58 +0100 | [diff] [blame] | 92 | #endif |
| 93 | |
| 94 | /* The DB3210-specific interrupt lines */ |
| 95 | #ifdef CONFIG_MACH_U300_BS365 |
| 96 | #define IRQ_U300_GPIO_PORT3 35 |
| 97 | #define IRQ_U300_GPIO_PORT4 36 |
| 98 | #define IRQ_U300_WDOG 37 |
| 99 | #define IRQ_U300_EVHIST 38 |
| 100 | #define IRQ_U300_MSPRO 39 |
| 101 | #define IRQ_U300_MMCSD_MCIINTR0 40 |
| 102 | #define IRQ_U300_MMCSD_MCIINTR1 41 |
| 103 | #define IRQ_U300_I2C0 42 |
| 104 | #define IRQ_U300_I2C1 43 |
| 105 | #define IRQ_U300_RTC 44 |
| 106 | #define IRQ_U300_NFIF 45 |
| 107 | #define IRQ_U300_NFIF2 46 |
| 108 | #define IRQ_U300_SYSCON_PLL_LOCK 47 |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 109 | #define U300_VIC_IRQS_END 48 |
Linus Walleij | fa59440 | 2009-04-23 10:19:58 +0100 | [diff] [blame] | 110 | #endif |
| 111 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 112 | /* Maximum 8*7 GPIO lines */ |
Linus Walleij | ca402d3 | 2011-11-16 09:22:59 +0100 | [diff] [blame] | 113 | #ifdef CONFIG_PINCTRL_COH901 |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 114 | #define IRQ_U300_GPIO_BASE (U300_VIC_IRQS_END) |
| 115 | #define IRQ_U300_GPIO_END (IRQ_U300_GPIO_BASE + 56) |
Mattias Wallin | d162251 | 2010-05-01 18:26:40 +0200 | [diff] [blame] | 116 | #else |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 117 | #define IRQ_U300_GPIO_END (U300_VIC_IRQS_END) |
Mattias Wallin | d162251 | 2010-05-01 18:26:40 +0200 | [diff] [blame] | 118 | #endif |
Linus Walleij | fa59440 | 2009-04-23 10:19:58 +0100 | [diff] [blame] | 119 | |
Linus Torvalds | a0a4194 | 2011-11-03 09:40:51 -0700 | [diff] [blame] | 120 | #define NR_IRQS (IRQ_U300_GPIO_END) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 121 | |
Linus Walleij | fa59440 | 2009-04-23 10:19:58 +0100 | [diff] [blame] | 122 | #endif |