Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008,2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Chris Wilson <chris@chris-wilson.co.uk> |
| 26 | * |
| 27 | */ |
| 28 | |
| 29 | #include "drmP.h" |
| 30 | #include "drm.h" |
| 31 | #include "i915_drm.h" |
| 32 | #include "i915_drv.h" |
| 33 | #include "i915_trace.h" |
| 34 | #include "intel_drv.h" |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 35 | #include <linux/dma_remapping.h> |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 36 | |
| 37 | struct change_domains { |
| 38 | uint32_t invalidate_domains; |
| 39 | uint32_t flush_domains; |
| 40 | uint32_t flush_rings; |
Chris Wilson | c59a333 | 2011-03-06 13:51:29 +0000 | [diff] [blame] | 41 | uint32_t flips; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 42 | }; |
| 43 | |
| 44 | /* |
| 45 | * Set the next domain for the specified object. This |
| 46 | * may not actually perform the necessary flushing/invaliding though, |
| 47 | * as that may want to be batched with other set_domain operations |
| 48 | * |
| 49 | * This is (we hope) the only really tricky part of gem. The goal |
| 50 | * is fairly simple -- track which caches hold bits of the object |
| 51 | * and make sure they remain coherent. A few concrete examples may |
| 52 | * help to explain how it works. For shorthand, we use the notation |
| 53 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 54 | * a pair of read and write domain masks. |
| 55 | * |
| 56 | * Case 1: the batch buffer |
| 57 | * |
| 58 | * 1. Allocated |
| 59 | * 2. Written by CPU |
| 60 | * 3. Mapped to GTT |
| 61 | * 4. Read by GPU |
| 62 | * 5. Unmapped from GTT |
| 63 | * 6. Freed |
| 64 | * |
| 65 | * Let's take these a step at a time |
| 66 | * |
| 67 | * 1. Allocated |
| 68 | * Pages allocated from the kernel may still have |
| 69 | * cache contents, so we set them to (CPU, CPU) always. |
| 70 | * 2. Written by CPU (using pwrite) |
| 71 | * The pwrite function calls set_domain (CPU, CPU) and |
| 72 | * this function does nothing (as nothing changes) |
| 73 | * 3. Mapped by GTT |
| 74 | * This function asserts that the object is not |
| 75 | * currently in any GPU-based read or write domains |
| 76 | * 4. Read by GPU |
| 77 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 78 | * As write_domain is zero, this function adds in the |
| 79 | * current read domains (CPU+COMMAND, 0). |
| 80 | * flush_domains is set to CPU. |
| 81 | * invalidate_domains is set to COMMAND |
| 82 | * clflush is run to get data out of the CPU caches |
| 83 | * then i915_dev_set_domain calls i915_gem_flush to |
| 84 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 85 | * 5. Unmapped from GTT |
| 86 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 87 | * flush_domains and invalidate_domains end up both zero |
| 88 | * so no flushing/invalidating happens |
| 89 | * 6. Freed |
| 90 | * yay, done |
| 91 | * |
| 92 | * Case 2: The shared render buffer |
| 93 | * |
| 94 | * 1. Allocated |
| 95 | * 2. Mapped to GTT |
| 96 | * 3. Read/written by GPU |
| 97 | * 4. set_domain to (CPU,CPU) |
| 98 | * 5. Read/written by CPU |
| 99 | * 6. Read/written by GPU |
| 100 | * |
| 101 | * 1. Allocated |
| 102 | * Same as last example, (CPU, CPU) |
| 103 | * 2. Mapped to GTT |
| 104 | * Nothing changes (assertions find that it is not in the GPU) |
| 105 | * 3. Read/written by GPU |
| 106 | * execbuffer calls set_domain (RENDER, RENDER) |
| 107 | * flush_domains gets CPU |
| 108 | * invalidate_domains gets GPU |
| 109 | * clflush (obj) |
| 110 | * MI_FLUSH and drm_agp_chipset_flush |
| 111 | * 4. set_domain (CPU, CPU) |
| 112 | * flush_domains gets GPU |
| 113 | * invalidate_domains gets CPU |
| 114 | * wait_rendering (obj) to make sure all drawing is complete. |
| 115 | * This will include an MI_FLUSH to get the data from GPU |
| 116 | * to memory |
| 117 | * clflush (obj) to invalidate the CPU cache |
| 118 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 119 | * 5. Read/written by CPU |
| 120 | * cache lines are loaded and dirtied |
| 121 | * 6. Read written by GPU |
| 122 | * Same as last GPU access |
| 123 | * |
| 124 | * Case 3: The constant buffer |
| 125 | * |
| 126 | * 1. Allocated |
| 127 | * 2. Written by CPU |
| 128 | * 3. Read by GPU |
| 129 | * 4. Updated (written) by CPU again |
| 130 | * 5. Read by GPU |
| 131 | * |
| 132 | * 1. Allocated |
| 133 | * (CPU, CPU) |
| 134 | * 2. Written by CPU |
| 135 | * (CPU, CPU) |
| 136 | * 3. Read by GPU |
| 137 | * (CPU+RENDER, 0) |
| 138 | * flush_domains = CPU |
| 139 | * invalidate_domains = RENDER |
| 140 | * clflush (obj) |
| 141 | * MI_FLUSH |
| 142 | * drm_agp_chipset_flush |
| 143 | * 4. Updated (written) by CPU again |
| 144 | * (CPU, CPU) |
| 145 | * flush_domains = 0 (no previous write domain) |
| 146 | * invalidate_domains = 0 (no new read domains) |
| 147 | * 5. Read by GPU |
| 148 | * (CPU+RENDER, 0) |
| 149 | * flush_domains = CPU |
| 150 | * invalidate_domains = RENDER |
| 151 | * clflush (obj) |
| 152 | * MI_FLUSH |
| 153 | * drm_agp_chipset_flush |
| 154 | */ |
| 155 | static void |
| 156 | i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj, |
| 157 | struct intel_ring_buffer *ring, |
| 158 | struct change_domains *cd) |
| 159 | { |
| 160 | uint32_t invalidate_domains = 0, flush_domains = 0; |
| 161 | |
| 162 | /* |
| 163 | * If the object isn't moving to a new write domain, |
| 164 | * let the object stay in multiple read domains |
| 165 | */ |
| 166 | if (obj->base.pending_write_domain == 0) |
| 167 | obj->base.pending_read_domains |= obj->base.read_domains; |
| 168 | |
| 169 | /* |
| 170 | * Flush the current write domain if |
| 171 | * the new read domains don't match. Invalidate |
| 172 | * any read domains which differ from the old |
| 173 | * write domain |
| 174 | */ |
| 175 | if (obj->base.write_domain && |
| 176 | (((obj->base.write_domain != obj->base.pending_read_domains || |
| 177 | obj->ring != ring)) || |
| 178 | (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) { |
| 179 | flush_domains |= obj->base.write_domain; |
| 180 | invalidate_domains |= |
| 181 | obj->base.pending_read_domains & ~obj->base.write_domain; |
| 182 | } |
| 183 | /* |
| 184 | * Invalidate any read caches which may have |
| 185 | * stale data. That is, any new read domains. |
| 186 | */ |
| 187 | invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains; |
| 188 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
| 189 | i915_gem_clflush_object(obj); |
| 190 | |
Chris Wilson | c59a333 | 2011-03-06 13:51:29 +0000 | [diff] [blame] | 191 | if (obj->base.pending_write_domain) |
| 192 | cd->flips |= atomic_read(&obj->pending_flip); |
| 193 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 194 | /* The actual obj->write_domain will be updated with |
| 195 | * pending_write_domain after we emit the accumulated flush for all |
| 196 | * of our domain changes in execbuffers (which clears objects' |
| 197 | * write_domains). So if we have a current write domain that we |
| 198 | * aren't changing, set pending_write_domain to that. |
| 199 | */ |
| 200 | if (flush_domains == 0 && obj->base.pending_write_domain == 0) |
| 201 | obj->base.pending_write_domain = obj->base.write_domain; |
| 202 | |
| 203 | cd->invalidate_domains |= invalidate_domains; |
| 204 | cd->flush_domains |= flush_domains; |
| 205 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 206 | cd->flush_rings |= intel_ring_flag(obj->ring); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 207 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 208 | cd->flush_rings |= intel_ring_flag(ring); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 209 | } |
| 210 | |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 211 | struct eb_objects { |
| 212 | int and; |
| 213 | struct hlist_head buckets[0]; |
| 214 | }; |
| 215 | |
| 216 | static struct eb_objects * |
| 217 | eb_create(int size) |
| 218 | { |
| 219 | struct eb_objects *eb; |
| 220 | int count = PAGE_SIZE / sizeof(struct hlist_head) / 2; |
| 221 | while (count > size) |
| 222 | count >>= 1; |
| 223 | eb = kzalloc(count*sizeof(struct hlist_head) + |
| 224 | sizeof(struct eb_objects), |
| 225 | GFP_KERNEL); |
| 226 | if (eb == NULL) |
| 227 | return eb; |
| 228 | |
| 229 | eb->and = count - 1; |
| 230 | return eb; |
| 231 | } |
| 232 | |
| 233 | static void |
| 234 | eb_reset(struct eb_objects *eb) |
| 235 | { |
| 236 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); |
| 237 | } |
| 238 | |
| 239 | static void |
| 240 | eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj) |
| 241 | { |
| 242 | hlist_add_head(&obj->exec_node, |
| 243 | &eb->buckets[obj->exec_handle & eb->and]); |
| 244 | } |
| 245 | |
| 246 | static struct drm_i915_gem_object * |
| 247 | eb_get_object(struct eb_objects *eb, unsigned long handle) |
| 248 | { |
| 249 | struct hlist_head *head; |
| 250 | struct hlist_node *node; |
| 251 | struct drm_i915_gem_object *obj; |
| 252 | |
| 253 | head = &eb->buckets[handle & eb->and]; |
| 254 | hlist_for_each(node, head) { |
| 255 | obj = hlist_entry(node, struct drm_i915_gem_object, exec_node); |
| 256 | if (obj->exec_handle == handle) |
| 257 | return obj; |
| 258 | } |
| 259 | |
| 260 | return NULL; |
| 261 | } |
| 262 | |
| 263 | static void |
| 264 | eb_destroy(struct eb_objects *eb) |
| 265 | { |
| 266 | kfree(eb); |
| 267 | } |
| 268 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 269 | static int |
| 270 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 271 | struct eb_objects *eb, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 272 | struct drm_i915_gem_relocation_entry *reloc) |
| 273 | { |
| 274 | struct drm_device *dev = obj->base.dev; |
| 275 | struct drm_gem_object *target_obj; |
| 276 | uint32_t target_offset; |
| 277 | int ret = -EINVAL; |
| 278 | |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 279 | /* we've already hold a reference to all valid objects */ |
| 280 | target_obj = &eb_get_object(eb, reloc->target_handle)->base; |
| 281 | if (unlikely(target_obj == NULL)) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 282 | return -ENOENT; |
| 283 | |
| 284 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
| 285 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 286 | /* The target buffer should have appeared before us in the |
| 287 | * exec_object list, so it should have a GTT space bound by now. |
| 288 | */ |
Chris Wilson | b8f7ab1 | 2010-12-08 10:43:06 +0000 | [diff] [blame] | 289 | if (unlikely(target_offset == 0)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 290 | DRM_DEBUG("No GTT space found for object %d\n", |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 291 | reloc->target_handle); |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 292 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 293 | } |
| 294 | |
| 295 | /* Validate that the target is in a valid r/w GPU domain */ |
Chris Wilson | b8f7ab1 | 2010-12-08 10:43:06 +0000 | [diff] [blame] | 296 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 297 | DRM_DEBUG("reloc with multiple write domains: " |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 298 | "obj %p target %d offset %d " |
| 299 | "read %08x write %08x", |
| 300 | obj, reloc->target_handle, |
| 301 | (int) reloc->offset, |
| 302 | reloc->read_domains, |
| 303 | reloc->write_domain); |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 304 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 305 | } |
Daniel Vetter | 4ca4a25 | 2011-12-14 13:57:27 +0100 | [diff] [blame] | 306 | if (unlikely((reloc->write_domain | reloc->read_domains) |
| 307 | & ~I915_GEM_GPU_DOMAINS)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 308 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 309 | "obj %p target %d offset %d " |
| 310 | "read %08x write %08x", |
| 311 | obj, reloc->target_handle, |
| 312 | (int) reloc->offset, |
| 313 | reloc->read_domains, |
| 314 | reloc->write_domain); |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 315 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 316 | } |
Chris Wilson | b8f7ab1 | 2010-12-08 10:43:06 +0000 | [diff] [blame] | 317 | if (unlikely(reloc->write_domain && target_obj->pending_write_domain && |
| 318 | reloc->write_domain != target_obj->pending_write_domain)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 319 | DRM_DEBUG("Write domain conflict: " |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 320 | "obj %p target %d offset %d " |
| 321 | "new %08x old %08x\n", |
| 322 | obj, reloc->target_handle, |
| 323 | (int) reloc->offset, |
| 324 | reloc->write_domain, |
| 325 | target_obj->pending_write_domain); |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 326 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | target_obj->pending_read_domains |= reloc->read_domains; |
| 330 | target_obj->pending_write_domain |= reloc->write_domain; |
| 331 | |
| 332 | /* If the relocation already has the right value in it, no |
| 333 | * more work needs to be done. |
| 334 | */ |
| 335 | if (target_offset == reloc->presumed_offset) |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 336 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 337 | |
| 338 | /* Check that the relocation address is valid... */ |
Chris Wilson | b8f7ab1 | 2010-12-08 10:43:06 +0000 | [diff] [blame] | 339 | if (unlikely(reloc->offset > obj->base.size - 4)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 340 | DRM_DEBUG("Relocation beyond object bounds: " |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 341 | "obj %p target %d offset %d size %d.\n", |
| 342 | obj, reloc->target_handle, |
| 343 | (int) reloc->offset, |
| 344 | (int) obj->base.size); |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 345 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 346 | } |
Chris Wilson | b8f7ab1 | 2010-12-08 10:43:06 +0000 | [diff] [blame] | 347 | if (unlikely(reloc->offset & 3)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 348 | DRM_DEBUG("Relocation not 4-byte aligned: " |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 349 | "obj %p target %d offset %d.\n", |
| 350 | obj, reloc->target_handle, |
| 351 | (int) reloc->offset); |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 352 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 353 | } |
| 354 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 355 | reloc->delta += target_offset; |
| 356 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { |
| 357 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; |
| 358 | char *vaddr; |
| 359 | |
| 360 | vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]); |
| 361 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; |
| 362 | kunmap_atomic(vaddr); |
| 363 | } else { |
| 364 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 365 | uint32_t __iomem *reloc_entry; |
| 366 | void __iomem *reloc_page; |
| 367 | |
Chris Wilson | d4aeee7 | 2011-03-14 15:11:24 +0000 | [diff] [blame] | 368 | /* We can't wait for rendering with pagefaults disabled */ |
| 369 | if (obj->active && in_atomic()) |
| 370 | return -EFAULT; |
| 371 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 372 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 373 | if (ret) |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 374 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 375 | |
| 376 | /* Map the page containing the relocation we're going to perform. */ |
| 377 | reloc->offset += obj->gtt_offset; |
| 378 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
| 379 | reloc->offset & PAGE_MASK); |
| 380 | reloc_entry = (uint32_t __iomem *) |
| 381 | (reloc_page + (reloc->offset & ~PAGE_MASK)); |
| 382 | iowrite32(reloc->delta, reloc_entry); |
| 383 | io_mapping_unmap_atomic(reloc_page); |
| 384 | } |
| 385 | |
| 386 | /* and update the user's relocation entry */ |
| 387 | reloc->presumed_offset = target_offset; |
| 388 | |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 389 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 390 | } |
| 391 | |
| 392 | static int |
| 393 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 394 | struct eb_objects *eb) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 395 | { |
| 396 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 397 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 398 | int i, ret; |
| 399 | |
| 400 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
| 401 | for (i = 0; i < entry->relocation_count; i++) { |
| 402 | struct drm_i915_gem_relocation_entry reloc; |
| 403 | |
| 404 | if (__copy_from_user_inatomic(&reloc, |
| 405 | user_relocs+i, |
| 406 | sizeof(reloc))) |
| 407 | return -EFAULT; |
| 408 | |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 409 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &reloc); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 410 | if (ret) |
| 411 | return ret; |
| 412 | |
| 413 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, |
| 414 | &reloc.presumed_offset, |
| 415 | sizeof(reloc.presumed_offset))) |
| 416 | return -EFAULT; |
| 417 | } |
| 418 | |
| 419 | return 0; |
| 420 | } |
| 421 | |
| 422 | static int |
| 423 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 424 | struct eb_objects *eb, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 425 | struct drm_i915_gem_relocation_entry *relocs) |
| 426 | { |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 427 | const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 428 | int i, ret; |
| 429 | |
| 430 | for (i = 0; i < entry->relocation_count; i++) { |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 431 | ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 432 | if (ret) |
| 433 | return ret; |
| 434 | } |
| 435 | |
| 436 | return 0; |
| 437 | } |
| 438 | |
| 439 | static int |
| 440 | i915_gem_execbuffer_relocate(struct drm_device *dev, |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 441 | struct eb_objects *eb, |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 442 | struct list_head *objects) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 443 | { |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 444 | struct drm_i915_gem_object *obj; |
Chris Wilson | d4aeee7 | 2011-03-14 15:11:24 +0000 | [diff] [blame] | 445 | int ret = 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 446 | |
Chris Wilson | d4aeee7 | 2011-03-14 15:11:24 +0000 | [diff] [blame] | 447 | /* This is the fast path and we cannot handle a pagefault whilst |
| 448 | * holding the struct mutex lest the user pass in the relocations |
| 449 | * contained within a mmaped bo. For in such a case we, the page |
| 450 | * fault handler would call i915_gem_fault() and we would try to |
| 451 | * acquire the struct mutex again. Obviously this is bad and so |
| 452 | * lockdep complains vehemently. |
| 453 | */ |
| 454 | pagefault_disable(); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 455 | list_for_each_entry(obj, objects, exec_list) { |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 456 | ret = i915_gem_execbuffer_relocate_object(obj, eb); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 457 | if (ret) |
Chris Wilson | d4aeee7 | 2011-03-14 15:11:24 +0000 | [diff] [blame] | 458 | break; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 459 | } |
Chris Wilson | d4aeee7 | 2011-03-14 15:11:24 +0000 | [diff] [blame] | 460 | pagefault_enable(); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 461 | |
Chris Wilson | d4aeee7 | 2011-03-14 15:11:24 +0000 | [diff] [blame] | 462 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 463 | } |
| 464 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 465 | #define __EXEC_OBJECT_HAS_FENCE (1<<31) |
| 466 | |
| 467 | static int |
| 468 | pin_and_fence_object(struct drm_i915_gem_object *obj, |
| 469 | struct intel_ring_buffer *ring) |
| 470 | { |
| 471 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
| 472 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
| 473 | bool need_fence, need_mappable; |
| 474 | int ret; |
| 475 | |
| 476 | need_fence = |
| 477 | has_fenced_gpu_access && |
| 478 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 479 | obj->tiling_mode != I915_TILING_NONE; |
| 480 | need_mappable = |
| 481 | entry->relocation_count ? true : need_fence; |
| 482 | |
| 483 | ret = i915_gem_object_pin(obj, entry->alignment, need_mappable); |
| 484 | if (ret) |
| 485 | return ret; |
| 486 | |
| 487 | if (has_fenced_gpu_access) { |
| 488 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
| 489 | if (obj->tiling_mode) { |
| 490 | ret = i915_gem_object_get_fence(obj, ring); |
| 491 | if (ret) |
| 492 | goto err_unpin; |
| 493 | |
| 494 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; |
| 495 | i915_gem_object_pin_fence(obj); |
| 496 | } else { |
| 497 | ret = i915_gem_object_put_fence(obj); |
| 498 | if (ret) |
| 499 | goto err_unpin; |
| 500 | } |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 501 | obj->pending_fenced_gpu_access = true; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 502 | } |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 503 | } |
| 504 | |
| 505 | entry->offset = obj->gtt_offset; |
| 506 | return 0; |
| 507 | |
| 508 | err_unpin: |
| 509 | i915_gem_object_unpin(obj); |
| 510 | return ret; |
| 511 | } |
| 512 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 513 | static int |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 514 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 515 | struct drm_file *file, |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 516 | struct list_head *objects) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 517 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 518 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 519 | struct drm_i915_gem_object *obj; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 520 | int ret, retry; |
Chris Wilson | 9b3826b | 2010-12-05 17:11:54 +0000 | [diff] [blame] | 521 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 522 | struct list_head ordered_objects; |
| 523 | |
| 524 | INIT_LIST_HEAD(&ordered_objects); |
| 525 | while (!list_empty(objects)) { |
| 526 | struct drm_i915_gem_exec_object2 *entry; |
| 527 | bool need_fence, need_mappable; |
| 528 | |
| 529 | obj = list_first_entry(objects, |
| 530 | struct drm_i915_gem_object, |
| 531 | exec_list); |
| 532 | entry = obj->exec_entry; |
| 533 | |
| 534 | need_fence = |
| 535 | has_fenced_gpu_access && |
| 536 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 537 | obj->tiling_mode != I915_TILING_NONE; |
| 538 | need_mappable = |
| 539 | entry->relocation_count ? true : need_fence; |
| 540 | |
| 541 | if (need_mappable) |
| 542 | list_move(&obj->exec_list, &ordered_objects); |
| 543 | else |
| 544 | list_move_tail(&obj->exec_list, &ordered_objects); |
Chris Wilson | 595dad7 | 2011-01-13 11:03:48 +0000 | [diff] [blame] | 545 | |
| 546 | obj->base.pending_read_domains = 0; |
| 547 | obj->base.pending_write_domain = 0; |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 548 | } |
| 549 | list_splice(&ordered_objects, objects); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 550 | |
| 551 | /* Attempt to pin all of the buffers into the GTT. |
| 552 | * This is done in 3 phases: |
| 553 | * |
| 554 | * 1a. Unbind all objects that do not match the GTT constraints for |
| 555 | * the execbuffer (fenceable, mappable, alignment etc). |
| 556 | * 1b. Increment pin count for already bound objects. |
| 557 | * 2. Bind new objects. |
| 558 | * 3. Decrement pin count. |
| 559 | * |
| 560 | * This avoid unnecessary unbinding of later objects in order to makr |
| 561 | * room for the earlier objects *unless* we need to defragment. |
| 562 | */ |
| 563 | retry = 0; |
| 564 | do { |
| 565 | ret = 0; |
| 566 | |
| 567 | /* Unbind any ill-fitting objects or pin. */ |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 568 | list_for_each_entry(obj, objects, exec_list) { |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 569 | struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 570 | bool need_fence, need_mappable; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 571 | |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 572 | if (!obj->gtt_space) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 573 | continue; |
| 574 | |
| 575 | need_fence = |
Chris Wilson | 9b3826b | 2010-12-05 17:11:54 +0000 | [diff] [blame] | 576 | has_fenced_gpu_access && |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 577 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 578 | obj->tiling_mode != I915_TILING_NONE; |
| 579 | need_mappable = |
| 580 | entry->relocation_count ? true : need_fence; |
| 581 | |
| 582 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || |
| 583 | (need_mappable && !obj->map_and_fenceable)) |
| 584 | ret = i915_gem_object_unbind(obj); |
| 585 | else |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 586 | ret = pin_and_fence_object(obj, ring); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 587 | if (ret) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 588 | goto err; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 589 | } |
| 590 | |
| 591 | /* Bind fresh objects */ |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 592 | list_for_each_entry(obj, objects, exec_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 593 | if (obj->gtt_space) |
| 594 | continue; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 595 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 596 | ret = pin_and_fence_object(obj, ring); |
| 597 | if (ret) { |
| 598 | int ret_ignore; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 599 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 600 | /* This can potentially raise a harmless |
| 601 | * -EINVAL if we failed to bind in the above |
| 602 | * call. It cannot raise -EINTR since we know |
| 603 | * that the bo is freshly bound and so will |
| 604 | * not need to be flushed or waited upon. |
| 605 | */ |
| 606 | ret_ignore = i915_gem_object_unbind(obj); |
| 607 | (void)ret_ignore; |
| 608 | WARN_ON(obj->gtt_space); |
| 609 | break; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 610 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 611 | } |
| 612 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 613 | /* Decrement pin count for bound objects */ |
| 614 | list_for_each_entry(obj, objects, exec_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 615 | struct drm_i915_gem_exec_object2 *entry; |
| 616 | |
| 617 | if (!obj->gtt_space) |
| 618 | continue; |
| 619 | |
| 620 | entry = obj->exec_entry; |
| 621 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { |
| 622 | i915_gem_object_unpin_fence(obj); |
| 623 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; |
| 624 | } |
| 625 | |
| 626 | i915_gem_object_unpin(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 627 | |
| 628 | /* ... and ensure ppgtt mapping exist if needed. */ |
| 629 | if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { |
| 630 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
| 631 | obj, obj->cache_level); |
| 632 | |
| 633 | obj->has_aliasing_ppgtt_mapping = 1; |
| 634 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 635 | } |
| 636 | |
| 637 | if (ret != -ENOSPC || retry > 1) |
| 638 | return ret; |
| 639 | |
| 640 | /* First attempt, just clear anything that is purgeable. |
| 641 | * Second attempt, clear the entire GTT. |
| 642 | */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 643 | ret = i915_gem_evict_everything(ring->dev, retry == 0); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 644 | if (ret) |
| 645 | return ret; |
| 646 | |
| 647 | retry++; |
| 648 | } while (1); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 649 | |
| 650 | err: |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 651 | list_for_each_entry_continue_reverse(obj, objects, exec_list) { |
| 652 | struct drm_i915_gem_exec_object2 *entry; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 653 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 654 | if (!obj->gtt_space) |
| 655 | continue; |
| 656 | |
| 657 | entry = obj->exec_entry; |
| 658 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { |
| 659 | i915_gem_object_unpin_fence(obj); |
| 660 | entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; |
| 661 | } |
| 662 | |
| 663 | i915_gem_object_unpin(obj); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 664 | } |
| 665 | |
| 666 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 667 | } |
| 668 | |
| 669 | static int |
| 670 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, |
| 671 | struct drm_file *file, |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 672 | struct intel_ring_buffer *ring, |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 673 | struct list_head *objects, |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 674 | struct eb_objects *eb, |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 675 | struct drm_i915_gem_exec_object2 *exec, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 676 | int count) |
| 677 | { |
| 678 | struct drm_i915_gem_relocation_entry *reloc; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 679 | struct drm_i915_gem_object *obj; |
Chris Wilson | dd6864a | 2011-01-12 23:49:13 +0000 | [diff] [blame] | 680 | int *reloc_offset; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 681 | int i, total, ret; |
| 682 | |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 683 | /* We may process another execbuffer during the unlock... */ |
Chris Wilson | 36cf174 | 2011-01-10 12:09:12 +0000 | [diff] [blame] | 684 | while (!list_empty(objects)) { |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 685 | obj = list_first_entry(objects, |
| 686 | struct drm_i915_gem_object, |
| 687 | exec_list); |
| 688 | list_del_init(&obj->exec_list); |
| 689 | drm_gem_object_unreference(&obj->base); |
| 690 | } |
| 691 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 692 | mutex_unlock(&dev->struct_mutex); |
| 693 | |
| 694 | total = 0; |
| 695 | for (i = 0; i < count; i++) |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 696 | total += exec[i].relocation_count; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 697 | |
Chris Wilson | dd6864a | 2011-01-12 23:49:13 +0000 | [diff] [blame] | 698 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 699 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
Chris Wilson | dd6864a | 2011-01-12 23:49:13 +0000 | [diff] [blame] | 700 | if (reloc == NULL || reloc_offset == NULL) { |
| 701 | drm_free_large(reloc); |
| 702 | drm_free_large(reloc_offset); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 703 | mutex_lock(&dev->struct_mutex); |
| 704 | return -ENOMEM; |
| 705 | } |
| 706 | |
| 707 | total = 0; |
| 708 | for (i = 0; i < count; i++) { |
| 709 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
| 710 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 711 | user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 712 | |
| 713 | if (copy_from_user(reloc+total, user_relocs, |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 714 | exec[i].relocation_count * sizeof(*reloc))) { |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 715 | ret = -EFAULT; |
| 716 | mutex_lock(&dev->struct_mutex); |
| 717 | goto err; |
| 718 | } |
| 719 | |
Chris Wilson | dd6864a | 2011-01-12 23:49:13 +0000 | [diff] [blame] | 720 | reloc_offset[i] = total; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 721 | total += exec[i].relocation_count; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 722 | } |
| 723 | |
| 724 | ret = i915_mutex_lock_interruptible(dev); |
| 725 | if (ret) { |
| 726 | mutex_lock(&dev->struct_mutex); |
| 727 | goto err; |
| 728 | } |
| 729 | |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 730 | /* reacquire the objects */ |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 731 | eb_reset(eb); |
| 732 | for (i = 0; i < count; i++) { |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 733 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
| 734 | exec[i].handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 735 | if (&obj->base == NULL) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 736 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 737 | exec[i].handle, i); |
| 738 | ret = -ENOENT; |
| 739 | goto err; |
| 740 | } |
| 741 | |
| 742 | list_add_tail(&obj->exec_list, objects); |
| 743 | obj->exec_handle = exec[i].handle; |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 744 | obj->exec_entry = &exec[i]; |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 745 | eb_add_object(eb, obj); |
| 746 | } |
| 747 | |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 748 | ret = i915_gem_execbuffer_reserve(ring, file, objects); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 749 | if (ret) |
| 750 | goto err; |
| 751 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 752 | list_for_each_entry(obj, objects, exec_list) { |
Chris Wilson | dd6864a | 2011-01-12 23:49:13 +0000 | [diff] [blame] | 753 | int offset = obj->exec_entry - exec; |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 754 | ret = i915_gem_execbuffer_relocate_object_slow(obj, eb, |
Chris Wilson | dd6864a | 2011-01-12 23:49:13 +0000 | [diff] [blame] | 755 | reloc + reloc_offset[offset]); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 756 | if (ret) |
| 757 | goto err; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 758 | } |
| 759 | |
| 760 | /* Leave the user relocations as are, this is the painfully slow path, |
| 761 | * and we want to avoid the complication of dropping the lock whilst |
| 762 | * having buffers reserved in the aperture and so causing spurious |
| 763 | * ENOSPC for random operations. |
| 764 | */ |
| 765 | |
| 766 | err: |
| 767 | drm_free_large(reloc); |
Chris Wilson | dd6864a | 2011-01-12 23:49:13 +0000 | [diff] [blame] | 768 | drm_free_large(reloc_offset); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 769 | return ret; |
| 770 | } |
| 771 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 772 | static int |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 773 | i915_gem_execbuffer_flush(struct drm_device *dev, |
| 774 | uint32_t invalidate_domains, |
| 775 | uint32_t flush_domains, |
| 776 | uint32_t flush_rings) |
| 777 | { |
| 778 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 779 | int i, ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 780 | |
| 781 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
| 782 | intel_gtt_chipset_flush(); |
| 783 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 784 | if (flush_domains & I915_GEM_DOMAIN_GTT) |
| 785 | wmb(); |
| 786 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 787 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 788 | for (i = 0; i < I915_NUM_RINGS; i++) |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 789 | if (flush_rings & (1 << i)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 790 | ret = i915_gem_flush_ring(&dev_priv->ring[i], |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 791 | invalidate_domains, |
| 792 | flush_domains); |
| 793 | if (ret) |
| 794 | return ret; |
| 795 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 796 | } |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 797 | |
| 798 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 799 | } |
| 800 | |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 801 | static bool |
| 802 | intel_enable_semaphores(struct drm_device *dev) |
| 803 | { |
| 804 | if (INTEL_INFO(dev)->gen < 6) |
| 805 | return 0; |
| 806 | |
| 807 | if (i915_semaphores >= 0) |
| 808 | return i915_semaphores; |
| 809 | |
Keith Packard | ebbd857 | 2011-12-26 17:02:10 -0800 | [diff] [blame] | 810 | /* Disable semaphores on SNB */ |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 811 | if (INTEL_INFO(dev)->gen == 6) |
Keith Packard | ebbd857 | 2011-12-26 17:02:10 -0800 | [diff] [blame] | 812 | return 0; |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 813 | |
| 814 | return 1; |
| 815 | } |
| 816 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 817 | static int |
| 818 | i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj, |
| 819 | struct intel_ring_buffer *to) |
| 820 | { |
| 821 | struct intel_ring_buffer *from = obj->ring; |
| 822 | u32 seqno; |
| 823 | int ret, idx; |
| 824 | |
| 825 | if (from == NULL || to == from) |
| 826 | return 0; |
| 827 | |
Chris Wilson | a1656b9 | 2011-03-04 18:48:03 +0000 | [diff] [blame] | 828 | /* XXX gpu semaphores are implicated in various hard hangs on SNB */ |
Eugeni Dodonov | f45b555 | 2011-12-09 17:16:37 -0800 | [diff] [blame] | 829 | if (!intel_enable_semaphores(obj->base.dev)) |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 830 | return i915_gem_object_wait_rendering(obj); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 831 | |
| 832 | idx = intel_ring_sync_index(from, to); |
| 833 | |
| 834 | seqno = obj->last_rendering_seqno; |
| 835 | if (seqno <= from->sync_seqno[idx]) |
| 836 | return 0; |
| 837 | |
| 838 | if (seqno == from->outstanding_lazy_request) { |
| 839 | struct drm_i915_gem_request *request; |
| 840 | |
| 841 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 842 | if (request == NULL) |
| 843 | return -ENOMEM; |
| 844 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 845 | ret = i915_add_request(from, NULL, request); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 846 | if (ret) { |
| 847 | kfree(request); |
| 848 | return ret; |
| 849 | } |
| 850 | |
| 851 | seqno = request->seqno; |
| 852 | } |
| 853 | |
| 854 | from->sync_seqno[idx] = seqno; |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 855 | |
| 856 | return to->sync_to(to, from, seqno - 1); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 857 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 858 | |
| 859 | static int |
Chris Wilson | c59a333 | 2011-03-06 13:51:29 +0000 | [diff] [blame] | 860 | i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips) |
| 861 | { |
| 862 | u32 plane, flip_mask; |
| 863 | int ret; |
| 864 | |
| 865 | /* Check for any pending flips. As we only maintain a flip queue depth |
| 866 | * of 1, we can simply insert a WAIT for the next display flip prior |
| 867 | * to executing the batch and avoid stalling the CPU. |
| 868 | */ |
| 869 | |
| 870 | for (plane = 0; flips >> plane; plane++) { |
| 871 | if (((flips >> plane) & 1) == 0) |
| 872 | continue; |
| 873 | |
| 874 | if (plane) |
| 875 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 876 | else |
| 877 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
| 878 | |
| 879 | ret = intel_ring_begin(ring, 2); |
| 880 | if (ret) |
| 881 | return ret; |
| 882 | |
| 883 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 884 | intel_ring_emit(ring, MI_NOOP); |
| 885 | intel_ring_advance(ring); |
| 886 | } |
| 887 | |
| 888 | return 0; |
| 889 | } |
| 890 | |
| 891 | |
| 892 | static int |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 893 | i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, |
| 894 | struct list_head *objects) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 895 | { |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 896 | struct drm_i915_gem_object *obj; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 897 | struct change_domains cd; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 898 | int ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 899 | |
Chris Wilson | c59a333 | 2011-03-06 13:51:29 +0000 | [diff] [blame] | 900 | memset(&cd, 0, sizeof(cd)); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 901 | list_for_each_entry(obj, objects, exec_list) |
| 902 | i915_gem_object_set_to_gpu_domain(obj, ring, &cd); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 903 | |
| 904 | if (cd.invalidate_domains | cd.flush_domains) { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 905 | ret = i915_gem_execbuffer_flush(ring->dev, |
| 906 | cd.invalidate_domains, |
| 907 | cd.flush_domains, |
| 908 | cd.flush_rings); |
| 909 | if (ret) |
| 910 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 911 | } |
| 912 | |
Chris Wilson | c59a333 | 2011-03-06 13:51:29 +0000 | [diff] [blame] | 913 | if (cd.flips) { |
| 914 | ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips); |
| 915 | if (ret) |
| 916 | return ret; |
| 917 | } |
| 918 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 919 | list_for_each_entry(obj, objects, exec_list) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 920 | ret = i915_gem_execbuffer_sync_rings(obj, ring); |
| 921 | if (ret) |
| 922 | return ret; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 923 | } |
| 924 | |
| 925 | return 0; |
| 926 | } |
| 927 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 928 | static bool |
| 929 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 930 | { |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 931 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 932 | } |
| 933 | |
| 934 | static int |
| 935 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
| 936 | int count) |
| 937 | { |
| 938 | int i; |
| 939 | |
| 940 | for (i = 0; i < count; i++) { |
| 941 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; |
| 942 | int length; /* limited by fault_in_pages_readable() */ |
| 943 | |
| 944 | /* First check for malicious input causing overflow */ |
| 945 | if (exec[i].relocation_count > |
| 946 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) |
| 947 | return -EINVAL; |
| 948 | |
| 949 | length = exec[i].relocation_count * |
| 950 | sizeof(struct drm_i915_gem_relocation_entry); |
| 951 | if (!access_ok(VERIFY_READ, ptr, length)) |
| 952 | return -EFAULT; |
| 953 | |
| 954 | /* we may also need to update the presumed offsets */ |
| 955 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
| 956 | return -EFAULT; |
| 957 | |
| 958 | if (fault_in_pages_readable(ptr, length)) |
| 959 | return -EFAULT; |
| 960 | } |
| 961 | |
| 962 | return 0; |
| 963 | } |
| 964 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 965 | static void |
| 966 | i915_gem_execbuffer_move_to_active(struct list_head *objects, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 967 | struct intel_ring_buffer *ring, |
| 968 | u32 seqno) |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 969 | { |
| 970 | struct drm_i915_gem_object *obj; |
| 971 | |
| 972 | list_for_each_entry(obj, objects, exec_list) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 973 | u32 old_read = obj->base.read_domains; |
| 974 | u32 old_write = obj->base.write_domain; |
| 975 | |
| 976 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 977 | obj->base.read_domains = obj->base.pending_read_domains; |
| 978 | obj->base.write_domain = obj->base.pending_write_domain; |
| 979 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
| 980 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 981 | i915_gem_object_move_to_active(obj, ring, seqno); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 982 | if (obj->base.write_domain) { |
| 983 | obj->dirty = 1; |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 984 | obj->pending_gpu_write = true; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 985 | list_move_tail(&obj->gpu_write_list, |
| 986 | &ring->gpu_write_list); |
| 987 | intel_mark_busy(ring->dev, obj); |
| 988 | } |
| 989 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 990 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 991 | } |
| 992 | } |
| 993 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 994 | static void |
| 995 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 996 | struct drm_file *file, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 997 | struct intel_ring_buffer *ring) |
| 998 | { |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 999 | struct drm_i915_gem_request *request; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1000 | u32 invalidate; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1001 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1002 | /* |
| 1003 | * Ensure that the commands in the batch buffer are |
| 1004 | * finished before the interrupt fires. |
| 1005 | * |
| 1006 | * The sampler always gets flushed on i965 (sigh). |
| 1007 | */ |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1008 | invalidate = I915_GEM_DOMAIN_COMMAND; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1009 | if (INTEL_INFO(dev)->gen >= 4) |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1010 | invalidate |= I915_GEM_DOMAIN_SAMPLER; |
| 1011 | if (ring->flush(ring, invalidate, 0)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1012 | i915_gem_next_request_seqno(ring); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1013 | return; |
| 1014 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1015 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1016 | /* Add a breadcrumb for the completion of the batch buffer */ |
| 1017 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1018 | if (request == NULL || i915_add_request(ring, file, request)) { |
| 1019 | i915_gem_next_request_seqno(ring); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1020 | kfree(request); |
| 1021 | } |
| 1022 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1023 | |
| 1024 | static int |
Eric Anholt | ae662d3 | 2012-01-03 09:23:29 -0800 | [diff] [blame] | 1025 | i915_reset_gen7_sol_offsets(struct drm_device *dev, |
| 1026 | struct intel_ring_buffer *ring) |
| 1027 | { |
| 1028 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1029 | int ret, i; |
| 1030 | |
| 1031 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) |
| 1032 | return 0; |
| 1033 | |
| 1034 | ret = intel_ring_begin(ring, 4 * 3); |
| 1035 | if (ret) |
| 1036 | return ret; |
| 1037 | |
| 1038 | for (i = 0; i < 4; i++) { |
| 1039 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 1040 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); |
| 1041 | intel_ring_emit(ring, 0); |
| 1042 | } |
| 1043 | |
| 1044 | intel_ring_advance(ring); |
| 1045 | |
| 1046 | return 0; |
| 1047 | } |
| 1048 | |
| 1049 | static int |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1050 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
| 1051 | struct drm_file *file, |
| 1052 | struct drm_i915_gem_execbuffer2 *args, |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1053 | struct drm_i915_gem_exec_object2 *exec) |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1054 | { |
| 1055 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1056 | struct list_head objects; |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 1057 | struct eb_objects *eb; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1058 | struct drm_i915_gem_object *batch_obj; |
| 1059 | struct drm_clip_rect *cliprects = NULL; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1060 | struct intel_ring_buffer *ring; |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1061 | u32 exec_start, exec_len; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1062 | u32 seqno; |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 1063 | u32 mask; |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 1064 | int ret, mode, i; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1065 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1066 | if (!i915_gem_check_execbuffer(args)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1067 | DRM_DEBUG("execbuf with invalid offset/length\n"); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1068 | return -EINVAL; |
| 1069 | } |
| 1070 | |
| 1071 | ret = validate_exec_list(exec, args->buffer_count); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1072 | if (ret) |
| 1073 | return ret; |
| 1074 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1075 | switch (args->flags & I915_EXEC_RING_MASK) { |
| 1076 | case I915_EXEC_DEFAULT: |
| 1077 | case I915_EXEC_RENDER: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1078 | ring = &dev_priv->ring[RCS]; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1079 | break; |
| 1080 | case I915_EXEC_BSD: |
| 1081 | if (!HAS_BSD(dev)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1082 | DRM_DEBUG("execbuf with invalid ring (BSD)\n"); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1083 | return -EINVAL; |
| 1084 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1085 | ring = &dev_priv->ring[VCS]; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1086 | break; |
| 1087 | case I915_EXEC_BLT: |
| 1088 | if (!HAS_BLT(dev)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1089 | DRM_DEBUG("execbuf with invalid ring (BLT)\n"); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1090 | return -EINVAL; |
| 1091 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1092 | ring = &dev_priv->ring[BCS]; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1093 | break; |
| 1094 | default: |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1095 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1096 | (int)(args->flags & I915_EXEC_RING_MASK)); |
| 1097 | return -EINVAL; |
| 1098 | } |
| 1099 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 1100 | mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 1101 | mask = I915_EXEC_CONSTANTS_MASK; |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 1102 | switch (mode) { |
| 1103 | case I915_EXEC_CONSTANTS_REL_GENERAL: |
| 1104 | case I915_EXEC_CONSTANTS_ABSOLUTE: |
| 1105 | case I915_EXEC_CONSTANTS_REL_SURFACE: |
| 1106 | if (ring == &dev_priv->ring[RCS] && |
| 1107 | mode != dev_priv->relative_constants_mode) { |
| 1108 | if (INTEL_INFO(dev)->gen < 4) |
| 1109 | return -EINVAL; |
| 1110 | |
| 1111 | if (INTEL_INFO(dev)->gen > 5 && |
| 1112 | mode == I915_EXEC_CONSTANTS_REL_SURFACE) |
| 1113 | return -EINVAL; |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 1114 | |
| 1115 | /* The HW changed the meaning on this bit on gen6 */ |
| 1116 | if (INTEL_INFO(dev)->gen >= 6) |
| 1117 | mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 1118 | } |
| 1119 | break; |
| 1120 | default: |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1121 | DRM_DEBUG("execbuf with unknown constants: %d\n", mode); |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 1122 | return -EINVAL; |
| 1123 | } |
| 1124 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1125 | if (args->buffer_count < 1) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1126 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1127 | return -EINVAL; |
| 1128 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1129 | |
| 1130 | if (args->num_cliprects != 0) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1131 | if (ring != &dev_priv->ring[RCS]) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1132 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1133 | return -EINVAL; |
| 1134 | } |
| 1135 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1136 | cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects), |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1137 | GFP_KERNEL); |
| 1138 | if (cliprects == NULL) { |
| 1139 | ret = -ENOMEM; |
| 1140 | goto pre_mutex_err; |
| 1141 | } |
| 1142 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1143 | if (copy_from_user(cliprects, |
| 1144 | (struct drm_clip_rect __user *)(uintptr_t) |
| 1145 | args->cliprects_ptr, |
| 1146 | sizeof(*cliprects)*args->num_cliprects)) { |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1147 | ret = -EFAULT; |
| 1148 | goto pre_mutex_err; |
| 1149 | } |
| 1150 | } |
| 1151 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1152 | ret = i915_mutex_lock_interruptible(dev); |
| 1153 | if (ret) |
| 1154 | goto pre_mutex_err; |
| 1155 | |
| 1156 | if (dev_priv->mm.suspended) { |
| 1157 | mutex_unlock(&dev->struct_mutex); |
| 1158 | ret = -EBUSY; |
| 1159 | goto pre_mutex_err; |
| 1160 | } |
| 1161 | |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 1162 | eb = eb_create(args->buffer_count); |
| 1163 | if (eb == NULL) { |
| 1164 | mutex_unlock(&dev->struct_mutex); |
| 1165 | ret = -ENOMEM; |
| 1166 | goto pre_mutex_err; |
| 1167 | } |
| 1168 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1169 | /* Look up object handles */ |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1170 | INIT_LIST_HEAD(&objects); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1171 | for (i = 0; i < args->buffer_count; i++) { |
| 1172 | struct drm_i915_gem_object *obj; |
| 1173 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1174 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, |
| 1175 | exec[i].handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1176 | if (&obj->base == NULL) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1177 | DRM_DEBUG("Invalid object handle %d at index %d\n", |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1178 | exec[i].handle, i); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1179 | /* prevent error path from reading uninitialized data */ |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1180 | ret = -ENOENT; |
| 1181 | goto err; |
| 1182 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1183 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1184 | if (!list_empty(&obj->exec_list)) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1185 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1186 | obj, exec[i].handle, i); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1187 | ret = -EINVAL; |
| 1188 | goto err; |
| 1189 | } |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1190 | |
| 1191 | list_add_tail(&obj->exec_list, &objects); |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 1192 | obj->exec_handle = exec[i].handle; |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 1193 | obj->exec_entry = &exec[i]; |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 1194 | eb_add_object(eb, obj); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1195 | } |
| 1196 | |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 1197 | /* take note of the batch buffer before we might reorder the lists */ |
| 1198 | batch_obj = list_entry(objects.prev, |
| 1199 | struct drm_i915_gem_object, |
| 1200 | exec_list); |
| 1201 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1202 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 1203 | ret = i915_gem_execbuffer_reserve(ring, file, &objects); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1204 | if (ret) |
| 1205 | goto err; |
| 1206 | |
| 1207 | /* The objects are in their final locations, apply the relocations. */ |
Chris Wilson | 6fe4f14 | 2011-01-10 17:35:37 +0000 | [diff] [blame] | 1208 | ret = i915_gem_execbuffer_relocate(dev, eb, &objects); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1209 | if (ret) { |
| 1210 | if (ret == -EFAULT) { |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1211 | ret = i915_gem_execbuffer_relocate_slow(dev, file, ring, |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 1212 | &objects, eb, |
| 1213 | exec, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1214 | args->buffer_count); |
| 1215 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1216 | } |
| 1217 | if (ret) |
| 1218 | goto err; |
| 1219 | } |
| 1220 | |
| 1221 | /* Set the pending read domains for the batch buffer to COMMAND */ |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1222 | if (batch_obj->base.pending_write_domain) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1223 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1224 | ret = -EINVAL; |
| 1225 | goto err; |
| 1226 | } |
| 1227 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
| 1228 | |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1229 | ret = i915_gem_execbuffer_move_to_gpu(ring, &objects); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1230 | if (ret) |
| 1231 | goto err; |
| 1232 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1233 | seqno = i915_gem_next_request_seqno(ring); |
Chris Wilson | 076e2c0 | 2011-01-21 10:07:18 +0000 | [diff] [blame] | 1234 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1235 | if (seqno < ring->sync_seqno[i]) { |
| 1236 | /* The GPU can not handle its semaphore value wrapping, |
| 1237 | * so every billion or so execbuffers, we need to stall |
| 1238 | * the GPU in order to reset the counters. |
| 1239 | */ |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 1240 | ret = i915_gpu_idle(dev, true); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1241 | if (ret) |
| 1242 | goto err; |
| 1243 | |
| 1244 | BUG_ON(ring->sync_seqno[i]); |
| 1245 | } |
| 1246 | } |
| 1247 | |
Ben Widawsky | e2971bd | 2011-12-12 19:21:57 -0800 | [diff] [blame] | 1248 | if (ring == &dev_priv->ring[RCS] && |
| 1249 | mode != dev_priv->relative_constants_mode) { |
| 1250 | ret = intel_ring_begin(ring, 4); |
| 1251 | if (ret) |
| 1252 | goto err; |
| 1253 | |
| 1254 | intel_ring_emit(ring, MI_NOOP); |
| 1255 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 1256 | intel_ring_emit(ring, INSTPM); |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 1257 | intel_ring_emit(ring, mask << 16 | mode); |
Ben Widawsky | e2971bd | 2011-12-12 19:21:57 -0800 | [diff] [blame] | 1258 | intel_ring_advance(ring); |
| 1259 | |
| 1260 | dev_priv->relative_constants_mode = mode; |
| 1261 | } |
| 1262 | |
Eric Anholt | ae662d3 | 2012-01-03 09:23:29 -0800 | [diff] [blame] | 1263 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
| 1264 | ret = i915_reset_gen7_sol_offsets(dev, ring); |
| 1265 | if (ret) |
| 1266 | goto err; |
| 1267 | } |
| 1268 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1269 | trace_i915_gem_ring_dispatch(ring, seqno); |
| 1270 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1271 | exec_start = batch_obj->gtt_offset + args->batch_start_offset; |
| 1272 | exec_len = args->batch_len; |
| 1273 | if (cliprects) { |
| 1274 | for (i = 0; i < args->num_cliprects; i++) { |
| 1275 | ret = i915_emit_box(dev, &cliprects[i], |
| 1276 | args->DR1, args->DR4); |
| 1277 | if (ret) |
| 1278 | goto err; |
| 1279 | |
| 1280 | ret = ring->dispatch_execbuffer(ring, |
| 1281 | exec_start, exec_len); |
| 1282 | if (ret) |
| 1283 | goto err; |
| 1284 | } |
| 1285 | } else { |
| 1286 | ret = ring->dispatch_execbuffer(ring, exec_start, exec_len); |
| 1287 | if (ret) |
| 1288 | goto err; |
| 1289 | } |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1290 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1291 | i915_gem_execbuffer_move_to_active(&objects, ring, seqno); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1292 | i915_gem_execbuffer_retire_commands(dev, file, ring); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1293 | |
| 1294 | err: |
Chris Wilson | 67731b8 | 2010-12-08 10:38:14 +0000 | [diff] [blame] | 1295 | eb_destroy(eb); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 1296 | while (!list_empty(&objects)) { |
| 1297 | struct drm_i915_gem_object *obj; |
| 1298 | |
| 1299 | obj = list_first_entry(&objects, |
| 1300 | struct drm_i915_gem_object, |
| 1301 | exec_list); |
| 1302 | list_del_init(&obj->exec_list); |
| 1303 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1304 | } |
| 1305 | |
| 1306 | mutex_unlock(&dev->struct_mutex); |
| 1307 | |
| 1308 | pre_mutex_err: |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1309 | kfree(cliprects); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1310 | return ret; |
| 1311 | } |
| 1312 | |
| 1313 | /* |
| 1314 | * Legacy execbuffer just creates an exec2 list from the original exec object |
| 1315 | * list array and passes it to the real function. |
| 1316 | */ |
| 1317 | int |
| 1318 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 1319 | struct drm_file *file) |
| 1320 | { |
| 1321 | struct drm_i915_gem_execbuffer *args = data; |
| 1322 | struct drm_i915_gem_execbuffer2 exec2; |
| 1323 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 1324 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 1325 | int ret, i; |
| 1326 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1327 | if (args->buffer_count < 1) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1328 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1329 | return -EINVAL; |
| 1330 | } |
| 1331 | |
| 1332 | /* Copy in the exec list from userland */ |
| 1333 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); |
| 1334 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 1335 | if (exec_list == NULL || exec2_list == NULL) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1336 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1337 | args->buffer_count); |
| 1338 | drm_free_large(exec_list); |
| 1339 | drm_free_large(exec2_list); |
| 1340 | return -ENOMEM; |
| 1341 | } |
| 1342 | ret = copy_from_user(exec_list, |
| 1343 | (struct drm_i915_relocation_entry __user *) |
| 1344 | (uintptr_t) args->buffers_ptr, |
| 1345 | sizeof(*exec_list) * args->buffer_count); |
| 1346 | if (ret != 0) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1347 | DRM_DEBUG("copy %d exec entries failed %d\n", |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1348 | args->buffer_count, ret); |
| 1349 | drm_free_large(exec_list); |
| 1350 | drm_free_large(exec2_list); |
| 1351 | return -EFAULT; |
| 1352 | } |
| 1353 | |
| 1354 | for (i = 0; i < args->buffer_count; i++) { |
| 1355 | exec2_list[i].handle = exec_list[i].handle; |
| 1356 | exec2_list[i].relocation_count = exec_list[i].relocation_count; |
| 1357 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; |
| 1358 | exec2_list[i].alignment = exec_list[i].alignment; |
| 1359 | exec2_list[i].offset = exec_list[i].offset; |
| 1360 | if (INTEL_INFO(dev)->gen < 4) |
| 1361 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
| 1362 | else |
| 1363 | exec2_list[i].flags = 0; |
| 1364 | } |
| 1365 | |
| 1366 | exec2.buffers_ptr = args->buffers_ptr; |
| 1367 | exec2.buffer_count = args->buffer_count; |
| 1368 | exec2.batch_start_offset = args->batch_start_offset; |
| 1369 | exec2.batch_len = args->batch_len; |
| 1370 | exec2.DR1 = args->DR1; |
| 1371 | exec2.DR4 = args->DR4; |
| 1372 | exec2.num_cliprects = args->num_cliprects; |
| 1373 | exec2.cliprects_ptr = args->cliprects_ptr; |
| 1374 | exec2.flags = I915_EXEC_RENDER; |
| 1375 | |
| 1376 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
| 1377 | if (!ret) { |
| 1378 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 1379 | for (i = 0; i < args->buffer_count; i++) |
| 1380 | exec_list[i].offset = exec2_list[i].offset; |
| 1381 | /* ... and back out to userspace */ |
| 1382 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 1383 | (uintptr_t) args->buffers_ptr, |
| 1384 | exec_list, |
| 1385 | sizeof(*exec_list) * args->buffer_count); |
| 1386 | if (ret) { |
| 1387 | ret = -EFAULT; |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1388 | DRM_DEBUG("failed to copy %d exec entries " |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1389 | "back to user (%d)\n", |
| 1390 | args->buffer_count, ret); |
| 1391 | } |
| 1392 | } |
| 1393 | |
| 1394 | drm_free_large(exec_list); |
| 1395 | drm_free_large(exec2_list); |
| 1396 | return ret; |
| 1397 | } |
| 1398 | |
| 1399 | int |
| 1400 | i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 1401 | struct drm_file *file) |
| 1402 | { |
| 1403 | struct drm_i915_gem_execbuffer2 *args = data; |
| 1404 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 1405 | int ret; |
| 1406 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1407 | if (args->buffer_count < 1) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1408 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1409 | return -EINVAL; |
| 1410 | } |
| 1411 | |
Chris Wilson | 8408c28 | 2011-02-21 12:54:48 +0000 | [diff] [blame] | 1412 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
| 1413 | GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY); |
| 1414 | if (exec2_list == NULL) |
| 1415 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), |
| 1416 | args->buffer_count); |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1417 | if (exec2_list == NULL) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1418 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1419 | args->buffer_count); |
| 1420 | return -ENOMEM; |
| 1421 | } |
| 1422 | ret = copy_from_user(exec2_list, |
| 1423 | (struct drm_i915_relocation_entry __user *) |
| 1424 | (uintptr_t) args->buffers_ptr, |
| 1425 | sizeof(*exec2_list) * args->buffer_count); |
| 1426 | if (ret != 0) { |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1427 | DRM_DEBUG("copy %d exec entries failed %d\n", |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1428 | args->buffer_count, ret); |
| 1429 | drm_free_large(exec2_list); |
| 1430 | return -EFAULT; |
| 1431 | } |
| 1432 | |
| 1433 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
| 1434 | if (!ret) { |
| 1435 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 1436 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 1437 | (uintptr_t) args->buffers_ptr, |
| 1438 | exec2_list, |
| 1439 | sizeof(*exec2_list) * args->buffer_count); |
| 1440 | if (ret) { |
| 1441 | ret = -EFAULT; |
Daniel Vetter | ff24019 | 2012-01-31 21:08:14 +0100 | [diff] [blame] | 1442 | DRM_DEBUG("failed to copy %d exec entries " |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1443 | "back to user (%d)\n", |
| 1444 | args->buffer_count, ret); |
| 1445 | } |
| 1446 | } |
| 1447 | |
| 1448 | drm_free_large(exec2_list); |
| 1449 | return ret; |
| 1450 | } |