Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel PRO/1000 Linux driver |
Bruce Allan | f5e261e | 2012-01-01 16:00:03 +0000 | [diff] [blame] | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | Linux NICS <linux.nics@intel.com> |
| 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 26 | |
| 27 | *******************************************************************************/ |
| 28 | |
| 29 | /* |
Bruce Allan | 1605927 | 2008-11-21 16:51:06 -0800 | [diff] [blame] | 30 | * 82562G 10/100 Network Connection |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 31 | * 82562G-2 10/100 Network Connection |
| 32 | * 82562GT 10/100 Network Connection |
| 33 | * 82562GT-2 10/100 Network Connection |
| 34 | * 82562V 10/100 Network Connection |
| 35 | * 82562V-2 10/100 Network Connection |
| 36 | * 82566DC-2 Gigabit Network Connection |
| 37 | * 82566DC Gigabit Network Connection |
| 38 | * 82566DM-2 Gigabit Network Connection |
| 39 | * 82566DM Gigabit Network Connection |
| 40 | * 82566MC Gigabit Network Connection |
| 41 | * 82566MM Gigabit Network Connection |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 42 | * 82567LM Gigabit Network Connection |
| 43 | * 82567LF Gigabit Network Connection |
Bruce Allan | 1605927 | 2008-11-21 16:51:06 -0800 | [diff] [blame] | 44 | * 82567V Gigabit Network Connection |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 45 | * 82567LM-2 Gigabit Network Connection |
| 46 | * 82567LF-2 Gigabit Network Connection |
| 47 | * 82567V-2 Gigabit Network Connection |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 48 | * 82567LF-3 Gigabit Network Connection |
| 49 | * 82567LM-3 Gigabit Network Connection |
Bruce Allan | 2f15f9d | 2008-08-26 18:36:36 -0700 | [diff] [blame] | 50 | * 82567LM-4 Gigabit Network Connection |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 51 | * 82577LM Gigabit Network Connection |
| 52 | * 82577LC Gigabit Network Connection |
| 53 | * 82578DM Gigabit Network Connection |
| 54 | * 82578DC Gigabit Network Connection |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 55 | * 82579LM Gigabit Network Connection |
| 56 | * 82579V Gigabit Network Connection |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 57 | */ |
| 58 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 59 | #include "e1000.h" |
| 60 | |
| 61 | #define ICH_FLASH_GFPREG 0x0000 |
| 62 | #define ICH_FLASH_HSFSTS 0x0004 |
| 63 | #define ICH_FLASH_HSFCTL 0x0006 |
| 64 | #define ICH_FLASH_FADDR 0x0008 |
| 65 | #define ICH_FLASH_FDATA0 0x0010 |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 66 | #define ICH_FLASH_PR0 0x0074 |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 67 | |
| 68 | #define ICH_FLASH_READ_COMMAND_TIMEOUT 500 |
| 69 | #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500 |
| 70 | #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000 |
| 71 | #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF |
| 72 | #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 |
| 73 | |
| 74 | #define ICH_CYCLE_READ 0 |
| 75 | #define ICH_CYCLE_WRITE 2 |
| 76 | #define ICH_CYCLE_ERASE 3 |
| 77 | |
| 78 | #define FLASH_GFPREG_BASE_MASK 0x1FFF |
| 79 | #define FLASH_SECTOR_ADDR_SHIFT 12 |
| 80 | |
| 81 | #define ICH_FLASH_SEG_SIZE_256 256 |
| 82 | #define ICH_FLASH_SEG_SIZE_4K 4096 |
| 83 | #define ICH_FLASH_SEG_SIZE_8K 8192 |
| 84 | #define ICH_FLASH_SEG_SIZE_64K 65536 |
| 85 | |
| 86 | |
| 87 | #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ |
Bruce Allan | 6dfaa76 | 2010-05-05 22:00:06 +0000 | [diff] [blame] | 88 | /* FW established a valid mode */ |
| 89 | #define E1000_ICH_FWSM_FW_VALID 0x00008000 |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 90 | |
| 91 | #define E1000_ICH_MNG_IAMT_MODE 0x2 |
| 92 | |
| 93 | #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ |
| 94 | (ID_LED_DEF1_OFF2 << 8) | \ |
| 95 | (ID_LED_DEF1_ON2 << 4) | \ |
| 96 | (ID_LED_DEF1_DEF2)) |
| 97 | |
| 98 | #define E1000_ICH_NVM_SIG_WORD 0x13 |
| 99 | #define E1000_ICH_NVM_SIG_MASK 0xC000 |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 100 | #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 |
| 101 | #define E1000_ICH_NVM_SIG_VALUE 0x80 |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 102 | |
| 103 | #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 |
| 104 | |
| 105 | #define E1000_FEXTNVM_SW_CONFIG 1 |
| 106 | #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */ |
| 107 | |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 108 | #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 |
| 109 | #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 |
| 110 | #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 |
| 111 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 112 | #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL |
| 113 | |
| 114 | #define E1000_ICH_RAR_ENTRIES 7 |
| 115 | |
| 116 | #define PHY_PAGE_SHIFT 5 |
| 117 | #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ |
| 118 | ((reg) & MAX_PHY_REG_ADDRESS)) |
| 119 | #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ |
| 120 | #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ |
| 121 | |
| 122 | #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 |
| 123 | #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 |
| 124 | #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 |
| 125 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 126 | #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ |
| 127 | |
Bruce Allan | 53ac5a8 | 2009-10-26 11:23:06 +0000 | [diff] [blame] | 128 | #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */ |
| 129 | |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 130 | /* SMBus Address Phy Register */ |
| 131 | #define HV_SMB_ADDR PHY_REG(768, 26) |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 132 | #define HV_SMB_ADDR_MASK 0x007F |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 133 | #define HV_SMB_ADDR_PEC_EN 0x0200 |
| 134 | #define HV_SMB_ADDR_VALID 0x0080 |
| 135 | |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 136 | /* PHY Power Management Control */ |
| 137 | #define HV_PM_CTRL PHY_REG(770, 17) |
| 138 | |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 139 | /* PHY Low Power Idle Control */ |
Bruce Allan | 0ed013e | 2011-07-29 05:52:56 +0000 | [diff] [blame] | 140 | #define I82579_LPI_CTRL PHY_REG(772, 20) |
| 141 | #define I82579_LPI_CTRL_ENABLE_MASK 0x6000 |
| 142 | #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80 |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 143 | |
Bruce Allan | 1effb45 | 2011-02-25 06:58:03 +0000 | [diff] [blame] | 144 | /* EMI Registers */ |
| 145 | #define I82579_EMI_ADDR 0x10 |
| 146 | #define I82579_EMI_DATA 0x11 |
| 147 | #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ |
Bruce Allan | 4d24136 | 2011-12-16 00:46:06 +0000 | [diff] [blame] | 148 | #define I82579_MSE_THRESHOLD 0x084F /* Mean Square Error Threshold */ |
| 149 | #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ |
Bruce Allan | 1effb45 | 2011-02-25 06:58:03 +0000 | [diff] [blame] | 150 | |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 151 | /* Strapping Option Register - RO */ |
| 152 | #define E1000_STRAP 0x0000C |
| 153 | #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 |
| 154 | #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 |
| 155 | |
Bruce Allan | fa2ce13 | 2009-10-26 11:23:25 +0000 | [diff] [blame] | 156 | /* OEM Bits Phy Register */ |
| 157 | #define HV_OEM_BITS PHY_REG(768, 25) |
| 158 | #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 159 | #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ |
Bruce Allan | fa2ce13 | 2009-10-26 11:23:25 +0000 | [diff] [blame] | 160 | #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ |
| 161 | |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 162 | #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ |
| 163 | #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ |
| 164 | |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 165 | /* KMRN Mode Control */ |
| 166 | #define HV_KMRN_MODE_CTRL PHY_REG(769, 16) |
| 167 | #define HV_KMRN_MDIO_SLOW 0x0400 |
| 168 | |
Bruce Allan | 1d2101a7 | 2011-07-22 06:21:56 +0000 | [diff] [blame] | 169 | /* KMRN FIFO Control and Status */ |
| 170 | #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16) |
| 171 | #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 |
| 172 | #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 |
| 173 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 174 | /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ |
| 175 | /* Offset 04h HSFSTS */ |
| 176 | union ich8_hws_flash_status { |
| 177 | struct ich8_hsfsts { |
| 178 | u16 flcdone :1; /* bit 0 Flash Cycle Done */ |
| 179 | u16 flcerr :1; /* bit 1 Flash Cycle Error */ |
| 180 | u16 dael :1; /* bit 2 Direct Access error Log */ |
| 181 | u16 berasesz :2; /* bit 4:3 Sector Erase Size */ |
| 182 | u16 flcinprog :1; /* bit 5 flash cycle in Progress */ |
| 183 | u16 reserved1 :2; /* bit 13:6 Reserved */ |
| 184 | u16 reserved2 :6; /* bit 13:6 Reserved */ |
| 185 | u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ |
| 186 | u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ |
| 187 | } hsf_status; |
| 188 | u16 regval; |
| 189 | }; |
| 190 | |
| 191 | /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ |
| 192 | /* Offset 06h FLCTL */ |
| 193 | union ich8_hws_flash_ctrl { |
| 194 | struct ich8_hsflctl { |
| 195 | u16 flcgo :1; /* 0 Flash Cycle Go */ |
| 196 | u16 flcycle :2; /* 2:1 Flash Cycle */ |
| 197 | u16 reserved :5; /* 7:3 Reserved */ |
| 198 | u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ |
| 199 | u16 flockdn :6; /* 15:10 Reserved */ |
| 200 | } hsf_ctrl; |
| 201 | u16 regval; |
| 202 | }; |
| 203 | |
| 204 | /* ICH Flash Region Access Permissions */ |
| 205 | union ich8_hws_flash_regacc { |
| 206 | struct ich8_flracc { |
| 207 | u32 grra :8; /* 0:7 GbE region Read Access */ |
| 208 | u32 grwa :8; /* 8:15 GbE region Write Access */ |
| 209 | u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ |
| 210 | u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ |
| 211 | } hsf_flregacc; |
| 212 | u16 regval; |
| 213 | }; |
| 214 | |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 215 | /* ICH Flash Protected Region */ |
| 216 | union ich8_flash_protected_range { |
| 217 | struct ich8_pr { |
| 218 | u32 base:13; /* 0:12 Protected Range Base */ |
| 219 | u32 reserved1:2; /* 13:14 Reserved */ |
| 220 | u32 rpe:1; /* 15 Read Protection Enable */ |
| 221 | u32 limit:13; /* 16:28 Protected Range Limit */ |
| 222 | u32 reserved2:2; /* 29:30 Reserved */ |
| 223 | u32 wpe:1; /* 31 Write Protection Enable */ |
| 224 | } range; |
| 225 | u32 regval; |
| 226 | }; |
| 227 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 228 | static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); |
| 229 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); |
| 230 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 231 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); |
| 232 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, |
| 233 | u32 offset, u8 byte); |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 234 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, |
| 235 | u8 *data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 236 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, |
| 237 | u16 *data); |
| 238 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, |
| 239 | u8 size, u16 *data); |
| 240 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); |
| 241 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 242 | static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 243 | static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); |
| 244 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); |
| 245 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); |
| 246 | static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); |
| 247 | static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); |
| 248 | static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); |
| 249 | static s32 e1000_led_on_pchlan(struct e1000_hw *hw); |
| 250 | static s32 e1000_led_off_pchlan(struct e1000_hw *hw); |
Bruce Allan | fa2ce13 | 2009-10-26 11:23:25 +0000 | [diff] [blame] | 251 | static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 252 | static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 253 | static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 254 | static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 255 | static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); |
Bruce Allan | eb7700d | 2010-06-16 13:27:05 +0000 | [diff] [blame] | 256 | static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); |
| 257 | static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 258 | static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 259 | static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 260 | |
| 261 | static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) |
| 262 | { |
| 263 | return readw(hw->flash_address + reg); |
| 264 | } |
| 265 | |
| 266 | static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) |
| 267 | { |
| 268 | return readl(hw->flash_address + reg); |
| 269 | } |
| 270 | |
| 271 | static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) |
| 272 | { |
| 273 | writew(val, hw->flash_address + reg); |
| 274 | } |
| 275 | |
| 276 | static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) |
| 277 | { |
| 278 | writel(val, hw->flash_address + reg); |
| 279 | } |
| 280 | |
| 281 | #define er16flash(reg) __er16flash(hw, (reg)) |
| 282 | #define er32flash(reg) __er32flash(hw, (reg)) |
Bruce Allan | 0e15df4 | 2012-01-31 06:37:11 +0000 | [diff] [blame] | 283 | #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) |
| 284 | #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 285 | |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 286 | static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw) |
| 287 | { |
| 288 | u32 ctrl; |
| 289 | |
| 290 | ctrl = er32(CTRL); |
| 291 | ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; |
| 292 | ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; |
| 293 | ew32(CTRL, ctrl); |
Jesse Brandeburg | 945a515 | 2011-07-20 00:56:21 +0000 | [diff] [blame] | 294 | e1e_flush(); |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 295 | udelay(10); |
| 296 | ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; |
| 297 | ew32(CTRL, ctrl); |
| 298 | } |
| 299 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 300 | /** |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 301 | * e1000_init_phy_params_pchlan - Initialize PHY function pointers |
| 302 | * @hw: pointer to the HW structure |
| 303 | * |
| 304 | * Initialize family-specific PHY parameters and function pointers. |
| 305 | **/ |
| 306 | static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) |
| 307 | { |
| 308 | struct e1000_phy_info *phy = &hw->phy; |
| 309 | s32 ret_val = 0; |
| 310 | |
| 311 | phy->addr = 1; |
| 312 | phy->reset_delay_us = 100; |
| 313 | |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 314 | phy->ops.set_page = e1000_set_page_igp; |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 315 | phy->ops.read_reg = e1000_read_phy_reg_hv; |
| 316 | phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 317 | phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; |
Bruce Allan | fa2ce13 | 2009-10-26 11:23:25 +0000 | [diff] [blame] | 318 | phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; |
| 319 | phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 320 | phy->ops.write_reg = e1000_write_phy_reg_hv; |
| 321 | phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 322 | phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 323 | phy->ops.power_up = e1000_power_up_phy_copper; |
| 324 | phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 325 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
| 326 | |
Bruce Allan | 44abd5c | 2012-02-22 09:02:37 +0000 | [diff] [blame] | 327 | if (!hw->phy.ops.check_reset_block(hw)) { |
Bruce Allan | 90b8298 | 2011-12-16 00:46:33 +0000 | [diff] [blame] | 328 | u32 fwsm = er32(FWSM); |
| 329 | |
| 330 | /* |
| 331 | * The MAC-PHY interconnect may still be in SMBus mode after |
| 332 | * Sx->S0. If resetting the PHY is not blocked, toggle the |
| 333 | * LANPHYPC Value bit to force the interconnect to PCIe mode. |
| 334 | */ |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 335 | e1000_toggle_lanphypc_value_ich8lan(hw); |
Bruce Allan | 6dfaa76 | 2010-05-05 22:00:06 +0000 | [diff] [blame] | 336 | msleep(50); |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 337 | |
| 338 | /* |
| 339 | * Gate automatic PHY configuration by hardware on |
| 340 | * non-managed 82579 |
| 341 | */ |
Bruce Allan | 90b8298 | 2011-12-16 00:46:33 +0000 | [diff] [blame] | 342 | if ((hw->mac.type == e1000_pch2lan) && |
| 343 | !(fwsm & E1000_ICH_FWSM_FW_VALID)) |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 344 | e1000_gate_hw_phy_config_ich8lan(hw, true); |
Bruce Allan | 6dfaa76 | 2010-05-05 22:00:06 +0000 | [diff] [blame] | 345 | |
Bruce Allan | 90b8298 | 2011-12-16 00:46:33 +0000 | [diff] [blame] | 346 | /* |
| 347 | * Reset the PHY before any access to it. Doing so, ensures |
| 348 | * that the PHY is in a known good state before we read/write |
| 349 | * PHY registers. The generic reset is sufficient here, |
| 350 | * because we haven't determined the PHY type yet. |
| 351 | */ |
| 352 | ret_val = e1000e_phy_hw_reset_generic(hw); |
| 353 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 354 | return ret_val; |
Bruce Allan | 627c8a0 | 2010-05-05 22:00:27 +0000 | [diff] [blame] | 355 | |
Bruce Allan | 90b8298 | 2011-12-16 00:46:33 +0000 | [diff] [blame] | 356 | /* Ungate automatic PHY configuration on non-managed 82579 */ |
| 357 | if ((hw->mac.type == e1000_pch2lan) && |
| 358 | !(fwsm & E1000_ICH_FWSM_FW_VALID)) { |
| 359 | usleep_range(10000, 20000); |
| 360 | e1000_gate_hw_phy_config_ich8lan(hw, false); |
| 361 | } |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 362 | } |
| 363 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 364 | phy->id = e1000_phy_unknown; |
Bruce Allan | 664dc87 | 2010-11-24 06:01:46 +0000 | [diff] [blame] | 365 | switch (hw->mac.type) { |
| 366 | default: |
| 367 | ret_val = e1000e_get_phy_id(hw); |
| 368 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 369 | return ret_val; |
Bruce Allan | 664dc87 | 2010-11-24 06:01:46 +0000 | [diff] [blame] | 370 | if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) |
| 371 | break; |
| 372 | /* fall-through */ |
| 373 | case e1000_pch2lan: |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 374 | /* |
Bruce Allan | 664dc87 | 2010-11-24 06:01:46 +0000 | [diff] [blame] | 375 | * In case the PHY needs to be in mdio slow mode, |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 376 | * set slow mode and try to get the PHY id again. |
| 377 | */ |
| 378 | ret_val = e1000_set_mdio_slow_mode_hv(hw); |
| 379 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 380 | return ret_val; |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 381 | ret_val = e1000e_get_phy_id(hw); |
| 382 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 383 | return ret_val; |
Bruce Allan | 664dc87 | 2010-11-24 06:01:46 +0000 | [diff] [blame] | 384 | break; |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 385 | } |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 386 | phy->type = e1000e_get_phy_type_from_id(phy->id); |
| 387 | |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 388 | switch (phy->type) { |
| 389 | case e1000_phy_82577: |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 390 | case e1000_phy_82579: |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 391 | phy->ops.check_polarity = e1000_check_polarity_82577; |
| 392 | phy->ops.force_speed_duplex = |
Bruce Allan | 6cc7aae | 2011-02-25 06:25:18 +0000 | [diff] [blame] | 393 | e1000_phy_force_speed_duplex_82577; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 394 | phy->ops.get_cable_length = e1000_get_cable_length_82577; |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 395 | phy->ops.get_info = e1000_get_phy_info_82577; |
| 396 | phy->ops.commit = e1000e_phy_sw_reset; |
Bruce Allan | eab50ff | 2010-05-10 15:01:30 +0000 | [diff] [blame] | 397 | break; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 398 | case e1000_phy_82578: |
| 399 | phy->ops.check_polarity = e1000_check_polarity_m88; |
| 400 | phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; |
| 401 | phy->ops.get_cable_length = e1000e_get_cable_length_m88; |
| 402 | phy->ops.get_info = e1000e_get_phy_info_m88; |
| 403 | break; |
| 404 | default: |
| 405 | ret_val = -E1000_ERR_PHY; |
| 406 | break; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 407 | } |
| 408 | |
| 409 | return ret_val; |
| 410 | } |
| 411 | |
| 412 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 413 | * e1000_init_phy_params_ich8lan - Initialize PHY function pointers |
| 414 | * @hw: pointer to the HW structure |
| 415 | * |
| 416 | * Initialize family-specific PHY parameters and function pointers. |
| 417 | **/ |
| 418 | static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) |
| 419 | { |
| 420 | struct e1000_phy_info *phy = &hw->phy; |
| 421 | s32 ret_val; |
| 422 | u16 i = 0; |
| 423 | |
| 424 | phy->addr = 1; |
| 425 | phy->reset_delay_us = 100; |
| 426 | |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 427 | phy->ops.power_up = e1000_power_up_phy_copper; |
| 428 | phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; |
| 429 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 430 | /* |
| 431 | * We may need to do this twice - once for IGP and if that fails, |
| 432 | * we'll set BM func pointers and try again |
| 433 | */ |
| 434 | ret_val = e1000e_determine_phy_address(hw); |
| 435 | if (ret_val) { |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 436 | phy->ops.write_reg = e1000e_write_phy_reg_bm; |
| 437 | phy->ops.read_reg = e1000e_read_phy_reg_bm; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 438 | ret_val = e1000e_determine_phy_address(hw); |
Bruce Allan | 9b71b41 | 2009-12-01 15:53:07 +0000 | [diff] [blame] | 439 | if (ret_val) { |
| 440 | e_dbg("Cannot determine PHY addr. Erroring out\n"); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 441 | return ret_val; |
Bruce Allan | 9b71b41 | 2009-12-01 15:53:07 +0000 | [diff] [blame] | 442 | } |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 443 | } |
| 444 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 445 | phy->id = 0; |
| 446 | while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && |
| 447 | (i++ < 100)) { |
Bruce Allan | 1bba438 | 2011-03-19 00:27:20 +0000 | [diff] [blame] | 448 | usleep_range(1000, 2000); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 449 | ret_val = e1000e_get_phy_id(hw); |
| 450 | if (ret_val) |
| 451 | return ret_val; |
| 452 | } |
| 453 | |
| 454 | /* Verify phy id */ |
| 455 | switch (phy->id) { |
| 456 | case IGP03E1000_E_PHY_ID: |
| 457 | phy->type = e1000_phy_igp_3; |
| 458 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 459 | phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; |
| 460 | phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 461 | phy->ops.get_info = e1000e_get_phy_info_igp; |
| 462 | phy->ops.check_polarity = e1000_check_polarity_igp; |
| 463 | phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 464 | break; |
| 465 | case IFE_E_PHY_ID: |
| 466 | case IFE_PLUS_E_PHY_ID: |
| 467 | case IFE_C_E_PHY_ID: |
| 468 | phy->type = e1000_phy_ife; |
| 469 | phy->autoneg_mask = E1000_ALL_NOT_GIG; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 470 | phy->ops.get_info = e1000_get_phy_info_ife; |
| 471 | phy->ops.check_polarity = e1000_check_polarity_ife; |
| 472 | phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 473 | break; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 474 | case BME1000_E_PHY_ID: |
| 475 | phy->type = e1000_phy_bm; |
| 476 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 477 | phy->ops.read_reg = e1000e_read_phy_reg_bm; |
| 478 | phy->ops.write_reg = e1000e_write_phy_reg_bm; |
| 479 | phy->ops.commit = e1000e_phy_sw_reset; |
Bruce Allan | 0be8401 | 2009-12-02 17:03:18 +0000 | [diff] [blame] | 480 | phy->ops.get_info = e1000e_get_phy_info_m88; |
| 481 | phy->ops.check_polarity = e1000_check_polarity_m88; |
| 482 | phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 483 | break; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 484 | default: |
| 485 | return -E1000_ERR_PHY; |
| 486 | break; |
| 487 | } |
| 488 | |
| 489 | return 0; |
| 490 | } |
| 491 | |
| 492 | /** |
| 493 | * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers |
| 494 | * @hw: pointer to the HW structure |
| 495 | * |
| 496 | * Initialize family-specific NVM parameters and function |
| 497 | * pointers. |
| 498 | **/ |
| 499 | static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) |
| 500 | { |
| 501 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 502 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 503 | u32 gfpreg, sector_base_addr, sector_end_addr; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 504 | u16 i; |
| 505 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 506 | /* Can't read flash registers if the register set isn't mapped. */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 507 | if (!hw->flash_address) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 508 | e_dbg("ERROR: Flash registers not mapped\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 509 | return -E1000_ERR_CONFIG; |
| 510 | } |
| 511 | |
| 512 | nvm->type = e1000_nvm_flash_sw; |
| 513 | |
| 514 | gfpreg = er32flash(ICH_FLASH_GFPREG); |
| 515 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 516 | /* |
| 517 | * sector_X_addr is a "sector"-aligned address (4096 bytes) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 518 | * Add 1 to sector_end_addr since this sector is included in |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 519 | * the overall size. |
| 520 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 521 | sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; |
| 522 | sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; |
| 523 | |
| 524 | /* flash_base_addr is byte-aligned */ |
| 525 | nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; |
| 526 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 527 | /* |
| 528 | * find total size of the NVM, then cut in half since the total |
| 529 | * size represents two separate NVM banks. |
| 530 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 531 | nvm->flash_bank_size = (sector_end_addr - sector_base_addr) |
| 532 | << FLASH_SECTOR_ADDR_SHIFT; |
| 533 | nvm->flash_bank_size /= 2; |
| 534 | /* Adjust to word count */ |
| 535 | nvm->flash_bank_size /= sizeof(u16); |
| 536 | |
| 537 | nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; |
| 538 | |
| 539 | /* Clear shadow ram */ |
| 540 | for (i = 0; i < nvm->word_size; i++) { |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 541 | dev_spec->shadow_ram[i].modified = false; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 542 | dev_spec->shadow_ram[i].value = 0xFFFF; |
| 543 | } |
| 544 | |
| 545 | return 0; |
| 546 | } |
| 547 | |
| 548 | /** |
| 549 | * e1000_init_mac_params_ich8lan - Initialize MAC function pointers |
| 550 | * @hw: pointer to the HW structure |
| 551 | * |
| 552 | * Initialize family-specific MAC parameters and function |
| 553 | * pointers. |
| 554 | **/ |
Bruce Allan | ec34c17 | 2012-02-01 10:53:05 +0000 | [diff] [blame] | 555 | static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 556 | { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 557 | struct e1000_mac_info *mac = &hw->mac; |
| 558 | |
| 559 | /* Set media type function pointer */ |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 560 | hw->phy.media_type = e1000_media_type_copper; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 561 | |
| 562 | /* Set mta register count */ |
| 563 | mac->mta_reg_count = 32; |
| 564 | /* Set rar entry count */ |
| 565 | mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; |
| 566 | if (mac->type == e1000_ich8lan) |
| 567 | mac->rar_entry_count--; |
Bruce Allan | a65a4a0 | 2010-05-10 15:01:51 +0000 | [diff] [blame] | 568 | /* FWSM register */ |
| 569 | mac->has_fwsm = true; |
| 570 | /* ARC subsystem not supported */ |
| 571 | mac->arc_subsystem_valid = false; |
Bruce Allan | f464ba8 | 2010-01-07 16:31:35 +0000 | [diff] [blame] | 572 | /* Adaptive IFS supported */ |
| 573 | mac->adaptive_ifs = true; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 574 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 575 | /* LED operations */ |
| 576 | switch (mac->type) { |
| 577 | case e1000_ich8lan: |
| 578 | case e1000_ich9lan: |
| 579 | case e1000_ich10lan: |
Bruce Allan | eb7700d | 2010-06-16 13:27:05 +0000 | [diff] [blame] | 580 | /* check management mode */ |
| 581 | mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 582 | /* ID LED init */ |
Bruce Allan | d1964eb | 2012-02-22 09:02:21 +0000 | [diff] [blame] | 583 | mac->ops.id_led_init = e1000e_id_led_init_generic; |
Bruce Allan | dbf80dc | 2011-04-16 00:34:40 +0000 | [diff] [blame] | 584 | /* blink LED */ |
| 585 | mac->ops.blink_led = e1000e_blink_led_generic; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 586 | /* setup LED */ |
| 587 | mac->ops.setup_led = e1000e_setup_led_generic; |
| 588 | /* cleanup LED */ |
| 589 | mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; |
| 590 | /* turn on/off LED */ |
| 591 | mac->ops.led_on = e1000_led_on_ich8lan; |
| 592 | mac->ops.led_off = e1000_led_off_ich8lan; |
| 593 | break; |
| 594 | case e1000_pchlan: |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 595 | case e1000_pch2lan: |
Bruce Allan | eb7700d | 2010-06-16 13:27:05 +0000 | [diff] [blame] | 596 | /* check management mode */ |
| 597 | mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 598 | /* ID LED init */ |
| 599 | mac->ops.id_led_init = e1000_id_led_init_pchlan; |
| 600 | /* setup LED */ |
| 601 | mac->ops.setup_led = e1000_setup_led_pchlan; |
| 602 | /* cleanup LED */ |
| 603 | mac->ops.cleanup_led = e1000_cleanup_led_pchlan; |
| 604 | /* turn on/off LED */ |
| 605 | mac->ops.led_on = e1000_led_on_pchlan; |
| 606 | mac->ops.led_off = e1000_led_off_pchlan; |
| 607 | break; |
| 608 | default: |
| 609 | break; |
| 610 | } |
| 611 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 612 | /* Enable PCS Lock-loss workaround for ICH8 */ |
| 613 | if (mac->type == e1000_ich8lan) |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 614 | e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 615 | |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 616 | /* Gate automatic PHY configuration by hardware on managed 82579 */ |
| 617 | if ((mac->type == e1000_pch2lan) && |
| 618 | (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) |
| 619 | e1000_gate_hw_phy_config_ich8lan(hw, true); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 620 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 621 | return 0; |
| 622 | } |
| 623 | |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 624 | /** |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 625 | * e1000_set_eee_pchlan - Enable/disable EEE support |
| 626 | * @hw: pointer to the HW structure |
| 627 | * |
| 628 | * Enable/disable EEE based on setting in dev_spec structure. The bits in |
| 629 | * the LPI Control register will remain set only if/when link is up. |
| 630 | **/ |
| 631 | static s32 e1000_set_eee_pchlan(struct e1000_hw *hw) |
| 632 | { |
| 633 | s32 ret_val = 0; |
| 634 | u16 phy_reg; |
| 635 | |
| 636 | if (hw->phy.type != e1000_phy_82579) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 637 | return 0; |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 638 | |
| 639 | ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg); |
| 640 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 641 | return ret_val; |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 642 | |
| 643 | if (hw->dev_spec.ich8lan.eee_disable) |
| 644 | phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; |
| 645 | else |
| 646 | phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; |
| 647 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 648 | return e1e_wphy(hw, I82579_LPI_CTRL, phy_reg); |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 649 | } |
| 650 | |
| 651 | /** |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 652 | * e1000_check_for_copper_link_ich8lan - Check for link (Copper) |
| 653 | * @hw: pointer to the HW structure |
| 654 | * |
| 655 | * Checks to see of the link status of the hardware has changed. If a |
| 656 | * change in link status has been detected, then we read the PHY registers |
| 657 | * to get the current speed/duplex if link exists. |
| 658 | **/ |
| 659 | static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) |
| 660 | { |
| 661 | struct e1000_mac_info *mac = &hw->mac; |
| 662 | s32 ret_val; |
| 663 | bool link; |
Bruce Allan | 1d2101a7 | 2011-07-22 06:21:56 +0000 | [diff] [blame] | 664 | u16 phy_reg; |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 665 | |
| 666 | /* |
| 667 | * We only want to go out to the PHY registers to see if Auto-Neg |
| 668 | * has completed and/or if our link status has changed. The |
| 669 | * get_link_status flag is set upon receiving a Link Status |
| 670 | * Change or Rx Sequence Error interrupt. |
| 671 | */ |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 672 | if (!mac->get_link_status) |
| 673 | return 0; |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 674 | |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 675 | /* |
| 676 | * First we want to see if the MII Status Register reports |
| 677 | * link. If so, then we want to get the current speed/duplex |
| 678 | * of the PHY. |
| 679 | */ |
| 680 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
| 681 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 682 | return ret_val; |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 683 | |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 684 | if (hw->mac.type == e1000_pchlan) { |
| 685 | ret_val = e1000_k1_gig_workaround_hv(hw, link); |
| 686 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 687 | return ret_val; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 688 | } |
| 689 | |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 690 | if (!link) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 691 | return 0; /* No link detected */ |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 692 | |
| 693 | mac->get_link_status = false; |
| 694 | |
Bruce Allan | 1d2101a7 | 2011-07-22 06:21:56 +0000 | [diff] [blame] | 695 | switch (hw->mac.type) { |
| 696 | case e1000_pch2lan: |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 697 | ret_val = e1000_k1_workaround_lv(hw); |
| 698 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 699 | return ret_val; |
Bruce Allan | 1d2101a7 | 2011-07-22 06:21:56 +0000 | [diff] [blame] | 700 | /* fall-thru */ |
| 701 | case e1000_pchlan: |
| 702 | if (hw->phy.type == e1000_phy_82578) { |
| 703 | ret_val = e1000_link_stall_workaround_hv(hw); |
| 704 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 705 | return ret_val; |
Bruce Allan | 1d2101a7 | 2011-07-22 06:21:56 +0000 | [diff] [blame] | 706 | } |
| 707 | |
| 708 | /* |
| 709 | * Workaround for PCHx parts in half-duplex: |
| 710 | * Set the number of preambles removed from the packet |
| 711 | * when it is passed from the PHY to the MAC to prevent |
| 712 | * the MAC from misinterpreting the packet type. |
| 713 | */ |
| 714 | e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); |
| 715 | phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; |
| 716 | |
| 717 | if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) |
| 718 | phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); |
| 719 | |
| 720 | e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); |
| 721 | break; |
| 722 | default: |
| 723 | break; |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 724 | } |
| 725 | |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 726 | /* |
| 727 | * Check if there was DownShift, must be checked |
| 728 | * immediately after link-up |
| 729 | */ |
| 730 | e1000e_check_downshift(hw); |
| 731 | |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 732 | /* Enable/Disable EEE after link up */ |
| 733 | ret_val = e1000_set_eee_pchlan(hw); |
| 734 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 735 | return ret_val; |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 736 | |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 737 | /* |
| 738 | * If we are forcing speed/duplex, then we simply return since |
| 739 | * we have already determined whether we have link or not. |
| 740 | */ |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 741 | if (!mac->autoneg) |
| 742 | return -E1000_ERR_CONFIG; |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 743 | |
| 744 | /* |
| 745 | * Auto-Neg is enabled. Auto Speed Detection takes care |
| 746 | * of MAC speed/duplex configuration. So we only need to |
| 747 | * configure Collision Distance in the MAC. |
| 748 | */ |
Bruce Allan | 57cde76 | 2012-02-22 09:02:58 +0000 | [diff] [blame] | 749 | mac->ops.config_collision_dist(hw); |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 750 | |
| 751 | /* |
| 752 | * Configure Flow Control now that Auto-Neg has completed. |
| 753 | * First, we need to restore the desired flow control |
| 754 | * settings because we may have had to re-autoneg with a |
| 755 | * different link partner. |
| 756 | */ |
| 757 | ret_val = e1000e_config_fc_after_link_up(hw); |
| 758 | if (ret_val) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 759 | e_dbg("Error configuring flow control\n"); |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 760 | |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 761 | return ret_val; |
| 762 | } |
| 763 | |
Jeff Kirsher | 69e3fd8 | 2008-04-02 13:48:18 -0700 | [diff] [blame] | 764 | static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 765 | { |
| 766 | struct e1000_hw *hw = &adapter->hw; |
| 767 | s32 rc; |
| 768 | |
Bruce Allan | ec34c17 | 2012-02-01 10:53:05 +0000 | [diff] [blame] | 769 | rc = e1000_init_mac_params_ich8lan(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 770 | if (rc) |
| 771 | return rc; |
| 772 | |
| 773 | rc = e1000_init_nvm_params_ich8lan(hw); |
| 774 | if (rc) |
| 775 | return rc; |
| 776 | |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 777 | switch (hw->mac.type) { |
| 778 | case e1000_ich8lan: |
| 779 | case e1000_ich9lan: |
| 780 | case e1000_ich10lan: |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 781 | rc = e1000_init_phy_params_ich8lan(hw); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 782 | break; |
| 783 | case e1000_pchlan: |
| 784 | case e1000_pch2lan: |
| 785 | rc = e1000_init_phy_params_pchlan(hw); |
| 786 | break; |
| 787 | default: |
| 788 | break; |
| 789 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 790 | if (rc) |
| 791 | return rc; |
| 792 | |
Bruce Allan | 23e4f06 | 2011-02-25 07:44:51 +0000 | [diff] [blame] | 793 | /* |
| 794 | * Disable Jumbo Frame support on parts with Intel 10/100 PHY or |
| 795 | * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). |
| 796 | */ |
| 797 | if ((adapter->hw.phy.type == e1000_phy_ife) || |
| 798 | ((adapter->hw.mac.type >= e1000_pch2lan) && |
| 799 | (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { |
Bruce Allan | 2adc55c | 2009-06-02 11:28:58 +0000 | [diff] [blame] | 800 | adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; |
| 801 | adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN; |
Bruce Allan | dbf80dc | 2011-04-16 00:34:40 +0000 | [diff] [blame] | 802 | |
| 803 | hw->mac.ops.blink_led = NULL; |
Bruce Allan | 2adc55c | 2009-06-02 11:28:58 +0000 | [diff] [blame] | 804 | } |
| 805 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 806 | if ((adapter->hw.mac.type == e1000_ich8lan) && |
Bruce Allan | 462d599 | 2011-09-30 08:07:11 +0000 | [diff] [blame] | 807 | (adapter->hw.phy.type != e1000_phy_ife)) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 808 | adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; |
| 809 | |
Bruce Allan | c6e7f51 | 2011-07-29 05:53:02 +0000 | [diff] [blame] | 810 | /* Enable workaround for 82579 w/ ME enabled */ |
| 811 | if ((adapter->hw.mac.type == e1000_pch2lan) && |
| 812 | (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) |
| 813 | adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; |
| 814 | |
Bruce Allan | 5a86f28 | 2010-06-29 18:13:13 +0000 | [diff] [blame] | 815 | /* Disable EEE by default until IEEE802.3az spec is finalized */ |
| 816 | if (adapter->flags2 & FLAG2_HAS_EEE) |
| 817 | adapter->hw.dev_spec.ich8lan.eee_disable = true; |
| 818 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 819 | return 0; |
| 820 | } |
| 821 | |
Thomas Gleixner | 717d438 | 2008-10-02 16:33:40 -0700 | [diff] [blame] | 822 | static DEFINE_MUTEX(nvm_mutex); |
Thomas Gleixner | 717d438 | 2008-10-02 16:33:40 -0700 | [diff] [blame] | 823 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 824 | /** |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 825 | * e1000_acquire_nvm_ich8lan - Acquire NVM mutex |
| 826 | * @hw: pointer to the HW structure |
| 827 | * |
| 828 | * Acquires the mutex for performing NVM operations. |
| 829 | **/ |
| 830 | static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) |
| 831 | { |
| 832 | mutex_lock(&nvm_mutex); |
| 833 | |
| 834 | return 0; |
| 835 | } |
| 836 | |
| 837 | /** |
| 838 | * e1000_release_nvm_ich8lan - Release NVM mutex |
| 839 | * @hw: pointer to the HW structure |
| 840 | * |
| 841 | * Releases the mutex used while performing NVM operations. |
| 842 | **/ |
| 843 | static void e1000_release_nvm_ich8lan(struct e1000_hw *hw) |
| 844 | { |
| 845 | mutex_unlock(&nvm_mutex); |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 846 | } |
| 847 | |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 848 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 849 | * e1000_acquire_swflag_ich8lan - Acquire software control flag |
| 850 | * @hw: pointer to the HW structure |
| 851 | * |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 852 | * Acquires the software control flag for performing PHY and select |
| 853 | * MAC CSR accesses. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 854 | **/ |
| 855 | static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) |
| 856 | { |
Bruce Allan | 373a88d | 2009-08-07 07:41:37 +0000 | [diff] [blame] | 857 | u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; |
| 858 | s32 ret_val = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 859 | |
Bruce Allan | a90b412 | 2011-10-07 03:50:38 +0000 | [diff] [blame] | 860 | if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, |
| 861 | &hw->adapter->state)) { |
Bruce Allan | 34c9ef8 | 2011-10-21 04:33:47 +0000 | [diff] [blame] | 862 | e_dbg("contention for Phy access\n"); |
Bruce Allan | a90b412 | 2011-10-07 03:50:38 +0000 | [diff] [blame] | 863 | return -E1000_ERR_PHY; |
| 864 | } |
Thomas Gleixner | 717d438 | 2008-10-02 16:33:40 -0700 | [diff] [blame] | 865 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 866 | while (timeout) { |
| 867 | extcnf_ctrl = er32(EXTCNF_CTRL); |
Bruce Allan | 373a88d | 2009-08-07 07:41:37 +0000 | [diff] [blame] | 868 | if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) |
| 869 | break; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 870 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 871 | mdelay(1); |
| 872 | timeout--; |
| 873 | } |
| 874 | |
| 875 | if (!timeout) { |
Bruce Allan | a90b412 | 2011-10-07 03:50:38 +0000 | [diff] [blame] | 876 | e_dbg("SW has already locked the resource.\n"); |
Bruce Allan | 373a88d | 2009-08-07 07:41:37 +0000 | [diff] [blame] | 877 | ret_val = -E1000_ERR_CONFIG; |
| 878 | goto out; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 879 | } |
| 880 | |
Bruce Allan | 53ac5a8 | 2009-10-26 11:23:06 +0000 | [diff] [blame] | 881 | timeout = SW_FLAG_TIMEOUT; |
Bruce Allan | 373a88d | 2009-08-07 07:41:37 +0000 | [diff] [blame] | 882 | |
| 883 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; |
| 884 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
| 885 | |
| 886 | while (timeout) { |
| 887 | extcnf_ctrl = er32(EXTCNF_CTRL); |
| 888 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) |
| 889 | break; |
| 890 | |
| 891 | mdelay(1); |
| 892 | timeout--; |
| 893 | } |
| 894 | |
| 895 | if (!timeout) { |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 896 | e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", |
Bruce Allan | a90b412 | 2011-10-07 03:50:38 +0000 | [diff] [blame] | 897 | er32(FWSM), extcnf_ctrl); |
Bruce Allan | 373a88d | 2009-08-07 07:41:37 +0000 | [diff] [blame] | 898 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
| 899 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
| 900 | ret_val = -E1000_ERR_CONFIG; |
| 901 | goto out; |
| 902 | } |
| 903 | |
| 904 | out: |
| 905 | if (ret_val) |
Bruce Allan | a90b412 | 2011-10-07 03:50:38 +0000 | [diff] [blame] | 906 | clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); |
Bruce Allan | 373a88d | 2009-08-07 07:41:37 +0000 | [diff] [blame] | 907 | |
| 908 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 909 | } |
| 910 | |
| 911 | /** |
| 912 | * e1000_release_swflag_ich8lan - Release software control flag |
| 913 | * @hw: pointer to the HW structure |
| 914 | * |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 915 | * Releases the software control flag for performing PHY and select |
| 916 | * MAC CSR accesses. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 917 | **/ |
| 918 | static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) |
| 919 | { |
| 920 | u32 extcnf_ctrl; |
| 921 | |
| 922 | extcnf_ctrl = er32(EXTCNF_CTRL); |
Bruce Allan | c5caf48 | 2011-05-13 07:19:53 +0000 | [diff] [blame] | 923 | |
| 924 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { |
| 925 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
| 926 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
| 927 | } else { |
| 928 | e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); |
| 929 | } |
Thomas Gleixner | 717d438 | 2008-10-02 16:33:40 -0700 | [diff] [blame] | 930 | |
Bruce Allan | a90b412 | 2011-10-07 03:50:38 +0000 | [diff] [blame] | 931 | clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 932 | } |
| 933 | |
| 934 | /** |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 935 | * e1000_check_mng_mode_ich8lan - Checks management mode |
| 936 | * @hw: pointer to the HW structure |
| 937 | * |
Bruce Allan | eb7700d | 2010-06-16 13:27:05 +0000 | [diff] [blame] | 938 | * This checks if the adapter has any manageability enabled. |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 939 | * This is a function pointer entry point only called by read/write |
| 940 | * routines for the PHY and NVM parts. |
| 941 | **/ |
| 942 | static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) |
| 943 | { |
Bruce Allan | a708dd8 | 2009-11-20 23:28:37 +0000 | [diff] [blame] | 944 | u32 fwsm; |
| 945 | |
| 946 | fwsm = er32(FWSM); |
Bruce Allan | eb7700d | 2010-06-16 13:27:05 +0000 | [diff] [blame] | 947 | return (fwsm & E1000_ICH_FWSM_FW_VALID) && |
| 948 | ((fwsm & E1000_FWSM_MODE_MASK) == |
| 949 | (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); |
| 950 | } |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 951 | |
Bruce Allan | eb7700d | 2010-06-16 13:27:05 +0000 | [diff] [blame] | 952 | /** |
| 953 | * e1000_check_mng_mode_pchlan - Checks management mode |
| 954 | * @hw: pointer to the HW structure |
| 955 | * |
| 956 | * This checks if the adapter has iAMT enabled. |
| 957 | * This is a function pointer entry point only called by read/write |
| 958 | * routines for the PHY and NVM parts. |
| 959 | **/ |
| 960 | static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) |
| 961 | { |
| 962 | u32 fwsm; |
| 963 | |
| 964 | fwsm = er32(FWSM); |
| 965 | return (fwsm & E1000_ICH_FWSM_FW_VALID) && |
| 966 | (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); |
Bruce Allan | 4662e82 | 2008-08-26 18:37:06 -0700 | [diff] [blame] | 967 | } |
| 968 | |
| 969 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 970 | * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked |
| 971 | * @hw: pointer to the HW structure |
| 972 | * |
| 973 | * Checks if firmware is blocking the reset of the PHY. |
| 974 | * This is a function pointer entry point only called by |
| 975 | * reset routines. |
| 976 | **/ |
| 977 | static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) |
| 978 | { |
| 979 | u32 fwsm; |
| 980 | |
| 981 | fwsm = er32(FWSM); |
| 982 | |
| 983 | return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET; |
| 984 | } |
| 985 | |
| 986 | /** |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 987 | * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states |
| 988 | * @hw: pointer to the HW structure |
| 989 | * |
| 990 | * Assumes semaphore already acquired. |
| 991 | * |
| 992 | **/ |
| 993 | static s32 e1000_write_smbus_addr(struct e1000_hw *hw) |
| 994 | { |
| 995 | u16 phy_data; |
| 996 | u32 strap = er32(STRAP); |
| 997 | s32 ret_val = 0; |
| 998 | |
| 999 | strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; |
| 1000 | |
| 1001 | ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); |
| 1002 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1003 | return ret_val; |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 1004 | |
| 1005 | phy_data &= ~HV_SMB_ADDR_MASK; |
| 1006 | phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); |
| 1007 | phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 1008 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1009 | return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 1010 | } |
| 1011 | |
| 1012 | /** |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1013 | * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration |
| 1014 | * @hw: pointer to the HW structure |
| 1015 | * |
| 1016 | * SW should configure the LCD from the NVM extended configuration region |
| 1017 | * as a workaround for certain parts. |
| 1018 | **/ |
| 1019 | static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) |
| 1020 | { |
| 1021 | struct e1000_phy_info *phy = &hw->phy; |
| 1022 | u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 1023 | s32 ret_val = 0; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1024 | u16 word_addr, reg_data, reg_addr, phy_page = 0; |
| 1025 | |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1026 | /* |
| 1027 | * Initialize the PHY from the NVM on ICH platforms. This |
| 1028 | * is needed due to an issue where the NVM configuration is |
| 1029 | * not properly autoloaded after power transitions. |
| 1030 | * Therefore, after each PHY reset, we will load the |
| 1031 | * configuration data out of the NVM manually. |
| 1032 | */ |
Bruce Allan | 3f0c16e | 2010-06-16 13:26:17 +0000 | [diff] [blame] | 1033 | switch (hw->mac.type) { |
| 1034 | case e1000_ich8lan: |
| 1035 | if (phy->type != e1000_phy_igp_3) |
| 1036 | return ret_val; |
| 1037 | |
Bruce Allan | 5f3eed6 | 2010-09-22 17:15:54 +0000 | [diff] [blame] | 1038 | if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || |
| 1039 | (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { |
Bruce Allan | 3f0c16e | 2010-06-16 13:26:17 +0000 | [diff] [blame] | 1040 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; |
| 1041 | break; |
| 1042 | } |
| 1043 | /* Fall-thru */ |
| 1044 | case e1000_pchlan: |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1045 | case e1000_pch2lan: |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 1046 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; |
Bruce Allan | 3f0c16e | 2010-06-16 13:26:17 +0000 | [diff] [blame] | 1047 | break; |
| 1048 | default: |
| 1049 | return ret_val; |
| 1050 | } |
| 1051 | |
| 1052 | ret_val = hw->phy.ops.acquire(hw); |
| 1053 | if (ret_val) |
| 1054 | return ret_val; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1055 | |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 1056 | data = er32(FEXTNVM); |
| 1057 | if (!(data & sw_cfg_mask)) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 1058 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1059 | |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 1060 | /* |
| 1061 | * Make sure HW does not configure LCD from PHY |
| 1062 | * extended configuration before SW configuration |
| 1063 | */ |
| 1064 | data = er32(EXTCNF_CTRL); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1065 | if (!(hw->mac.type == e1000_pch2lan)) { |
| 1066 | if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 1067 | goto release; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1068 | } |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1069 | |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 1070 | cnf_size = er32(EXTCNF_SIZE); |
| 1071 | cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; |
| 1072 | cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; |
| 1073 | if (!cnf_size) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 1074 | goto release; |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 1075 | |
| 1076 | cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; |
| 1077 | cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; |
| 1078 | |
Bruce Allan | 87fb741 | 2010-09-22 17:15:33 +0000 | [diff] [blame] | 1079 | if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) && |
| 1080 | (hw->mac.type == e1000_pchlan)) || |
| 1081 | (hw->mac.type == e1000_pch2lan)) { |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1082 | /* |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 1083 | * HW configures the SMBus address and LEDs when the |
| 1084 | * OEM and LCD Write Enable bits are set in the NVM. |
| 1085 | * When both NVM bits are cleared, SW will configure |
| 1086 | * them instead. |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1087 | */ |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 1088 | ret_val = e1000_write_smbus_addr(hw); |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 1089 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 1090 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1091 | |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 1092 | data = er32(LEDCTL); |
| 1093 | ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, |
| 1094 | (u16)data); |
| 1095 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 1096 | goto release; |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 1097 | } |
| 1098 | |
| 1099 | /* Configure LCD from extended configuration region. */ |
| 1100 | |
| 1101 | /* cnf_base_addr is in DWORD */ |
| 1102 | word_addr = (u16)(cnf_base_addr << 1); |
| 1103 | |
| 1104 | for (i = 0; i < cnf_size; i++) { |
| 1105 | ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, |
| 1106 | ®_data); |
| 1107 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 1108 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1109 | |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 1110 | ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), |
| 1111 | 1, ®_addr); |
| 1112 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 1113 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1114 | |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 1115 | /* Save off the PHY page for future writes. */ |
| 1116 | if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { |
| 1117 | phy_page = reg_data; |
| 1118 | continue; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1119 | } |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1120 | |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 1121 | reg_addr &= PHY_REG_MASK; |
| 1122 | reg_addr |= phy_page; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1123 | |
Bruce Allan | 8b802a7 | 2010-05-10 15:01:10 +0000 | [diff] [blame] | 1124 | ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, |
| 1125 | reg_data); |
| 1126 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 1127 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1128 | } |
| 1129 | |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 1130 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 1131 | hw->phy.ops.release(hw); |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1132 | return ret_val; |
| 1133 | } |
| 1134 | |
| 1135 | /** |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1136 | * e1000_k1_gig_workaround_hv - K1 Si workaround |
| 1137 | * @hw: pointer to the HW structure |
| 1138 | * @link: link up bool flag |
| 1139 | * |
| 1140 | * If K1 is enabled for 1Gbps, the MAC might stall when transitioning |
| 1141 | * from a lower speed. This workaround disables K1 whenever link is at 1Gig |
| 1142 | * If link is down, the function will restore the default K1 setting located |
| 1143 | * in the NVM. |
| 1144 | **/ |
| 1145 | static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) |
| 1146 | { |
| 1147 | s32 ret_val = 0; |
| 1148 | u16 status_reg = 0; |
| 1149 | bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; |
| 1150 | |
| 1151 | if (hw->mac.type != e1000_pchlan) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1152 | return 0; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1153 | |
| 1154 | /* Wrap the whole flow with the sw flag */ |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 1155 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1156 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1157 | return ret_val; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1158 | |
| 1159 | /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ |
| 1160 | if (link) { |
| 1161 | if (hw->phy.type == e1000_phy_82578) { |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 1162 | ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS, |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1163 | &status_reg); |
| 1164 | if (ret_val) |
| 1165 | goto release; |
| 1166 | |
| 1167 | status_reg &= BM_CS_STATUS_LINK_UP | |
| 1168 | BM_CS_STATUS_RESOLVED | |
| 1169 | BM_CS_STATUS_SPEED_MASK; |
| 1170 | |
| 1171 | if (status_reg == (BM_CS_STATUS_LINK_UP | |
| 1172 | BM_CS_STATUS_RESOLVED | |
| 1173 | BM_CS_STATUS_SPEED_1000)) |
| 1174 | k1_enable = false; |
| 1175 | } |
| 1176 | |
| 1177 | if (hw->phy.type == e1000_phy_82577) { |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 1178 | ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS, |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1179 | &status_reg); |
| 1180 | if (ret_val) |
| 1181 | goto release; |
| 1182 | |
| 1183 | status_reg &= HV_M_STATUS_LINK_UP | |
| 1184 | HV_M_STATUS_AUTONEG_COMPLETE | |
| 1185 | HV_M_STATUS_SPEED_MASK; |
| 1186 | |
| 1187 | if (status_reg == (HV_M_STATUS_LINK_UP | |
| 1188 | HV_M_STATUS_AUTONEG_COMPLETE | |
| 1189 | HV_M_STATUS_SPEED_1000)) |
| 1190 | k1_enable = false; |
| 1191 | } |
| 1192 | |
| 1193 | /* Link stall fix for link up */ |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 1194 | ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1195 | 0x0100); |
| 1196 | if (ret_val) |
| 1197 | goto release; |
| 1198 | |
| 1199 | } else { |
| 1200 | /* Link stall fix for link down */ |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 1201 | ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1202 | 0x4100); |
| 1203 | if (ret_val) |
| 1204 | goto release; |
| 1205 | } |
| 1206 | |
| 1207 | ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); |
| 1208 | |
| 1209 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 1210 | hw->phy.ops.release(hw); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1211 | |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1212 | return ret_val; |
| 1213 | } |
| 1214 | |
| 1215 | /** |
| 1216 | * e1000_configure_k1_ich8lan - Configure K1 power state |
| 1217 | * @hw: pointer to the HW structure |
| 1218 | * @enable: K1 state to configure |
| 1219 | * |
| 1220 | * Configure the K1 power state based on the provided parameter. |
| 1221 | * Assumes semaphore already acquired. |
| 1222 | * |
| 1223 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
| 1224 | **/ |
Bruce Allan | bb436b2 | 2009-11-20 23:24:11 +0000 | [diff] [blame] | 1225 | s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1226 | { |
| 1227 | s32 ret_val = 0; |
| 1228 | u32 ctrl_reg = 0; |
| 1229 | u32 ctrl_ext = 0; |
| 1230 | u32 reg = 0; |
| 1231 | u16 kmrn_reg = 0; |
| 1232 | |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1233 | ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, |
| 1234 | &kmrn_reg); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1235 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1236 | return ret_val; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1237 | |
| 1238 | if (k1_enable) |
| 1239 | kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; |
| 1240 | else |
| 1241 | kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; |
| 1242 | |
Bruce Allan | 3d3a167 | 2012-02-23 03:13:18 +0000 | [diff] [blame] | 1243 | ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, |
| 1244 | kmrn_reg); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1245 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1246 | return ret_val; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1247 | |
| 1248 | udelay(20); |
| 1249 | ctrl_ext = er32(CTRL_EXT); |
| 1250 | ctrl_reg = er32(CTRL); |
| 1251 | |
| 1252 | reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
| 1253 | reg |= E1000_CTRL_FRCSPD; |
| 1254 | ew32(CTRL, reg); |
| 1255 | |
| 1256 | ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); |
Jesse Brandeburg | 945a515 | 2011-07-20 00:56:21 +0000 | [diff] [blame] | 1257 | e1e_flush(); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1258 | udelay(20); |
| 1259 | ew32(CTRL, ctrl_reg); |
| 1260 | ew32(CTRL_EXT, ctrl_ext); |
Jesse Brandeburg | 945a515 | 2011-07-20 00:56:21 +0000 | [diff] [blame] | 1261 | e1e_flush(); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1262 | udelay(20); |
| 1263 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1264 | return 0; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1265 | } |
| 1266 | |
| 1267 | /** |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1268 | * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration |
| 1269 | * @hw: pointer to the HW structure |
| 1270 | * @d0_state: boolean if entering d0 or d3 device state |
| 1271 | * |
| 1272 | * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are |
| 1273 | * collectively called OEM bits. The OEM Write Enable bit and SW Config bit |
| 1274 | * in NVM determines whether HW should configure LPLU and Gbe Disable. |
| 1275 | **/ |
| 1276 | static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) |
| 1277 | { |
| 1278 | s32 ret_val = 0; |
| 1279 | u32 mac_reg; |
| 1280 | u16 oem_reg; |
| 1281 | |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1282 | if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan)) |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1283 | return ret_val; |
| 1284 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 1285 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1286 | if (ret_val) |
| 1287 | return ret_val; |
| 1288 | |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1289 | if (!(hw->mac.type == e1000_pch2lan)) { |
| 1290 | mac_reg = er32(EXTCNF_CTRL); |
| 1291 | if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 1292 | goto release; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1293 | } |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1294 | |
| 1295 | mac_reg = er32(FEXTNVM); |
| 1296 | if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 1297 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1298 | |
| 1299 | mac_reg = er32(PHY_CTRL); |
| 1300 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 1301 | ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1302 | if (ret_val) |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 1303 | goto release; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1304 | |
| 1305 | oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); |
| 1306 | |
| 1307 | if (d0_state) { |
| 1308 | if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) |
| 1309 | oem_reg |= HV_OEM_BITS_GBE_DIS; |
| 1310 | |
| 1311 | if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) |
| 1312 | oem_reg |= HV_OEM_BITS_LPLU; |
Bruce Allan | 03299e4 | 2011-09-30 08:07:05 +0000 | [diff] [blame] | 1313 | |
| 1314 | /* Set Restart auto-neg to activate the bits */ |
Bruce Allan | 44abd5c | 2012-02-22 09:02:37 +0000 | [diff] [blame] | 1315 | if (!hw->phy.ops.check_reset_block(hw)) |
Bruce Allan | 03299e4 | 2011-09-30 08:07:05 +0000 | [diff] [blame] | 1316 | oem_reg |= HV_OEM_BITS_RESTART_AN; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1317 | } else { |
Bruce Allan | 03299e4 | 2011-09-30 08:07:05 +0000 | [diff] [blame] | 1318 | if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | |
| 1319 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1320 | oem_reg |= HV_OEM_BITS_GBE_DIS; |
| 1321 | |
Bruce Allan | 03299e4 | 2011-09-30 08:07:05 +0000 | [diff] [blame] | 1322 | if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | |
| 1323 | E1000_PHY_CTRL_NOND0A_LPLU)) |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1324 | oem_reg |= HV_OEM_BITS_LPLU; |
| 1325 | } |
Bruce Allan | 03299e4 | 2011-09-30 08:07:05 +0000 | [diff] [blame] | 1326 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 1327 | ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1328 | |
Bruce Allan | 75ce153 | 2012-02-08 02:54:48 +0000 | [diff] [blame] | 1329 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 1330 | hw->phy.ops.release(hw); |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1331 | |
| 1332 | return ret_val; |
| 1333 | } |
| 1334 | |
| 1335 | |
| 1336 | /** |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 1337 | * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode |
| 1338 | * @hw: pointer to the HW structure |
| 1339 | **/ |
| 1340 | static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) |
| 1341 | { |
| 1342 | s32 ret_val; |
| 1343 | u16 data; |
| 1344 | |
| 1345 | ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); |
| 1346 | if (ret_val) |
| 1347 | return ret_val; |
| 1348 | |
| 1349 | data |= HV_KMRN_MDIO_SLOW; |
| 1350 | |
| 1351 | ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); |
| 1352 | |
| 1353 | return ret_val; |
| 1354 | } |
| 1355 | |
| 1356 | /** |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1357 | * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be |
| 1358 | * done after every PHY reset. |
| 1359 | **/ |
| 1360 | static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) |
| 1361 | { |
| 1362 | s32 ret_val = 0; |
Bruce Allan | baf86c9 | 2010-01-13 01:53:08 +0000 | [diff] [blame] | 1363 | u16 phy_data; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1364 | |
| 1365 | if (hw->mac.type != e1000_pchlan) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1366 | return 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1367 | |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 1368 | /* Set MDIO slow mode before any other MDIO access */ |
| 1369 | if (hw->phy.type == e1000_phy_82577) { |
| 1370 | ret_val = e1000_set_mdio_slow_mode_hv(hw); |
| 1371 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1372 | return ret_val; |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 1373 | } |
| 1374 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1375 | if (((hw->phy.type == e1000_phy_82577) && |
| 1376 | ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || |
| 1377 | ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { |
| 1378 | /* Disable generation of early preamble */ |
| 1379 | ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); |
| 1380 | if (ret_val) |
| 1381 | return ret_val; |
| 1382 | |
| 1383 | /* Preamble tuning for SSC */ |
Bruce Allan | 1d2101a7 | 2011-07-22 06:21:56 +0000 | [diff] [blame] | 1384 | ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1385 | if (ret_val) |
| 1386 | return ret_val; |
| 1387 | } |
| 1388 | |
| 1389 | if (hw->phy.type == e1000_phy_82578) { |
| 1390 | /* |
| 1391 | * Return registers to default by doing a soft reset then |
| 1392 | * writing 0x3140 to the control register. |
| 1393 | */ |
| 1394 | if (hw->phy.revision < 2) { |
| 1395 | e1000e_phy_sw_reset(hw); |
| 1396 | ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140); |
| 1397 | } |
| 1398 | } |
| 1399 | |
| 1400 | /* Select page 0 */ |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 1401 | ret_val = hw->phy.ops.acquire(hw); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1402 | if (ret_val) |
| 1403 | return ret_val; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1404 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1405 | hw->phy.addr = 1; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1406 | ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); |
Bruce Allan | baf86c9 | 2010-01-13 01:53:08 +0000 | [diff] [blame] | 1407 | hw->phy.ops.release(hw); |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1408 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1409 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1410 | |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1411 | /* |
| 1412 | * Configure the K1 Si workaround during phy reset assuming there is |
| 1413 | * link so that it disables K1 if link is in 1Gbps. |
| 1414 | */ |
| 1415 | ret_val = e1000_k1_gig_workaround_hv(hw, true); |
Bruce Allan | baf86c9 | 2010-01-13 01:53:08 +0000 | [diff] [blame] | 1416 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1417 | return ret_val; |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 1418 | |
Bruce Allan | baf86c9 | 2010-01-13 01:53:08 +0000 | [diff] [blame] | 1419 | /* Workaround for link disconnects on a busy hub in half duplex */ |
| 1420 | ret_val = hw->phy.ops.acquire(hw); |
| 1421 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1422 | return ret_val; |
Bruce Allan | 3ebfc7c | 2011-05-13 07:20:14 +0000 | [diff] [blame] | 1423 | ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data); |
Bruce Allan | baf86c9 | 2010-01-13 01:53:08 +0000 | [diff] [blame] | 1424 | if (ret_val) |
| 1425 | goto release; |
Bruce Allan | 3ebfc7c | 2011-05-13 07:20:14 +0000 | [diff] [blame] | 1426 | ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG, |
| 1427 | phy_data & 0x00FF); |
Bruce Allan | baf86c9 | 2010-01-13 01:53:08 +0000 | [diff] [blame] | 1428 | release: |
| 1429 | hw->phy.ops.release(hw); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1430 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1431 | return ret_val; |
| 1432 | } |
| 1433 | |
| 1434 | /** |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1435 | * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY |
| 1436 | * @hw: pointer to the HW structure |
| 1437 | **/ |
| 1438 | void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) |
| 1439 | { |
| 1440 | u32 mac_reg; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 1441 | u16 i, phy_reg = 0; |
| 1442 | s32 ret_val; |
| 1443 | |
| 1444 | ret_val = hw->phy.ops.acquire(hw); |
| 1445 | if (ret_val) |
| 1446 | return; |
| 1447 | ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
| 1448 | if (ret_val) |
| 1449 | goto release; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1450 | |
| 1451 | /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */ |
| 1452 | for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { |
| 1453 | mac_reg = er32(RAL(i)); |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 1454 | hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), |
| 1455 | (u16)(mac_reg & 0xFFFF)); |
| 1456 | hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), |
| 1457 | (u16)((mac_reg >> 16) & 0xFFFF)); |
| 1458 | |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1459 | mac_reg = er32(RAH(i)); |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 1460 | hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), |
| 1461 | (u16)(mac_reg & 0xFFFF)); |
| 1462 | hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), |
| 1463 | (u16)((mac_reg & E1000_RAH_AV) |
| 1464 | >> 16)); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1465 | } |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 1466 | |
| 1467 | e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
| 1468 | |
| 1469 | release: |
| 1470 | hw->phy.ops.release(hw); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1471 | } |
| 1472 | |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1473 | /** |
| 1474 | * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation |
| 1475 | * with 82579 PHY |
| 1476 | * @hw: pointer to the HW structure |
| 1477 | * @enable: flag to enable/disable workaround when enabling/disabling jumbos |
| 1478 | **/ |
| 1479 | s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) |
| 1480 | { |
| 1481 | s32 ret_val = 0; |
| 1482 | u16 phy_reg, data; |
| 1483 | u32 mac_reg; |
| 1484 | u16 i; |
| 1485 | |
| 1486 | if (hw->mac.type != e1000_pch2lan) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1487 | return 0; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1488 | |
| 1489 | /* disable Rx path while enabling/disabling workaround */ |
| 1490 | e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); |
| 1491 | ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); |
| 1492 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1493 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1494 | |
| 1495 | if (enable) { |
| 1496 | /* |
| 1497 | * Write Rx addresses (rar_entry_count for RAL/H, +4 for |
| 1498 | * SHRAL/H) and initial CRC values to the MAC |
| 1499 | */ |
| 1500 | for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { |
| 1501 | u8 mac_addr[ETH_ALEN] = {0}; |
| 1502 | u32 addr_high, addr_low; |
| 1503 | |
| 1504 | addr_high = er32(RAH(i)); |
| 1505 | if (!(addr_high & E1000_RAH_AV)) |
| 1506 | continue; |
| 1507 | addr_low = er32(RAL(i)); |
| 1508 | mac_addr[0] = (addr_low & 0xFF); |
| 1509 | mac_addr[1] = ((addr_low >> 8) & 0xFF); |
| 1510 | mac_addr[2] = ((addr_low >> 16) & 0xFF); |
| 1511 | mac_addr[3] = ((addr_low >> 24) & 0xFF); |
| 1512 | mac_addr[4] = (addr_high & 0xFF); |
| 1513 | mac_addr[5] = ((addr_high >> 8) & 0xFF); |
| 1514 | |
Bruce Allan | fe46f58 | 2011-01-06 14:29:51 +0000 | [diff] [blame] | 1515 | ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1516 | } |
| 1517 | |
| 1518 | /* Write Rx addresses to the PHY */ |
| 1519 | e1000_copy_rx_addrs_to_phy_ich8lan(hw); |
| 1520 | |
| 1521 | /* Enable jumbo frame workaround in the MAC */ |
| 1522 | mac_reg = er32(FFLT_DBG); |
| 1523 | mac_reg &= ~(1 << 14); |
| 1524 | mac_reg |= (7 << 15); |
| 1525 | ew32(FFLT_DBG, mac_reg); |
| 1526 | |
| 1527 | mac_reg = er32(RCTL); |
| 1528 | mac_reg |= E1000_RCTL_SECRC; |
| 1529 | ew32(RCTL, mac_reg); |
| 1530 | |
| 1531 | ret_val = e1000e_read_kmrn_reg(hw, |
| 1532 | E1000_KMRNCTRLSTA_CTRL_OFFSET, |
| 1533 | &data); |
| 1534 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1535 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1536 | ret_val = e1000e_write_kmrn_reg(hw, |
| 1537 | E1000_KMRNCTRLSTA_CTRL_OFFSET, |
| 1538 | data | (1 << 0)); |
| 1539 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1540 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1541 | ret_val = e1000e_read_kmrn_reg(hw, |
| 1542 | E1000_KMRNCTRLSTA_HD_CTRL, |
| 1543 | &data); |
| 1544 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1545 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1546 | data &= ~(0xF << 8); |
| 1547 | data |= (0xB << 8); |
| 1548 | ret_val = e1000e_write_kmrn_reg(hw, |
| 1549 | E1000_KMRNCTRLSTA_HD_CTRL, |
| 1550 | data); |
| 1551 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1552 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1553 | |
| 1554 | /* Enable jumbo frame workaround in the PHY */ |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1555 | e1e_rphy(hw, PHY_REG(769, 23), &data); |
| 1556 | data &= ~(0x7F << 5); |
| 1557 | data |= (0x37 << 5); |
| 1558 | ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); |
| 1559 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1560 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1561 | e1e_rphy(hw, PHY_REG(769, 16), &data); |
| 1562 | data &= ~(1 << 13); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1563 | ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); |
| 1564 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1565 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1566 | e1e_rphy(hw, PHY_REG(776, 20), &data); |
| 1567 | data &= ~(0x3FF << 2); |
| 1568 | data |= (0x1A << 2); |
| 1569 | ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); |
| 1570 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1571 | return ret_val; |
Bruce Allan | b64e9dd | 2011-09-30 08:07:00 +0000 | [diff] [blame] | 1572 | ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1573 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1574 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1575 | e1e_rphy(hw, HV_PM_CTRL, &data); |
| 1576 | ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10)); |
| 1577 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1578 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1579 | } else { |
| 1580 | /* Write MAC register values back to h/w defaults */ |
| 1581 | mac_reg = er32(FFLT_DBG); |
| 1582 | mac_reg &= ~(0xF << 14); |
| 1583 | ew32(FFLT_DBG, mac_reg); |
| 1584 | |
| 1585 | mac_reg = er32(RCTL); |
| 1586 | mac_reg &= ~E1000_RCTL_SECRC; |
Bruce Allan | a1ce647 | 2010-09-22 17:16:40 +0000 | [diff] [blame] | 1587 | ew32(RCTL, mac_reg); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1588 | |
| 1589 | ret_val = e1000e_read_kmrn_reg(hw, |
| 1590 | E1000_KMRNCTRLSTA_CTRL_OFFSET, |
| 1591 | &data); |
| 1592 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1593 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1594 | ret_val = e1000e_write_kmrn_reg(hw, |
| 1595 | E1000_KMRNCTRLSTA_CTRL_OFFSET, |
| 1596 | data & ~(1 << 0)); |
| 1597 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1598 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1599 | ret_val = e1000e_read_kmrn_reg(hw, |
| 1600 | E1000_KMRNCTRLSTA_HD_CTRL, |
| 1601 | &data); |
| 1602 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1603 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1604 | data &= ~(0xF << 8); |
| 1605 | data |= (0xB << 8); |
| 1606 | ret_val = e1000e_write_kmrn_reg(hw, |
| 1607 | E1000_KMRNCTRLSTA_HD_CTRL, |
| 1608 | data); |
| 1609 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1610 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1611 | |
| 1612 | /* Write PHY register values back to h/w defaults */ |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1613 | e1e_rphy(hw, PHY_REG(769, 23), &data); |
| 1614 | data &= ~(0x7F << 5); |
| 1615 | ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); |
| 1616 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1617 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1618 | e1e_rphy(hw, PHY_REG(769, 16), &data); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1619 | data |= (1 << 13); |
| 1620 | ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); |
| 1621 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1622 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1623 | e1e_rphy(hw, PHY_REG(776, 20), &data); |
| 1624 | data &= ~(0x3FF << 2); |
| 1625 | data |= (0x8 << 2); |
| 1626 | ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); |
| 1627 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1628 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1629 | ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); |
| 1630 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1631 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1632 | e1e_rphy(hw, HV_PM_CTRL, &data); |
| 1633 | ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10)); |
| 1634 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1635 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1636 | } |
| 1637 | |
| 1638 | /* re-enable Rx path after enabling/disabling workaround */ |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1639 | return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14)); |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1640 | } |
| 1641 | |
| 1642 | /** |
| 1643 | * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be |
| 1644 | * done after every PHY reset. |
| 1645 | **/ |
| 1646 | static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) |
| 1647 | { |
| 1648 | s32 ret_val = 0; |
| 1649 | |
| 1650 | if (hw->mac.type != e1000_pch2lan) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1651 | return 0; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1652 | |
| 1653 | /* Set MDIO slow mode before any other MDIO access */ |
| 1654 | ret_val = e1000_set_mdio_slow_mode_hv(hw); |
| 1655 | |
Bruce Allan | 4d24136 | 2011-12-16 00:46:06 +0000 | [diff] [blame] | 1656 | ret_val = hw->phy.ops.acquire(hw); |
| 1657 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1658 | return ret_val; |
Bruce Allan | 4d24136 | 2011-12-16 00:46:06 +0000 | [diff] [blame] | 1659 | ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, |
| 1660 | I82579_MSE_THRESHOLD); |
| 1661 | if (ret_val) |
| 1662 | goto release; |
| 1663 | /* set MSE higher to enable link to stay up when noise is high */ |
| 1664 | ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0034); |
| 1665 | if (ret_val) |
| 1666 | goto release; |
| 1667 | ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, |
| 1668 | I82579_MSE_LINK_DOWN); |
| 1669 | if (ret_val) |
| 1670 | goto release; |
| 1671 | /* drop link after 5 times MSE threshold was reached */ |
| 1672 | ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0005); |
| 1673 | release: |
| 1674 | hw->phy.ops.release(hw); |
| 1675 | |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1676 | return ret_val; |
| 1677 | } |
| 1678 | |
| 1679 | /** |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 1680 | * e1000_k1_gig_workaround_lv - K1 Si workaround |
| 1681 | * @hw: pointer to the HW structure |
| 1682 | * |
| 1683 | * Workaround to set the K1 beacon duration for 82579 parts |
| 1684 | **/ |
| 1685 | static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) |
| 1686 | { |
| 1687 | s32 ret_val = 0; |
| 1688 | u16 status_reg = 0; |
| 1689 | u32 mac_reg; |
Bruce Allan | 0ed013e | 2011-07-29 05:52:56 +0000 | [diff] [blame] | 1690 | u16 phy_reg; |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 1691 | |
| 1692 | if (hw->mac.type != e1000_pch2lan) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1693 | return 0; |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 1694 | |
| 1695 | /* Set K1 beacon duration based on 1Gbps speed or otherwise */ |
| 1696 | ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); |
| 1697 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1698 | return ret_val; |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 1699 | |
| 1700 | if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) |
| 1701 | == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { |
| 1702 | mac_reg = er32(FEXTNVM4); |
| 1703 | mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; |
| 1704 | |
Bruce Allan | 0ed013e | 2011-07-29 05:52:56 +0000 | [diff] [blame] | 1705 | ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg); |
| 1706 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1707 | return ret_val; |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 1708 | |
Bruce Allan | 0ed013e | 2011-07-29 05:52:56 +0000 | [diff] [blame] | 1709 | if (status_reg & HV_M_STATUS_SPEED_1000) { |
| 1710 | mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; |
| 1711 | phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; |
| 1712 | } else { |
| 1713 | mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; |
| 1714 | phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; |
| 1715 | } |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 1716 | ew32(FEXTNVM4, mac_reg); |
Bruce Allan | 0ed013e | 2011-07-29 05:52:56 +0000 | [diff] [blame] | 1717 | ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg); |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 1718 | } |
| 1719 | |
Bruce Allan | 831bd2e | 2010-09-22 17:16:18 +0000 | [diff] [blame] | 1720 | return ret_val; |
| 1721 | } |
| 1722 | |
| 1723 | /** |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 1724 | * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware |
| 1725 | * @hw: pointer to the HW structure |
| 1726 | * @gate: boolean set to true to gate, false to ungate |
| 1727 | * |
| 1728 | * Gate/ungate the automatic PHY configuration via hardware; perform |
| 1729 | * the configuration via software instead. |
| 1730 | **/ |
| 1731 | static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) |
| 1732 | { |
| 1733 | u32 extcnf_ctrl; |
| 1734 | |
| 1735 | if (hw->mac.type != e1000_pch2lan) |
| 1736 | return; |
| 1737 | |
| 1738 | extcnf_ctrl = er32(EXTCNF_CTRL); |
| 1739 | |
| 1740 | if (gate) |
| 1741 | extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; |
| 1742 | else |
| 1743 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; |
| 1744 | |
| 1745 | ew32(EXTCNF_CTRL, extcnf_ctrl); |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 1746 | } |
| 1747 | |
| 1748 | /** |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 1749 | * e1000_lan_init_done_ich8lan - Check for PHY config completion |
| 1750 | * @hw: pointer to the HW structure |
| 1751 | * |
| 1752 | * Check the appropriate indication the MAC has finished configuring the |
| 1753 | * PHY after a software reset. |
| 1754 | **/ |
| 1755 | static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) |
| 1756 | { |
| 1757 | u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; |
| 1758 | |
| 1759 | /* Wait for basic configuration completes before proceeding */ |
| 1760 | do { |
| 1761 | data = er32(STATUS); |
| 1762 | data &= E1000_STATUS_LAN_INIT_DONE; |
| 1763 | udelay(100); |
| 1764 | } while ((!data) && --loop); |
| 1765 | |
| 1766 | /* |
| 1767 | * If basic configuration is incomplete before the above loop |
| 1768 | * count reaches 0, loading the configuration from NVM will |
| 1769 | * leave the PHY in a bad state possibly resulting in no link. |
| 1770 | */ |
| 1771 | if (loop == 0) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1772 | e_dbg("LAN_INIT_DONE not set, increase timeout\n"); |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 1773 | |
| 1774 | /* Clear the Init Done bit for the next init event */ |
| 1775 | data = er32(STATUS); |
| 1776 | data &= ~E1000_STATUS_LAN_INIT_DONE; |
| 1777 | ew32(STATUS, data); |
| 1778 | } |
| 1779 | |
| 1780 | /** |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 1781 | * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1782 | * @hw: pointer to the HW structure |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1783 | **/ |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 1784 | static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1785 | { |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1786 | s32 ret_val = 0; |
| 1787 | u16 reg; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1788 | |
Bruce Allan | 44abd5c | 2012-02-22 09:02:37 +0000 | [diff] [blame] | 1789 | if (hw->phy.ops.check_reset_block(hw)) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1790 | return 0; |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 1791 | |
Bruce Allan | 5f3eed6 | 2010-09-22 17:15:54 +0000 | [diff] [blame] | 1792 | /* Allow time for h/w to get to quiescent state after reset */ |
Bruce Allan | 1bba438 | 2011-03-19 00:27:20 +0000 | [diff] [blame] | 1793 | usleep_range(10000, 20000); |
Bruce Allan | 5f3eed6 | 2010-09-22 17:15:54 +0000 | [diff] [blame] | 1794 | |
Bruce Allan | fddaa1a | 2010-01-13 01:52:49 +0000 | [diff] [blame] | 1795 | /* Perform any necessary post-reset workarounds */ |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 1796 | switch (hw->mac.type) { |
| 1797 | case e1000_pchlan: |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1798 | ret_val = e1000_hv_phy_workarounds_ich8lan(hw); |
| 1799 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1800 | return ret_val; |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 1801 | break; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1802 | case e1000_pch2lan: |
| 1803 | ret_val = e1000_lv_phy_workarounds_ich8lan(hw); |
| 1804 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1805 | return ret_val; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 1806 | break; |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 1807 | default: |
| 1808 | break; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1809 | } |
| 1810 | |
Bruce Allan | 3ebfc7c | 2011-05-13 07:20:14 +0000 | [diff] [blame] | 1811 | /* Clear the host wakeup bit after lcd reset */ |
| 1812 | if (hw->mac.type >= e1000_pchlan) { |
| 1813 | e1e_rphy(hw, BM_PORT_GEN_CFG, ®); |
| 1814 | reg &= ~BM_WUC_HOST_WU_BIT; |
| 1815 | e1e_wphy(hw, BM_PORT_GEN_CFG, reg); |
| 1816 | } |
Bruce Allan | db2932e | 2009-10-26 11:22:47 +0000 | [diff] [blame] | 1817 | |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1818 | /* Configure the LCD with the extended configuration region in NVM */ |
| 1819 | ret_val = e1000_sw_lcd_config_ich8lan(hw); |
| 1820 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1821 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1822 | |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 1823 | /* Configure the LCD with the OEM bits in NVM */ |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 1824 | ret_val = e1000_oem_bits_config_ich8lan(hw, true); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1825 | |
Bruce Allan | 1effb45 | 2011-02-25 06:58:03 +0000 | [diff] [blame] | 1826 | if (hw->mac.type == e1000_pch2lan) { |
| 1827 | /* Ungate automatic PHY configuration on non-managed 82579 */ |
| 1828 | if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { |
Bruce Allan | 1bba438 | 2011-03-19 00:27:20 +0000 | [diff] [blame] | 1829 | usleep_range(10000, 20000); |
Bruce Allan | 1effb45 | 2011-02-25 06:58:03 +0000 | [diff] [blame] | 1830 | e1000_gate_hw_phy_config_ich8lan(hw, false); |
| 1831 | } |
| 1832 | |
| 1833 | /* Set EEE LPI Update Timer to 200usec */ |
| 1834 | ret_val = hw->phy.ops.acquire(hw); |
| 1835 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1836 | return ret_val; |
Bruce Allan | 1effb45 | 2011-02-25 06:58:03 +0000 | [diff] [blame] | 1837 | ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, |
| 1838 | I82579_LPI_UPDATE_TIMER); |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1839 | if (!ret_val) |
| 1840 | ret_val = hw->phy.ops.write_reg_locked(hw, |
| 1841 | I82579_EMI_DATA, |
| 1842 | 0x1387); |
Bruce Allan | 1effb45 | 2011-02-25 06:58:03 +0000 | [diff] [blame] | 1843 | hw->phy.ops.release(hw); |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 1844 | } |
| 1845 | |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 1846 | return ret_val; |
| 1847 | } |
| 1848 | |
| 1849 | /** |
| 1850 | * e1000_phy_hw_reset_ich8lan - Performs a PHY reset |
| 1851 | * @hw: pointer to the HW structure |
| 1852 | * |
| 1853 | * Resets the PHY |
| 1854 | * This is a function pointer entry point called by drivers |
| 1855 | * or other shared routines. |
| 1856 | **/ |
| 1857 | static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) |
| 1858 | { |
| 1859 | s32 ret_val = 0; |
| 1860 | |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 1861 | /* Gate automatic PHY configuration by hardware on non-managed 82579 */ |
| 1862 | if ((hw->mac.type == e1000_pch2lan) && |
| 1863 | !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) |
| 1864 | e1000_gate_hw_phy_config_ich8lan(hw, true); |
| 1865 | |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 1866 | ret_val = e1000e_phy_hw_reset_generic(hw); |
| 1867 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1868 | return ret_val; |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 1869 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1870 | return e1000_post_phy_reset_ich8lan(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1871 | } |
| 1872 | |
| 1873 | /** |
Bruce Allan | fa2ce13 | 2009-10-26 11:23:25 +0000 | [diff] [blame] | 1874 | * e1000_set_lplu_state_pchlan - Set Low Power Link Up state |
| 1875 | * @hw: pointer to the HW structure |
| 1876 | * @active: true to enable LPLU, false to disable |
| 1877 | * |
| 1878 | * Sets the LPLU state according to the active flag. For PCH, if OEM write |
| 1879 | * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set |
| 1880 | * the phy speed. This function will manually set the LPLU bit and restart |
| 1881 | * auto-neg as hw would do. D3 and D0 LPLU will call the same function |
| 1882 | * since it configures the same bit. |
| 1883 | **/ |
| 1884 | static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) |
| 1885 | { |
| 1886 | s32 ret_val = 0; |
| 1887 | u16 oem_reg; |
| 1888 | |
| 1889 | ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); |
| 1890 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1891 | return ret_val; |
Bruce Allan | fa2ce13 | 2009-10-26 11:23:25 +0000 | [diff] [blame] | 1892 | |
| 1893 | if (active) |
| 1894 | oem_reg |= HV_OEM_BITS_LPLU; |
| 1895 | else |
| 1896 | oem_reg &= ~HV_OEM_BITS_LPLU; |
| 1897 | |
Bruce Allan | 44abd5c | 2012-02-22 09:02:37 +0000 | [diff] [blame] | 1898 | if (!hw->phy.ops.check_reset_block(hw)) |
Bruce Allan | 464c85e | 2011-12-16 00:46:49 +0000 | [diff] [blame] | 1899 | oem_reg |= HV_OEM_BITS_RESTART_AN; |
| 1900 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 1901 | return e1e_wphy(hw, HV_OEM_BITS, oem_reg); |
Bruce Allan | fa2ce13 | 2009-10-26 11:23:25 +0000 | [diff] [blame] | 1902 | } |
| 1903 | |
| 1904 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1905 | * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state |
| 1906 | * @hw: pointer to the HW structure |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 1907 | * @active: true to enable LPLU, false to disable |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1908 | * |
| 1909 | * Sets the LPLU D0 state according to the active flag. When |
| 1910 | * activating LPLU this function also disables smart speed |
| 1911 | * and vice versa. LPLU will not be activated unless the |
| 1912 | * device autonegotiation advertisement meets standards of |
| 1913 | * either 10 or 10/100 or 10/100/1000 at all duplexes. |
| 1914 | * This is a function pointer entry point only called by |
| 1915 | * PHY setup routines. |
| 1916 | **/ |
| 1917 | static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) |
| 1918 | { |
| 1919 | struct e1000_phy_info *phy = &hw->phy; |
| 1920 | u32 phy_ctrl; |
| 1921 | s32 ret_val = 0; |
| 1922 | u16 data; |
| 1923 | |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 1924 | if (phy->type == e1000_phy_ife) |
Bruce Allan | 8260725 | 2012-02-08 02:55:09 +0000 | [diff] [blame] | 1925 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1926 | |
| 1927 | phy_ctrl = er32(PHY_CTRL); |
| 1928 | |
| 1929 | if (active) { |
| 1930 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; |
| 1931 | ew32(PHY_CTRL, phy_ctrl); |
| 1932 | |
Bruce Allan | 60f1292 | 2009-07-01 13:28:14 +0000 | [diff] [blame] | 1933 | if (phy->type != e1000_phy_igp_3) |
| 1934 | return 0; |
| 1935 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1936 | /* |
| 1937 | * Call gig speed drop workaround on LPLU before accessing |
| 1938 | * any PHY registers |
| 1939 | */ |
Bruce Allan | 60f1292 | 2009-07-01 13:28:14 +0000 | [diff] [blame] | 1940 | if (hw->mac.type == e1000_ich8lan) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1941 | e1000e_gig_downshift_workaround_ich8lan(hw); |
| 1942 | |
| 1943 | /* When LPLU is enabled, we should disable SmartSpeed */ |
| 1944 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
| 1945 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 1946 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
| 1947 | if (ret_val) |
| 1948 | return ret_val; |
| 1949 | } else { |
| 1950 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; |
| 1951 | ew32(PHY_CTRL, phy_ctrl); |
| 1952 | |
Bruce Allan | 60f1292 | 2009-07-01 13:28:14 +0000 | [diff] [blame] | 1953 | if (phy->type != e1000_phy_igp_3) |
| 1954 | return 0; |
| 1955 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1956 | /* |
| 1957 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1958 | * during Dx states where the power conservation is most |
| 1959 | * important. During driver activity we should enable |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1960 | * SmartSpeed, so performance is maintained. |
| 1961 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1962 | if (phy->smart_speed == e1000_smart_speed_on) { |
| 1963 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1964 | &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1965 | if (ret_val) |
| 1966 | return ret_val; |
| 1967 | |
| 1968 | data |= IGP01E1000_PSCFR_SMART_SPEED; |
| 1969 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1970 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1971 | if (ret_val) |
| 1972 | return ret_val; |
| 1973 | } else if (phy->smart_speed == e1000_smart_speed_off) { |
| 1974 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1975 | &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1976 | if (ret_val) |
| 1977 | return ret_val; |
| 1978 | |
| 1979 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 1980 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1981 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1982 | if (ret_val) |
| 1983 | return ret_val; |
| 1984 | } |
| 1985 | } |
| 1986 | |
| 1987 | return 0; |
| 1988 | } |
| 1989 | |
| 1990 | /** |
| 1991 | * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state |
| 1992 | * @hw: pointer to the HW structure |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 1993 | * @active: true to enable LPLU, false to disable |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1994 | * |
| 1995 | * Sets the LPLU D3 state according to the active flag. When |
| 1996 | * activating LPLU this function also disables smart speed |
| 1997 | * and vice versa. LPLU will not be activated unless the |
| 1998 | * device autonegotiation advertisement meets standards of |
| 1999 | * either 10 or 10/100 or 10/100/1000 at all duplexes. |
| 2000 | * This is a function pointer entry point only called by |
| 2001 | * PHY setup routines. |
| 2002 | **/ |
| 2003 | static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) |
| 2004 | { |
| 2005 | struct e1000_phy_info *phy = &hw->phy; |
| 2006 | u32 phy_ctrl; |
Bruce Allan | d7eb338 | 2012-02-08 02:55:14 +0000 | [diff] [blame] | 2007 | s32 ret_val = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2008 | u16 data; |
| 2009 | |
| 2010 | phy_ctrl = er32(PHY_CTRL); |
| 2011 | |
| 2012 | if (!active) { |
| 2013 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; |
| 2014 | ew32(PHY_CTRL, phy_ctrl); |
Bruce Allan | 60f1292 | 2009-07-01 13:28:14 +0000 | [diff] [blame] | 2015 | |
| 2016 | if (phy->type != e1000_phy_igp_3) |
| 2017 | return 0; |
| 2018 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2019 | /* |
| 2020 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2021 | * during Dx states where the power conservation is most |
| 2022 | * important. During driver activity we should enable |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2023 | * SmartSpeed, so performance is maintained. |
| 2024 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2025 | if (phy->smart_speed == e1000_smart_speed_on) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2026 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 2027 | &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2028 | if (ret_val) |
| 2029 | return ret_val; |
| 2030 | |
| 2031 | data |= IGP01E1000_PSCFR_SMART_SPEED; |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2032 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 2033 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2034 | if (ret_val) |
| 2035 | return ret_val; |
| 2036 | } else if (phy->smart_speed == e1000_smart_speed_off) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2037 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 2038 | &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2039 | if (ret_val) |
| 2040 | return ret_val; |
| 2041 | |
| 2042 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2043 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 2044 | data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2045 | if (ret_val) |
| 2046 | return ret_val; |
| 2047 | } |
| 2048 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || |
| 2049 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || |
| 2050 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { |
| 2051 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; |
| 2052 | ew32(PHY_CTRL, phy_ctrl); |
| 2053 | |
Bruce Allan | 60f1292 | 2009-07-01 13:28:14 +0000 | [diff] [blame] | 2054 | if (phy->type != e1000_phy_igp_3) |
| 2055 | return 0; |
| 2056 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2057 | /* |
| 2058 | * Call gig speed drop workaround on LPLU before accessing |
| 2059 | * any PHY registers |
| 2060 | */ |
Bruce Allan | 60f1292 | 2009-07-01 13:28:14 +0000 | [diff] [blame] | 2061 | if (hw->mac.type == e1000_ich8lan) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2062 | e1000e_gig_downshift_workaround_ich8lan(hw); |
| 2063 | |
| 2064 | /* When LPLU is enabled, we should disable SmartSpeed */ |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2065 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2066 | if (ret_val) |
| 2067 | return ret_val; |
| 2068 | |
| 2069 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2070 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2071 | } |
| 2072 | |
Bruce Allan | d7eb338 | 2012-02-08 02:55:14 +0000 | [diff] [blame] | 2073 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2074 | } |
| 2075 | |
| 2076 | /** |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2077 | * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 |
| 2078 | * @hw: pointer to the HW structure |
| 2079 | * @bank: pointer to the variable that returns the active bank |
| 2080 | * |
| 2081 | * Reads signature byte from the NVM using the flash access registers. |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2082 | * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2083 | **/ |
| 2084 | static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) |
| 2085 | { |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2086 | u32 eecd; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2087 | struct e1000_nvm_info *nvm = &hw->nvm; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2088 | u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); |
| 2089 | u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2090 | u8 sig_byte = 0; |
Bruce Allan | f71dde6 | 2012-02-08 02:55:35 +0000 | [diff] [blame] | 2091 | s32 ret_val; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2092 | |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2093 | switch (hw->mac.type) { |
| 2094 | case e1000_ich8lan: |
| 2095 | case e1000_ich9lan: |
| 2096 | eecd = er32(EECD); |
| 2097 | if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == |
| 2098 | E1000_EECD_SEC1VAL_VALID_MASK) { |
| 2099 | if (eecd & E1000_EECD_SEC1VAL) |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2100 | *bank = 1; |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2101 | else |
| 2102 | *bank = 0; |
| 2103 | |
| 2104 | return 0; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2105 | } |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 2106 | e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2107 | /* fall-thru */ |
| 2108 | default: |
| 2109 | /* set bank to 0 in case flash read fails */ |
| 2110 | *bank = 0; |
| 2111 | |
| 2112 | /* Check bank 0 */ |
| 2113 | ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, |
| 2114 | &sig_byte); |
| 2115 | if (ret_val) |
| 2116 | return ret_val; |
| 2117 | if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == |
| 2118 | E1000_ICH_NVM_SIG_VALUE) { |
| 2119 | *bank = 0; |
| 2120 | return 0; |
| 2121 | } |
| 2122 | |
| 2123 | /* Check bank 1 */ |
| 2124 | ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + |
| 2125 | bank1_offset, |
| 2126 | &sig_byte); |
| 2127 | if (ret_val) |
| 2128 | return ret_val; |
| 2129 | if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == |
| 2130 | E1000_ICH_NVM_SIG_VALUE) { |
| 2131 | *bank = 1; |
| 2132 | return 0; |
| 2133 | } |
| 2134 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 2135 | e_dbg("ERROR: No valid NVM bank present\n"); |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2136 | return -E1000_ERR_NVM; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2137 | } |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2138 | } |
| 2139 | |
| 2140 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2141 | * e1000_read_nvm_ich8lan - Read word(s) from the NVM |
| 2142 | * @hw: pointer to the HW structure |
| 2143 | * @offset: The offset (in bytes) of the word(s) to read. |
| 2144 | * @words: Size of data to read in words |
| 2145 | * @data: Pointer to the word(s) to read at offset. |
| 2146 | * |
| 2147 | * Reads a word(s) from the NVM using the flash access registers. |
| 2148 | **/ |
| 2149 | static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, |
| 2150 | u16 *data) |
| 2151 | { |
| 2152 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 2153 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
| 2154 | u32 act_offset; |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 2155 | s32 ret_val = 0; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2156 | u32 bank = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2157 | u16 i, word; |
| 2158 | |
| 2159 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || |
| 2160 | (words == 0)) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 2161 | e_dbg("nvm parameter(s) out of bounds\n"); |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 2162 | ret_val = -E1000_ERR_NVM; |
| 2163 | goto out; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2164 | } |
| 2165 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2166 | nvm->ops.acquire(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2167 | |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2168 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 2169 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 2170 | e_dbg("Could not detect valid bank, assuming bank 0\n"); |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 2171 | bank = 0; |
| 2172 | } |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2173 | |
| 2174 | act_offset = (bank) ? nvm->flash_bank_size : 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2175 | act_offset += offset; |
| 2176 | |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 2177 | ret_val = 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2178 | for (i = 0; i < words; i++) { |
Bruce Allan | b9e06f7 | 2011-07-22 06:21:41 +0000 | [diff] [blame] | 2179 | if (dev_spec->shadow_ram[offset+i].modified) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2180 | data[i] = dev_spec->shadow_ram[offset+i].value; |
| 2181 | } else { |
| 2182 | ret_val = e1000_read_flash_word_ich8lan(hw, |
| 2183 | act_offset + i, |
| 2184 | &word); |
| 2185 | if (ret_val) |
| 2186 | break; |
| 2187 | data[i] = word; |
| 2188 | } |
| 2189 | } |
| 2190 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2191 | nvm->ops.release(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2192 | |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2193 | out: |
| 2194 | if (ret_val) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 2195 | e_dbg("NVM read error: %d\n", ret_val); |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2196 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2197 | return ret_val; |
| 2198 | } |
| 2199 | |
| 2200 | /** |
| 2201 | * e1000_flash_cycle_init_ich8lan - Initialize flash |
| 2202 | * @hw: pointer to the HW structure |
| 2203 | * |
| 2204 | * This function does initial flash setup so that a new read/write/erase cycle |
| 2205 | * can be started. |
| 2206 | **/ |
| 2207 | static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) |
| 2208 | { |
| 2209 | union ich8_hws_flash_status hsfsts; |
| 2210 | s32 ret_val = -E1000_ERR_NVM; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2211 | |
| 2212 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
| 2213 | |
| 2214 | /* Check if the flash descriptor is valid */ |
| 2215 | if (hsfsts.hsf_status.fldesvalid == 0) { |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 2216 | e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2217 | return -E1000_ERR_NVM; |
| 2218 | } |
| 2219 | |
| 2220 | /* Clear FCERR and DAEL in hw status by writing 1 */ |
| 2221 | hsfsts.hsf_status.flcerr = 1; |
| 2222 | hsfsts.hsf_status.dael = 1; |
| 2223 | |
| 2224 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); |
| 2225 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2226 | /* |
| 2227 | * Either we should have a hardware SPI cycle in progress |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2228 | * bit to check against, in order to start a new cycle or |
| 2229 | * FDONE bit should be changed in the hardware so that it |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 2230 | * is 1 after hardware reset, which can then be used as an |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2231 | * indication whether a cycle is in progress or has been |
| 2232 | * completed. |
| 2233 | */ |
| 2234 | |
| 2235 | if (hsfsts.hsf_status.flcinprog == 0) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2236 | /* |
| 2237 | * There is no cycle running at present, |
Bruce Allan | 5ff5b66 | 2009-12-01 15:51:11 +0000 | [diff] [blame] | 2238 | * so we can start a cycle. |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2239 | * Begin by setting Flash Cycle Done. |
| 2240 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2241 | hsfsts.hsf_status.flcdone = 1; |
| 2242 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); |
| 2243 | ret_val = 0; |
| 2244 | } else { |
Bruce Allan | f71dde6 | 2012-02-08 02:55:35 +0000 | [diff] [blame] | 2245 | s32 i; |
Bruce Allan | 90da066 | 2011-01-06 07:02:53 +0000 | [diff] [blame] | 2246 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2247 | /* |
Bruce Allan | 5ff5b66 | 2009-12-01 15:51:11 +0000 | [diff] [blame] | 2248 | * Otherwise poll for sometime so the current |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2249 | * cycle has a chance to end before giving up. |
| 2250 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2251 | for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { |
Bruce Allan | c8243ee | 2011-12-17 08:32:57 +0000 | [diff] [blame] | 2252 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2253 | if (hsfsts.hsf_status.flcinprog == 0) { |
| 2254 | ret_val = 0; |
| 2255 | break; |
| 2256 | } |
| 2257 | udelay(1); |
| 2258 | } |
Bruce Allan | 9e2d765 | 2012-01-31 06:37:27 +0000 | [diff] [blame] | 2259 | if (!ret_val) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2260 | /* |
| 2261 | * Successful in waiting for previous cycle to timeout, |
| 2262 | * now set the Flash Cycle Done. |
| 2263 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2264 | hsfsts.hsf_status.flcdone = 1; |
| 2265 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); |
| 2266 | } else { |
Joe Perches | 2c73e1f | 2010-03-26 20:16:59 +0000 | [diff] [blame] | 2267 | e_dbg("Flash controller busy, cannot get access\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2268 | } |
| 2269 | } |
| 2270 | |
| 2271 | return ret_val; |
| 2272 | } |
| 2273 | |
| 2274 | /** |
| 2275 | * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) |
| 2276 | * @hw: pointer to the HW structure |
| 2277 | * @timeout: maximum time to wait for completion |
| 2278 | * |
| 2279 | * This function starts a flash cycle and waits for its completion. |
| 2280 | **/ |
| 2281 | static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) |
| 2282 | { |
| 2283 | union ich8_hws_flash_ctrl hsflctl; |
| 2284 | union ich8_hws_flash_status hsfsts; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2285 | u32 i = 0; |
| 2286 | |
| 2287 | /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ |
| 2288 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
| 2289 | hsflctl.hsf_ctrl.flcgo = 1; |
| 2290 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); |
| 2291 | |
| 2292 | /* wait till FDONE bit is set to 1 */ |
| 2293 | do { |
| 2294 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
| 2295 | if (hsfsts.hsf_status.flcdone == 1) |
| 2296 | break; |
| 2297 | udelay(1); |
| 2298 | } while (i++ < timeout); |
| 2299 | |
| 2300 | if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) |
| 2301 | return 0; |
| 2302 | |
Bruce Allan | 55920b5 | 2012-02-08 02:55:25 +0000 | [diff] [blame] | 2303 | return -E1000_ERR_NVM; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2304 | } |
| 2305 | |
| 2306 | /** |
| 2307 | * e1000_read_flash_word_ich8lan - Read word from flash |
| 2308 | * @hw: pointer to the HW structure |
| 2309 | * @offset: offset to data location |
| 2310 | * @data: pointer to the location for storing the data |
| 2311 | * |
| 2312 | * Reads the flash word at offset into data. Offset is converted |
| 2313 | * to bytes before read. |
| 2314 | **/ |
| 2315 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, |
| 2316 | u16 *data) |
| 2317 | { |
| 2318 | /* Must convert offset into bytes. */ |
| 2319 | offset <<= 1; |
| 2320 | |
| 2321 | return e1000_read_flash_data_ich8lan(hw, offset, 2, data); |
| 2322 | } |
| 2323 | |
| 2324 | /** |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2325 | * e1000_read_flash_byte_ich8lan - Read byte from flash |
| 2326 | * @hw: pointer to the HW structure |
| 2327 | * @offset: The offset of the byte to read. |
| 2328 | * @data: Pointer to a byte to store the value read. |
| 2329 | * |
| 2330 | * Reads a single byte from the NVM using the flash access registers. |
| 2331 | **/ |
| 2332 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, |
| 2333 | u8 *data) |
| 2334 | { |
| 2335 | s32 ret_val; |
| 2336 | u16 word = 0; |
| 2337 | |
| 2338 | ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); |
| 2339 | if (ret_val) |
| 2340 | return ret_val; |
| 2341 | |
| 2342 | *data = (u8)word; |
| 2343 | |
| 2344 | return 0; |
| 2345 | } |
| 2346 | |
| 2347 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2348 | * e1000_read_flash_data_ich8lan - Read byte or word from NVM |
| 2349 | * @hw: pointer to the HW structure |
| 2350 | * @offset: The offset (in bytes) of the byte or word to read. |
| 2351 | * @size: Size of data to read, 1=byte 2=word |
| 2352 | * @data: Pointer to the word to store the value read. |
| 2353 | * |
| 2354 | * Reads a byte or word from the NVM using the flash access registers. |
| 2355 | **/ |
| 2356 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, |
| 2357 | u8 size, u16 *data) |
| 2358 | { |
| 2359 | union ich8_hws_flash_status hsfsts; |
| 2360 | union ich8_hws_flash_ctrl hsflctl; |
| 2361 | u32 flash_linear_addr; |
| 2362 | u32 flash_data = 0; |
| 2363 | s32 ret_val = -E1000_ERR_NVM; |
| 2364 | u8 count = 0; |
| 2365 | |
| 2366 | if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) |
| 2367 | return -E1000_ERR_NVM; |
| 2368 | |
| 2369 | flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + |
| 2370 | hw->nvm.flash_base_addr; |
| 2371 | |
| 2372 | do { |
| 2373 | udelay(1); |
| 2374 | /* Steps */ |
| 2375 | ret_val = e1000_flash_cycle_init_ich8lan(hw); |
Bruce Allan | 9e2d765 | 2012-01-31 06:37:27 +0000 | [diff] [blame] | 2376 | if (ret_val) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2377 | break; |
| 2378 | |
| 2379 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
| 2380 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
| 2381 | hsflctl.hsf_ctrl.fldbcount = size - 1; |
| 2382 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; |
| 2383 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); |
| 2384 | |
| 2385 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); |
| 2386 | |
| 2387 | ret_val = e1000_flash_cycle_ich8lan(hw, |
| 2388 | ICH_FLASH_READ_COMMAND_TIMEOUT); |
| 2389 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2390 | /* |
| 2391 | * Check if FCERR is set to 1, if set to 1, clear it |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2392 | * and try the whole sequence a few more times, else |
| 2393 | * read in (shift in) the Flash Data0, the order is |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2394 | * least significant byte first msb to lsb |
| 2395 | */ |
Bruce Allan | 9e2d765 | 2012-01-31 06:37:27 +0000 | [diff] [blame] | 2396 | if (!ret_val) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2397 | flash_data = er32flash(ICH_FLASH_FDATA0); |
Bruce Allan | b1cdfea | 2010-12-11 05:53:47 +0000 | [diff] [blame] | 2398 | if (size == 1) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2399 | *data = (u8)(flash_data & 0x000000FF); |
Bruce Allan | b1cdfea | 2010-12-11 05:53:47 +0000 | [diff] [blame] | 2400 | else if (size == 2) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2401 | *data = (u16)(flash_data & 0x0000FFFF); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2402 | break; |
| 2403 | } else { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2404 | /* |
| 2405 | * If we've gotten here, then things are probably |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2406 | * completely hosed, but if the error condition is |
| 2407 | * detected, it won't hurt to give it another try... |
| 2408 | * ICH_FLASH_CYCLE_REPEAT_COUNT times. |
| 2409 | */ |
| 2410 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
| 2411 | if (hsfsts.hsf_status.flcerr == 1) { |
| 2412 | /* Repeat for some time before giving up. */ |
| 2413 | continue; |
| 2414 | } else if (hsfsts.hsf_status.flcdone == 0) { |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 2415 | e_dbg("Timeout error - flash cycle did not complete.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2416 | break; |
| 2417 | } |
| 2418 | } |
| 2419 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
| 2420 | |
| 2421 | return ret_val; |
| 2422 | } |
| 2423 | |
| 2424 | /** |
| 2425 | * e1000_write_nvm_ich8lan - Write word(s) to the NVM |
| 2426 | * @hw: pointer to the HW structure |
| 2427 | * @offset: The offset (in bytes) of the word(s) to write. |
| 2428 | * @words: Size of data to write in words |
| 2429 | * @data: Pointer to the word(s) to write at offset. |
| 2430 | * |
| 2431 | * Writes a byte or word to the NVM using the flash access registers. |
| 2432 | **/ |
| 2433 | static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, |
| 2434 | u16 *data) |
| 2435 | { |
| 2436 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 2437 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2438 | u16 i; |
| 2439 | |
| 2440 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || |
| 2441 | (words == 0)) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 2442 | e_dbg("nvm parameter(s) out of bounds\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2443 | return -E1000_ERR_NVM; |
| 2444 | } |
| 2445 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2446 | nvm->ops.acquire(hw); |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 2447 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2448 | for (i = 0; i < words; i++) { |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 2449 | dev_spec->shadow_ram[offset+i].modified = true; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2450 | dev_spec->shadow_ram[offset+i].value = data[i]; |
| 2451 | } |
| 2452 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2453 | nvm->ops.release(hw); |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 2454 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2455 | return 0; |
| 2456 | } |
| 2457 | |
| 2458 | /** |
| 2459 | * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM |
| 2460 | * @hw: pointer to the HW structure |
| 2461 | * |
| 2462 | * The NVM checksum is updated by calling the generic update_nvm_checksum, |
| 2463 | * which writes the checksum to the shadow ram. The changes in the shadow |
| 2464 | * ram are then committed to the EEPROM by processing each bank at a time |
| 2465 | * checking for the modified bit and writing only the pending changes. |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 2466 | * After a successful commit, the shadow ram is cleared and is ready for |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2467 | * future writes. |
| 2468 | **/ |
| 2469 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) |
| 2470 | { |
| 2471 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 2472 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2473 | u32 i, act_offset, new_bank_offset, old_bank_offset, bank; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2474 | s32 ret_val; |
| 2475 | u16 data; |
| 2476 | |
| 2477 | ret_val = e1000e_update_nvm_checksum_generic(hw); |
| 2478 | if (ret_val) |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2479 | goto out; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2480 | |
| 2481 | if (nvm->type != e1000_nvm_flash_sw) |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2482 | goto out; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2483 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2484 | nvm->ops.acquire(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2485 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2486 | /* |
| 2487 | * We're writing to the opposite bank so if we're on bank 1, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2488 | * write to bank 0 etc. We also need to erase the segment that |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2489 | * is going to be written |
| 2490 | */ |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2491 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2492 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 2493 | e_dbg("Could not detect valid bank, assuming bank 0\n"); |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 2494 | bank = 0; |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2495 | } |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 2496 | |
| 2497 | if (bank == 0) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2498 | new_bank_offset = nvm->flash_bank_size; |
| 2499 | old_bank_offset = 0; |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2500 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 2501 | if (ret_val) |
| 2502 | goto release; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2503 | } else { |
| 2504 | old_bank_offset = nvm->flash_bank_size; |
| 2505 | new_bank_offset = 0; |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2506 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 2507 | if (ret_val) |
| 2508 | goto release; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2509 | } |
| 2510 | |
| 2511 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2512 | /* |
| 2513 | * Determine whether to write the value stored |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2514 | * in the other NVM bank or a modified value stored |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2515 | * in the shadow RAM |
| 2516 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2517 | if (dev_spec->shadow_ram[i].modified) { |
| 2518 | data = dev_spec->shadow_ram[i].value; |
| 2519 | } else { |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2520 | ret_val = e1000_read_flash_word_ich8lan(hw, i + |
| 2521 | old_bank_offset, |
| 2522 | &data); |
| 2523 | if (ret_val) |
| 2524 | break; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2525 | } |
| 2526 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2527 | /* |
| 2528 | * If the word is 0x13, then make sure the signature bits |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2529 | * (15:14) are 11b until the commit has completed. |
| 2530 | * This will allow us to write 10b which indicates the |
| 2531 | * signature is valid. We want to do this after the write |
| 2532 | * has completed so that we don't mark the segment valid |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2533 | * while the write is still in progress |
| 2534 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2535 | if (i == E1000_ICH_NVM_SIG_WORD) |
| 2536 | data |= E1000_ICH_NVM_SIG_MASK; |
| 2537 | |
| 2538 | /* Convert offset to bytes. */ |
| 2539 | act_offset = (i + new_bank_offset) << 1; |
| 2540 | |
| 2541 | udelay(100); |
| 2542 | /* Write the bytes to the new bank. */ |
| 2543 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, |
| 2544 | act_offset, |
| 2545 | (u8)data); |
| 2546 | if (ret_val) |
| 2547 | break; |
| 2548 | |
| 2549 | udelay(100); |
| 2550 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, |
| 2551 | act_offset + 1, |
| 2552 | (u8)(data >> 8)); |
| 2553 | if (ret_val) |
| 2554 | break; |
| 2555 | } |
| 2556 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2557 | /* |
| 2558 | * Don't bother writing the segment valid bits if sector |
| 2559 | * programming failed. |
| 2560 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2561 | if (ret_val) { |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 2562 | /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 2563 | e_dbg("Flash commit failed.\n"); |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 2564 | goto release; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2565 | } |
| 2566 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2567 | /* |
| 2568 | * Finally validate the new segment by setting bit 15:14 |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2569 | * to 10b in word 0x13 , this can be done without an |
| 2570 | * erase as well since these bits are 11 to start with |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2571 | * and we need to change bit 14 to 0b |
| 2572 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2573 | act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2574 | ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 2575 | if (ret_val) |
| 2576 | goto release; |
| 2577 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2578 | data &= 0xBFFF; |
| 2579 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, |
| 2580 | act_offset * 2 + 1, |
| 2581 | (u8)(data >> 8)); |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 2582 | if (ret_val) |
| 2583 | goto release; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2584 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2585 | /* |
| 2586 | * And invalidate the previously valid segment by setting |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2587 | * its signature word (0x13) high_byte to 0b. This can be |
| 2588 | * done without an erase because flash erase sets all bits |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2589 | * to 1's. We can write 1's to 0's without an erase |
| 2590 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2591 | act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; |
| 2592 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 2593 | if (ret_val) |
| 2594 | goto release; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2595 | |
| 2596 | /* Great! Everything worked, we can now clear the cached entries. */ |
| 2597 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 2598 | dev_spec->shadow_ram[i].modified = false; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2599 | dev_spec->shadow_ram[i].value = 0xFFFF; |
| 2600 | } |
| 2601 | |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 2602 | release: |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2603 | nvm->ops.release(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2604 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2605 | /* |
| 2606 | * Reload the EEPROM, or else modifications will not appear |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2607 | * until after the next adapter reset. |
| 2608 | */ |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 2609 | if (!ret_val) { |
Bruce Allan | e85e363 | 2012-02-22 09:03:14 +0000 | [diff] [blame] | 2610 | nvm->ops.reload(hw); |
Bruce Allan | 1bba438 | 2011-03-19 00:27:20 +0000 | [diff] [blame] | 2611 | usleep_range(10000, 20000); |
Bruce Allan | 9c5e209 | 2010-05-10 15:00:31 +0000 | [diff] [blame] | 2612 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2613 | |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2614 | out: |
| 2615 | if (ret_val) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 2616 | e_dbg("NVM update error: %d\n", ret_val); |
Bruce Allan | e243455 | 2008-11-21 17:02:41 -0800 | [diff] [blame] | 2617 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2618 | return ret_val; |
| 2619 | } |
| 2620 | |
| 2621 | /** |
| 2622 | * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum |
| 2623 | * @hw: pointer to the HW structure |
| 2624 | * |
| 2625 | * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. |
| 2626 | * If the bit is 0, that the EEPROM had been modified, but the checksum was not |
| 2627 | * calculated, in which case we need to calculate the checksum and set bit 6. |
| 2628 | **/ |
| 2629 | static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) |
| 2630 | { |
| 2631 | s32 ret_val; |
| 2632 | u16 data; |
| 2633 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2634 | /* |
| 2635 | * Read 0x19 and check bit 6. If this bit is 0, the checksum |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2636 | * needs to be fixed. This bit is an indication that the NVM |
| 2637 | * was prepared by OEM software and did not calculate the |
| 2638 | * checksum...a likely scenario. |
| 2639 | */ |
| 2640 | ret_val = e1000_read_nvm(hw, 0x19, 1, &data); |
| 2641 | if (ret_val) |
| 2642 | return ret_val; |
| 2643 | |
| 2644 | if ((data & 0x40) == 0) { |
| 2645 | data |= 0x40; |
| 2646 | ret_val = e1000_write_nvm(hw, 0x19, 1, &data); |
| 2647 | if (ret_val) |
| 2648 | return ret_val; |
| 2649 | ret_val = e1000e_update_nvm_checksum(hw); |
| 2650 | if (ret_val) |
| 2651 | return ret_val; |
| 2652 | } |
| 2653 | |
| 2654 | return e1000e_validate_nvm_checksum_generic(hw); |
| 2655 | } |
| 2656 | |
| 2657 | /** |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 2658 | * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only |
| 2659 | * @hw: pointer to the HW structure |
| 2660 | * |
| 2661 | * To prevent malicious write/erase of the NVM, set it to be read-only |
| 2662 | * so that the hardware ignores all write/erase cycles of the NVM via |
| 2663 | * the flash control registers. The shadow-ram copy of the NVM will |
| 2664 | * still be updated, however any updates to this copy will not stick |
| 2665 | * across driver reloads. |
| 2666 | **/ |
| 2667 | void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) |
| 2668 | { |
Bruce Allan | ca15df5 | 2009-10-26 11:23:43 +0000 | [diff] [blame] | 2669 | struct e1000_nvm_info *nvm = &hw->nvm; |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 2670 | union ich8_flash_protected_range pr0; |
| 2671 | union ich8_hws_flash_status hsfsts; |
| 2672 | u32 gfpreg; |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 2673 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2674 | nvm->ops.acquire(hw); |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 2675 | |
| 2676 | gfpreg = er32flash(ICH_FLASH_GFPREG); |
| 2677 | |
| 2678 | /* Write-protect GbE Sector of NVM */ |
| 2679 | pr0.regval = er32flash(ICH_FLASH_PR0); |
| 2680 | pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; |
| 2681 | pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); |
| 2682 | pr0.range.wpe = true; |
| 2683 | ew32flash(ICH_FLASH_PR0, pr0.regval); |
| 2684 | |
| 2685 | /* |
| 2686 | * Lock down a subset of GbE Flash Control Registers, e.g. |
| 2687 | * PR0 to prevent the write-protection from being lifted. |
| 2688 | * Once FLOCKDN is set, the registers protected by it cannot |
| 2689 | * be written until FLOCKDN is cleared by a hardware reset. |
| 2690 | */ |
| 2691 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
| 2692 | hsfsts.hsf_status.flockdn = true; |
| 2693 | ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); |
| 2694 | |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 2695 | nvm->ops.release(hw); |
Bruce Allan | 4a77035 | 2008-10-01 17:18:35 -0700 | [diff] [blame] | 2696 | } |
| 2697 | |
| 2698 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2699 | * e1000_write_flash_data_ich8lan - Writes bytes to the NVM |
| 2700 | * @hw: pointer to the HW structure |
| 2701 | * @offset: The offset (in bytes) of the byte/word to read. |
| 2702 | * @size: Size of data to read, 1=byte 2=word |
| 2703 | * @data: The byte(s) to write to the NVM. |
| 2704 | * |
| 2705 | * Writes one/two bytes to the NVM using the flash access registers. |
| 2706 | **/ |
| 2707 | static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, |
| 2708 | u8 size, u16 data) |
| 2709 | { |
| 2710 | union ich8_hws_flash_status hsfsts; |
| 2711 | union ich8_hws_flash_ctrl hsflctl; |
| 2712 | u32 flash_linear_addr; |
| 2713 | u32 flash_data = 0; |
| 2714 | s32 ret_val; |
| 2715 | u8 count = 0; |
| 2716 | |
| 2717 | if (size < 1 || size > 2 || data > size * 0xff || |
| 2718 | offset > ICH_FLASH_LINEAR_ADDR_MASK) |
| 2719 | return -E1000_ERR_NVM; |
| 2720 | |
| 2721 | flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + |
| 2722 | hw->nvm.flash_base_addr; |
| 2723 | |
| 2724 | do { |
| 2725 | udelay(1); |
| 2726 | /* Steps */ |
| 2727 | ret_val = e1000_flash_cycle_init_ich8lan(hw); |
| 2728 | if (ret_val) |
| 2729 | break; |
| 2730 | |
| 2731 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
| 2732 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
| 2733 | hsflctl.hsf_ctrl.fldbcount = size -1; |
| 2734 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; |
| 2735 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); |
| 2736 | |
| 2737 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); |
| 2738 | |
| 2739 | if (size == 1) |
| 2740 | flash_data = (u32)data & 0x00FF; |
| 2741 | else |
| 2742 | flash_data = (u32)data; |
| 2743 | |
| 2744 | ew32flash(ICH_FLASH_FDATA0, flash_data); |
| 2745 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2746 | /* |
| 2747 | * check if FCERR is set to 1 , if set to 1, clear it |
| 2748 | * and try the whole sequence a few more times else done |
| 2749 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2750 | ret_val = e1000_flash_cycle_ich8lan(hw, |
| 2751 | ICH_FLASH_WRITE_COMMAND_TIMEOUT); |
| 2752 | if (!ret_val) |
| 2753 | break; |
| 2754 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2755 | /* |
| 2756 | * If we're here, then things are most likely |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2757 | * completely hosed, but if the error condition |
| 2758 | * is detected, it won't hurt to give it another |
| 2759 | * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. |
| 2760 | */ |
| 2761 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
| 2762 | if (hsfsts.hsf_status.flcerr == 1) |
| 2763 | /* Repeat for some time before giving up. */ |
| 2764 | continue; |
| 2765 | if (hsfsts.hsf_status.flcdone == 0) { |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 2766 | e_dbg("Timeout error - flash cycle did not complete.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2767 | break; |
| 2768 | } |
| 2769 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
| 2770 | |
| 2771 | return ret_val; |
| 2772 | } |
| 2773 | |
| 2774 | /** |
| 2775 | * e1000_write_flash_byte_ich8lan - Write a single byte to NVM |
| 2776 | * @hw: pointer to the HW structure |
| 2777 | * @offset: The index of the byte to read. |
| 2778 | * @data: The byte to write to the NVM. |
| 2779 | * |
| 2780 | * Writes a single byte to the NVM using the flash access registers. |
| 2781 | **/ |
| 2782 | static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, |
| 2783 | u8 data) |
| 2784 | { |
| 2785 | u16 word = (u16)data; |
| 2786 | |
| 2787 | return e1000_write_flash_data_ich8lan(hw, offset, 1, word); |
| 2788 | } |
| 2789 | |
| 2790 | /** |
| 2791 | * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM |
| 2792 | * @hw: pointer to the HW structure |
| 2793 | * @offset: The offset of the byte to write. |
| 2794 | * @byte: The byte to write to the NVM. |
| 2795 | * |
| 2796 | * Writes a single byte to the NVM using the flash access registers. |
| 2797 | * Goes through a retry algorithm before giving up. |
| 2798 | **/ |
| 2799 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, |
| 2800 | u32 offset, u8 byte) |
| 2801 | { |
| 2802 | s32 ret_val; |
| 2803 | u16 program_retries; |
| 2804 | |
| 2805 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); |
| 2806 | if (!ret_val) |
| 2807 | return ret_val; |
| 2808 | |
| 2809 | for (program_retries = 0; program_retries < 100; program_retries++) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 2810 | e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2811 | udelay(100); |
| 2812 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); |
| 2813 | if (!ret_val) |
| 2814 | break; |
| 2815 | } |
| 2816 | if (program_retries == 100) |
| 2817 | return -E1000_ERR_NVM; |
| 2818 | |
| 2819 | return 0; |
| 2820 | } |
| 2821 | |
| 2822 | /** |
| 2823 | * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM |
| 2824 | * @hw: pointer to the HW structure |
| 2825 | * @bank: 0 for first bank, 1 for second bank, etc. |
| 2826 | * |
| 2827 | * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. |
| 2828 | * bank N is 4096 * N + flash_reg_addr. |
| 2829 | **/ |
| 2830 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) |
| 2831 | { |
| 2832 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 2833 | union ich8_hws_flash_status hsfsts; |
| 2834 | union ich8_hws_flash_ctrl hsflctl; |
| 2835 | u32 flash_linear_addr; |
| 2836 | /* bank size is in 16bit words - adjust to bytes */ |
| 2837 | u32 flash_bank_size = nvm->flash_bank_size * 2; |
| 2838 | s32 ret_val; |
| 2839 | s32 count = 0; |
Bruce Allan | a708dd8 | 2009-11-20 23:28:37 +0000 | [diff] [blame] | 2840 | s32 j, iteration, sector_size; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2841 | |
| 2842 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
| 2843 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2844 | /* |
| 2845 | * Determine HW Sector size: Read BERASE bits of hw flash status |
| 2846 | * register |
| 2847 | * 00: The Hw sector is 256 bytes, hence we need to erase 16 |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2848 | * consecutive sectors. The start index for the nth Hw sector |
| 2849 | * can be calculated as = bank * 4096 + n * 256 |
| 2850 | * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. |
| 2851 | * The start index for the nth Hw sector can be calculated |
| 2852 | * as = bank * 4096 |
| 2853 | * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 |
| 2854 | * (ich9 only, otherwise error condition) |
| 2855 | * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 |
| 2856 | */ |
| 2857 | switch (hsfsts.hsf_status.berasesz) { |
| 2858 | case 0: |
| 2859 | /* Hw sector size 256 */ |
| 2860 | sector_size = ICH_FLASH_SEG_SIZE_256; |
| 2861 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; |
| 2862 | break; |
| 2863 | case 1: |
| 2864 | sector_size = ICH_FLASH_SEG_SIZE_4K; |
Bruce Allan | 28c9195 | 2009-07-01 13:28:32 +0000 | [diff] [blame] | 2865 | iteration = 1; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2866 | break; |
| 2867 | case 2: |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 2868 | sector_size = ICH_FLASH_SEG_SIZE_8K; |
| 2869 | iteration = 1; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2870 | break; |
| 2871 | case 3: |
| 2872 | sector_size = ICH_FLASH_SEG_SIZE_64K; |
Bruce Allan | 28c9195 | 2009-07-01 13:28:32 +0000 | [diff] [blame] | 2873 | iteration = 1; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2874 | break; |
| 2875 | default: |
| 2876 | return -E1000_ERR_NVM; |
| 2877 | } |
| 2878 | |
| 2879 | /* Start with the base address, then add the sector offset. */ |
| 2880 | flash_linear_addr = hw->nvm.flash_base_addr; |
Bruce Allan | 148675a | 2009-08-07 07:41:56 +0000 | [diff] [blame] | 2881 | flash_linear_addr += (bank) ? flash_bank_size : 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2882 | |
| 2883 | for (j = 0; j < iteration ; j++) { |
| 2884 | do { |
| 2885 | /* Steps */ |
| 2886 | ret_val = e1000_flash_cycle_init_ich8lan(hw); |
| 2887 | if (ret_val) |
| 2888 | return ret_val; |
| 2889 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2890 | /* |
| 2891 | * Write a value 11 (block Erase) in Flash |
| 2892 | * Cycle field in hw flash control |
| 2893 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2894 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
| 2895 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; |
| 2896 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); |
| 2897 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2898 | /* |
| 2899 | * Write the last 24 bits of an index within the |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2900 | * block into Flash Linear address field in Flash |
| 2901 | * Address. |
| 2902 | */ |
| 2903 | flash_linear_addr += (j * sector_size); |
| 2904 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); |
| 2905 | |
| 2906 | ret_val = e1000_flash_cycle_ich8lan(hw, |
| 2907 | ICH_FLASH_ERASE_COMMAND_TIMEOUT); |
Bruce Allan | 9e2d765 | 2012-01-31 06:37:27 +0000 | [diff] [blame] | 2908 | if (!ret_val) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2909 | break; |
| 2910 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2911 | /* |
| 2912 | * Check if FCERR is set to 1. If 1, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2913 | * clear it and try the whole sequence |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2914 | * a few more times else Done |
| 2915 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2916 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
| 2917 | if (hsfsts.hsf_status.flcerr == 1) |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 2918 | /* repeat for some time before giving up */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2919 | continue; |
| 2920 | else if (hsfsts.hsf_status.flcdone == 0) |
| 2921 | return ret_val; |
| 2922 | } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); |
| 2923 | } |
| 2924 | |
| 2925 | return 0; |
| 2926 | } |
| 2927 | |
| 2928 | /** |
| 2929 | * e1000_valid_led_default_ich8lan - Set the default LED settings |
| 2930 | * @hw: pointer to the HW structure |
| 2931 | * @data: Pointer to the LED settings |
| 2932 | * |
| 2933 | * Reads the LED default settings from the NVM to data. If the NVM LED |
| 2934 | * settings is all 0's or F's, set the LED default to a valid LED default |
| 2935 | * setting. |
| 2936 | **/ |
| 2937 | static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) |
| 2938 | { |
| 2939 | s32 ret_val; |
| 2940 | |
| 2941 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); |
| 2942 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 2943 | e_dbg("NVM Read Error\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 2944 | return ret_val; |
| 2945 | } |
| 2946 | |
| 2947 | if (*data == ID_LED_RESERVED_0000 || |
| 2948 | *data == ID_LED_RESERVED_FFFF) |
| 2949 | *data = ID_LED_DEFAULT_ICH8LAN; |
| 2950 | |
| 2951 | return 0; |
| 2952 | } |
| 2953 | |
| 2954 | /** |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2955 | * e1000_id_led_init_pchlan - store LED configurations |
| 2956 | * @hw: pointer to the HW structure |
| 2957 | * |
| 2958 | * PCH does not control LEDs via the LEDCTL register, rather it uses |
| 2959 | * the PHY LED configuration register. |
| 2960 | * |
| 2961 | * PCH also does not have an "always on" or "always off" mode which |
| 2962 | * complicates the ID feature. Instead of using the "on" mode to indicate |
Bruce Allan | d1964eb | 2012-02-22 09:02:21 +0000 | [diff] [blame] | 2963 | * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2964 | * use "link_up" mode. The LEDs will still ID on request if there is no |
| 2965 | * link based on logic in e1000_led_[on|off]_pchlan(). |
| 2966 | **/ |
| 2967 | static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) |
| 2968 | { |
| 2969 | struct e1000_mac_info *mac = &hw->mac; |
| 2970 | s32 ret_val; |
| 2971 | const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; |
| 2972 | const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; |
| 2973 | u16 data, i, temp, shift; |
| 2974 | |
| 2975 | /* Get default ID LED modes */ |
| 2976 | ret_val = hw->nvm.ops.valid_led_default(hw, &data); |
| 2977 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 2978 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 2979 | |
| 2980 | mac->ledctl_default = er32(LEDCTL); |
| 2981 | mac->ledctl_mode1 = mac->ledctl_default; |
| 2982 | mac->ledctl_mode2 = mac->ledctl_default; |
| 2983 | |
| 2984 | for (i = 0; i < 4; i++) { |
| 2985 | temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; |
| 2986 | shift = (i * 5); |
| 2987 | switch (temp) { |
| 2988 | case ID_LED_ON1_DEF2: |
| 2989 | case ID_LED_ON1_ON2: |
| 2990 | case ID_LED_ON1_OFF2: |
| 2991 | mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); |
| 2992 | mac->ledctl_mode1 |= (ledctl_on << shift); |
| 2993 | break; |
| 2994 | case ID_LED_OFF1_DEF2: |
| 2995 | case ID_LED_OFF1_ON2: |
| 2996 | case ID_LED_OFF1_OFF2: |
| 2997 | mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); |
| 2998 | mac->ledctl_mode1 |= (ledctl_off << shift); |
| 2999 | break; |
| 3000 | default: |
| 3001 | /* Do nothing */ |
| 3002 | break; |
| 3003 | } |
| 3004 | switch (temp) { |
| 3005 | case ID_LED_DEF1_ON2: |
| 3006 | case ID_LED_ON1_ON2: |
| 3007 | case ID_LED_OFF1_ON2: |
| 3008 | mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); |
| 3009 | mac->ledctl_mode2 |= (ledctl_on << shift); |
| 3010 | break; |
| 3011 | case ID_LED_DEF1_OFF2: |
| 3012 | case ID_LED_ON1_OFF2: |
| 3013 | case ID_LED_OFF1_OFF2: |
| 3014 | mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); |
| 3015 | mac->ledctl_mode2 |= (ledctl_off << shift); |
| 3016 | break; |
| 3017 | default: |
| 3018 | /* Do nothing */ |
| 3019 | break; |
| 3020 | } |
| 3021 | } |
| 3022 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3023 | return 0; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3024 | } |
| 3025 | |
| 3026 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3027 | * e1000_get_bus_info_ich8lan - Get/Set the bus type and width |
| 3028 | * @hw: pointer to the HW structure |
| 3029 | * |
| 3030 | * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability |
| 3031 | * register, so the the bus width is hard coded. |
| 3032 | **/ |
| 3033 | static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) |
| 3034 | { |
| 3035 | struct e1000_bus_info *bus = &hw->bus; |
| 3036 | s32 ret_val; |
| 3037 | |
| 3038 | ret_val = e1000e_get_bus_info_pcie(hw); |
| 3039 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3040 | /* |
| 3041 | * ICH devices are "PCI Express"-ish. They have |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3042 | * a configuration space, but do not contain |
| 3043 | * PCI Express Capability registers, so bus width |
| 3044 | * must be hardcoded. |
| 3045 | */ |
| 3046 | if (bus->width == e1000_bus_width_unknown) |
| 3047 | bus->width = e1000_bus_width_pcie_x1; |
| 3048 | |
| 3049 | return ret_val; |
| 3050 | } |
| 3051 | |
| 3052 | /** |
| 3053 | * e1000_reset_hw_ich8lan - Reset the hardware |
| 3054 | * @hw: pointer to the HW structure |
| 3055 | * |
| 3056 | * Does a full reset of the hardware which includes a reset of the PHY and |
| 3057 | * MAC. |
| 3058 | **/ |
| 3059 | static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) |
| 3060 | { |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 3061 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
Bruce Allan | db2932e | 2009-10-26 11:22:47 +0000 | [diff] [blame] | 3062 | u16 reg; |
Bruce Allan | dd93f95 | 2011-01-06 14:29:48 +0000 | [diff] [blame] | 3063 | u32 ctrl, kab; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3064 | s32 ret_val; |
| 3065 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3066 | /* |
| 3067 | * Prevent the PCI-E bus from sticking if there is no TLP connection |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3068 | * on the last TLP read/write transaction when MAC is reset. |
| 3069 | */ |
| 3070 | ret_val = e1000e_disable_pcie_master(hw); |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3071 | if (ret_val) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3072 | e_dbg("PCI-E Master disable polling has failed.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3073 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3074 | e_dbg("Masking off all interrupts\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3075 | ew32(IMC, 0xffffffff); |
| 3076 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3077 | /* |
| 3078 | * Disable the Transmit and Receive units. Then delay to allow |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3079 | * any pending transactions to complete before we hit the MAC |
| 3080 | * with the global reset. |
| 3081 | */ |
| 3082 | ew32(RCTL, 0); |
| 3083 | ew32(TCTL, E1000_TCTL_PSP); |
| 3084 | e1e_flush(); |
| 3085 | |
Bruce Allan | 1bba438 | 2011-03-19 00:27:20 +0000 | [diff] [blame] | 3086 | usleep_range(10000, 20000); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3087 | |
| 3088 | /* Workaround for ICH8 bit corruption issue in FIFO memory */ |
| 3089 | if (hw->mac.type == e1000_ich8lan) { |
| 3090 | /* Set Tx and Rx buffer allocation to 8k apiece. */ |
| 3091 | ew32(PBA, E1000_PBA_8K); |
| 3092 | /* Set Packet Buffer Size to 16k. */ |
| 3093 | ew32(PBS, E1000_PBS_16K); |
| 3094 | } |
| 3095 | |
Bruce Allan | 1d5846b | 2009-10-29 13:46:05 +0000 | [diff] [blame] | 3096 | if (hw->mac.type == e1000_pchlan) { |
| 3097 | /* Save the NVM K1 bit setting*/ |
| 3098 | ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®); |
| 3099 | if (ret_val) |
| 3100 | return ret_val; |
| 3101 | |
| 3102 | if (reg & E1000_NVM_K1_ENABLE) |
| 3103 | dev_spec->nvm_k1_enabled = true; |
| 3104 | else |
| 3105 | dev_spec->nvm_k1_enabled = false; |
| 3106 | } |
| 3107 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3108 | ctrl = er32(CTRL); |
| 3109 | |
Bruce Allan | 44abd5c | 2012-02-22 09:02:37 +0000 | [diff] [blame] | 3110 | if (!hw->phy.ops.check_reset_block(hw)) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3111 | /* |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3112 | * Full-chip reset requires MAC and PHY reset at the same |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3113 | * time to make sure the interface between MAC and the |
| 3114 | * external PHY is reset. |
| 3115 | */ |
| 3116 | ctrl |= E1000_CTRL_PHY_RST; |
Bruce Allan | 605c82b | 2010-09-22 17:17:01 +0000 | [diff] [blame] | 3117 | |
| 3118 | /* |
| 3119 | * Gate automatic PHY configuration by hardware on |
| 3120 | * non-managed 82579 |
| 3121 | */ |
| 3122 | if ((hw->mac.type == e1000_pch2lan) && |
| 3123 | !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) |
| 3124 | e1000_gate_hw_phy_config_ich8lan(hw, true); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3125 | } |
| 3126 | ret_val = e1000_acquire_swflag_ich8lan(hw); |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3127 | e_dbg("Issuing a global reset to ich8lan\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3128 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); |
Jesse Brandeburg | 945a515 | 2011-07-20 00:56:21 +0000 | [diff] [blame] | 3129 | /* cannot issue a flush here because it hangs the hardware */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3130 | msleep(20); |
| 3131 | |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 3132 | if (!ret_val) |
Bruce Allan | a90b412 | 2011-10-07 03:50:38 +0000 | [diff] [blame] | 3133 | clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); |
Jesse Brandeburg | 37f4023 | 2008-10-02 16:33:20 -0700 | [diff] [blame] | 3134 | |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3135 | if (ctrl & E1000_CTRL_PHY_RST) { |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 3136 | ret_val = hw->phy.ops.get_cfg_done(hw); |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3137 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3138 | return ret_val; |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 3139 | |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3140 | ret_val = e1000_post_phy_reset_ich8lan(hw); |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 3141 | if (ret_val) |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3142 | return ret_val; |
Bruce Allan | f523d21 | 2009-10-29 13:45:45 +0000 | [diff] [blame] | 3143 | } |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3144 | |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 3145 | /* |
| 3146 | * For PCH, this write will make sure that any noise |
| 3147 | * will be detected as a CRC error and be dropped rather than show up |
| 3148 | * as a bad packet to the DMA engine. |
| 3149 | */ |
| 3150 | if (hw->mac.type == e1000_pchlan) |
| 3151 | ew32(CRC_OFFSET, 0x65656565); |
| 3152 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3153 | ew32(IMC, 0xffffffff); |
Bruce Allan | dd93f95 | 2011-01-06 14:29:48 +0000 | [diff] [blame] | 3154 | er32(ICR); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3155 | |
| 3156 | kab = er32(KABGTXD); |
| 3157 | kab |= E1000_KABGTXD_BGSQLBIAS; |
| 3158 | ew32(KABGTXD, kab); |
| 3159 | |
Bruce Allan | 5015e53 | 2012-02-08 02:55:56 +0000 | [diff] [blame] | 3160 | return 0; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3161 | } |
| 3162 | |
| 3163 | /** |
| 3164 | * e1000_init_hw_ich8lan - Initialize the hardware |
| 3165 | * @hw: pointer to the HW structure |
| 3166 | * |
| 3167 | * Prepares the hardware for transmit and receive by doing the following: |
| 3168 | * - initialize hardware bits |
| 3169 | * - initialize LED identification |
| 3170 | * - setup receive address registers |
| 3171 | * - setup flow control |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 3172 | * - setup transmit descriptors |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3173 | * - clear statistics |
| 3174 | **/ |
| 3175 | static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) |
| 3176 | { |
| 3177 | struct e1000_mac_info *mac = &hw->mac; |
| 3178 | u32 ctrl_ext, txdctl, snoop; |
| 3179 | s32 ret_val; |
| 3180 | u16 i; |
| 3181 | |
| 3182 | e1000_initialize_hw_bits_ich8lan(hw); |
| 3183 | |
| 3184 | /* Initialize identification LED */ |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3185 | ret_val = mac->ops.id_led_init(hw); |
Bruce Allan | de39b75 | 2009-11-20 23:27:59 +0000 | [diff] [blame] | 3186 | if (ret_val) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3187 | e_dbg("Error initializing identification LED\n"); |
Bruce Allan | de39b75 | 2009-11-20 23:27:59 +0000 | [diff] [blame] | 3188 | /* This is not fatal and we should not stop init due to this */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3189 | |
| 3190 | /* Setup the receive address. */ |
| 3191 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); |
| 3192 | |
| 3193 | /* Zero out the Multicast HASH table */ |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3194 | e_dbg("Zeroing the MTA\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3195 | for (i = 0; i < mac->mta_reg_count; i++) |
| 3196 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); |
| 3197 | |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 3198 | /* |
| 3199 | * The 82578 Rx buffer will stall if wakeup is enabled in host and |
Bruce Allan | 3ebfc7c | 2011-05-13 07:20:14 +0000 | [diff] [blame] | 3200 | * the ME. Disable wakeup by clearing the host wakeup bit. |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 3201 | * Reset the phy after disabling host wakeup to reset the Rx buffer. |
| 3202 | */ |
| 3203 | if (hw->phy.type == e1000_phy_82578) { |
Bruce Allan | 3ebfc7c | 2011-05-13 07:20:14 +0000 | [diff] [blame] | 3204 | e1e_rphy(hw, BM_PORT_GEN_CFG, &i); |
| 3205 | i &= ~BM_WUC_HOST_WU_BIT; |
| 3206 | e1e_wphy(hw, BM_PORT_GEN_CFG, i); |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 3207 | ret_val = e1000_phy_hw_reset_ich8lan(hw); |
| 3208 | if (ret_val) |
| 3209 | return ret_val; |
| 3210 | } |
| 3211 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3212 | /* Setup link and flow control */ |
Bruce Allan | 1a46b40 | 2012-02-22 09:02:26 +0000 | [diff] [blame] | 3213 | ret_val = mac->ops.setup_link(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3214 | |
| 3215 | /* Set the transmit descriptor write-back policy for both queues */ |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 3216 | txdctl = er32(TXDCTL(0)); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3217 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
| 3218 | E1000_TXDCTL_FULL_TX_DESC_WB; |
| 3219 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | |
| 3220 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 3221 | ew32(TXDCTL(0), txdctl); |
| 3222 | txdctl = er32(TXDCTL(1)); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3223 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
| 3224 | E1000_TXDCTL_FULL_TX_DESC_WB; |
| 3225 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | |
| 3226 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 3227 | ew32(TXDCTL(1), txdctl); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3228 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3229 | /* |
| 3230 | * ICH8 has opposite polarity of no_snoop bits. |
| 3231 | * By default, we should use snoop behavior. |
| 3232 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3233 | if (mac->type == e1000_ich8lan) |
| 3234 | snoop = PCIE_ICH8_SNOOP_ALL; |
| 3235 | else |
| 3236 | snoop = (u32) ~(PCIE_NO_SNOOP_ALL); |
| 3237 | e1000e_set_pcie_no_snoop(hw, snoop); |
| 3238 | |
| 3239 | ctrl_ext = er32(CTRL_EXT); |
| 3240 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; |
| 3241 | ew32(CTRL_EXT, ctrl_ext); |
| 3242 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3243 | /* |
| 3244 | * Clear all of the statistics registers (clear on read). It is |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3245 | * important that we do this after we have tried to establish link |
| 3246 | * because the symbol error count will increment wildly if there |
| 3247 | * is no link. |
| 3248 | */ |
| 3249 | e1000_clear_hw_cntrs_ich8lan(hw); |
| 3250 | |
Bruce Allan | e561a70 | 2012-02-08 02:55:46 +0000 | [diff] [blame] | 3251 | return ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3252 | } |
| 3253 | /** |
| 3254 | * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits |
| 3255 | * @hw: pointer to the HW structure |
| 3256 | * |
| 3257 | * Sets/Clears required hardware bits necessary for correctly setting up the |
| 3258 | * hardware for transmit and receive. |
| 3259 | **/ |
| 3260 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) |
| 3261 | { |
| 3262 | u32 reg; |
| 3263 | |
| 3264 | /* Extended Device Control */ |
| 3265 | reg = er32(CTRL_EXT); |
| 3266 | reg |= (1 << 22); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3267 | /* Enable PHY low-power state when MAC is at D3 w/o WoL */ |
| 3268 | if (hw->mac.type >= e1000_pchlan) |
| 3269 | reg |= E1000_CTRL_EXT_PHYPDEN; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3270 | ew32(CTRL_EXT, reg); |
| 3271 | |
| 3272 | /* Transmit Descriptor Control 0 */ |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 3273 | reg = er32(TXDCTL(0)); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3274 | reg |= (1 << 22); |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 3275 | ew32(TXDCTL(0), reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3276 | |
| 3277 | /* Transmit Descriptor Control 1 */ |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 3278 | reg = er32(TXDCTL(1)); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3279 | reg |= (1 << 22); |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 3280 | ew32(TXDCTL(1), reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3281 | |
| 3282 | /* Transmit Arbitration Control 0 */ |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 3283 | reg = er32(TARC(0)); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3284 | if (hw->mac.type == e1000_ich8lan) |
| 3285 | reg |= (1 << 28) | (1 << 29); |
| 3286 | reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 3287 | ew32(TARC(0), reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3288 | |
| 3289 | /* Transmit Arbitration Control 1 */ |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 3290 | reg = er32(TARC(1)); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3291 | if (er32(TCTL) & E1000_TCTL_MULR) |
| 3292 | reg &= ~(1 << 28); |
| 3293 | else |
| 3294 | reg |= (1 << 28); |
| 3295 | reg |= (1 << 24) | (1 << 26) | (1 << 30); |
Jeff Kirsher | e9ec2c0 | 2008-04-02 13:48:13 -0700 | [diff] [blame] | 3296 | ew32(TARC(1), reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3297 | |
| 3298 | /* Device Status */ |
| 3299 | if (hw->mac.type == e1000_ich8lan) { |
| 3300 | reg = er32(STATUS); |
| 3301 | reg &= ~(1 << 31); |
| 3302 | ew32(STATUS, reg); |
| 3303 | } |
Jesse Brandeburg | a80483d | 2010-03-05 02:21:44 +0000 | [diff] [blame] | 3304 | |
| 3305 | /* |
| 3306 | * work-around descriptor data corruption issue during nfs v2 udp |
| 3307 | * traffic, just disable the nfs filtering capability |
| 3308 | */ |
| 3309 | reg = er32(RFCTL); |
| 3310 | reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); |
| 3311 | ew32(RFCTL, reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3312 | } |
| 3313 | |
| 3314 | /** |
| 3315 | * e1000_setup_link_ich8lan - Setup flow control and link settings |
| 3316 | * @hw: pointer to the HW structure |
| 3317 | * |
| 3318 | * Determines which flow control settings to use, then configures flow |
| 3319 | * control. Calls the appropriate media-specific link configuration |
| 3320 | * function. Assuming the adapter has a valid link partner, a valid link |
| 3321 | * should be established. Assumes the hardware has previously been reset |
| 3322 | * and the transmitter and receiver are not enabled. |
| 3323 | **/ |
| 3324 | static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) |
| 3325 | { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3326 | s32 ret_val; |
| 3327 | |
Bruce Allan | 44abd5c | 2012-02-22 09:02:37 +0000 | [diff] [blame] | 3328 | if (hw->phy.ops.check_reset_block(hw)) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3329 | return 0; |
| 3330 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3331 | /* |
| 3332 | * ICH parts do not have a word in the NVM to determine |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3333 | * the default flow control setting, so we explicitly |
| 3334 | * set it to full. |
| 3335 | */ |
Bruce Allan | 37289d9 | 2009-06-02 11:29:37 +0000 | [diff] [blame] | 3336 | if (hw->fc.requested_mode == e1000_fc_default) { |
| 3337 | /* Workaround h/w hang when Tx flow control enabled */ |
| 3338 | if (hw->mac.type == e1000_pchlan) |
| 3339 | hw->fc.requested_mode = e1000_fc_rx_pause; |
| 3340 | else |
| 3341 | hw->fc.requested_mode = e1000_fc_full; |
| 3342 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3343 | |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 3344 | /* |
| 3345 | * Save off the requested flow control mode for use later. Depending |
| 3346 | * on the link partner's capabilities, we may or may not use this mode. |
| 3347 | */ |
| 3348 | hw->fc.current_mode = hw->fc.requested_mode; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3349 | |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3350 | e_dbg("After fix-ups FlowControl is now = %x\n", |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 3351 | hw->fc.current_mode); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3352 | |
| 3353 | /* Continue to configure the copper link. */ |
Bruce Allan | 944ce01 | 2012-02-22 09:02:42 +0000 | [diff] [blame] | 3354 | ret_val = hw->mac.ops.setup_physical_interface(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3355 | if (ret_val) |
| 3356 | return ret_val; |
| 3357 | |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 3358 | ew32(FCTTV, hw->fc.pause_time); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3359 | if ((hw->phy.type == e1000_phy_82578) || |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 3360 | (hw->phy.type == e1000_phy_82579) || |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3361 | (hw->phy.type == e1000_phy_82577)) { |
Bruce Allan | a305595 | 2010-05-10 15:02:12 +0000 | [diff] [blame] | 3362 | ew32(FCRTV_PCH, hw->fc.refresh_time); |
| 3363 | |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3364 | ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), |
| 3365 | hw->fc.pause_time); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3366 | if (ret_val) |
| 3367 | return ret_val; |
| 3368 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3369 | |
| 3370 | return e1000e_set_fc_watermarks(hw); |
| 3371 | } |
| 3372 | |
| 3373 | /** |
| 3374 | * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface |
| 3375 | * @hw: pointer to the HW structure |
| 3376 | * |
| 3377 | * Configures the kumeran interface to the PHY to wait the appropriate time |
| 3378 | * when polling the PHY, then call the generic setup_copper_link to finish |
| 3379 | * configuring the copper link. |
| 3380 | **/ |
| 3381 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) |
| 3382 | { |
| 3383 | u32 ctrl; |
| 3384 | s32 ret_val; |
| 3385 | u16 reg_data; |
| 3386 | |
| 3387 | ctrl = er32(CTRL); |
| 3388 | ctrl |= E1000_CTRL_SLU; |
| 3389 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 3390 | ew32(CTRL, ctrl); |
| 3391 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3392 | /* |
| 3393 | * Set the mac to wait the maximum time between each iteration |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3394 | * and increase the max iterations when polling the phy; |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3395 | * this fixes erroneous timeouts at 10Mbps. |
| 3396 | */ |
Bruce Allan | 0781895 | 2009-12-08 07:28:01 +0000 | [diff] [blame] | 3397 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3398 | if (ret_val) |
| 3399 | return ret_val; |
Bruce Allan | 0781895 | 2009-12-08 07:28:01 +0000 | [diff] [blame] | 3400 | ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, |
| 3401 | ®_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3402 | if (ret_val) |
| 3403 | return ret_val; |
| 3404 | reg_data |= 0x3F; |
Bruce Allan | 0781895 | 2009-12-08 07:28:01 +0000 | [diff] [blame] | 3405 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, |
| 3406 | reg_data); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3407 | if (ret_val) |
| 3408 | return ret_val; |
| 3409 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3410 | switch (hw->phy.type) { |
| 3411 | case e1000_phy_igp_3: |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3412 | ret_val = e1000e_copper_link_setup_igp(hw); |
| 3413 | if (ret_val) |
| 3414 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3415 | break; |
| 3416 | case e1000_phy_bm: |
| 3417 | case e1000_phy_82578: |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 3418 | ret_val = e1000e_copper_link_setup_m88(hw); |
| 3419 | if (ret_val) |
| 3420 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3421 | break; |
| 3422 | case e1000_phy_82577: |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 3423 | case e1000_phy_82579: |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3424 | ret_val = e1000_copper_link_setup_82577(hw); |
| 3425 | if (ret_val) |
| 3426 | return ret_val; |
| 3427 | break; |
| 3428 | case e1000_phy_ife: |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3429 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 3430 | if (ret_val) |
| 3431 | return ret_val; |
| 3432 | |
| 3433 | reg_data &= ~IFE_PMC_AUTO_MDIX; |
| 3434 | |
| 3435 | switch (hw->phy.mdix) { |
| 3436 | case 1: |
| 3437 | reg_data &= ~IFE_PMC_FORCE_MDIX; |
| 3438 | break; |
| 3439 | case 2: |
| 3440 | reg_data |= IFE_PMC_FORCE_MDIX; |
| 3441 | break; |
| 3442 | case 0: |
| 3443 | default: |
| 3444 | reg_data |= IFE_PMC_AUTO_MDIX; |
| 3445 | break; |
| 3446 | } |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3447 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 3448 | if (ret_val) |
| 3449 | return ret_val; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3450 | break; |
| 3451 | default: |
| 3452 | break; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 3453 | } |
Bruce Allan | 3fa8293 | 2012-02-08 02:55:40 +0000 | [diff] [blame] | 3454 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3455 | return e1000e_setup_copper_link(hw); |
| 3456 | } |
| 3457 | |
| 3458 | /** |
| 3459 | * e1000_get_link_up_info_ich8lan - Get current link speed and duplex |
| 3460 | * @hw: pointer to the HW structure |
| 3461 | * @speed: pointer to store current link speed |
| 3462 | * @duplex: pointer to store the current link duplex |
| 3463 | * |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3464 | * Calls the generic get_speed_and_duplex to retrieve the current link |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3465 | * information and then calls the Kumeran lock loss workaround for links at |
| 3466 | * gigabit speeds. |
| 3467 | **/ |
| 3468 | static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, |
| 3469 | u16 *duplex) |
| 3470 | { |
| 3471 | s32 ret_val; |
| 3472 | |
| 3473 | ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); |
| 3474 | if (ret_val) |
| 3475 | return ret_val; |
| 3476 | |
| 3477 | if ((hw->mac.type == e1000_ich8lan) && |
| 3478 | (hw->phy.type == e1000_phy_igp_3) && |
| 3479 | (*speed == SPEED_1000)) { |
| 3480 | ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); |
| 3481 | } |
| 3482 | |
| 3483 | return ret_val; |
| 3484 | } |
| 3485 | |
| 3486 | /** |
| 3487 | * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround |
| 3488 | * @hw: pointer to the HW structure |
| 3489 | * |
| 3490 | * Work-around for 82566 Kumeran PCS lock loss: |
| 3491 | * On link status change (i.e. PCI reset, speed change) and link is up and |
| 3492 | * speed is gigabit- |
| 3493 | * 0) if workaround is optionally disabled do nothing |
| 3494 | * 1) wait 1ms for Kumeran link to come up |
| 3495 | * 2) check Kumeran Diagnostic register PCS lock loss bit |
| 3496 | * 3) if not set the link is locked (all is good), otherwise... |
| 3497 | * 4) reset the PHY |
| 3498 | * 5) repeat up to 10 times |
| 3499 | * Note: this is only called for IGP3 copper when speed is 1gb. |
| 3500 | **/ |
| 3501 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) |
| 3502 | { |
| 3503 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
| 3504 | u32 phy_ctrl; |
| 3505 | s32 ret_val; |
| 3506 | u16 i, data; |
| 3507 | bool link; |
| 3508 | |
| 3509 | if (!dev_spec->kmrn_lock_loss_workaround_enabled) |
| 3510 | return 0; |
| 3511 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3512 | /* |
| 3513 | * Make sure link is up before proceeding. If not just return. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3514 | * Attempting this while link is negotiating fouled up link |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3515 | * stability |
| 3516 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3517 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
| 3518 | if (!link) |
| 3519 | return 0; |
| 3520 | |
| 3521 | for (i = 0; i < 10; i++) { |
| 3522 | /* read once to clear */ |
| 3523 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); |
| 3524 | if (ret_val) |
| 3525 | return ret_val; |
| 3526 | /* and again to get new status */ |
| 3527 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); |
| 3528 | if (ret_val) |
| 3529 | return ret_val; |
| 3530 | |
| 3531 | /* check for PCS lock */ |
| 3532 | if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) |
| 3533 | return 0; |
| 3534 | |
| 3535 | /* Issue PHY reset */ |
| 3536 | e1000_phy_hw_reset(hw); |
| 3537 | mdelay(5); |
| 3538 | } |
| 3539 | /* Disable GigE link negotiation */ |
| 3540 | phy_ctrl = er32(PHY_CTRL); |
| 3541 | phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | |
| 3542 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
| 3543 | ew32(PHY_CTRL, phy_ctrl); |
| 3544 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3545 | /* |
| 3546 | * Call gig speed drop workaround on Gig disable before accessing |
| 3547 | * any PHY registers |
| 3548 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3549 | e1000e_gig_downshift_workaround_ich8lan(hw); |
| 3550 | |
| 3551 | /* unable to acquire PCS lock */ |
| 3552 | return -E1000_ERR_PHY; |
| 3553 | } |
| 3554 | |
| 3555 | /** |
Bruce Allan | 6e3c807 | 2012-02-22 09:02:47 +0000 | [diff] [blame] | 3556 | * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3557 | * @hw: pointer to the HW structure |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 3558 | * @state: boolean value used to set the current Kumeran workaround state |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3559 | * |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 3560 | * If ICH8, set the current Kumeran workaround state (enabled - true |
| 3561 | * /disabled - false). |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3562 | **/ |
| 3563 | void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, |
| 3564 | bool state) |
| 3565 | { |
| 3566 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
| 3567 | |
| 3568 | if (hw->mac.type != e1000_ich8lan) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3569 | e_dbg("Workaround applies to ICH8 only.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3570 | return; |
| 3571 | } |
| 3572 | |
| 3573 | dev_spec->kmrn_lock_loss_workaround_enabled = state; |
| 3574 | } |
| 3575 | |
| 3576 | /** |
| 3577 | * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 |
| 3578 | * @hw: pointer to the HW structure |
| 3579 | * |
| 3580 | * Workaround for 82566 power-down on D3 entry: |
| 3581 | * 1) disable gigabit link |
| 3582 | * 2) write VR power-down enable |
| 3583 | * 3) read it back |
| 3584 | * Continue if successful, else issue LCD reset and repeat |
| 3585 | **/ |
| 3586 | void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) |
| 3587 | { |
| 3588 | u32 reg; |
| 3589 | u16 data; |
| 3590 | u8 retry = 0; |
| 3591 | |
| 3592 | if (hw->phy.type != e1000_phy_igp_3) |
| 3593 | return; |
| 3594 | |
| 3595 | /* Try the workaround twice (if needed) */ |
| 3596 | do { |
| 3597 | /* Disable link */ |
| 3598 | reg = er32(PHY_CTRL); |
| 3599 | reg |= (E1000_PHY_CTRL_GBE_DISABLE | |
| 3600 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
| 3601 | ew32(PHY_CTRL, reg); |
| 3602 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 3603 | /* |
| 3604 | * Call gig speed drop workaround on Gig disable before |
| 3605 | * accessing any PHY registers |
| 3606 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3607 | if (hw->mac.type == e1000_ich8lan) |
| 3608 | e1000e_gig_downshift_workaround_ich8lan(hw); |
| 3609 | |
| 3610 | /* Write VR power-down enable */ |
| 3611 | e1e_rphy(hw, IGP3_VR_CTRL, &data); |
| 3612 | data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; |
| 3613 | e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); |
| 3614 | |
| 3615 | /* Read it back and test */ |
| 3616 | e1e_rphy(hw, IGP3_VR_CTRL, &data); |
| 3617 | data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; |
| 3618 | if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) |
| 3619 | break; |
| 3620 | |
| 3621 | /* Issue PHY reset and repeat at most one more time */ |
| 3622 | reg = er32(CTRL); |
| 3623 | ew32(CTRL, reg | E1000_CTRL_PHY_RST); |
| 3624 | retry++; |
| 3625 | } while (retry); |
| 3626 | } |
| 3627 | |
| 3628 | /** |
| 3629 | * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working |
| 3630 | * @hw: pointer to the HW structure |
| 3631 | * |
| 3632 | * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 3633 | * LPLU, Gig disable, MDIC PHY reset): |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3634 | * 1) Set Kumeran Near-end loopback |
| 3635 | * 2) Clear Kumeran Near-end loopback |
Bruce Allan | 462d599 | 2011-09-30 08:07:11 +0000 | [diff] [blame] | 3636 | * Should only be called for ICH8[m] devices with any 1G Phy. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3637 | **/ |
| 3638 | void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) |
| 3639 | { |
| 3640 | s32 ret_val; |
| 3641 | u16 reg_data; |
| 3642 | |
Bruce Allan | 462d599 | 2011-09-30 08:07:11 +0000 | [diff] [blame] | 3643 | if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3644 | return; |
| 3645 | |
| 3646 | ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, |
| 3647 | ®_data); |
| 3648 | if (ret_val) |
| 3649 | return; |
| 3650 | reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; |
| 3651 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, |
| 3652 | reg_data); |
| 3653 | if (ret_val) |
| 3654 | return; |
| 3655 | reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; |
| 3656 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, |
| 3657 | reg_data); |
| 3658 | } |
| 3659 | |
| 3660 | /** |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 3661 | * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 3662 | * @hw: pointer to the HW structure |
| 3663 | * |
| 3664 | * During S0 to Sx transition, it is possible the link remains at gig |
| 3665 | * instead of negotiating to a lower speed. Before going to Sx, set |
Bruce Allan | c077a90 | 2011-12-16 00:46:38 +0000 | [diff] [blame] | 3666 | * 'Gig Disable' to force link speed negotiation to a lower speed based on |
| 3667 | * the LPLU setting in the NVM or custom setting. For PCH and newer parts, |
| 3668 | * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also |
| 3669 | * needs to be written. |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 3670 | **/ |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 3671 | void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 3672 | { |
| 3673 | u32 phy_ctrl; |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 3674 | s32 ret_val; |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 3675 | |
Bruce Allan | 17f085d | 2010-06-17 18:59:48 +0000 | [diff] [blame] | 3676 | phy_ctrl = er32(PHY_CTRL); |
Bruce Allan | c077a90 | 2011-12-16 00:46:38 +0000 | [diff] [blame] | 3677 | phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; |
Bruce Allan | 17f085d | 2010-06-17 18:59:48 +0000 | [diff] [blame] | 3678 | ew32(PHY_CTRL, phy_ctrl); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3679 | |
Bruce Allan | 462d599 | 2011-09-30 08:07:11 +0000 | [diff] [blame] | 3680 | if (hw->mac.type == e1000_ich8lan) |
| 3681 | e1000e_gig_downshift_workaround_ich8lan(hw); |
| 3682 | |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 3683 | if (hw->mac.type >= e1000_pchlan) { |
Bruce Allan | ce54afd | 2010-11-24 06:01:41 +0000 | [diff] [blame] | 3684 | e1000_oem_bits_config_ich8lan(hw, false); |
Bruce Allan | 03299e4 | 2011-09-30 08:07:05 +0000 | [diff] [blame] | 3685 | e1000_phy_hw_reset_ich8lan(hw); |
Bruce Allan | 8395ae8 | 2010-09-22 17:15:08 +0000 | [diff] [blame] | 3686 | ret_val = hw->phy.ops.acquire(hw); |
| 3687 | if (ret_val) |
| 3688 | return; |
| 3689 | e1000_write_smbus_addr(hw); |
| 3690 | hw->phy.ops.release(hw); |
| 3691 | } |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 3692 | } |
| 3693 | |
| 3694 | /** |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 3695 | * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 |
| 3696 | * @hw: pointer to the HW structure |
| 3697 | * |
| 3698 | * During Sx to S0 transitions on non-managed devices or managed devices |
| 3699 | * on which PHY resets are not blocked, if the PHY registers cannot be |
| 3700 | * accessed properly by the s/w toggle the LANPHYPC value to power cycle |
| 3701 | * the PHY. |
| 3702 | **/ |
| 3703 | void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) |
| 3704 | { |
Bruce Allan | 90b8298 | 2011-12-16 00:46:33 +0000 | [diff] [blame] | 3705 | u16 phy_id1, phy_id2; |
| 3706 | s32 ret_val; |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 3707 | |
Bruce Allan | 44abd5c | 2012-02-22 09:02:37 +0000 | [diff] [blame] | 3708 | if ((hw->mac.type != e1000_pch2lan) || |
| 3709 | hw->phy.ops.check_reset_block(hw)) |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 3710 | return; |
| 3711 | |
Bruce Allan | 90b8298 | 2011-12-16 00:46:33 +0000 | [diff] [blame] | 3712 | ret_val = hw->phy.ops.acquire(hw); |
| 3713 | if (ret_val) { |
| 3714 | e_dbg("Failed to acquire PHY semaphore in resume\n"); |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 3715 | return; |
| 3716 | } |
| 3717 | |
Bruce Allan | 90b8298 | 2011-12-16 00:46:33 +0000 | [diff] [blame] | 3718 | /* Test access to the PHY registers by reading the ID regs */ |
| 3719 | ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1); |
| 3720 | if (ret_val) |
| 3721 | goto release; |
| 3722 | ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2); |
| 3723 | if (ret_val) |
| 3724 | goto release; |
| 3725 | |
| 3726 | if (hw->phy.id == ((u32)(phy_id1 << 16) | |
| 3727 | (u32)(phy_id2 & PHY_REVISION_MASK))) |
| 3728 | goto release; |
| 3729 | |
| 3730 | e1000_toggle_lanphypc_value_ich8lan(hw); |
| 3731 | |
| 3732 | hw->phy.ops.release(hw); |
| 3733 | msleep(50); |
| 3734 | e1000_phy_hw_reset(hw); |
| 3735 | msleep(50); |
| 3736 | return; |
| 3737 | |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 3738 | release: |
| 3739 | hw->phy.ops.release(hw); |
Bruce Allan | 99730e4 | 2011-05-13 07:19:48 +0000 | [diff] [blame] | 3740 | } |
| 3741 | |
| 3742 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3743 | * e1000_cleanup_led_ich8lan - Restore the default LED operation |
| 3744 | * @hw: pointer to the HW structure |
| 3745 | * |
| 3746 | * Return the LED back to the default configuration. |
| 3747 | **/ |
| 3748 | static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) |
| 3749 | { |
| 3750 | if (hw->phy.type == e1000_phy_ife) |
| 3751 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); |
| 3752 | |
| 3753 | ew32(LEDCTL, hw->mac.ledctl_default); |
| 3754 | return 0; |
| 3755 | } |
| 3756 | |
| 3757 | /** |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 3758 | * e1000_led_on_ich8lan - Turn LEDs on |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3759 | * @hw: pointer to the HW structure |
| 3760 | * |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 3761 | * Turn on the LEDs. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3762 | **/ |
| 3763 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) |
| 3764 | { |
| 3765 | if (hw->phy.type == e1000_phy_ife) |
| 3766 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, |
| 3767 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); |
| 3768 | |
| 3769 | ew32(LEDCTL, hw->mac.ledctl_mode2); |
| 3770 | return 0; |
| 3771 | } |
| 3772 | |
| 3773 | /** |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 3774 | * e1000_led_off_ich8lan - Turn LEDs off |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3775 | * @hw: pointer to the HW structure |
| 3776 | * |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 3777 | * Turn off the LEDs. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3778 | **/ |
| 3779 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) |
| 3780 | { |
| 3781 | if (hw->phy.type == e1000_phy_ife) |
| 3782 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3783 | (IFE_PSCL_PROBE_MODE | |
| 3784 | IFE_PSCL_PROBE_LEDS_OFF)); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3785 | |
| 3786 | ew32(LEDCTL, hw->mac.ledctl_mode1); |
| 3787 | return 0; |
| 3788 | } |
| 3789 | |
| 3790 | /** |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3791 | * e1000_setup_led_pchlan - Configures SW controllable LED |
| 3792 | * @hw: pointer to the HW structure |
| 3793 | * |
| 3794 | * This prepares the SW controllable LED for use. |
| 3795 | **/ |
| 3796 | static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) |
| 3797 | { |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3798 | return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3799 | } |
| 3800 | |
| 3801 | /** |
| 3802 | * e1000_cleanup_led_pchlan - Restore the default LED operation |
| 3803 | * @hw: pointer to the HW structure |
| 3804 | * |
| 3805 | * Return the LED back to the default configuration. |
| 3806 | **/ |
| 3807 | static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) |
| 3808 | { |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3809 | return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3810 | } |
| 3811 | |
| 3812 | /** |
| 3813 | * e1000_led_on_pchlan - Turn LEDs on |
| 3814 | * @hw: pointer to the HW structure |
| 3815 | * |
| 3816 | * Turn on the LEDs. |
| 3817 | **/ |
| 3818 | static s32 e1000_led_on_pchlan(struct e1000_hw *hw) |
| 3819 | { |
| 3820 | u16 data = (u16)hw->mac.ledctl_mode2; |
| 3821 | u32 i, led; |
| 3822 | |
| 3823 | /* |
| 3824 | * If no link, then turn LED on by setting the invert bit |
| 3825 | * for each LED that's mode is "link_up" in ledctl_mode2. |
| 3826 | */ |
| 3827 | if (!(er32(STATUS) & E1000_STATUS_LU)) { |
| 3828 | for (i = 0; i < 3; i++) { |
| 3829 | led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; |
| 3830 | if ((led & E1000_PHY_LED0_MODE_MASK) != |
| 3831 | E1000_LEDCTL_MODE_LINK_UP) |
| 3832 | continue; |
| 3833 | if (led & E1000_PHY_LED0_IVRT) |
| 3834 | data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); |
| 3835 | else |
| 3836 | data |= (E1000_PHY_LED0_IVRT << (i * 5)); |
| 3837 | } |
| 3838 | } |
| 3839 | |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3840 | return e1e_wphy(hw, HV_LED_CONFIG, data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3841 | } |
| 3842 | |
| 3843 | /** |
| 3844 | * e1000_led_off_pchlan - Turn LEDs off |
| 3845 | * @hw: pointer to the HW structure |
| 3846 | * |
| 3847 | * Turn off the LEDs. |
| 3848 | **/ |
| 3849 | static s32 e1000_led_off_pchlan(struct e1000_hw *hw) |
| 3850 | { |
| 3851 | u16 data = (u16)hw->mac.ledctl_mode1; |
| 3852 | u32 i, led; |
| 3853 | |
| 3854 | /* |
| 3855 | * If no link, then turn LED off by clearing the invert bit |
| 3856 | * for each LED that's mode is "link_up" in ledctl_mode1. |
| 3857 | */ |
| 3858 | if (!(er32(STATUS) & E1000_STATUS_LU)) { |
| 3859 | for (i = 0; i < 3; i++) { |
| 3860 | led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; |
| 3861 | if ((led & E1000_PHY_LED0_MODE_MASK) != |
| 3862 | E1000_LEDCTL_MODE_LINK_UP) |
| 3863 | continue; |
| 3864 | if (led & E1000_PHY_LED0_IVRT) |
| 3865 | data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); |
| 3866 | else |
| 3867 | data |= (E1000_PHY_LED0_IVRT << (i * 5)); |
| 3868 | } |
| 3869 | } |
| 3870 | |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 3871 | return e1e_wphy(hw, HV_LED_CONFIG, data); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3872 | } |
| 3873 | |
| 3874 | /** |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3875 | * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3876 | * @hw: pointer to the HW structure |
| 3877 | * |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3878 | * Read appropriate register for the config done bit for completion status |
| 3879 | * and configure the PHY through s/w for EEPROM-less parts. |
| 3880 | * |
| 3881 | * NOTE: some silicon which is EEPROM-less will fail trying to read the |
| 3882 | * config done bit, so only an error is logged and continues. If we were |
| 3883 | * to return with error, EEPROM-less silicon would not be able to be reset |
| 3884 | * or change link. |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3885 | **/ |
| 3886 | static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) |
| 3887 | { |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3888 | s32 ret_val = 0; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3889 | u32 bank = 0; |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3890 | u32 status; |
Bruce Allan | fc0c776 | 2009-07-01 13:27:55 +0000 | [diff] [blame] | 3891 | |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3892 | e1000e_get_cfg_done(hw); |
| 3893 | |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3894 | /* Wait for indication from h/w that it has completed basic config */ |
| 3895 | if (hw->mac.type >= e1000_ich10lan) { |
| 3896 | e1000_lan_init_done_ich8lan(hw); |
| 3897 | } else { |
| 3898 | ret_val = e1000e_get_auto_rd_done(hw); |
| 3899 | if (ret_val) { |
| 3900 | /* |
| 3901 | * When auto config read does not complete, do not |
| 3902 | * return with an error. This can happen in situations |
| 3903 | * where there is no eeprom and prevents getting link. |
| 3904 | */ |
| 3905 | e_dbg("Auto Read Done did not complete\n"); |
| 3906 | ret_val = 0; |
| 3907 | } |
| 3908 | } |
| 3909 | |
| 3910 | /* Clear PHY Reset Asserted bit */ |
| 3911 | status = er32(STATUS); |
| 3912 | if (status & E1000_STATUS_PHYRA) |
| 3913 | ew32(STATUS, status & ~E1000_STATUS_PHYRA); |
| 3914 | else |
| 3915 | e_dbg("PHY Reset Asserted not set - needs delay\n"); |
| 3916 | |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3917 | /* If EEPROM is not marked present, init the IGP 3 PHY manually */ |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3918 | if (hw->mac.type <= e1000_ich9lan) { |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3919 | if (((er32(EECD) & E1000_EECD_PRES) == 0) && |
| 3920 | (hw->phy.type == e1000_phy_igp_3)) { |
| 3921 | e1000e_phy_init_script_igp3(hw); |
| 3922 | } |
| 3923 | } else { |
| 3924 | if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { |
| 3925 | /* Maybe we should do a basic PHY config */ |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 3926 | e_dbg("EEPROM not present\n"); |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3927 | ret_val = -E1000_ERR_CONFIG; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3928 | } |
| 3929 | } |
| 3930 | |
Bruce Allan | e98cac4 | 2010-05-10 15:02:32 +0000 | [diff] [blame] | 3931 | return ret_val; |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 3932 | } |
| 3933 | |
| 3934 | /** |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 3935 | * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down |
| 3936 | * @hw: pointer to the HW structure |
| 3937 | * |
| 3938 | * In the case of a PHY power down to save power, or to turn off link during a |
| 3939 | * driver unload, or wake on lan is not enabled, remove the link. |
| 3940 | **/ |
| 3941 | static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) |
| 3942 | { |
| 3943 | /* If the management interface is not enabled, then power down */ |
| 3944 | if (!(hw->mac.ops.check_mng_mode(hw) || |
| 3945 | hw->phy.ops.check_reset_block(hw))) |
| 3946 | e1000_power_down_phy_copper(hw); |
Bruce Allan | 17f208d | 2009-12-01 15:47:22 +0000 | [diff] [blame] | 3947 | } |
| 3948 | |
| 3949 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3950 | * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters |
| 3951 | * @hw: pointer to the HW structure |
| 3952 | * |
| 3953 | * Clears hardware counters specific to the silicon family and calls |
| 3954 | * clear_hw_cntrs_generic to clear all general purpose counters. |
| 3955 | **/ |
| 3956 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) |
| 3957 | { |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3958 | u16 phy_data; |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 3959 | s32 ret_val; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3960 | |
| 3961 | e1000e_clear_hw_cntrs_base(hw); |
| 3962 | |
Bruce Allan | 99673d9 | 2009-11-20 23:27:21 +0000 | [diff] [blame] | 3963 | er32(ALGNERRC); |
| 3964 | er32(RXERRC); |
| 3965 | er32(TNCRS); |
| 3966 | er32(CEXTERR); |
| 3967 | er32(TSCTC); |
| 3968 | er32(TSCTFC); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3969 | |
Bruce Allan | 99673d9 | 2009-11-20 23:27:21 +0000 | [diff] [blame] | 3970 | er32(MGTPRC); |
| 3971 | er32(MGTPDC); |
| 3972 | er32(MGTPTC); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3973 | |
Bruce Allan | 99673d9 | 2009-11-20 23:27:21 +0000 | [diff] [blame] | 3974 | er32(IAC); |
| 3975 | er32(ICRXOC); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 3976 | |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3977 | /* Clear PHY statistics registers */ |
| 3978 | if ((hw->phy.type == e1000_phy_82578) || |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 3979 | (hw->phy.type == e1000_phy_82579) || |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 3980 | (hw->phy.type == e1000_phy_82577)) { |
Bruce Allan | 2b6b168 | 2011-05-13 07:20:09 +0000 | [diff] [blame] | 3981 | ret_val = hw->phy.ops.acquire(hw); |
| 3982 | if (ret_val) |
| 3983 | return; |
| 3984 | ret_val = hw->phy.ops.set_page(hw, |
| 3985 | HV_STATS_PAGE << IGP_PAGE_SHIFT); |
| 3986 | if (ret_val) |
| 3987 | goto release; |
| 3988 | hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); |
| 3989 | hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); |
| 3990 | hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); |
| 3991 | hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); |
| 3992 | hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); |
| 3993 | hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); |
| 3994 | hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); |
| 3995 | hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); |
| 3996 | hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); |
| 3997 | hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); |
| 3998 | hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); |
| 3999 | hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); |
| 4000 | hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); |
| 4001 | hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); |
| 4002 | release: |
| 4003 | hw->phy.ops.release(hw); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4004 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4005 | } |
| 4006 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 4007 | static const struct e1000_mac_operations ich8_mac_ops = { |
Bruce Allan | eb7700d | 2010-06-16 13:27:05 +0000 | [diff] [blame] | 4008 | /* check_mng_mode dependent on mac type */ |
Bruce Allan | 7d3cabb | 2009-07-01 13:29:08 +0000 | [diff] [blame] | 4009 | .check_for_link = e1000_check_for_copper_link_ich8lan, |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4010 | /* cleanup_led dependent on mac type */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4011 | .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, |
| 4012 | .get_bus_info = e1000_get_bus_info_ich8lan, |
Bruce Allan | f4d2dd4 | 2010-01-13 02:05:18 +0000 | [diff] [blame] | 4013 | .set_lan_id = e1000_set_lan_id_single_port, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4014 | .get_link_up_info = e1000_get_link_up_info_ich8lan, |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4015 | /* led_on dependent on mac type */ |
| 4016 | /* led_off dependent on mac type */ |
Jeff Kirsher | e2de3eb | 2008-03-28 09:15:11 -0700 | [diff] [blame] | 4017 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4018 | .reset_hw = e1000_reset_hw_ich8lan, |
| 4019 | .init_hw = e1000_init_hw_ich8lan, |
| 4020 | .setup_link = e1000_setup_link_ich8lan, |
| 4021 | .setup_physical_interface= e1000_setup_copper_link_ich8lan, |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4022 | /* id_led_init dependent on mac type */ |
Bruce Allan | 57cde76 | 2012-02-22 09:02:58 +0000 | [diff] [blame] | 4023 | .config_collision_dist = e1000e_config_collision_dist_generic, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4024 | }; |
| 4025 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 4026 | static const struct e1000_phy_operations ich8_phy_ops = { |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 4027 | .acquire = e1000_acquire_swflag_ich8lan, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4028 | .check_reset_block = e1000_check_reset_block_ich8lan, |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 4029 | .commit = NULL, |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 4030 | .get_cfg_done = e1000_get_cfg_done_ich8lan, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4031 | .get_cable_length = e1000e_get_cable_length_igp_2, |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 4032 | .read_reg = e1000e_read_phy_reg_igp, |
| 4033 | .release = e1000_release_swflag_ich8lan, |
| 4034 | .reset = e1000_phy_hw_reset_ich8lan, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4035 | .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, |
| 4036 | .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 4037 | .write_reg = e1000e_write_phy_reg_igp, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4038 | }; |
| 4039 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 4040 | static const struct e1000_nvm_operations ich8_nvm_ops = { |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 4041 | .acquire = e1000_acquire_nvm_ich8lan, |
| 4042 | .read = e1000_read_nvm_ich8lan, |
| 4043 | .release = e1000_release_nvm_ich8lan, |
Bruce Allan | e85e363 | 2012-02-22 09:03:14 +0000 | [diff] [blame] | 4044 | .reload = e1000e_reload_nvm_generic, |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 4045 | .update = e1000_update_nvm_checksum_ich8lan, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4046 | .valid_led_default = e1000_valid_led_default_ich8lan, |
Bruce Allan | 94d8186 | 2009-11-20 23:25:26 +0000 | [diff] [blame] | 4047 | .validate = e1000_validate_nvm_checksum_ich8lan, |
| 4048 | .write = e1000_write_nvm_ich8lan, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4049 | }; |
| 4050 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 4051 | const struct e1000_info e1000_ich8_info = { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4052 | .mac = e1000_ich8lan, |
| 4053 | .flags = FLAG_HAS_WOL |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 4054 | | FLAG_IS_ICH |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4055 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 4056 | | FLAG_HAS_AMT |
| 4057 | | FLAG_HAS_FLASH |
| 4058 | | FLAG_APME_IN_WUC, |
| 4059 | .pba = 8, |
Bruce Allan | 2adc55c | 2009-06-02 11:28:58 +0000 | [diff] [blame] | 4060 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
Jeff Kirsher | 69e3fd8 | 2008-04-02 13:48:18 -0700 | [diff] [blame] | 4061 | .get_variants = e1000_get_variants_ich8lan, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4062 | .mac_ops = &ich8_mac_ops, |
| 4063 | .phy_ops = &ich8_phy_ops, |
| 4064 | .nvm_ops = &ich8_nvm_ops, |
| 4065 | }; |
| 4066 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 4067 | const struct e1000_info e1000_ich9_info = { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4068 | .mac = e1000_ich9lan, |
| 4069 | .flags = FLAG_HAS_JUMBO_FRAMES |
Bruce Allan | 97ac8ca | 2008-04-29 09:16:05 -0700 | [diff] [blame] | 4070 | | FLAG_IS_ICH |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4071 | | FLAG_HAS_WOL |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4072 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 4073 | | FLAG_HAS_AMT |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4074 | | FLAG_HAS_FLASH |
| 4075 | | FLAG_APME_IN_WUC, |
Bruce Allan | 7f1557e | 2011-12-16 00:46:43 +0000 | [diff] [blame] | 4076 | .pba = 18, |
Bruce Allan | 2adc55c | 2009-06-02 11:28:58 +0000 | [diff] [blame] | 4077 | .max_hw_frame_size = DEFAULT_JUMBO, |
Jeff Kirsher | 69e3fd8 | 2008-04-02 13:48:18 -0700 | [diff] [blame] | 4078 | .get_variants = e1000_get_variants_ich8lan, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 4079 | .mac_ops = &ich8_mac_ops, |
| 4080 | .phy_ops = &ich8_phy_ops, |
| 4081 | .nvm_ops = &ich8_nvm_ops, |
| 4082 | }; |
| 4083 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 4084 | const struct e1000_info e1000_ich10_info = { |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 4085 | .mac = e1000_ich10lan, |
| 4086 | .flags = FLAG_HAS_JUMBO_FRAMES |
| 4087 | | FLAG_IS_ICH |
| 4088 | | FLAG_HAS_WOL |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 4089 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 4090 | | FLAG_HAS_AMT |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 4091 | | FLAG_HAS_FLASH |
| 4092 | | FLAG_APME_IN_WUC, |
Bruce Allan | 7f1557e | 2011-12-16 00:46:43 +0000 | [diff] [blame] | 4093 | .pba = 18, |
Bruce Allan | 2adc55c | 2009-06-02 11:28:58 +0000 | [diff] [blame] | 4094 | .max_hw_frame_size = DEFAULT_JUMBO, |
Bruce Allan | f4187b5 | 2008-08-26 18:36:50 -0700 | [diff] [blame] | 4095 | .get_variants = e1000_get_variants_ich8lan, |
| 4096 | .mac_ops = &ich8_mac_ops, |
| 4097 | .phy_ops = &ich8_phy_ops, |
| 4098 | .nvm_ops = &ich8_nvm_ops, |
| 4099 | }; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4100 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 4101 | const struct e1000_info e1000_pch_info = { |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4102 | .mac = e1000_pchlan, |
| 4103 | .flags = FLAG_IS_ICH |
| 4104 | | FLAG_HAS_WOL |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4105 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 4106 | | FLAG_HAS_AMT |
| 4107 | | FLAG_HAS_FLASH |
| 4108 | | FLAG_HAS_JUMBO_FRAMES |
Bruce Allan | 38eb394 | 2009-11-19 12:34:20 +0000 | [diff] [blame] | 4109 | | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4110 | | FLAG_APME_IN_WUC, |
Bruce Allan | 8c7bbb9 | 2010-06-16 13:26:41 +0000 | [diff] [blame] | 4111 | .flags2 = FLAG2_HAS_PHY_STATS, |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 4112 | .pba = 26, |
| 4113 | .max_hw_frame_size = 4096, |
| 4114 | .get_variants = e1000_get_variants_ich8lan, |
| 4115 | .mac_ops = &ich8_mac_ops, |
| 4116 | .phy_ops = &ich8_phy_ops, |
| 4117 | .nvm_ops = &ich8_nvm_ops, |
| 4118 | }; |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 4119 | |
Jeff Kirsher | 8ce9d6c | 2011-09-24 13:23:52 +0000 | [diff] [blame] | 4120 | const struct e1000_info e1000_pch2_info = { |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 4121 | .mac = e1000_pch2lan, |
| 4122 | .flags = FLAG_IS_ICH |
| 4123 | | FLAG_HAS_WOL |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 4124 | | FLAG_HAS_CTRLEXT_ON_LOAD |
| 4125 | | FLAG_HAS_AMT |
| 4126 | | FLAG_HAS_FLASH |
| 4127 | | FLAG_HAS_JUMBO_FRAMES |
| 4128 | | FLAG_APME_IN_WUC, |
Bruce Allan | e52997f | 2010-06-16 13:27:49 +0000 | [diff] [blame] | 4129 | .flags2 = FLAG2_HAS_PHY_STATS |
| 4130 | | FLAG2_HAS_EEE, |
Bruce Allan | 828bac8 | 2010-09-29 21:39:37 +0000 | [diff] [blame] | 4131 | .pba = 26, |
Bruce Allan | d3738bb | 2010-06-16 13:27:28 +0000 | [diff] [blame] | 4132 | .max_hw_frame_size = DEFAULT_JUMBO, |
| 4133 | .get_variants = e1000_get_variants_ich8lan, |
| 4134 | .mac_ops = &ich8_mac_ops, |
| 4135 | .phy_ops = &ich8_phy_ops, |
| 4136 | .nvm_ops = &ich8_nvm_ops, |
| 4137 | }; |