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Romain Perier6eacf312014-09-08 17:14:47 +00001/**
2 * emac-rockchip.c - Rockchip EMAC specific glue layer
3 *
4 * Copyright (C) 2014 Romain Perier <romain.perier@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/etherdevice.h>
18#include <linux/mfd/syscon.h>
19#include <linux/module.h>
20#include <linux/of_net.h>
21#include <linux/platform_device.h>
22#include <linux/regmap.h>
23#include <linux/regulator/consumer.h>
24
25#include "emac.h"
26
27#define DRV_NAME "rockchip_emac"
Xing Zhengf4c9d3e2016-01-08 09:35:01 +080028#define DRV_VERSION "1.1"
Romain Perier6eacf312014-09-08 17:14:47 +000029
30struct emac_rockchip_soc_data {
Xing Zhengf4c9d3e2016-01-08 09:35:01 +080031 unsigned int grf_offset;
32 unsigned int grf_mode_offset;
33 unsigned int grf_speed_offset;
34 bool need_div_macclk;
Romain Perier6eacf312014-09-08 17:14:47 +000035};
36
37struct rockchip_priv_data {
38 struct arc_emac_priv emac;
39 struct regmap *grf;
40 const struct emac_rockchip_soc_data *soc_data;
41 struct regulator *regulator;
42 struct clk *refclk;
Xing Zhengf4c9d3e2016-01-08 09:35:01 +080043 struct clk *macclk;
Romain Perier6eacf312014-09-08 17:14:47 +000044};
45
46static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed)
47{
48 struct rockchip_priv_data *emac = priv;
Xing Zhengf4c9d3e2016-01-08 09:35:01 +080049 u32 speed_offset = emac->soc_data->grf_speed_offset;
Romain Perier6eacf312014-09-08 17:14:47 +000050 u32 data;
51 int err = 0;
52
Romain Perier6eacf312014-09-08 17:14:47 +000053 switch(speed) {
54 case 10:
Xing Zhengf4c9d3e2016-01-08 09:35:01 +080055 data = (1 << (speed_offset + 16)) | (0 << speed_offset);
Romain Perier6eacf312014-09-08 17:14:47 +000056 break;
57 case 100:
Xing Zhengf4c9d3e2016-01-08 09:35:01 +080058 data = (1 << (speed_offset + 16)) | (1 << speed_offset);
Romain Perier6eacf312014-09-08 17:14:47 +000059 break;
60 default:
61 pr_err("speed %u not supported\n", speed);
62 return;
63 }
64
65 err = regmap_write(emac->grf, emac->soc_data->grf_offset, data);
66 if (err)
67 pr_err("unable to apply speed %u to grf (%d)\n", speed, err);
68}
69
Xing Zhengaf722612016-01-08 09:35:02 +080070static const struct emac_rockchip_soc_data emac_rk3036_emac_data = {
71 .grf_offset = 0x140, .grf_mode_offset = 8,
72 .grf_speed_offset = 9, .need_div_macclk = 1,
73};
74
Xing Zhengf4c9d3e2016-01-08 09:35:01 +080075static const struct emac_rockchip_soc_data emac_rk3066_emac_data = {
76 .grf_offset = 0x154, .grf_mode_offset = 0,
77 .grf_speed_offset = 1, .need_div_macclk = 0,
78};
79
80static const struct emac_rockchip_soc_data emac_rk3188_emac_data = {
81 .grf_offset = 0x0a4, .grf_mode_offset = 0,
82 .grf_speed_offset = 1, .need_div_macclk = 0,
Romain Perier6eacf312014-09-08 17:14:47 +000083};
84
85static const struct of_device_id emac_rockchip_dt_ids[] = {
Xing Zhengaf722612016-01-08 09:35:02 +080086 { .compatible = "rockchip,rk3036-emac", .data = &emac_rk3036_emac_data },
Xing Zhengf4c9d3e2016-01-08 09:35:01 +080087 { .compatible = "rockchip,rk3066-emac", .data = &emac_rk3066_emac_data },
88 { .compatible = "rockchip,rk3188-emac", .data = &emac_rk3188_emac_data },
Romain Perier6eacf312014-09-08 17:14:47 +000089 { /* Sentinel */ }
90};
91
92MODULE_DEVICE_TABLE(of, emac_rockchip_dt_ids);
93
94static int emac_rockchip_probe(struct platform_device *pdev)
95{
96 struct device *dev = &pdev->dev;
97 struct net_device *ndev;
98 struct rockchip_priv_data *priv;
99 const struct of_device_id *match;
100 u32 data;
101 int err, interface;
102
103 if (!pdev->dev.of_node)
104 return -ENODEV;
105
106 ndev = alloc_etherdev(sizeof(struct rockchip_priv_data));
107 if (!ndev)
108 return -ENOMEM;
109 platform_set_drvdata(pdev, ndev);
110 SET_NETDEV_DEV(ndev, dev);
111
112 priv = netdev_priv(ndev);
113 priv->emac.drv_name = DRV_NAME;
114 priv->emac.drv_version = DRV_VERSION;
115 priv->emac.set_mac_speed = emac_rockchip_set_mac_speed;
116
117 interface = of_get_phy_mode(dev->of_node);
118
Xing Zhengaf722612016-01-08 09:35:02 +0800119 /* RK3036/RK3066/RK3188 SoCs only support RMII */
Romain Perier6eacf312014-09-08 17:14:47 +0000120 if (interface != PHY_INTERFACE_MODE_RMII) {
121 dev_err(dev, "unsupported phy interface mode %d\n", interface);
122 err = -ENOTSUPP;
123 goto out_netdev;
124 }
125
126 priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
127 if (IS_ERR(priv->grf)) {
128 dev_err(dev, "failed to retrieve global register file (%ld)\n", PTR_ERR(priv->grf));
129 err = PTR_ERR(priv->grf);
130 goto out_netdev;
131 }
132
133 match = of_match_node(emac_rockchip_dt_ids, dev->of_node);
134 priv->soc_data = match->data;
135
136 priv->emac.clk = devm_clk_get(dev, "hclk");
137 if (IS_ERR(priv->emac.clk)) {
138 dev_err(dev, "failed to retrieve host clock (%ld)\n", PTR_ERR(priv->emac.clk));
139 err = PTR_ERR(priv->emac.clk);
140 goto out_netdev;
141 }
142
143 priv->refclk = devm_clk_get(dev, "macref");
144 if (IS_ERR(priv->refclk)) {
145 dev_err(dev, "failed to retrieve reference clock (%ld)\n", PTR_ERR(priv->refclk));
146 err = PTR_ERR(priv->refclk);
147 goto out_netdev;
148 }
149
150 err = clk_prepare_enable(priv->refclk);
151 if (err) {
152 dev_err(dev, "failed to enable reference clock (%d)\n", err);
153 goto out_netdev;
154 }
155
156 /* Optional regulator for PHY */
157 priv->regulator = devm_regulator_get_optional(dev, "phy");
158 if (IS_ERR(priv->regulator)) {
159 if (PTR_ERR(priv->regulator) == -EPROBE_DEFER)
160 return -EPROBE_DEFER;
161 dev_err(dev, "no regulator found\n");
162 priv->regulator = NULL;
163 }
164
165 if (priv->regulator) {
166 err = regulator_enable(priv->regulator);
167 if (err) {
168 dev_err(dev, "failed to enable phy-supply (%d)\n", err);
169 goto out_clk_disable;
170 }
171 }
172
Xing Zhengf4c9d3e2016-01-08 09:35:01 +0800173 /* Set speed 100M */
174 data = (1 << (priv->soc_data->grf_speed_offset + 16)) |
175 (1 << priv->soc_data->grf_speed_offset);
176 /* Set RMII mode */
177 data |= (1 << (priv->soc_data->grf_mode_offset + 16)) |
178 (0 << priv->soc_data->grf_mode_offset);
Romain Perier6eacf312014-09-08 17:14:47 +0000179
180 err = regmap_write(priv->grf, priv->soc_data->grf_offset, data);
181 if (err) {
182 dev_err(dev, "unable to apply initial settings to grf (%d)\n", err);
183 goto out_regulator_disable;
184 }
185
186 /* RMII interface needs always a rate of 50MHz */
187 err = clk_set_rate(priv->refclk, 50000000);
188 if (err)
189 dev_err(dev, "failed to change reference clock rate (%d)\n", err);
Xing Zhengc9bca2f2016-01-08 09:35:00 +0800190
Xing Zhengf4c9d3e2016-01-08 09:35:01 +0800191 if (priv->soc_data->need_div_macclk) {
192 priv->macclk = devm_clk_get(dev, "macclk");
193 if (IS_ERR(priv->macclk)) {
194 dev_err(dev, "failed to retrieve mac clock (%ld)\n", PTR_ERR(priv->macclk));
195 err = PTR_ERR(priv->macclk);
196 goto out_regulator_disable;
197 }
198
199 err = clk_prepare_enable(priv->macclk);
200 if (err) {
201 dev_err(dev, "failed to enable mac clock (%d)\n", err);
202 goto out_regulator_disable;
203 }
204
205 /* RMII TX/RX needs always a rate of 25MHz */
206 err = clk_set_rate(priv->macclk, 25000000);
207 if (err)
208 dev_err(dev, "failed to change mac clock rate (%d)\n", err);
209 }
210
Xing Zhengc9bca2f2016-01-08 09:35:00 +0800211 err = arc_emac_probe(ndev, interface);
212 if (err) {
213 dev_err(dev, "failed to probe arc emac (%d)\n", err);
214 goto out_regulator_disable;
215 }
216
Romain Perier6eacf312014-09-08 17:14:47 +0000217 return 0;
218
219out_regulator_disable:
220 if (priv->regulator)
221 regulator_disable(priv->regulator);
222out_clk_disable:
223 clk_disable_unprepare(priv->refclk);
224out_netdev:
225 free_netdev(ndev);
226 return err;
227}
228
229static int emac_rockchip_remove(struct platform_device *pdev)
230{
231 struct net_device *ndev = platform_get_drvdata(pdev);
232 struct rockchip_priv_data *priv = netdev_priv(ndev);
233 int err;
234
Romain Periercf98192d2014-09-10 07:51:13 +0000235 err = arc_emac_remove(ndev);
236
Romain Perier6eacf312014-09-08 17:14:47 +0000237 clk_disable_unprepare(priv->refclk);
238
239 if (priv->regulator)
240 regulator_disable(priv->regulator);
241
Romain Perier6eacf312014-09-08 17:14:47 +0000242 free_netdev(ndev);
243 return err;
244}
245
246static struct platform_driver emac_rockchip_driver = {
247 .probe = emac_rockchip_probe,
248 .remove = emac_rockchip_remove,
249 .driver = {
250 .name = DRV_NAME,
251 .of_match_table = emac_rockchip_dt_ids,
252 },
253};
254
255module_platform_driver(emac_rockchip_driver);
256
257MODULE_AUTHOR("Romain Perier <romain.perier@gmail.com>");
258MODULE_DESCRIPTION("Rockchip EMAC platform driver");
259MODULE_LICENSE("GPL");