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gerrit-public.fairphone.software / kernel / msm-4.9 / afa17a500a3667f66df450100538d06769529bba / . / drivers / net / can / mscan / mscan.h
blob: 57820f5fb817e998f887a8c7bf97f8e29a1ae8dd [file] [log] [blame]
Wolfram Sangafa17a52009-11-13 06:14:52 +0000[diff] [blame^]1/*
2 * Definitions of consts/structs to drive the Freescale MSCAN.
3 *
4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
5 * Varma Electronics Oy
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the version 2 of the GNU General Public License
9 * as published by the Free Software Foundation
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __MSCAN_H__
22#define __MSCAN_H__
23
24#include <linux/types.h>
25
26/* MSCAN control register 0 (CANCTL0) bits */
27#define MSCAN_RXFRM 0x80
28#define MSCAN_RXACT 0x40
29#define MSCAN_CSWAI 0x20
30#define MSCAN_SYNCH 0x10
31#define MSCAN_TIME 0x08
32#define MSCAN_WUPE 0x04
33#define MSCAN_SLPRQ 0x02
34#define MSCAN_INITRQ 0x01
35
36/* MSCAN control register 1 (CANCTL1) bits */
37#define MSCAN_CANE 0x80
38#define MSCAN_CLKSRC 0x40
39#define MSCAN_LOOPB 0x20
40#define MSCAN_LISTEN 0x10
41#define MSCAN_WUPM 0x04
42#define MSCAN_SLPAK 0x02
43#define MSCAN_INITAK 0x01
44
45/* Use the MPC5200 MSCAN variant? */
46#ifdef CONFIG_PPC
47#define MSCAN_FOR_MPC5200
48#endif
49
50#ifdef MSCAN_FOR_MPC5200
51#define MSCAN_CLKSRC_BUS 0
52#define MSCAN_CLKSRC_XTAL MSCAN_CLKSRC
53#else
54#define MSCAN_CLKSRC_BUS MSCAN_CLKSRC
55#define MSCAN_CLKSRC_XTAL 0
56#endif
57
58/* MSCAN receiver flag register (CANRFLG) bits */
59#define MSCAN_WUPIF 0x80
60#define MSCAN_CSCIF 0x40
61#define MSCAN_RSTAT1 0x20
62#define MSCAN_RSTAT0 0x10
63#define MSCAN_TSTAT1 0x08
64#define MSCAN_TSTAT0 0x04
65#define MSCAN_OVRIF 0x02
66#define MSCAN_RXF 0x01
67#define MSCAN_ERR_IF (MSCAN_OVRIF | MSCAN_CSCIF)
68#define MSCAN_RSTAT_MSK (MSCAN_RSTAT1 | MSCAN_RSTAT0)
69#define MSCAN_TSTAT_MSK (MSCAN_TSTAT1 | MSCAN_TSTAT0)
70#define MSCAN_STAT_MSK (MSCAN_RSTAT_MSK | MSCAN_TSTAT_MSK)
71
72#define MSCAN_STATE_BUS_OFF (MSCAN_RSTAT1 | MSCAN_RSTAT0 | \
73 MSCAN_TSTAT1 | MSCAN_TSTAT0)
74#define MSCAN_STATE_TX(canrflg) (((canrflg)&MSCAN_TSTAT_MSK)>>2)
75#define MSCAN_STATE_RX(canrflg) (((canrflg)&MSCAN_RSTAT_MSK)>>4)
76#define MSCAN_STATE_ACTIVE 0
77#define MSCAN_STATE_WARNING 1
78#define MSCAN_STATE_PASSIVE 2
79#define MSCAN_STATE_BUSOFF 3
80
81/* MSCAN receiver interrupt enable register (CANRIER) bits */
82#define MSCAN_WUPIE 0x80
83#define MSCAN_CSCIE 0x40
84#define MSCAN_RSTATE1 0x20
85#define MSCAN_RSTATE0 0x10
86#define MSCAN_TSTATE1 0x08
87#define MSCAN_TSTATE0 0x04
88#define MSCAN_OVRIE 0x02
89#define MSCAN_RXFIE 0x01
90
91/* MSCAN transmitter flag register (CANTFLG) bits */
92#define MSCAN_TXE2 0x04
93#define MSCAN_TXE1 0x02
94#define MSCAN_TXE0 0x01
95#define MSCAN_TXE (MSCAN_TXE2 | MSCAN_TXE1 | MSCAN_TXE0)
96
97/* MSCAN transmitter interrupt enable register (CANTIER) bits */
98#define MSCAN_TXIE2 0x04
99#define MSCAN_TXIE1 0x02
100#define MSCAN_TXIE0 0x01
101#define MSCAN_TXIE (MSCAN_TXIE2 | MSCAN_TXIE1 | MSCAN_TXIE0)
102
103/* MSCAN transmitter message abort request (CANTARQ) bits */
104#define MSCAN_ABTRQ2 0x04
105#define MSCAN_ABTRQ1 0x02
106#define MSCAN_ABTRQ0 0x01
107
108/* MSCAN transmitter message abort ack (CANTAAK) bits */
109#define MSCAN_ABTAK2 0x04
110#define MSCAN_ABTAK1 0x02
111#define MSCAN_ABTAK0 0x01
112
113/* MSCAN transmit buffer selection (CANTBSEL) bits */
114#define MSCAN_TX2 0x04
115#define MSCAN_TX1 0x02
116#define MSCAN_TX0 0x01
117
118/* MSCAN ID acceptance control register (CANIDAC) bits */
119#define MSCAN_IDAM1 0x20
120#define MSCAN_IDAM0 0x10
121#define MSCAN_IDHIT2 0x04
122#define MSCAN_IDHIT1 0x02
123#define MSCAN_IDHIT0 0x01
124
125#define MSCAN_AF_32BIT 0x00
126#define MSCAN_AF_16BIT MSCAN_IDAM0
127#define MSCAN_AF_8BIT MSCAN_IDAM1
128#define MSCAN_AF_CLOSED (MSCAN_IDAM0|MSCAN_IDAM1)
129#define MSCAN_AF_MASK (~(MSCAN_IDAM0|MSCAN_IDAM1))
130
131/* MSCAN Miscellaneous Register (CANMISC) bits */
132#define MSCAN_BOHOLD 0x01
133
134#ifdef MSCAN_FOR_MPC5200
135#define _MSCAN_RESERVED_(n, num) u8 _res##n[num]
136#define _MSCAN_RESERVED_DSR_SIZE 2
137#else
138#define _MSCAN_RESERVED_(n, num)
139#define _MSCAN_RESERVED_DSR_SIZE 0
140#endif
141
142/* Structure of the hardware registers */
143struct mscan_regs {
144 /* (see doc S12MSCANV3/D) MPC5200 MSCAN */
145 u8 canctl0; /* + 0x00 0x00 */
146 u8 canctl1; /* + 0x01 0x01 */
147 _MSCAN_RESERVED_(1, 2); /* + 0x02 */
148 u8 canbtr0; /* + 0x04 0x02 */
149 u8 canbtr1; /* + 0x05 0x03 */
150 _MSCAN_RESERVED_(2, 2); /* + 0x06 */
151 u8 canrflg; /* + 0x08 0x04 */
152 u8 canrier; /* + 0x09 0x05 */
153 _MSCAN_RESERVED_(3, 2); /* + 0x0a */
154 u8 cantflg; /* + 0x0c 0x06 */
155 u8 cantier; /* + 0x0d 0x07 */
156 _MSCAN_RESERVED_(4, 2); /* + 0x0e */
157 u8 cantarq; /* + 0x10 0x08 */
158 u8 cantaak; /* + 0x11 0x09 */
159 _MSCAN_RESERVED_(5, 2); /* + 0x12 */
160 u8 cantbsel; /* + 0x14 0x0a */
161 u8 canidac; /* + 0x15 0x0b */
162 u8 reserved; /* + 0x16 0x0c */
163 _MSCAN_RESERVED_(6, 5); /* + 0x17 */
164#ifndef MSCAN_FOR_MPC5200
165 u8 canmisc; /* 0x0d */
166#endif
167 u8 canrxerr; /* + 0x1c 0x0e */
168 u8 cantxerr; /* + 0x1d 0x0f */
169 _MSCAN_RESERVED_(7, 2); /* + 0x1e */
170 u16 canidar1_0; /* + 0x20 0x10 */
171 _MSCAN_RESERVED_(8, 2); /* + 0x22 */
172 u16 canidar3_2; /* + 0x24 0x12 */
173 _MSCAN_RESERVED_(9, 2); /* + 0x26 */
174 u16 canidmr1_0; /* + 0x28 0x14 */
175 _MSCAN_RESERVED_(10, 2); /* + 0x2a */
176 u16 canidmr3_2; /* + 0x2c 0x16 */
177 _MSCAN_RESERVED_(11, 2); /* + 0x2e */
178 u16 canidar5_4; /* + 0x30 0x18 */
179 _MSCAN_RESERVED_(12, 2); /* + 0x32 */
180 u16 canidar7_6; /* + 0x34 0x1a */
181 _MSCAN_RESERVED_(13, 2); /* + 0x36 */
182 u16 canidmr5_4; /* + 0x38 0x1c */
183 _MSCAN_RESERVED_(14, 2); /* + 0x3a */
184 u16 canidmr7_6; /* + 0x3c 0x1e */
185 _MSCAN_RESERVED_(15, 2); /* + 0x3e */
186 struct {
187 u16 idr1_0; /* + 0x40 0x20 */
188 _MSCAN_RESERVED_(16, 2); /* + 0x42 */
189 u16 idr3_2; /* + 0x44 0x22 */
190 _MSCAN_RESERVED_(17, 2); /* + 0x46 */
191 u16 dsr1_0; /* + 0x48 0x24 */
192 _MSCAN_RESERVED_(18, 2); /* + 0x4a */
193 u16 dsr3_2; /* + 0x4c 0x26 */
194 _MSCAN_RESERVED_(19, 2); /* + 0x4e */
195 u16 dsr5_4; /* + 0x50 0x28 */
196 _MSCAN_RESERVED_(20, 2); /* + 0x52 */
197 u16 dsr7_6; /* + 0x54 0x2a */
198 _MSCAN_RESERVED_(21, 2); /* + 0x56 */
199 u8 dlr; /* + 0x58 0x2c */
200 u8:8; /* + 0x59 0x2d */
201 _MSCAN_RESERVED_(22, 2); /* + 0x5a */
202 u16 time; /* + 0x5c 0x2e */
203 } rx;
204 _MSCAN_RESERVED_(23, 2); /* + 0x5e */
205 struct {
206 u16 idr1_0; /* + 0x60 0x30 */
207 _MSCAN_RESERVED_(24, 2); /* + 0x62 */
208 u16 idr3_2; /* + 0x64 0x32 */
209 _MSCAN_RESERVED_(25, 2); /* + 0x66 */
210 u16 dsr1_0; /* + 0x68 0x34 */
211 _MSCAN_RESERVED_(26, 2); /* + 0x6a */
212 u16 dsr3_2; /* + 0x6c 0x36 */
213 _MSCAN_RESERVED_(27, 2); /* + 0x6e */
214 u16 dsr5_4; /* + 0x70 0x38 */
215 _MSCAN_RESERVED_(28, 2); /* + 0x72 */
216 u16 dsr7_6; /* + 0x74 0x3a */
217 _MSCAN_RESERVED_(29, 2); /* + 0x76 */
218 u8 dlr; /* + 0x78 0x3c */
219 u8 tbpr; /* + 0x79 0x3d */
220 _MSCAN_RESERVED_(30, 2); /* + 0x7a */
221 u16 time; /* + 0x7c 0x3e */
222 } tx;
223 _MSCAN_RESERVED_(31, 2); /* + 0x7e */
224} __attribute__ ((packed));
225
226#undef _MSCAN_RESERVED_
227#define MSCAN_REGION sizeof(struct mscan)
228
229#define TX_QUEUE_SIZE 3
230
231struct tx_queue_entry {
232 struct list_head list;
233 u8 mask;
234 u8 id;
235};
236
237struct mscan_priv {
238 struct can_priv can; /* must be the first member */
239 long open_time;
240 unsigned long flags;
241 void __iomem *reg_base; /* ioremap'ed address to registers */
242 u8 shadow_statflg;
243 u8 shadow_canrier;
244 u8 cur_pri;
245 u8 prev_buf_id;
246 u8 tx_active;
247
248 struct list_head tx_head;
249 struct tx_queue_entry tx_queue[TX_QUEUE_SIZE];
250 struct napi_struct napi;
251};
252
253struct net_device *alloc_mscandev(void);
254/*
255 * clock_src:
256 * 1 = The MSCAN clock source is the onchip Bus Clock.
257 * 0 = The MSCAN clock source is the chip Oscillator Clock.
258 */
259extern int register_mscandev(struct net_device *dev, int clock_src);
260extern void unregister_mscandev(struct net_device *dev);
261
262#endif /* __MSCAN_H__ */