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Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata_oldpiix.c - Intel PATA/SATA controllers
3 *
4 * (C) 2005 Red Hat <alan@redhat.com>
5 *
6 * Some parts based on ata_piix.c by Jeff Garzik and others.
7 *
8 * Early PIIX differs significantly from the later PIIX as it lacks
9 * SITRE and the slave timing registers. This means that you have to
10 * set timing per channel, or be clever. Libata tells us whenever it
11 * does drive selection and we use this to reload the timings.
12 *
13 * Because of these behaviour differences PIIX gets its own driver module.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/blkdev.h>
21#include <linux/delay.h>
22#include <linux/device.h>
23#include <scsi/scsi_host.h>
24#include <linux/libata.h>
25#include <linux/ata.h>
26
27#define DRV_NAME "pata_oldpiix"
Alan Coxc9619222006-09-26 17:53:38 +010028#define DRV_VERSION "0.5.2"
Jeff Garzik669a5db2006-08-29 18:12:40 -040029
30/**
31 * oldpiix_pre_reset - probe begin
32 * @ap: ATA port
33 *
34 * Set up cable type and use generic probe init
35 */
36
37static int oldpiix_pre_reset(struct ata_port *ap)
38{
39 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
40 static const struct pci_bits oldpiix_enable_bits[] = {
41 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
42 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
43 };
44
Alan Coxc9619222006-09-26 17:53:38 +010045 if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no]))
46 return -ENOENT;
Jeff Garzik669a5db2006-08-29 18:12:40 -040047 ap->cbl = ATA_CBL_PATA40;
48 return ata_std_prereset(ap);
49}
50
51/**
52 * oldpiix_pata_error_handler - Probe specified port on PATA host controller
53 * @ap: Port to probe
54 * @classes:
55 *
56 * LOCKING:
57 * None (inherited from caller).
58 */
59
60static void oldpiix_pata_error_handler(struct ata_port *ap)
61{
62 ata_bmdma_drive_eh(ap, oldpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
63}
64
65/**
66 * oldpiix_set_piomode - Initialize host controller PATA PIO timings
67 * @ap: Port whose timings we are configuring
68 * @adev: um
69 *
70 * Set PIO mode for device, in host controller PCI config space.
71 *
72 * LOCKING:
73 * None (inherited from caller).
74 */
75
76static void oldpiix_set_piomode (struct ata_port *ap, struct ata_device *adev)
77{
78 unsigned int pio = adev->pio_mode - XFER_PIO_0;
79 struct pci_dev *dev = to_pci_dev(ap->host->dev);
80 unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
81 u16 idetm_data;
82 int control = 0;
83
84 /*
85 * See Intel Document 298600-004 for the timing programing rules
86 * for PIIX/ICH. Note that the early PIIX does not have the slave
87 * timing port at 0x44.
88 */
89
90 static const /* ISP RTC */
91 u8 timings[][2] = { { 0, 0 },
92 { 0, 0 },
93 { 1, 0 },
94 { 2, 1 },
95 { 2, 3 }, };
96
97 if (pio > 2)
98 control |= 1; /* TIME1 enable */
99 if (ata_pio_need_iordy(adev))
100 control |= 2; /* IE IORDY */
101
102 /* Intel specifies that the PPE functionality is for disk only */
103 if (adev->class == ATA_DEV_ATA)
104 control |= 4; /* PPE enable */
105
106 pci_read_config_word(dev, idetm_port, &idetm_data);
107
108 /* Enable PPE, IE and TIME as appropriate. Clear the other
109 drive timing bits */
110 if (adev->devno == 0) {
111 idetm_data &= 0xCCE0;
112 idetm_data |= control;
113 } else {
114 idetm_data &= 0xCC0E;
115 idetm_data |= (control << 4);
116 }
117 idetm_data |= (timings[pio][0] << 12) |
118 (timings[pio][1] << 8);
119 pci_write_config_word(dev, idetm_port, idetm_data);
120
121 /* Track which port is configured */
122 ap->private_data = adev;
123}
124
125/**
126 * oldpiix_set_dmamode - Initialize host controller PATA DMA timings
127 * @ap: Port whose timings we are configuring
128 * @adev: Device to program
129 * @isich: True if the device is an ICH and has IOCFG registers
130 *
131 * Set MWDMA mode for device, in host controller PCI config space.
132 *
133 * LOCKING:
134 * None (inherited from caller).
135 */
136
137static void oldpiix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
138{
139 struct pci_dev *dev = to_pci_dev(ap->host->dev);
140 u8 idetm_port = ap->port_no ? 0x42 : 0x40;
141 u16 idetm_data;
142
143 static const /* ISP RTC */
144 u8 timings[][2] = { { 0, 0 },
145 { 0, 0 },
146 { 1, 0 },
147 { 2, 1 },
148 { 2, 3 }, };
149
150 /*
151 * MWDMA is driven by the PIO timings. We must also enable
152 * IORDY unconditionally along with TIME1. PPE has already
153 * been set when the PIO timing was set.
154 */
155
156 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
157 unsigned int control;
158 const unsigned int needed_pio[3] = {
159 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
160 };
161 int pio = needed_pio[mwdma] - XFER_PIO_0;
162
163 pci_read_config_word(dev, idetm_port, &idetm_data);
164
165 control = 3; /* IORDY|TIME0 */
166 /* Intel specifies that the PPE functionality is for disk only */
167 if (adev->class == ATA_DEV_ATA)
168 control |= 4; /* PPE enable */
169
170 /* If the drive MWDMA is faster than it can do PIO then
171 we must force PIO into PIO0 */
172
173 if (adev->pio_mode < needed_pio[mwdma])
174 /* Enable DMA timing only */
175 control |= 8; /* PIO cycles in PIO0 */
176
177 /* Mask out the relevant control and timing bits we will load. Also
178 clear the other drive TIME register as a precaution */
179 if (adev->devno == 0) {
180 idetm_data &= 0xCCE0;
181 idetm_data |= control;
182 } else {
183 idetm_data &= 0xCC0E;
184 idetm_data |= (control << 4);
185 }
186 idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
187 pci_write_config_word(dev, idetm_port, idetm_data);
188
189 /* Track which port is configured */
190 ap->private_data = adev;
191}
192
193/**
194 * oldpiix_qc_issue_prot - command issue
195 * @qc: command pending
196 *
197 * Called when the libata layer is about to issue a command. We wrap
198 * this interface so that we can load the correct ATA timings if
199 * neccessary. Our logic also clears TIME0/TIME1 for the other device so
200 * that, even if we get this wrong, cycles to the other device will
201 * be made PIO0.
202 */
203
204static unsigned int oldpiix_qc_issue_prot(struct ata_queued_cmd *qc)
205{
206 struct ata_port *ap = qc->ap;
207 struct ata_device *adev = qc->dev;
208
209 if (adev != ap->private_data) {
210 if (adev->dma_mode)
211 oldpiix_set_dmamode(ap, adev);
212 else if (adev->pio_mode)
213 oldpiix_set_piomode(ap, adev);
214 }
215 return ata_qc_issue_prot(qc);
216}
217
218
219static struct scsi_host_template oldpiix_sht = {
220 .module = THIS_MODULE,
221 .name = DRV_NAME,
222 .ioctl = ata_scsi_ioctl,
223 .queuecommand = ata_scsi_queuecmd,
224 .can_queue = ATA_DEF_QUEUE,
225 .this_id = ATA_SHT_THIS_ID,
226 .sg_tablesize = LIBATA_MAX_PRD,
227 .max_sectors = ATA_MAX_SECTORS,
228 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
229 .emulated = ATA_SHT_EMULATED,
230 .use_clustering = ATA_SHT_USE_CLUSTERING,
231 .proc_name = DRV_NAME,
232 .dma_boundary = ATA_DMA_BOUNDARY,
233 .slave_configure = ata_scsi_slave_config,
Tejun Heoafdfe892006-11-29 11:26:47 +0900234 .slave_destroy = ata_scsi_slave_destroy,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400235 .bios_param = ata_std_bios_param,
236};
237
238static const struct ata_port_operations oldpiix_pata_ops = {
239 .port_disable = ata_port_disable,
240 .set_piomode = oldpiix_set_piomode,
241 .set_dmamode = oldpiix_set_dmamode,
242 .mode_filter = ata_pci_default_filter,
243
244 .tf_load = ata_tf_load,
245 .tf_read = ata_tf_read,
246 .check_status = ata_check_status,
247 .exec_command = ata_exec_command,
248 .dev_select = ata_std_dev_select,
249
250 .freeze = ata_bmdma_freeze,
251 .thaw = ata_bmdma_thaw,
252 .error_handler = oldpiix_pata_error_handler,
253 .post_internal_cmd = ata_bmdma_post_internal_cmd,
254
255 .bmdma_setup = ata_bmdma_setup,
256 .bmdma_start = ata_bmdma_start,
257 .bmdma_stop = ata_bmdma_stop,
258 .bmdma_status = ata_bmdma_status,
259 .qc_prep = ata_qc_prep,
260 .qc_issue = oldpiix_qc_issue_prot,
261 .data_xfer = ata_pio_data_xfer,
262
263 .irq_handler = ata_interrupt,
264 .irq_clear = ata_bmdma_irq_clear,
265
266 .port_start = ata_port_start,
267 .port_stop = ata_port_stop,
268 .host_stop = ata_host_stop,
269};
270
271
272/**
273 * oldpiix_init_one - Register PIIX ATA PCI device with kernel services
274 * @pdev: PCI device to register
275 * @ent: Entry in oldpiix_pci_tbl matching with @pdev
276 *
277 * Called from kernel PCI layer. We probe for combined mode (sigh),
278 * and then hand over control to libata, for it to do the rest.
279 *
280 * LOCKING:
281 * Inherited from PCI layer (may sleep).
282 *
283 * RETURNS:
284 * Zero on success, or -ERRNO value.
285 */
286
287static int oldpiix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
288{
289 static int printed_version;
290 static struct ata_port_info info = {
291 .sht = &oldpiix_sht,
292 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
293 .pio_mask = 0x1f, /* pio0-4 */
294 .mwdma_mask = 0x07, /* mwdma1-2 */
295 .port_ops = &oldpiix_pata_ops,
296 };
297 static struct ata_port_info *port_info[2] = { &info, &info };
298
299 if (!printed_version++)
300 dev_printk(KERN_DEBUG, &pdev->dev,
301 "version " DRV_VERSION "\n");
302
303 return ata_pci_init_one(pdev, port_info, 2);
304}
305
306static const struct pci_device_id oldpiix_pci_tbl[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400307 { PCI_VDEVICE(INTEL, 0x1230), },
308
Jeff Garzik669a5db2006-08-29 18:12:40 -0400309 { } /* terminate list */
310};
311
312static struct pci_driver oldpiix_pci_driver = {
313 .name = DRV_NAME,
314 .id_table = oldpiix_pci_tbl,
315 .probe = oldpiix_init_one,
316 .remove = ata_pci_remove_one,
317};
318
319static int __init oldpiix_init(void)
320{
321 return pci_register_driver(&oldpiix_pci_driver);
322}
323
324static void __exit oldpiix_exit(void)
325{
326 pci_unregister_driver(&oldpiix_pci_driver);
327}
328
Jeff Garzik669a5db2006-08-29 18:12:40 -0400329module_init(oldpiix_init);
330module_exit(oldpiix_exit);
331
332MODULE_AUTHOR("Alan Cox");
333MODULE_DESCRIPTION("SCSI low-level driver for early PIIX series controllers");
334MODULE_LICENSE("GPL");
335MODULE_DEVICE_TABLE(pci, oldpiix_pci_tbl);
336MODULE_VERSION(DRV_VERSION);
337