Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 1 | Booting AArch64 Linux |
| 2 | ===================== |
| 3 | |
| 4 | Author: Will Deacon <will.deacon@arm.com> |
| 5 | Date : 07 September 2012 |
| 6 | |
| 7 | This document is based on the ARM booting document by Russell King and |
| 8 | is relevant to all public releases of the AArch64 Linux kernel. |
| 9 | |
| 10 | The AArch64 exception model is made up of a number of exception levels |
| 11 | (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure |
| 12 | counterpart. EL2 is the hypervisor level and exists only in non-secure |
| 13 | mode. EL3 is the highest priority level and exists only in secure mode. |
| 14 | |
| 15 | For the purposes of this document, we will use the term `boot loader' |
| 16 | simply to define all software that executes on the CPU(s) before control |
| 17 | is passed to the Linux kernel. This may include secure monitor and |
| 18 | hypervisor code, or it may just be a handful of instructions for |
| 19 | preparing a minimal boot environment. |
| 20 | |
| 21 | Essentially, the boot loader should provide (as a minimum) the |
| 22 | following: |
| 23 | |
| 24 | 1. Setup and initialise the RAM |
| 25 | 2. Setup the device tree |
| 26 | 3. Decompress the kernel image |
| 27 | 4. Call the kernel image |
| 28 | |
| 29 | |
| 30 | 1. Setup and initialise RAM |
| 31 | --------------------------- |
| 32 | |
| 33 | Requirement: MANDATORY |
| 34 | |
| 35 | The boot loader is expected to find and initialise all RAM that the |
| 36 | kernel will use for volatile data storage in the system. It performs |
| 37 | this in a machine dependent manner. (It may use internal algorithms |
| 38 | to automatically locate and size all RAM, or it may use knowledge of |
| 39 | the RAM in the machine, or any other method the boot loader designer |
| 40 | sees fit.) |
| 41 | |
| 42 | |
| 43 | 2. Setup the device tree |
| 44 | ------------------------- |
| 45 | |
| 46 | Requirement: MANDATORY |
| 47 | |
Mark Salter | 4d5e0b1 | 2013-09-04 15:10:02 +0100 | [diff] [blame] | 48 | The device tree blob (dtb) must be placed on an 8-byte boundary within |
| 49 | the first 512 megabytes from the start of the kernel image and must not |
| 50 | cross a 2-megabyte boundary. This is to allow the kernel to map the |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 51 | blob using a single section mapping in the initial page tables. |
| 52 | |
| 53 | |
| 54 | 3. Decompress the kernel image |
| 55 | ------------------------------ |
| 56 | |
| 57 | Requirement: OPTIONAL |
| 58 | |
| 59 | The AArch64 kernel does not currently provide a decompressor and |
| 60 | therefore requires decompression (gzip etc.) to be performed by the boot |
| 61 | loader if a compressed Image target (e.g. Image.gz) is used. For |
| 62 | bootloaders that do not implement this requirement, the uncompressed |
| 63 | Image target is available instead. |
| 64 | |
| 65 | |
| 66 | 4. Call the kernel image |
| 67 | ------------------------ |
| 68 | |
| 69 | Requirement: MANDATORY |
| 70 | |
Roy Franz | 4370eec | 2013-08-15 00:10:00 +0100 | [diff] [blame] | 71 | The decompressed kernel image contains a 64-byte header as follows: |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 72 | |
Roy Franz | 4370eec | 2013-08-15 00:10:00 +0100 | [diff] [blame] | 73 | u32 code0; /* Executable code */ |
| 74 | u32 code1; /* Executable code */ |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 75 | u64 text_offset; /* Image load offset */ |
Roy Franz | 4370eec | 2013-08-15 00:10:00 +0100 | [diff] [blame] | 76 | u64 res0 = 0; /* reserved */ |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 77 | u64 res1 = 0; /* reserved */ |
| 78 | u64 res2 = 0; /* reserved */ |
Roy Franz | 4370eec | 2013-08-15 00:10:00 +0100 | [diff] [blame] | 79 | u64 res3 = 0; /* reserved */ |
| 80 | u64 res4 = 0; /* reserved */ |
| 81 | u32 magic = 0x644d5241; /* Magic number, little endian, "ARM\x64" */ |
| 82 | u32 res5 = 0; /* reserved */ |
| 83 | |
| 84 | |
| 85 | Header notes: |
| 86 | |
| 87 | - code0/code1 are responsible for branching to stext. |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 88 | |
| 89 | The image must be placed at the specified offset (currently 0x80000) |
| 90 | from the start of the system RAM and called there. The start of the |
| 91 | system RAM must be aligned to 2MB. |
| 92 | |
| 93 | Before jumping into the kernel, the following conditions must be met: |
| 94 | |
| 95 | - Quiesce all DMA capable devices so that memory does not get |
| 96 | corrupted by bogus network packets or disk data. This will save |
| 97 | you many hours of debug. |
| 98 | |
| 99 | - Primary CPU general-purpose register settings |
| 100 | x0 = physical address of device tree blob (dtb) in system RAM. |
| 101 | x1 = 0 (reserved for future use) |
| 102 | x2 = 0 (reserved for future use) |
| 103 | x3 = 0 (reserved for future use) |
| 104 | |
| 105 | - CPU mode |
| 106 | All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError, |
| 107 | IRQ and FIQ). |
| 108 | The CPU must be in either EL2 (RECOMMENDED in order to have access to |
| 109 | the virtualisation extensions) or non-secure EL1. |
| 110 | |
| 111 | - Caches, MMUs |
| 112 | The MMU must be off. |
| 113 | Instruction cache may be on or off. |
Catalin Marinas | c218bca | 2014-03-26 18:25:55 +0000 | [diff] [blame] | 114 | The address range corresponding to the loaded kernel image must be |
| 115 | cleaned to the PoC. In the presence of a system cache or other |
| 116 | coherent masters with caches enabled, this will typically require |
| 117 | cache maintenance by VA rather than set/way operations. |
| 118 | System caches which respect the architected cache maintenance by VA |
| 119 | operations must be configured and may be enabled. |
| 120 | System caches which do not respect architected cache maintenance by VA |
| 121 | operations (not recommended) must be configured and disabled. |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 122 | |
| 123 | - Architected timers |
Mark Rutland | 4fcd6e1 | 2013-10-11 14:52:07 +0100 | [diff] [blame] | 124 | CNTFRQ must be programmed with the timer frequency and CNTVOFF must |
| 125 | be programmed with a consistent value on all CPUs. If entering the |
| 126 | kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where |
| 127 | available. |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 128 | |
| 129 | - Coherency |
| 130 | All CPUs to be booted by the kernel must be part of the same coherency |
| 131 | domain on entry to the kernel. This may require IMPLEMENTATION DEFINED |
| 132 | initialisation to enable the receiving of maintenance operations on |
| 133 | each CPU. |
| 134 | |
| 135 | - System registers |
| 136 | All writable architected system registers at the exception level where |
| 137 | the kernel image will be entered must be initialised by software at a |
| 138 | higher exception level to prevent execution in an UNKNOWN state. |
| 139 | |
Mark Rutland | 4fcd6e1 | 2013-10-11 14:52:07 +0100 | [diff] [blame] | 140 | The requirements described above for CPU mode, caches, MMUs, architected |
| 141 | timers, coherency and system registers apply to all CPUs. All CPUs must |
| 142 | enter the kernel in the same exception level. |
| 143 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 144 | The boot loader is expected to enter the kernel on each CPU in the |
| 145 | following manner: |
| 146 | |
| 147 | - The primary CPU must jump directly to the first instruction of the |
| 148 | kernel image. The device tree blob passed by this CPU must contain |
Mark Rutland | 4fcd6e1 | 2013-10-11 14:52:07 +0100 | [diff] [blame] | 149 | an 'enable-method' property for each cpu node. The supported |
| 150 | enable-methods are described below. |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 151 | |
| 152 | It is expected that the bootloader will generate these device tree |
| 153 | properties and insert them into the blob prior to kernel entry. |
| 154 | |
Mark Rutland | 4fcd6e1 | 2013-10-11 14:52:07 +0100 | [diff] [blame] | 155 | - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr' |
| 156 | property in their cpu node. This property identifies a |
| 157 | naturally-aligned 64-bit zero-initalised memory location. |
| 158 | |
| 159 | These CPUs should spin outside of the kernel in a reserved area of |
| 160 | memory (communicated to the kernel by a /memreserve/ region in the |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 161 | device tree) polling their cpu-release-addr location, which must be |
| 162 | contained in the reserved region. A wfe instruction may be inserted |
| 163 | to reduce the overhead of the busy-loop and a sev will be issued by |
| 164 | the primary CPU. When a read of the location pointed to by the |
Mark Rutland | 4fcd6e1 | 2013-10-11 14:52:07 +0100 | [diff] [blame] | 165 | cpu-release-addr returns a non-zero value, the CPU must jump to this |
| 166 | value. The value will be written as a single 64-bit little-endian |
| 167 | value, so CPUs must convert the read value to their native endianness |
| 168 | before jumping to it. |
| 169 | |
| 170 | - CPUs with a "psci" enable method should remain outside of |
| 171 | the kernel (i.e. outside of the regions of memory described to the |
| 172 | kernel in the memory node, or in a reserved area of memory described |
| 173 | to the kernel by a /memreserve/ region in the device tree). The |
| 174 | kernel will issue CPU_ON calls as described in ARM document number ARM |
| 175 | DEN 0022A ("Power State Coordination Interface System Software on ARM |
| 176 | processors") to bring CPUs into the kernel. |
| 177 | |
| 178 | The device tree should contain a 'psci' node, as described in |
| 179 | Documentation/devicetree/bindings/arm/psci.txt. |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 180 | |
| 181 | - Secondary CPU general-purpose register settings |
| 182 | x0 = 0 (reserved for future use) |
| 183 | x1 = 0 (reserved for future use) |
| 184 | x2 = 0 (reserved for future use) |
| 185 | x3 = 0 (reserved for future use) |