Kukjin Kim | b024043b | 2011-12-22 23:27:42 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
| 3 | * http://www.samsung.com |
| 4 | * |
| 5 | * Copyright 2008 Openmoko, Inc. |
| 6 | * Copyright 2008 Simtec Electronics |
| 7 | * Ben Dooks <ben@simtec.co.uk> |
| 8 | * http://armlinux.simtec.co.uk/ |
| 9 | * |
| 10 | * Common Codes for S3C64XX machines |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License version 2 as |
| 14 | * published by the Free Software Foundation. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/ioport.h> |
| 22 | #include <linux/sysdev.h> |
| 23 | #include <linux/serial_core.h> |
| 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/io.h> |
| 26 | #include <linux/dma-mapping.h> |
| 27 | #include <linux/irq.h> |
| 28 | #include <linux/gpio.h> |
| 29 | |
| 30 | #include <asm/mach/arch.h> |
| 31 | #include <asm/mach/map.h> |
| 32 | #include <asm/hardware/vic.h> |
| 33 | |
| 34 | #include <mach/map.h> |
| 35 | #include <mach/hardware.h> |
| 36 | #include <mach/regs-gpio.h> |
| 37 | |
| 38 | #include <plat/cpu.h> |
| 39 | #include <plat/clock.h> |
| 40 | #include <plat/devs.h> |
| 41 | #include <plat/pm.h> |
| 42 | #include <plat/gpio-cfg.h> |
| 43 | #include <plat/irq-uart.h> |
| 44 | #include <plat/irq-vic-timer.h> |
| 45 | #include <plat/regs-irqtype.h> |
| 46 | #include <plat/regs-serial.h> |
| 47 | |
| 48 | #include "common.h" |
| 49 | |
| 50 | /* uart registration process */ |
| 51 | |
| 52 | void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) |
| 53 | { |
| 54 | s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); |
| 55 | } |
| 56 | |
| 57 | /* table of supported CPUs */ |
| 58 | |
| 59 | static const char name_s3c6400[] = "S3C6400"; |
| 60 | static const char name_s3c6410[] = "S3C6410"; |
| 61 | |
| 62 | static struct cpu_table cpu_ids[] __initdata = { |
| 63 | { |
| 64 | .idcode = S3C6400_CPU_ID, |
| 65 | .idmask = S3C64XX_CPU_MASK, |
| 66 | .map_io = s3c6400_map_io, |
| 67 | .init_clocks = s3c6400_init_clocks, |
| 68 | .init_uarts = s3c64xx_init_uarts, |
| 69 | .init = s3c6400_init, |
| 70 | .name = name_s3c6400, |
| 71 | }, { |
| 72 | .idcode = S3C6410_CPU_ID, |
| 73 | .idmask = S3C64XX_CPU_MASK, |
| 74 | .map_io = s3c6410_map_io, |
| 75 | .init_clocks = s3c6410_init_clocks, |
| 76 | .init_uarts = s3c64xx_init_uarts, |
| 77 | .init = s3c6410_init, |
| 78 | .name = name_s3c6410, |
| 79 | }, |
| 80 | }; |
| 81 | |
| 82 | /* minimal IO mapping */ |
| 83 | |
| 84 | /* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */ |
| 85 | #define UART_OFFS (S3C_PA_UART & 0xfffff) |
| 86 | |
| 87 | static struct map_desc s3c_iodesc[] __initdata = { |
| 88 | { |
| 89 | .virtual = (unsigned long)S3C_VA_SYS, |
| 90 | .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON), |
| 91 | .length = SZ_4K, |
| 92 | .type = MT_DEVICE, |
| 93 | }, { |
| 94 | .virtual = (unsigned long)S3C_VA_MEM, |
| 95 | .pfn = __phys_to_pfn(S3C64XX_PA_SROM), |
| 96 | .length = SZ_4K, |
| 97 | .type = MT_DEVICE, |
| 98 | }, { |
| 99 | .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS), |
| 100 | .pfn = __phys_to_pfn(S3C_PA_UART), |
| 101 | .length = SZ_4K, |
| 102 | .type = MT_DEVICE, |
| 103 | }, { |
| 104 | .virtual = (unsigned long)VA_VIC0, |
| 105 | .pfn = __phys_to_pfn(S3C64XX_PA_VIC0), |
| 106 | .length = SZ_16K, |
| 107 | .type = MT_DEVICE, |
| 108 | }, { |
| 109 | .virtual = (unsigned long)VA_VIC1, |
| 110 | .pfn = __phys_to_pfn(S3C64XX_PA_VIC1), |
| 111 | .length = SZ_16K, |
| 112 | .type = MT_DEVICE, |
| 113 | }, { |
| 114 | .virtual = (unsigned long)S3C_VA_TIMER, |
| 115 | .pfn = __phys_to_pfn(S3C_PA_TIMER), |
| 116 | .length = SZ_16K, |
| 117 | .type = MT_DEVICE, |
| 118 | }, { |
| 119 | .virtual = (unsigned long)S3C64XX_VA_GPIO, |
| 120 | .pfn = __phys_to_pfn(S3C64XX_PA_GPIO), |
| 121 | .length = SZ_4K, |
| 122 | .type = MT_DEVICE, |
| 123 | }, { |
| 124 | .virtual = (unsigned long)S3C64XX_VA_MODEM, |
| 125 | .pfn = __phys_to_pfn(S3C64XX_PA_MODEM), |
| 126 | .length = SZ_4K, |
| 127 | .type = MT_DEVICE, |
| 128 | }, { |
| 129 | .virtual = (unsigned long)S3C_VA_WATCHDOG, |
| 130 | .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG), |
| 131 | .length = SZ_4K, |
| 132 | .type = MT_DEVICE, |
| 133 | }, { |
| 134 | .virtual = (unsigned long)S3C_VA_USB_HSPHY, |
| 135 | .pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY), |
| 136 | .length = SZ_1K, |
| 137 | .type = MT_DEVICE, |
| 138 | }, |
| 139 | }; |
| 140 | |
| 141 | struct sysdev_class s3c64xx_sysclass = { |
| 142 | .name = "s3c64xx-core", |
| 143 | }; |
| 144 | |
| 145 | static struct sys_device s3c64xx_sysdev = { |
| 146 | .cls = &s3c64xx_sysclass, |
| 147 | }; |
| 148 | |
| 149 | /* read cpu identification code */ |
| 150 | |
| 151 | void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) |
| 152 | { |
| 153 | /* initialise the io descriptors we need for initialisation */ |
| 154 | iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); |
| 155 | iotable_init(mach_desc, size); |
| 156 | init_consistent_dma_size(SZ_8M); |
| 157 | |
| 158 | /* detect cpu id */ |
| 159 | s3c64xx_init_cpu(); |
| 160 | |
| 161 | s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); |
| 162 | } |
| 163 | |
| 164 | static __init int s3c64xx_sysdev_init(void) |
| 165 | { |
| 166 | sysdev_class_register(&s3c64xx_sysclass); |
| 167 | return sysdev_register(&s3c64xx_sysdev); |
| 168 | } |
| 169 | core_initcall(s3c64xx_sysdev_init); |
| 170 | |
| 171 | /* |
| 172 | * setup the sources the vic should advertise resume |
| 173 | * for, even though it is not doing the wake |
| 174 | * (set_irq_wake needs to be valid) |
| 175 | */ |
| 176 | #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE)) |
| 177 | #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \ |
| 178 | 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \ |
| 179 | 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \ |
| 180 | 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \ |
| 181 | 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE)) |
| 182 | |
| 183 | void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) |
| 184 | { |
| 185 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); |
| 186 | |
| 187 | /* initialise the pair of VICs */ |
| 188 | vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME); |
| 189 | vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME); |
| 190 | |
| 191 | /* add the timer sub-irqs */ |
| 192 | s3c_init_vic_timer_irq(5, IRQ_TIMER0); |
| 193 | } |
| 194 | |
| 195 | #define eint_offset(irq) ((irq) - IRQ_EINT(0)) |
| 196 | #define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq))) |
| 197 | |
| 198 | static inline void s3c_irq_eint_mask(struct irq_data *data) |
| 199 | { |
| 200 | u32 mask; |
| 201 | |
| 202 | mask = __raw_readl(S3C64XX_EINT0MASK); |
| 203 | mask |= (u32)data->chip_data; |
| 204 | __raw_writel(mask, S3C64XX_EINT0MASK); |
| 205 | } |
| 206 | |
| 207 | static void s3c_irq_eint_unmask(struct irq_data *data) |
| 208 | { |
| 209 | u32 mask; |
| 210 | |
| 211 | mask = __raw_readl(S3C64XX_EINT0MASK); |
| 212 | mask &= ~((u32)data->chip_data); |
| 213 | __raw_writel(mask, S3C64XX_EINT0MASK); |
| 214 | } |
| 215 | |
| 216 | static inline void s3c_irq_eint_ack(struct irq_data *data) |
| 217 | { |
| 218 | __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND); |
| 219 | } |
| 220 | |
| 221 | static void s3c_irq_eint_maskack(struct irq_data *data) |
| 222 | { |
| 223 | /* compiler should in-line these */ |
| 224 | s3c_irq_eint_mask(data); |
| 225 | s3c_irq_eint_ack(data); |
| 226 | } |
| 227 | |
| 228 | static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type) |
| 229 | { |
| 230 | int offs = eint_offset(data->irq); |
| 231 | int pin, pin_val; |
| 232 | int shift; |
| 233 | u32 ctrl, mask; |
| 234 | u32 newvalue = 0; |
| 235 | void __iomem *reg; |
| 236 | |
| 237 | if (offs > 27) |
| 238 | return -EINVAL; |
| 239 | |
| 240 | if (offs <= 15) |
| 241 | reg = S3C64XX_EINT0CON0; |
| 242 | else |
| 243 | reg = S3C64XX_EINT0CON1; |
| 244 | |
| 245 | switch (type) { |
| 246 | case IRQ_TYPE_NONE: |
| 247 | printk(KERN_WARNING "No edge setting!\n"); |
| 248 | break; |
| 249 | |
| 250 | case IRQ_TYPE_EDGE_RISING: |
| 251 | newvalue = S3C2410_EXTINT_RISEEDGE; |
| 252 | break; |
| 253 | |
| 254 | case IRQ_TYPE_EDGE_FALLING: |
| 255 | newvalue = S3C2410_EXTINT_FALLEDGE; |
| 256 | break; |
| 257 | |
| 258 | case IRQ_TYPE_EDGE_BOTH: |
| 259 | newvalue = S3C2410_EXTINT_BOTHEDGE; |
| 260 | break; |
| 261 | |
| 262 | case IRQ_TYPE_LEVEL_LOW: |
| 263 | newvalue = S3C2410_EXTINT_LOWLEV; |
| 264 | break; |
| 265 | |
| 266 | case IRQ_TYPE_LEVEL_HIGH: |
| 267 | newvalue = S3C2410_EXTINT_HILEV; |
| 268 | break; |
| 269 | |
| 270 | default: |
| 271 | printk(KERN_ERR "No such irq type %d", type); |
| 272 | return -1; |
| 273 | } |
| 274 | |
| 275 | if (offs <= 15) |
| 276 | shift = (offs / 2) * 4; |
| 277 | else |
| 278 | shift = ((offs - 16) / 2) * 4; |
| 279 | mask = 0x7 << shift; |
| 280 | |
| 281 | ctrl = __raw_readl(reg); |
| 282 | ctrl &= ~mask; |
| 283 | ctrl |= newvalue << shift; |
| 284 | __raw_writel(ctrl, reg); |
| 285 | |
| 286 | /* set the GPIO pin appropriately */ |
| 287 | |
| 288 | if (offs < 16) { |
| 289 | pin = S3C64XX_GPN(offs); |
| 290 | pin_val = S3C_GPIO_SFN(2); |
| 291 | } else if (offs < 23) { |
| 292 | pin = S3C64XX_GPL(offs + 8 - 16); |
| 293 | pin_val = S3C_GPIO_SFN(3); |
| 294 | } else { |
| 295 | pin = S3C64XX_GPM(offs - 23); |
| 296 | pin_val = S3C_GPIO_SFN(3); |
| 297 | } |
| 298 | |
| 299 | s3c_gpio_cfgpin(pin, pin_val); |
| 300 | |
| 301 | return 0; |
| 302 | } |
| 303 | |
| 304 | static struct irq_chip s3c_irq_eint = { |
| 305 | .name = "s3c-eint", |
| 306 | .irq_mask = s3c_irq_eint_mask, |
| 307 | .irq_unmask = s3c_irq_eint_unmask, |
| 308 | .irq_mask_ack = s3c_irq_eint_maskack, |
| 309 | .irq_ack = s3c_irq_eint_ack, |
| 310 | .irq_set_type = s3c_irq_eint_set_type, |
| 311 | .irq_set_wake = s3c_irqext_wake, |
| 312 | }; |
| 313 | |
| 314 | /* s3c_irq_demux_eint |
| 315 | * |
| 316 | * This function demuxes the IRQ from the group0 external interrupts, |
| 317 | * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into |
| 318 | * the specific handlers s3c_irq_demux_eintX_Y. |
| 319 | */ |
| 320 | static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end) |
| 321 | { |
| 322 | u32 status = __raw_readl(S3C64XX_EINT0PEND); |
| 323 | u32 mask = __raw_readl(S3C64XX_EINT0MASK); |
| 324 | unsigned int irq; |
| 325 | |
| 326 | status &= ~mask; |
| 327 | status >>= start; |
| 328 | status &= (1 << (end - start + 1)) - 1; |
| 329 | |
| 330 | for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { |
| 331 | if (status & 1) |
| 332 | generic_handle_irq(irq); |
| 333 | |
| 334 | status >>= 1; |
| 335 | } |
| 336 | } |
| 337 | |
| 338 | static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc) |
| 339 | { |
| 340 | s3c_irq_demux_eint(0, 3); |
| 341 | } |
| 342 | |
| 343 | static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc) |
| 344 | { |
| 345 | s3c_irq_demux_eint(4, 11); |
| 346 | } |
| 347 | |
| 348 | static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc) |
| 349 | { |
| 350 | s3c_irq_demux_eint(12, 19); |
| 351 | } |
| 352 | |
| 353 | static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc) |
| 354 | { |
| 355 | s3c_irq_demux_eint(20, 27); |
| 356 | } |
| 357 | |
| 358 | static int __init s3c64xx_init_irq_eint(void) |
| 359 | { |
| 360 | int irq; |
| 361 | |
| 362 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { |
| 363 | irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq); |
| 364 | irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq)); |
| 365 | set_irq_flags(irq, IRQF_VALID); |
| 366 | } |
| 367 | |
| 368 | irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); |
| 369 | irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); |
| 370 | irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); |
| 371 | irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); |
| 372 | |
| 373 | return 0; |
| 374 | } |
| 375 | arch_initcall(s3c64xx_init_irq_eint); |