David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1 | /* |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 2 | * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #define pr_fmt(fmt) "LCDB: %s: " fmt, __func__ |
| 15 | |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/device.h> |
| 18 | #include <linux/interrupt.h> |
Anirudh Ghayal | 264f927 | 2017-03-05 22:34:37 +0530 | [diff] [blame] | 19 | #include <linux/ktime.h> |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 20 | #include <linux/module.h> |
| 21 | #include <linux/of_irq.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/regmap.h> |
| 24 | #include <linux/regulator/driver.h> |
| 25 | #include <linux/regulator/of_regulator.h> |
| 26 | #include <linux/regulator/machine.h> |
Anirudh Ghayal | 968862c | 2017-03-31 15:34:05 +0530 | [diff] [blame] | 27 | #include <linux/qpnp/qpnp-revid.h> |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 28 | |
| 29 | #define QPNP_LCDB_REGULATOR_DRIVER_NAME "qcom,qpnp-lcdb-regulator" |
| 30 | |
| 31 | /* LCDB */ |
| 32 | #define LCDB_STS1_REG 0x08 |
| 33 | |
| 34 | #define INT_RT_STATUS_REG 0x10 |
| 35 | #define VREG_OK_RT_STS_BIT BIT(0) |
Anirudh Ghayal | 264f927 | 2017-03-05 22:34:37 +0530 | [diff] [blame] | 36 | #define SC_ERROR_RT_STS_BIT BIT(1) |
| 37 | |
| 38 | #define LCDB_STS3_REG 0x0A |
| 39 | #define LDO_VREG_OK_BIT BIT(7) |
| 40 | |
| 41 | #define LCDB_STS4_REG 0x0B |
| 42 | #define NCP_VREG_OK_BIT BIT(7) |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 43 | |
| 44 | #define LCDB_AUTO_TOUCH_WAKE_CTL_REG 0x40 |
| 45 | #define EN_AUTO_TOUCH_WAKE_BIT BIT(7) |
| 46 | #define ATTW_TOFF_TIME_MASK GENMASK(3, 2) |
| 47 | #define ATTW_TON_TIME_MASK GENMASK(1, 0) |
| 48 | #define ATTW_TOFF_TIME_SHIFT 2 |
| 49 | #define ATTW_MIN_MS 4 |
| 50 | #define ATTW_MAX_MS 32 |
| 51 | |
| 52 | #define LCDB_BST_OUTPUT_VOLTAGE_REG 0x41 |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 53 | #define PM660_BST_OUTPUT_VOLTAGE_MASK GENMASK(4, 0) |
| 54 | #define BST_OUTPUT_VOLTAGE_MASK GENMASK(5, 0) |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 55 | |
| 56 | #define LCDB_MODULE_RDY_REG 0x45 |
| 57 | #define MODULE_RDY_BIT BIT(7) |
| 58 | |
| 59 | #define LCDB_ENABLE_CTL1_REG 0x46 |
| 60 | #define MODULE_EN_BIT BIT(7) |
| 61 | #define HWEN_RDY_BIT BIT(6) |
| 62 | |
| 63 | /* BST */ |
| 64 | #define LCDB_BST_PD_CTL_REG 0x47 |
| 65 | #define BOOST_DIS_PULLDOWN_BIT BIT(1) |
| 66 | #define BOOST_PD_STRENGTH_BIT BIT(0) |
| 67 | |
| 68 | #define LCDB_BST_ILIM_CTL_REG 0x4B |
| 69 | #define EN_BST_ILIM_BIT BIT(7) |
| 70 | #define SET_BST_ILIM_MASK GENMASK(2, 0) |
| 71 | #define MIN_BST_ILIM_MA 200 |
| 72 | #define MAX_BST_ILIM_MA 1600 |
| 73 | |
| 74 | #define LCDB_PS_CTL_REG 0x50 |
| 75 | #define EN_PS_BIT BIT(7) |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 76 | #define PM660_PS_THRESH_MASK GENMASK(1, 0) |
| 77 | #define PS_THRESH_MASK GENMASK(2, 0) |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 78 | #define MIN_BST_PS_MA 50 |
| 79 | #define MAX_BST_PS_MA 80 |
| 80 | |
| 81 | #define LCDB_RDSON_MGMNT_REG 0x53 |
| 82 | #define NFET_SW_SIZE_MASK GENMASK(3, 2) |
| 83 | #define NFET_SW_SIZE_SHIFT 2 |
| 84 | #define PFET_SW_SIZE_MASK GENMASK(1, 0) |
| 85 | |
| 86 | #define LCDB_BST_VREG_OK_CTL_REG 0x55 |
| 87 | #define BST_VREG_OK_DEB_MASK GENMASK(1, 0) |
| 88 | |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 89 | #define LCDB_BST_SS_CTL_REG 0x5B |
| 90 | #define BST_SS_TIME_MASK GENMASK(1, 0) |
| 91 | #define BST_PRECHG_SHORT_ALARM_SHIFT 2 |
| 92 | #define BST_PRECHARGE_DONE_DEB_BIT BIT(4) |
| 93 | #define BST_SS_TIME_OVERRIDE_SHIFT 5 |
| 94 | |
| 95 | #define BST_SS_TIME_OVERRIDE_0MS 0 |
| 96 | #define BST_SS_TIME_OVERRIDE_0P5_MS 1 |
| 97 | #define BST_SS_TIME_OVERRIDE_1MS 2 |
| 98 | #define BST_SS_TIME_OVERRIDE_2MS 3 |
| 99 | |
| 100 | #define EN_BST_PRECHG_SHORT_ALARM 0 |
| 101 | #define DIS_BST_PRECHG_SHORT_ALARM 1 |
| 102 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 103 | #define LCDB_SOFT_START_CTL_REG 0x5F |
| 104 | |
| 105 | #define LCDB_MISC_CTL_REG 0x60 |
| 106 | #define AUTO_GM_EN_BIT BIT(4) |
| 107 | #define EN_TOUCH_WAKE_BIT BIT(3) |
| 108 | #define DIS_SCP_BIT BIT(0) |
| 109 | |
| 110 | #define LCDB_PFM_CTL_REG 0x62 |
| 111 | #define EN_PFM_BIT BIT(7) |
| 112 | #define BYP_BST_SOFT_START_COMP_BIT BIT(0) |
| 113 | #define PFM_HYSTERESIS_SHIFT 4 |
| 114 | #define PFM_CURRENT_SHIFT 2 |
| 115 | |
| 116 | #define LCDB_PWRUP_PWRDN_CTL_REG 0x66 |
| 117 | |
| 118 | /* LDO */ |
| 119 | #define LCDB_LDO_OUTPUT_VOLTAGE_REG 0x71 |
| 120 | #define SET_OUTPUT_VOLTAGE_MASK GENMASK(4, 0) |
| 121 | |
| 122 | #define LCDB_LDO_VREG_OK_CTL_REG 0x75 |
| 123 | #define VREG_OK_DEB_MASK GENMASK(1, 0) |
| 124 | |
| 125 | #define LCDB_LDO_PD_CTL_REG 0x77 |
| 126 | #define LDO_DIS_PULLDOWN_BIT BIT(1) |
| 127 | #define LDO_PD_STRENGTH_BIT BIT(0) |
| 128 | |
| 129 | #define LCDB_LDO_ILIM_CTL1_REG 0x7B |
| 130 | #define EN_LDO_ILIM_BIT BIT(7) |
| 131 | #define SET_LDO_ILIM_MASK GENMASK(2, 0) |
| 132 | #define MIN_LDO_ILIM_MA 110 |
| 133 | #define MAX_LDO_ILIM_MA 460 |
| 134 | #define LDO_ILIM_STEP_MA 50 |
| 135 | |
| 136 | #define LCDB_LDO_ILIM_CTL2_REG 0x7C |
| 137 | |
| 138 | #define LCDB_LDO_SOFT_START_CTL_REG 0x7F |
| 139 | #define SOFT_START_MASK GENMASK(1, 0) |
| 140 | |
| 141 | /* NCP */ |
| 142 | #define LCDB_NCP_OUTPUT_VOLTAGE_REG 0x81 |
| 143 | |
| 144 | #define LCDB_NCP_VREG_OK_CTL_REG 0x85 |
| 145 | |
| 146 | #define LCDB_NCP_PD_CTL_REG 0x87 |
| 147 | #define NCP_DIS_PULLDOWN_BIT BIT(1) |
| 148 | #define NCP_PD_STRENGTH_BIT BIT(0) |
| 149 | |
| 150 | #define LCDB_NCP_ILIM_CTL1_REG 0x8B |
| 151 | #define EN_NCP_ILIM_BIT BIT(7) |
| 152 | #define SET_NCP_ILIM_MASK GENMASK(1, 0) |
| 153 | #define MIN_NCP_ILIM_MA 260 |
| 154 | #define MAX_NCP_ILIM_MA 810 |
| 155 | |
| 156 | #define LCDB_NCP_ILIM_CTL2_REG 0x8C |
| 157 | |
| 158 | #define LCDB_NCP_SOFT_START_CTL_REG 0x8F |
| 159 | |
| 160 | /* common for BST/NCP/LDO */ |
| 161 | #define MIN_DBC_US 2 |
| 162 | #define MAX_DBC_US 32 |
| 163 | |
| 164 | #define MIN_SOFT_START_US 0 |
| 165 | #define MAX_SOFT_START_US 2000 |
| 166 | |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 167 | #define PM660_BST_HEADROOM_DEFAULT_MV 200 |
| 168 | #define BST_HEADROOM_DEFAULT_MV 150 |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 169 | |
Kiran Gunda | df7fa66 | 2018-06-11 12:41:51 +0530 | [diff] [blame] | 170 | #define PMIC5_LCDB_OFF_ON_DELAY_US 20000 |
| 171 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 172 | struct ldo_regulator { |
| 173 | struct regulator_desc rdesc; |
| 174 | struct regulator_dev *rdev; |
| 175 | struct device_node *node; |
| 176 | |
| 177 | /* LDO DT params */ |
| 178 | int pd; |
| 179 | int pd_strength; |
| 180 | int ilim_ma; |
| 181 | int soft_start_us; |
| 182 | int vreg_ok_dbc_us; |
| 183 | int voltage_mv; |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 184 | int prev_voltage_mv; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 185 | }; |
| 186 | |
| 187 | struct ncp_regulator { |
| 188 | struct regulator_desc rdesc; |
| 189 | struct regulator_dev *rdev; |
| 190 | struct device_node *node; |
| 191 | |
| 192 | /* NCP DT params */ |
| 193 | int pd; |
| 194 | int pd_strength; |
| 195 | int ilim_ma; |
| 196 | int soft_start_us; |
| 197 | int vreg_ok_dbc_us; |
| 198 | int voltage_mv; |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 199 | int prev_voltage_mv; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 200 | }; |
| 201 | |
| 202 | struct bst_params { |
| 203 | struct device_node *node; |
| 204 | |
| 205 | /* BST DT params */ |
| 206 | int pd; |
| 207 | int pd_strength; |
| 208 | int ilim_ma; |
| 209 | int ps; |
| 210 | int ps_threshold; |
| 211 | int soft_start_us; |
| 212 | int vreg_ok_dbc_us; |
| 213 | int voltage_mv; |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 214 | u16 headroom_mv; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 215 | }; |
| 216 | |
| 217 | struct qpnp_lcdb { |
| 218 | struct device *dev; |
| 219 | struct platform_device *pdev; |
| 220 | struct regmap *regmap; |
Kavya Nunna | 80bc150 | 2018-10-01 14:50:23 +0530 | [diff] [blame] | 221 | struct class lcdb_class; |
Anirudh Ghayal | 968862c | 2017-03-31 15:34:05 +0530 | [diff] [blame] | 222 | struct pmic_revid_data *pmic_rev_id; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 223 | u32 base; |
Kiran Gunda | a722892 | 2018-06-27 11:14:21 +0530 | [diff] [blame] | 224 | u32 wa_flags; |
Anirudh Ghayal | 264f927 | 2017-03-05 22:34:37 +0530 | [diff] [blame] | 225 | int sc_irq; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 226 | |
| 227 | /* TTW params */ |
| 228 | bool ttw_enable; |
| 229 | bool ttw_mode_sw; |
| 230 | |
| 231 | /* status parameters */ |
| 232 | bool lcdb_enabled; |
| 233 | bool settings_saved; |
Anirudh Ghayal | 264f927 | 2017-03-05 22:34:37 +0530 | [diff] [blame] | 234 | bool lcdb_sc_disable; |
Kavya Nunna | 80bc150 | 2018-10-01 14:50:23 +0530 | [diff] [blame] | 235 | bool secure_mode; |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 236 | bool voltage_step_ramp; |
Anirudh Ghayal | 264f927 | 2017-03-05 22:34:37 +0530 | [diff] [blame] | 237 | int sc_count; |
| 238 | ktime_t sc_module_enable_time; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 239 | |
| 240 | struct mutex lcdb_mutex; |
| 241 | struct mutex read_write_mutex; |
| 242 | struct bst_params bst; |
| 243 | struct ldo_regulator ldo; |
| 244 | struct ncp_regulator ncp; |
| 245 | }; |
| 246 | |
| 247 | struct settings { |
| 248 | u16 address; |
| 249 | u8 value; |
| 250 | bool sec_access; |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 251 | bool valid; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 252 | }; |
| 253 | |
| 254 | enum lcdb_module { |
| 255 | LDO, |
| 256 | NCP, |
| 257 | BST, |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 258 | LDO_NCP, |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 259 | }; |
| 260 | |
| 261 | enum pfm_hysteresis { |
| 262 | PFM_HYST_15MV, |
| 263 | PFM_HYST_25MV, |
| 264 | PFM_HYST_35MV, |
| 265 | PFM_HYST_45MV, |
| 266 | }; |
| 267 | |
| 268 | enum pfm_peak_current { |
| 269 | PFM_PEAK_CURRENT_300MA, |
| 270 | PFM_PEAK_CURRENT_400MA, |
| 271 | PFM_PEAK_CURRENT_500MA, |
| 272 | PFM_PEAK_CURRENT_600MA, |
| 273 | }; |
| 274 | |
| 275 | enum rdson_fet_size { |
| 276 | RDSON_QUARTER, |
| 277 | RDSON_HALF, |
| 278 | RDSON_THREE_FOURTH, |
| 279 | RDSON_FULLSIZE, |
| 280 | }; |
| 281 | |
| 282 | enum lcdb_settings_index { |
| 283 | LCDB_BST_PD_CTL = 0, |
| 284 | LCDB_RDSON_MGMNT, |
| 285 | LCDB_MISC_CTL, |
| 286 | LCDB_SOFT_START_CTL, |
| 287 | LCDB_PFM_CTL, |
| 288 | LCDB_PWRUP_PWRDN_CTL, |
| 289 | LCDB_LDO_PD_CTL, |
| 290 | LCDB_LDO_SOFT_START_CTL, |
| 291 | LCDB_NCP_PD_CTL, |
| 292 | LCDB_NCP_SOFT_START_CTL, |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 293 | LCDB_BST_SS_CTL, |
| 294 | LCDB_LDO_VREG_OK_CTL, |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 295 | LCDB_SETTING_MAX, |
| 296 | }; |
| 297 | |
Kiran Gunda | a722892 | 2018-06-27 11:14:21 +0530 | [diff] [blame] | 298 | enum lcdb_wa_flags { |
| 299 | NCP_SCP_DISABLE_WA = BIT(0), |
| 300 | }; |
| 301 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 302 | static u32 soft_start_us[] = { |
| 303 | 0, |
| 304 | 500, |
| 305 | 1000, |
| 306 | 2000, |
| 307 | }; |
| 308 | |
| 309 | static u32 dbc_us[] = { |
| 310 | 2, |
| 311 | 4, |
| 312 | 16, |
| 313 | 32, |
| 314 | }; |
| 315 | |
| 316 | static u32 ncp_ilim_ma[] = { |
| 317 | 260, |
| 318 | 460, |
| 319 | 640, |
| 320 | 810, |
| 321 | }; |
| 322 | |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 323 | #define SETTING(_id, _sec_access, _valid) \ |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 324 | [_id] = { \ |
| 325 | .address = _id##_REG, \ |
| 326 | .sec_access = _sec_access, \ |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 327 | .valid = _valid \ |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 328 | } \ |
| 329 | |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 330 | static int qpnp_lcdb_set_voltage_step(struct qpnp_lcdb *lcdb, |
| 331 | int voltage_start_mv, u8 type); |
| 332 | |
| 333 | static int qpnp_lcdb_set_voltage(struct qpnp_lcdb *lcdb, |
| 334 | int voltage_mv, u8 type); |
| 335 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 336 | static bool is_between(int value, int min, int max) |
| 337 | { |
| 338 | if (value < min || value > max) |
| 339 | return false; |
| 340 | return true; |
| 341 | } |
| 342 | |
| 343 | static int qpnp_lcdb_read(struct qpnp_lcdb *lcdb, |
| 344 | u16 addr, u8 *value, u8 count) |
| 345 | { |
| 346 | int rc = 0; |
| 347 | |
| 348 | mutex_lock(&lcdb->read_write_mutex); |
| 349 | rc = regmap_bulk_read(lcdb->regmap, addr, value, count); |
| 350 | if (rc < 0) |
| 351 | pr_err("Failed to read from addr=0x%02x rc=%d\n", addr, rc); |
| 352 | mutex_unlock(&lcdb->read_write_mutex); |
| 353 | |
| 354 | return rc; |
| 355 | } |
| 356 | |
| 357 | static int qpnp_lcdb_write(struct qpnp_lcdb *lcdb, |
| 358 | u16 addr, u8 *value, u8 count) |
| 359 | { |
| 360 | int rc; |
| 361 | |
| 362 | mutex_lock(&lcdb->read_write_mutex); |
| 363 | rc = regmap_bulk_write(lcdb->regmap, addr, value, count); |
| 364 | if (rc < 0) |
| 365 | pr_err("Failed to write to addr=0x%02x rc=%d\n", addr, rc); |
| 366 | mutex_unlock(&lcdb->read_write_mutex); |
| 367 | |
| 368 | return rc; |
| 369 | } |
| 370 | |
| 371 | #define SEC_ADDRESS_REG 0xD0 |
| 372 | #define SECURE_UNLOCK_VALUE 0xA5 |
| 373 | static int qpnp_lcdb_secure_write(struct qpnp_lcdb *lcdb, |
| 374 | u16 addr, u8 value) |
| 375 | { |
| 376 | int rc; |
| 377 | u8 val = SECURE_UNLOCK_VALUE; |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 378 | u8 pmic_subtype = lcdb->pmic_rev_id->pmic_subtype; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 379 | |
| 380 | mutex_lock(&lcdb->read_write_mutex); |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 381 | if (pmic_subtype == PM660L_SUBTYPE) { |
| 382 | rc = regmap_write(lcdb->regmap, lcdb->base + SEC_ADDRESS_REG, |
| 383 | val); |
| 384 | if (rc < 0) { |
| 385 | pr_err("Failed to unlock register rc=%d\n", rc); |
| 386 | goto fail_write; |
| 387 | } |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 388 | } |
| 389 | rc = regmap_write(lcdb->regmap, addr, value); |
| 390 | if (rc < 0) |
| 391 | pr_err("Failed to write to addr=0x%02x rc=%d\n", addr, rc); |
| 392 | |
| 393 | fail_write: |
| 394 | mutex_unlock(&lcdb->read_write_mutex); |
| 395 | return rc; |
| 396 | } |
| 397 | |
| 398 | static int qpnp_lcdb_masked_write(struct qpnp_lcdb *lcdb, |
| 399 | u16 addr, u8 mask, u8 value) |
| 400 | { |
| 401 | int rc = 0; |
| 402 | |
| 403 | mutex_lock(&lcdb->read_write_mutex); |
| 404 | rc = regmap_update_bits(lcdb->regmap, addr, mask, value); |
| 405 | if (rc < 0) |
| 406 | pr_err("Failed to write addr=0x%02x value=0x%02x rc=%d\n", |
| 407 | addr, value, rc); |
| 408 | mutex_unlock(&lcdb->read_write_mutex); |
| 409 | |
| 410 | return rc; |
| 411 | } |
| 412 | |
| 413 | static bool is_lcdb_enabled(struct qpnp_lcdb *lcdb) |
| 414 | { |
| 415 | int rc; |
| 416 | u8 val = 0; |
| 417 | |
| 418 | rc = qpnp_lcdb_read(lcdb, lcdb->base + LCDB_ENABLE_CTL1_REG, &val, 1); |
| 419 | if (rc < 0) |
| 420 | pr_err("Failed to read ENABLE_CTL1 rc=%d\n", rc); |
| 421 | |
| 422 | return rc ? false : !!(val & MODULE_EN_BIT); |
| 423 | } |
| 424 | |
| 425 | static int dump_status_registers(struct qpnp_lcdb *lcdb) |
| 426 | { |
| 427 | int rc = 0; |
| 428 | u8 sts[6] = {0}; |
| 429 | |
| 430 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_STS1_REG, &sts[0], 6); |
| 431 | if (rc < 0) { |
| 432 | pr_err("Failed to write to STS registers rc=%d\n", rc); |
| 433 | } else { |
| 434 | rc = qpnp_lcdb_read(lcdb, lcdb->base + LCDB_STS1_REG, sts, 6); |
| 435 | if (rc < 0) |
| 436 | pr_err("Failed to read lcdb status rc=%d\n", rc); |
| 437 | else |
| 438 | pr_err("STS1=0x%02x STS2=0x%02x STS3=0x%02x STS4=0x%02x STS5=0x%02x, STS6=0x%02x\n", |
| 439 | sts[0], sts[1], sts[2], sts[3], sts[4], sts[5]); |
| 440 | } |
| 441 | |
| 442 | return rc; |
| 443 | } |
| 444 | |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 445 | static struct settings lcdb_settings_pm660l[] = { |
| 446 | SETTING(LCDB_BST_PD_CTL, false, true), |
| 447 | SETTING(LCDB_RDSON_MGMNT, false, true), |
| 448 | SETTING(LCDB_MISC_CTL, false, true), |
| 449 | SETTING(LCDB_SOFT_START_CTL, false, true), |
| 450 | SETTING(LCDB_PFM_CTL, false, true), |
| 451 | SETTING(LCDB_PWRUP_PWRDN_CTL, true, true), |
| 452 | SETTING(LCDB_LDO_PD_CTL, false, true), |
| 453 | SETTING(LCDB_LDO_SOFT_START_CTL, false, true), |
| 454 | SETTING(LCDB_NCP_PD_CTL, false, true), |
| 455 | SETTING(LCDB_NCP_SOFT_START_CTL, false, true), |
| 456 | SETTING(LCDB_BST_SS_CTL, false, false), |
| 457 | SETTING(LCDB_LDO_VREG_OK_CTL, false, false), |
| 458 | }; |
| 459 | |
| 460 | /* For PMICs like pmi632/pm855L */ |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 461 | static struct settings lcdb_settings[] = { |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 462 | SETTING(LCDB_BST_PD_CTL, false, true), |
| 463 | SETTING(LCDB_RDSON_MGMNT, false, false), |
| 464 | SETTING(LCDB_MISC_CTL, false, false), |
| 465 | SETTING(LCDB_SOFT_START_CTL, false, false), |
| 466 | SETTING(LCDB_PFM_CTL, false, false), |
| 467 | SETTING(LCDB_PWRUP_PWRDN_CTL, false, true), |
| 468 | SETTING(LCDB_LDO_PD_CTL, false, true), |
| 469 | SETTING(LCDB_LDO_SOFT_START_CTL, false, true), |
| 470 | SETTING(LCDB_NCP_PD_CTL, false, true), |
| 471 | SETTING(LCDB_NCP_SOFT_START_CTL, false, true), |
| 472 | SETTING(LCDB_BST_SS_CTL, false, true), |
| 473 | SETTING(LCDB_LDO_VREG_OK_CTL, false, true), |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 474 | }; |
| 475 | |
| 476 | static int qpnp_lcdb_save_settings(struct qpnp_lcdb *lcdb) |
| 477 | { |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 478 | int i, size, rc = 0; |
| 479 | struct settings *setting; |
| 480 | u16 pmic_subtype = lcdb->pmic_rev_id->pmic_subtype; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 481 | |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 482 | if (pmic_subtype == PM660L_SUBTYPE) { |
| 483 | setting = lcdb_settings_pm660l; |
| 484 | size = ARRAY_SIZE(lcdb_settings_pm660l); |
| 485 | } else { |
| 486 | setting = lcdb_settings; |
| 487 | size = ARRAY_SIZE(lcdb_settings); |
| 488 | } |
| 489 | |
| 490 | for (i = 0; i < size; i++) { |
| 491 | if (setting[i].valid) { |
| 492 | rc = qpnp_lcdb_read(lcdb, lcdb->base + |
| 493 | setting[i].address, |
| 494 | &setting[i].value, 1); |
| 495 | if (rc < 0) { |
| 496 | pr_err("Failed to read lcdb register address=%x\n", |
| 497 | setting[i].address); |
| 498 | return rc; |
| 499 | } |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 500 | } |
| 501 | } |
| 502 | |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 503 | return 0; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 504 | } |
| 505 | |
| 506 | static int qpnp_lcdb_restore_settings(struct qpnp_lcdb *lcdb) |
| 507 | { |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 508 | int i, size, rc = 0; |
| 509 | struct settings *setting; |
| 510 | u16 pmic_subtype = lcdb->pmic_rev_id->pmic_subtype; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 511 | |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 512 | if (pmic_subtype == PM660L_SUBTYPE) { |
| 513 | setting = lcdb_settings_pm660l; |
| 514 | size = ARRAY_SIZE(lcdb_settings_pm660l); |
| 515 | } else { |
| 516 | setting = lcdb_settings; |
| 517 | size = ARRAY_SIZE(lcdb_settings); |
| 518 | } |
| 519 | |
| 520 | for (i = 0; i < size; i++) { |
| 521 | if (setting[i].valid) { |
| 522 | if (setting[i].sec_access) |
| 523 | rc = qpnp_lcdb_secure_write(lcdb, lcdb->base + |
| 524 | setting[i].address, |
| 525 | setting[i].value); |
| 526 | else |
| 527 | rc = qpnp_lcdb_write(lcdb, lcdb->base + |
| 528 | setting[i].address, |
| 529 | &setting[i].value, 1); |
| 530 | if (rc < 0) { |
| 531 | pr_err("Failed to write register address=%x\n", |
| 532 | setting[i].address); |
| 533 | return rc; |
| 534 | } |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 535 | } |
| 536 | } |
| 537 | |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 538 | return 0; |
| 539 | } |
| 540 | |
| 541 | static int qpnp_lcdb_ttw_enter(struct qpnp_lcdb *lcdb) |
| 542 | { |
| 543 | int rc; |
| 544 | u8 val; |
| 545 | |
| 546 | if (!lcdb->settings_saved) { |
| 547 | rc = qpnp_lcdb_save_settings(lcdb); |
| 548 | if (rc < 0) { |
| 549 | pr_err("Failed to save LCDB settings rc=%d\n", rc); |
| 550 | return rc; |
| 551 | } |
| 552 | lcdb->settings_saved = true; |
| 553 | } |
| 554 | |
| 555 | val = HWEN_RDY_BIT; |
| 556 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_ENABLE_CTL1_REG, |
| 557 | &val, 1); |
| 558 | if (rc < 0) { |
| 559 | pr_err("Failed to hw_enable lcdb rc= %d\n", rc); |
| 560 | return rc; |
| 561 | } |
| 562 | |
| 563 | val = (BST_SS_TIME_OVERRIDE_1MS << BST_SS_TIME_OVERRIDE_SHIFT) | |
| 564 | (DIS_BST_PRECHG_SHORT_ALARM << BST_PRECHG_SHORT_ALARM_SHIFT); |
| 565 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_BST_SS_CTL_REG, &val, 1); |
| 566 | if (rc < 0) |
| 567 | return rc; |
| 568 | |
| 569 | val = 0; |
| 570 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_LDO_SOFT_START_CTL_REG, |
| 571 | &val, 1); |
| 572 | if (rc < 0) |
| 573 | return rc; |
| 574 | |
| 575 | val = 0; |
| 576 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_NCP_SOFT_START_CTL_REG, |
| 577 | &val, 1); |
| 578 | if (rc < 0) |
| 579 | return rc; |
| 580 | |
| 581 | val = BOOST_DIS_PULLDOWN_BIT | BOOST_PD_STRENGTH_BIT; |
| 582 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_BST_PD_CTL_REG, |
| 583 | &val, 1); |
| 584 | if (rc < 0) |
| 585 | return rc; |
| 586 | |
| 587 | val = LDO_DIS_PULLDOWN_BIT | LDO_PD_STRENGTH_BIT; |
| 588 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_LDO_PD_CTL_REG, |
| 589 | &val, 1); |
| 590 | if (rc < 0) |
| 591 | return rc; |
| 592 | |
| 593 | val = NCP_DIS_PULLDOWN_BIT | NCP_PD_STRENGTH_BIT; |
| 594 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_NCP_PD_CTL_REG, |
| 595 | &val, 1); |
| 596 | if (rc < 0) |
| 597 | return rc; |
| 598 | |
| 599 | val = 0; |
| 600 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_PWRUP_PWRDN_CTL_REG, |
| 601 | &val, 1); |
| 602 | if (rc < 0) |
| 603 | return rc; |
| 604 | |
| 605 | val = 0; |
| 606 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_BST_VREG_OK_CTL_REG, |
| 607 | &val, 1); |
| 608 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 609 | return rc; |
| 610 | } |
| 611 | |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 612 | static int qpnp_lcdb_ttw_enter_pm660l(struct qpnp_lcdb *lcdb) |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 613 | { |
| 614 | int rc; |
| 615 | u8 val; |
| 616 | |
| 617 | if (!lcdb->settings_saved) { |
| 618 | rc = qpnp_lcdb_save_settings(lcdb); |
| 619 | if (rc < 0) { |
| 620 | pr_err("Failed to save LCDB settings rc=%d\n", rc); |
| 621 | return rc; |
| 622 | } |
| 623 | lcdb->settings_saved = true; |
| 624 | } |
| 625 | |
| 626 | val = BOOST_DIS_PULLDOWN_BIT; |
| 627 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_BST_PD_CTL_REG, |
| 628 | &val, 1); |
| 629 | if (rc < 0) { |
| 630 | pr_err("Failed to set BST PD rc=%d\n", rc); |
| 631 | return rc; |
| 632 | } |
| 633 | |
| 634 | val = (RDSON_HALF << NFET_SW_SIZE_SHIFT) | RDSON_HALF; |
| 635 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_RDSON_MGMNT_REG, |
| 636 | &val, 1); |
| 637 | if (rc < 0) { |
| 638 | pr_err("Failed to set RDSON MGMT rc=%d\n", rc); |
| 639 | return rc; |
| 640 | } |
| 641 | |
| 642 | val = AUTO_GM_EN_BIT | EN_TOUCH_WAKE_BIT | DIS_SCP_BIT; |
| 643 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_MISC_CTL_REG, |
| 644 | &val, 1); |
| 645 | if (rc < 0) { |
| 646 | pr_err("Failed to set MISC CTL rc=%d\n", rc); |
| 647 | return rc; |
| 648 | } |
| 649 | |
| 650 | val = 0; |
| 651 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_SOFT_START_CTL_REG, |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 652 | &val, 1); |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 653 | if (rc < 0) { |
| 654 | pr_err("Failed to set LCDB_SOFT_START rc=%d\n", rc); |
| 655 | return rc; |
| 656 | } |
| 657 | |
| 658 | val = EN_PFM_BIT | (PFM_HYST_25MV << PFM_HYSTERESIS_SHIFT) | |
| 659 | (PFM_PEAK_CURRENT_400MA << PFM_CURRENT_SHIFT) | |
| 660 | BYP_BST_SOFT_START_COMP_BIT; |
| 661 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_PFM_CTL_REG, |
| 662 | &val, 1); |
| 663 | if (rc < 0) { |
| 664 | pr_err("Failed to set PFM_CTL rc=%d\n", rc); |
| 665 | return rc; |
| 666 | } |
| 667 | |
| 668 | val = 0; |
| 669 | rc = qpnp_lcdb_secure_write(lcdb, lcdb->base + LCDB_PWRUP_PWRDN_CTL_REG, |
| 670 | val); |
| 671 | if (rc < 0) { |
| 672 | pr_err("Failed to set PWRUP_PWRDN_CTL rc=%d\n", rc); |
| 673 | return rc; |
| 674 | } |
| 675 | |
| 676 | val = LDO_DIS_PULLDOWN_BIT; |
| 677 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_LDO_PD_CTL_REG, |
| 678 | &val, 1); |
| 679 | if (rc < 0) { |
| 680 | pr_err("Failed to set LDO_PD_CTL rc=%d\n", rc); |
| 681 | return rc; |
| 682 | } |
| 683 | |
| 684 | val = 0; |
| 685 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_LDO_SOFT_START_CTL_REG, |
| 686 | &val, 1); |
| 687 | if (rc < 0) { |
| 688 | pr_err("Failed to set LDO_SOFT_START rc=%d\n", rc); |
| 689 | return rc; |
| 690 | } |
| 691 | |
| 692 | val = NCP_DIS_PULLDOWN_BIT; |
| 693 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_NCP_PD_CTL_REG, |
| 694 | &val, 1); |
| 695 | if (rc < 0) { |
| 696 | pr_err("Failed to set NCP_PD_CTL rc=%d\n", rc); |
| 697 | return rc; |
| 698 | } |
| 699 | |
| 700 | val = 0; |
| 701 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_NCP_SOFT_START_CTL_REG, |
| 702 | &val, 1); |
| 703 | if (rc < 0) { |
| 704 | pr_err("Failed to set NCP_SOFT_START rc=%d\n", rc); |
| 705 | return rc; |
| 706 | } |
| 707 | |
| 708 | if (lcdb->ttw_mode_sw) { |
| 709 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
| 710 | LCDB_AUTO_TOUCH_WAKE_CTL_REG, |
| 711 | EN_AUTO_TOUCH_WAKE_BIT, |
| 712 | EN_AUTO_TOUCH_WAKE_BIT); |
| 713 | if (rc < 0) |
| 714 | pr_err("Failed to enable auto(sw) TTW\n rc = %d\n", rc); |
| 715 | } else { |
| 716 | val = HWEN_RDY_BIT; |
| 717 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_ENABLE_CTL1_REG, |
| 718 | &val, 1); |
| 719 | if (rc < 0) |
| 720 | pr_err("Failed to hw_enable lcdb rc= %d\n", rc); |
| 721 | } |
| 722 | |
| 723 | return rc; |
| 724 | } |
| 725 | |
| 726 | static int qpnp_lcdb_ttw_exit(struct qpnp_lcdb *lcdb) |
| 727 | { |
| 728 | int rc; |
| 729 | |
| 730 | if (lcdb->settings_saved) { |
| 731 | rc = qpnp_lcdb_restore_settings(lcdb); |
| 732 | if (rc < 0) { |
| 733 | pr_err("Failed to restore lcdb settings rc=%d\n", rc); |
| 734 | return rc; |
| 735 | } |
| 736 | lcdb->settings_saved = false; |
| 737 | } |
| 738 | |
| 739 | return 0; |
| 740 | } |
| 741 | |
Anirudh Ghayal | 968862c | 2017-03-31 15:34:05 +0530 | [diff] [blame] | 742 | static int qpnp_lcdb_enable_wa(struct qpnp_lcdb *lcdb) |
| 743 | { |
| 744 | int rc; |
| 745 | u8 val = 0; |
| 746 | |
| 747 | /* required only for PM660L */ |
| 748 | if (lcdb->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE) |
| 749 | return 0; |
| 750 | |
| 751 | val = MODULE_EN_BIT; |
| 752 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_ENABLE_CTL1_REG, |
| 753 | &val, 1); |
| 754 | if (rc < 0) { |
| 755 | pr_err("Failed to enable lcdb rc= %d\n", rc); |
| 756 | return rc; |
| 757 | } |
| 758 | |
| 759 | val = 0; |
| 760 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_ENABLE_CTL1_REG, |
| 761 | &val, 1); |
| 762 | if (rc < 0) { |
| 763 | pr_err("Failed to disable lcdb rc= %d\n", rc); |
| 764 | return rc; |
| 765 | } |
| 766 | |
Kiran Gunda | a722892 | 2018-06-27 11:14:21 +0530 | [diff] [blame] | 767 | if (lcdb->wa_flags & NCP_SCP_DISABLE_WA) { |
Anirudh Ghayal | 968862c | 2017-03-31 15:34:05 +0530 | [diff] [blame] | 768 | /* |
| 769 | * delay to make sure that the MID pin – ie the |
| 770 | * output of the LCDB boost – returns to 0V |
| 771 | * after the module is disabled |
| 772 | */ |
| 773 | usleep_range(10000, 10100); |
| 774 | |
| 775 | rc = qpnp_lcdb_masked_write(lcdb, |
| 776 | lcdb->base + LCDB_MISC_CTL_REG, |
| 777 | DIS_SCP_BIT, DIS_SCP_BIT); |
| 778 | if (rc < 0) { |
| 779 | pr_err("Failed to disable SC rc=%d\n", rc); |
| 780 | return rc; |
| 781 | } |
| 782 | /* delay for SC-disable to take effect */ |
| 783 | usleep_range(1000, 1100); |
| 784 | |
| 785 | rc = qpnp_lcdb_masked_write(lcdb, |
| 786 | lcdb->base + LCDB_MISC_CTL_REG, |
| 787 | DIS_SCP_BIT, 0); |
| 788 | if (rc < 0) { |
| 789 | pr_err("Failed to enable SC rc=%d\n", rc); |
| 790 | return rc; |
| 791 | } |
| 792 | /* delay for SC-enable to take effect */ |
| 793 | usleep_range(1000, 1100); |
| 794 | } |
| 795 | |
| 796 | return 0; |
| 797 | } |
| 798 | |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 799 | #define VOLTAGE_START_MV 4500 |
| 800 | #define VOLTAGE_STEP_MV 500 |
| 801 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 802 | static int qpnp_lcdb_enable(struct qpnp_lcdb *lcdb) |
| 803 | { |
| 804 | int rc = 0, timeout, delay; |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 805 | int voltage_mv = VOLTAGE_START_MV; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 806 | u8 val = 0; |
| 807 | |
Anirudh Ghayal | 264f927 | 2017-03-05 22:34:37 +0530 | [diff] [blame] | 808 | if (lcdb->lcdb_enabled || lcdb->lcdb_sc_disable) { |
| 809 | pr_debug("lcdb_enabled=%d lcdb_sc_disable=%d\n", |
| 810 | lcdb->lcdb_enabled, lcdb->lcdb_sc_disable); |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 811 | return 0; |
Anirudh Ghayal | 264f927 | 2017-03-05 22:34:37 +0530 | [diff] [blame] | 812 | } |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 813 | |
| 814 | if (lcdb->ttw_enable) { |
| 815 | rc = qpnp_lcdb_ttw_exit(lcdb); |
| 816 | if (rc < 0) { |
| 817 | pr_err("Failed to exit TTW mode rc=%d\n", rc); |
| 818 | return rc; |
| 819 | } |
| 820 | } |
| 821 | |
Anirudh Ghayal | 968862c | 2017-03-31 15:34:05 +0530 | [diff] [blame] | 822 | rc = qpnp_lcdb_enable_wa(lcdb); |
| 823 | if (rc < 0) { |
| 824 | pr_err("Failed to execute enable_wa rc=%d\n", rc); |
| 825 | return rc; |
| 826 | } |
| 827 | |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 828 | if (lcdb->voltage_step_ramp) { |
| 829 | if (lcdb->ldo.voltage_mv < VOLTAGE_START_MV) |
| 830 | voltage_mv = lcdb->ldo.voltage_mv; |
| 831 | |
| 832 | rc = qpnp_lcdb_set_voltage(lcdb, voltage_mv, LDO); |
| 833 | if (rc < 0) |
| 834 | return rc; |
| 835 | |
| 836 | if (lcdb->ncp.voltage_mv < VOLTAGE_START_MV) |
| 837 | voltage_mv = lcdb->ncp.voltage_mv; |
| 838 | |
| 839 | rc = qpnp_lcdb_set_voltage(lcdb, voltage_mv, NCP); |
| 840 | if (rc < 0) |
| 841 | return rc; |
| 842 | } |
| 843 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 844 | val = MODULE_EN_BIT; |
| 845 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_ENABLE_CTL1_REG, |
| 846 | &val, 1); |
| 847 | if (rc < 0) { |
Anirudh Ghayal | 968862c | 2017-03-31 15:34:05 +0530 | [diff] [blame] | 848 | pr_err("Failed to disable lcdb rc= %d\n", rc); |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 849 | goto fail_enable; |
| 850 | } |
| 851 | |
| 852 | /* poll for vreg_ok */ |
| 853 | timeout = 10; |
| 854 | delay = lcdb->bst.soft_start_us + lcdb->ldo.soft_start_us + |
| 855 | lcdb->ncp.soft_start_us; |
| 856 | delay += lcdb->bst.vreg_ok_dbc_us + lcdb->ldo.vreg_ok_dbc_us + |
| 857 | lcdb->ncp.vreg_ok_dbc_us; |
| 858 | while (timeout--) { |
| 859 | rc = qpnp_lcdb_read(lcdb, lcdb->base + INT_RT_STATUS_REG, |
| 860 | &val, 1); |
| 861 | if (rc < 0) { |
| 862 | pr_err("Failed to poll for vreg-ok status rc=%d\n", rc); |
| 863 | break; |
| 864 | } |
| 865 | if (val & VREG_OK_RT_STS_BIT) |
| 866 | break; |
| 867 | |
| 868 | usleep_range(delay, delay + 100); |
| 869 | } |
| 870 | |
| 871 | if (rc || !timeout) { |
| 872 | if (!timeout) { |
| 873 | pr_err("lcdb-vreg-ok status failed to change\n"); |
| 874 | rc = -ETIMEDOUT; |
| 875 | } |
| 876 | goto fail_enable; |
| 877 | } |
| 878 | |
| 879 | lcdb->lcdb_enabled = true; |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 880 | if (lcdb->voltage_step_ramp) { |
| 881 | usleep_range(10000, 11000); |
| 882 | rc = qpnp_lcdb_set_voltage_step(lcdb, |
| 883 | voltage_mv + VOLTAGE_STEP_MV, |
| 884 | LDO_NCP); |
| 885 | if (rc < 0) { |
| 886 | pr_err("Failed to set LCDB voltage rc=%d\n", rc); |
| 887 | return rc; |
| 888 | } |
| 889 | } |
| 890 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 891 | pr_debug("lcdb enabled successfully!\n"); |
| 892 | |
| 893 | return 0; |
| 894 | |
| 895 | fail_enable: |
| 896 | dump_status_registers(lcdb); |
| 897 | pr_err("Failed to enable lcdb rc=%d\n", rc); |
| 898 | return rc; |
| 899 | } |
| 900 | |
| 901 | static int qpnp_lcdb_disable(struct qpnp_lcdb *lcdb) |
| 902 | { |
| 903 | int rc = 0; |
| 904 | u8 val; |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 905 | u16 pmic_subtype = lcdb->pmic_rev_id->pmic_subtype; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 906 | |
| 907 | if (!lcdb->lcdb_enabled) |
| 908 | return 0; |
| 909 | |
| 910 | if (lcdb->ttw_enable) { |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 911 | if (pmic_subtype == PM660L_SUBTYPE) |
| 912 | rc = qpnp_lcdb_ttw_enter_pm660l(lcdb); |
| 913 | else |
| 914 | rc = qpnp_lcdb_ttw_enter(lcdb); |
| 915 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 916 | if (rc < 0) { |
| 917 | pr_err("Failed to enable TTW mode rc=%d\n", rc); |
| 918 | return rc; |
| 919 | } |
| 920 | lcdb->lcdb_enabled = false; |
| 921 | |
| 922 | return 0; |
| 923 | } |
| 924 | |
| 925 | val = 0; |
| 926 | rc = qpnp_lcdb_write(lcdb, lcdb->base + LCDB_ENABLE_CTL1_REG, |
| 927 | &val, 1); |
| 928 | if (rc < 0) |
| 929 | pr_err("Failed to disable lcdb rc= %d\n", rc); |
| 930 | else |
| 931 | lcdb->lcdb_enabled = false; |
| 932 | |
| 933 | return rc; |
| 934 | } |
| 935 | |
Anirudh Ghayal | 264f927 | 2017-03-05 22:34:37 +0530 | [diff] [blame] | 936 | #define LCDB_SC_RESET_CNT_DLY_US 1000000 |
| 937 | #define LCDB_SC_CNT_MAX 10 |
| 938 | static int qpnp_lcdb_handle_sc_event(struct qpnp_lcdb *lcdb) |
| 939 | { |
| 940 | int rc = 0; |
| 941 | s64 elapsed_time_us; |
| 942 | |
| 943 | mutex_lock(&lcdb->lcdb_mutex); |
| 944 | rc = qpnp_lcdb_disable(lcdb); |
| 945 | if (rc < 0) { |
| 946 | pr_err("Failed to disable lcdb rc=%d\n", rc); |
| 947 | goto unlock_mutex; |
| 948 | } |
| 949 | |
| 950 | /* Check if the SC re-occurred immediately */ |
| 951 | elapsed_time_us = ktime_us_delta(ktime_get(), |
| 952 | lcdb->sc_module_enable_time); |
| 953 | if (elapsed_time_us > LCDB_SC_RESET_CNT_DLY_US) { |
| 954 | lcdb->sc_count = 0; |
| 955 | } else if (lcdb->sc_count > LCDB_SC_CNT_MAX) { |
| 956 | pr_err("SC trigged %d times, disabling LCDB forever!\n", |
| 957 | lcdb->sc_count); |
| 958 | lcdb->lcdb_sc_disable = true; |
| 959 | goto unlock_mutex; |
| 960 | } |
| 961 | lcdb->sc_count++; |
| 962 | lcdb->sc_module_enable_time = ktime_get(); |
| 963 | |
| 964 | /* delay for SC to clear */ |
| 965 | usleep_range(10000, 10100); |
| 966 | |
| 967 | rc = qpnp_lcdb_enable(lcdb); |
| 968 | if (rc < 0) |
| 969 | pr_err("Failed to enable lcdb rc=%d\n", rc); |
| 970 | |
| 971 | unlock_mutex: |
| 972 | mutex_unlock(&lcdb->lcdb_mutex); |
| 973 | return rc; |
| 974 | } |
| 975 | |
| 976 | static irqreturn_t qpnp_lcdb_sc_irq_handler(int irq, void *data) |
| 977 | { |
| 978 | struct qpnp_lcdb *lcdb = data; |
| 979 | int rc; |
| 980 | u8 val, val2[2] = {0}; |
| 981 | |
| 982 | rc = qpnp_lcdb_read(lcdb, lcdb->base + INT_RT_STATUS_REG, &val, 1); |
| 983 | if (rc < 0) |
| 984 | goto irq_handled; |
| 985 | |
| 986 | if (val & SC_ERROR_RT_STS_BIT) { |
| 987 | rc = qpnp_lcdb_read(lcdb, |
| 988 | lcdb->base + LCDB_MISC_CTL_REG, &val, 1); |
| 989 | if (rc < 0) |
| 990 | goto irq_handled; |
| 991 | |
| 992 | if (val & EN_TOUCH_WAKE_BIT) { |
| 993 | /* blanking time */ |
| 994 | usleep_range(300, 310); |
| 995 | /* |
| 996 | * The status registers need to written with any value |
| 997 | * before reading |
| 998 | */ |
| 999 | rc = qpnp_lcdb_write(lcdb, |
| 1000 | lcdb->base + LCDB_STS3_REG, val2, 2); |
| 1001 | if (rc < 0) |
| 1002 | goto irq_handled; |
| 1003 | |
| 1004 | rc = qpnp_lcdb_read(lcdb, |
| 1005 | lcdb->base + LCDB_STS3_REG, val2, 2); |
| 1006 | if (rc < 0) |
| 1007 | goto irq_handled; |
| 1008 | |
| 1009 | if (!(val2[0] & LDO_VREG_OK_BIT) || |
| 1010 | !(val2[1] & NCP_VREG_OK_BIT)) { |
| 1011 | rc = qpnp_lcdb_handle_sc_event(lcdb); |
| 1012 | if (rc < 0) { |
| 1013 | pr_err("Failed to handle SC rc=%d\n", |
| 1014 | rc); |
| 1015 | goto irq_handled; |
| 1016 | } |
| 1017 | } |
| 1018 | } else { |
| 1019 | /* blanking time */ |
| 1020 | usleep_range(2000, 2100); |
| 1021 | /* Read the SC status again to confirm true SC */ |
| 1022 | rc = qpnp_lcdb_read(lcdb, |
| 1023 | lcdb->base + INT_RT_STATUS_REG, &val, 1); |
| 1024 | if (rc < 0) |
| 1025 | goto irq_handled; |
| 1026 | |
| 1027 | if (val & SC_ERROR_RT_STS_BIT) { |
| 1028 | rc = qpnp_lcdb_handle_sc_event(lcdb); |
| 1029 | if (rc < 0) { |
| 1030 | pr_err("Failed to handle SC rc=%d\n", |
| 1031 | rc); |
| 1032 | goto irq_handled; |
| 1033 | } |
| 1034 | } |
| 1035 | } |
| 1036 | } |
| 1037 | irq_handled: |
| 1038 | return IRQ_HANDLED; |
| 1039 | } |
| 1040 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1041 | #define MIN_BST_VOLTAGE_MV 4700 |
Subbaraman Narayanamurthy | 841eb43 | 2018-04-10 13:20:56 -0700 | [diff] [blame] | 1042 | #define PM660_MAX_BST_VOLTAGE_MV 6250 |
| 1043 | #define MAX_BST_VOLTAGE_MV 6275 |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1044 | #define MIN_VOLTAGE_MV 4000 |
| 1045 | #define MAX_VOLTAGE_MV 6000 |
| 1046 | #define VOLTAGE_MIN_STEP_100_MV 4000 |
| 1047 | #define VOLTAGE_MIN_STEP_50_MV 4950 |
| 1048 | #define VOLTAGE_STEP_100_MV 100 |
| 1049 | #define VOLTAGE_STEP_50_MV 50 |
Kiran Gunda | a5a1cb1 | 2018-03-05 12:57:59 +0530 | [diff] [blame] | 1050 | #define VOLTAGE_STEP_25_MV 25 |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1051 | #define VOLTAGE_STEP_50MV_OFFSET 0xA |
| 1052 | static int qpnp_lcdb_set_bst_voltage(struct qpnp_lcdb *lcdb, |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1053 | int voltage_mv, u8 type) |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1054 | { |
| 1055 | int rc = 0; |
Kiran Gunda | a5a1cb1 | 2018-03-05 12:57:59 +0530 | [diff] [blame] | 1056 | u8 val, voltage_step, mask = 0; |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1057 | int bst_voltage_mv; |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 1058 | u16 pmic_subtype = lcdb->pmic_rev_id->pmic_subtype; |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1059 | struct ldo_regulator *ldo = &lcdb->ldo; |
| 1060 | struct ncp_regulator *ncp = &lcdb->ncp; |
| 1061 | struct bst_params *bst = &lcdb->bst; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1062 | |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1063 | /* Vout_Boost = headroom_mv + max( Vout_LDO, abs (Vout_NCP)) */ |
| 1064 | bst_voltage_mv = max(voltage_mv, max(ldo->voltage_mv, ncp->voltage_mv)); |
| 1065 | bst_voltage_mv += bst->headroom_mv; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1066 | |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1067 | if (bst_voltage_mv < MIN_BST_VOLTAGE_MV) |
| 1068 | bst_voltage_mv = MIN_BST_VOLTAGE_MV; |
Subbaraman Narayanamurthy | 841eb43 | 2018-04-10 13:20:56 -0700 | [diff] [blame] | 1069 | |
| 1070 | if (pmic_subtype == PM660L_SUBTYPE) { |
| 1071 | if (bst_voltage_mv > PM660_MAX_BST_VOLTAGE_MV) |
| 1072 | bst_voltage_mv = PM660_MAX_BST_VOLTAGE_MV; |
| 1073 | } else { |
| 1074 | if (bst_voltage_mv > MAX_BST_VOLTAGE_MV) |
| 1075 | bst_voltage_mv = MAX_BST_VOLTAGE_MV; |
| 1076 | } |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1077 | |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1078 | if (bst_voltage_mv != bst->voltage_mv) { |
Kiran Gunda | a5a1cb1 | 2018-03-05 12:57:59 +0530 | [diff] [blame] | 1079 | if (pmic_subtype == PM660L_SUBTYPE) { |
| 1080 | mask = PM660_BST_OUTPUT_VOLTAGE_MASK; |
| 1081 | voltage_step = VOLTAGE_STEP_50_MV; |
| 1082 | } else { |
| 1083 | mask = BST_OUTPUT_VOLTAGE_MASK; |
| 1084 | voltage_step = VOLTAGE_STEP_25_MV; |
| 1085 | } |
| 1086 | |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1087 | val = DIV_ROUND_UP(bst_voltage_mv - MIN_BST_VOLTAGE_MV, |
Kiran Gunda | a5a1cb1 | 2018-03-05 12:57:59 +0530 | [diff] [blame] | 1088 | voltage_step); |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1089 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
| 1090 | LCDB_BST_OUTPUT_VOLTAGE_REG, |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 1091 | mask, val); |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1092 | if (rc < 0) { |
| 1093 | pr_err("Failed to set boost voltage %d mv rc=%d\n", |
| 1094 | bst_voltage_mv, rc); |
| 1095 | } else { |
| 1096 | pr_debug("Boost voltage set = %d mv (0x%02x = 0x%02x)\n", |
| 1097 | bst_voltage_mv, LCDB_BST_OUTPUT_VOLTAGE_REG, val); |
| 1098 | bst->voltage_mv = bst_voltage_mv; |
| 1099 | } |
| 1100 | } |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1101 | |
| 1102 | return rc; |
| 1103 | } |
| 1104 | |
| 1105 | static int qpnp_lcdb_get_bst_voltage(struct qpnp_lcdb *lcdb, |
| 1106 | int *voltage_mv) |
| 1107 | { |
| 1108 | int rc; |
Kiran Gunda | a5a1cb1 | 2018-03-05 12:57:59 +0530 | [diff] [blame] | 1109 | u8 val, voltage_step, mask = 0; |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 1110 | u16 pmic_subtype = lcdb->pmic_rev_id->pmic_subtype; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1111 | |
| 1112 | rc = qpnp_lcdb_read(lcdb, lcdb->base + LCDB_BST_OUTPUT_VOLTAGE_REG, |
| 1113 | &val, 1); |
| 1114 | if (rc < 0) { |
| 1115 | pr_err("Failed to reat BST voltage rc=%d\n", rc); |
| 1116 | return rc; |
| 1117 | } |
| 1118 | |
Kiran Gunda | a5a1cb1 | 2018-03-05 12:57:59 +0530 | [diff] [blame] | 1119 | if (pmic_subtype == PM660L_SUBTYPE) { |
| 1120 | mask = PM660_BST_OUTPUT_VOLTAGE_MASK; |
| 1121 | voltage_step = VOLTAGE_STEP_50_MV; |
| 1122 | } else { |
| 1123 | mask = BST_OUTPUT_VOLTAGE_MASK; |
| 1124 | voltage_step = VOLTAGE_STEP_25_MV; |
| 1125 | } |
| 1126 | |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 1127 | val &= mask; |
Kiran Gunda | a5a1cb1 | 2018-03-05 12:57:59 +0530 | [diff] [blame] | 1128 | *voltage_mv = (val * voltage_step) + MIN_BST_VOLTAGE_MV; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1129 | |
| 1130 | return 0; |
| 1131 | } |
| 1132 | |
| 1133 | static int qpnp_lcdb_set_voltage(struct qpnp_lcdb *lcdb, |
| 1134 | int voltage_mv, u8 type) |
| 1135 | { |
| 1136 | int rc = 0; |
| 1137 | u16 offset = LCDB_LDO_OUTPUT_VOLTAGE_REG; |
| 1138 | u8 val = 0; |
| 1139 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1140 | if (!is_between(voltage_mv, MIN_VOLTAGE_MV, MAX_VOLTAGE_MV)) { |
| 1141 | pr_err("Invalid voltage %dmv (min=%d max=%d)\n", |
| 1142 | voltage_mv, MIN_VOLTAGE_MV, MAX_VOLTAGE_MV); |
| 1143 | return -EINVAL; |
| 1144 | } |
| 1145 | |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1146 | rc = qpnp_lcdb_set_bst_voltage(lcdb, voltage_mv, type); |
| 1147 | if (rc < 0) { |
| 1148 | pr_err("Failed to set boost voltage rc=%d\n", rc); |
| 1149 | return rc; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1150 | } |
| 1151 | |
| 1152 | /* Below logic is only valid for LDO and NCP type */ |
| 1153 | if (voltage_mv < VOLTAGE_MIN_STEP_50_MV) { |
| 1154 | val = DIV_ROUND_UP(voltage_mv - VOLTAGE_MIN_STEP_100_MV, |
| 1155 | VOLTAGE_STEP_100_MV); |
| 1156 | } else { |
| 1157 | val = DIV_ROUND_UP(voltage_mv - VOLTAGE_MIN_STEP_50_MV, |
| 1158 | VOLTAGE_STEP_50_MV); |
| 1159 | val += VOLTAGE_STEP_50MV_OFFSET; |
| 1160 | } |
| 1161 | |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1162 | if (type == NCP) |
| 1163 | offset = LCDB_NCP_OUTPUT_VOLTAGE_REG; |
| 1164 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1165 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + offset, |
| 1166 | SET_OUTPUT_VOLTAGE_MASK, val); |
| 1167 | if (rc < 0) |
| 1168 | pr_err("Failed to set output voltage %d mv for %s rc=%d\n", |
| 1169 | voltage_mv, (type == LDO) ? "LDO" : "NCP", rc); |
| 1170 | else |
| 1171 | pr_debug("%s voltage set = %d mv (0x%02x = 0x%02x)\n", |
| 1172 | (type == LDO) ? "LDO" : "NCP", voltage_mv, offset, val); |
| 1173 | |
| 1174 | return rc; |
| 1175 | } |
| 1176 | |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 1177 | static int qpnp_lcdb_set_voltage_step(struct qpnp_lcdb *lcdb, |
| 1178 | int voltage_start_mv, u8 type) |
| 1179 | { |
| 1180 | int i, ldo_voltage, ncp_voltage, voltage, rc = 0; |
| 1181 | |
| 1182 | for (i = voltage_start_mv; i <= (MAX_VOLTAGE_MV + VOLTAGE_STEP_MV); |
| 1183 | i += VOLTAGE_STEP_MV) { |
| 1184 | |
| 1185 | ldo_voltage = (lcdb->ldo.voltage_mv < i) ? |
| 1186 | lcdb->ldo.voltage_mv : i; |
| 1187 | |
| 1188 | ncp_voltage = (lcdb->ncp.voltage_mv < i) ? |
| 1189 | lcdb->ncp.voltage_mv : i; |
| 1190 | if (type == LDO_NCP) { |
| 1191 | rc = qpnp_lcdb_set_voltage(lcdb, ldo_voltage, LDO); |
| 1192 | if (rc < 0) |
| 1193 | return rc; |
| 1194 | |
| 1195 | rc = qpnp_lcdb_set_voltage(lcdb, ncp_voltage, NCP); |
| 1196 | if (rc < 0) |
| 1197 | return rc; |
| 1198 | |
| 1199 | pr_debug(" LDO voltage step %d NCP voltage step %d\n", |
| 1200 | ldo_voltage, ncp_voltage); |
| 1201 | |
| 1202 | if ((i >= lcdb->ncp.voltage_mv) && |
| 1203 | (i >= lcdb->ldo.voltage_mv)) |
| 1204 | break; |
| 1205 | } else { |
| 1206 | voltage = (type == LDO) ? ldo_voltage : ncp_voltage; |
| 1207 | rc = qpnp_lcdb_set_voltage(lcdb, voltage, type); |
| 1208 | if (rc < 0) |
| 1209 | return rc; |
| 1210 | |
| 1211 | pr_debug("%s voltage step %d\n", |
| 1212 | (type == LDO) ? "LDO" : "NCP", voltage); |
| 1213 | if ((type == LDO) && (i >= lcdb->ldo.voltage_mv)) |
| 1214 | break; |
| 1215 | |
| 1216 | if ((type == NCP) && (i >= lcdb->ncp.voltage_mv)) |
| 1217 | break; |
| 1218 | |
| 1219 | } |
| 1220 | |
| 1221 | usleep_range(1000, 1100); |
| 1222 | } |
| 1223 | |
| 1224 | return rc; |
| 1225 | } |
| 1226 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1227 | static int qpnp_lcdb_get_voltage(struct qpnp_lcdb *lcdb, |
| 1228 | u32 *voltage_mv, u8 type) |
| 1229 | { |
| 1230 | int rc = 0; |
| 1231 | u16 offset = LCDB_LDO_OUTPUT_VOLTAGE_REG; |
| 1232 | u8 val = 0; |
| 1233 | |
| 1234 | if (type == BST) |
| 1235 | return qpnp_lcdb_get_bst_voltage(lcdb, voltage_mv); |
| 1236 | |
| 1237 | if (type == NCP) |
| 1238 | offset = LCDB_NCP_OUTPUT_VOLTAGE_REG; |
| 1239 | |
| 1240 | rc = qpnp_lcdb_read(lcdb, lcdb->base + offset, &val, 1); |
| 1241 | if (rc < 0) { |
| 1242 | pr_err("Failed to read %s volatge rc=%d\n", |
| 1243 | (type == LDO) ? "LDO" : "NCP", rc); |
| 1244 | return rc; |
| 1245 | } |
| 1246 | |
Kiran Gunda | 9c40b58 | 2018-09-10 12:16:41 +0530 | [diff] [blame] | 1247 | val &= SET_OUTPUT_VOLTAGE_MASK; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1248 | if (val < VOLTAGE_STEP_50MV_OFFSET) { |
| 1249 | *voltage_mv = VOLTAGE_MIN_STEP_100_MV + |
| 1250 | (val * VOLTAGE_STEP_100_MV); |
| 1251 | } else { |
| 1252 | *voltage_mv = VOLTAGE_MIN_STEP_50_MV + |
| 1253 | ((val - VOLTAGE_STEP_50MV_OFFSET) * VOLTAGE_STEP_50_MV); |
| 1254 | } |
| 1255 | |
| 1256 | if (!rc) |
| 1257 | pr_debug("%s voltage read-back = %d mv (0x%02x = 0x%02x)\n", |
| 1258 | (type == LDO) ? "LDO" : "NCP", |
| 1259 | *voltage_mv, offset, val); |
| 1260 | |
| 1261 | return rc; |
| 1262 | } |
| 1263 | |
| 1264 | static int qpnp_lcdb_set_soft_start(struct qpnp_lcdb *lcdb, |
| 1265 | u32 ss_us, u8 type) |
| 1266 | { |
| 1267 | int rc = 0, i = 0; |
| 1268 | u16 offset = LCDB_LDO_SOFT_START_CTL_REG; |
| 1269 | u8 val = 0; |
| 1270 | |
| 1271 | if (type == NCP) |
| 1272 | offset = LCDB_NCP_SOFT_START_CTL_REG; |
| 1273 | |
| 1274 | if (!is_between(ss_us, MIN_SOFT_START_US, MAX_SOFT_START_US)) { |
| 1275 | pr_err("Invalid soft_start_us %d (min=%d max=%d)\n", |
| 1276 | ss_us, MIN_SOFT_START_US, MAX_SOFT_START_US); |
| 1277 | return -EINVAL; |
| 1278 | } |
| 1279 | |
| 1280 | i = 0; |
| 1281 | while (ss_us > soft_start_us[i]) |
| 1282 | i++; |
| 1283 | val = ((i == 0) ? 0 : i - 1) & SOFT_START_MASK; |
| 1284 | |
| 1285 | rc = qpnp_lcdb_masked_write(lcdb, |
| 1286 | lcdb->base + offset, SOFT_START_MASK, val); |
| 1287 | if (rc < 0) |
| 1288 | pr_err("Failed to write %s soft-start time %d rc=%d", |
| 1289 | (type == LDO) ? "LDO" : "NCP", soft_start_us[i], rc); |
| 1290 | |
| 1291 | return rc; |
| 1292 | } |
| 1293 | |
| 1294 | static int qpnp_lcdb_ldo_regulator_enable(struct regulator_dev *rdev) |
| 1295 | { |
| 1296 | int rc = 0; |
| 1297 | struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev); |
| 1298 | |
Kavya Nunna | 80bc150 | 2018-10-01 14:50:23 +0530 | [diff] [blame] | 1299 | if (lcdb->secure_mode) |
| 1300 | return 0; |
| 1301 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1302 | mutex_lock(&lcdb->lcdb_mutex); |
| 1303 | rc = qpnp_lcdb_enable(lcdb); |
| 1304 | if (rc < 0) |
| 1305 | pr_err("Failed to enable lcdb rc=%d\n", rc); |
| 1306 | mutex_unlock(&lcdb->lcdb_mutex); |
| 1307 | |
| 1308 | return rc; |
| 1309 | } |
| 1310 | |
| 1311 | static int qpnp_lcdb_ldo_regulator_disable(struct regulator_dev *rdev) |
| 1312 | { |
| 1313 | int rc = 0; |
| 1314 | struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev); |
| 1315 | |
Kavya Nunna | 80bc150 | 2018-10-01 14:50:23 +0530 | [diff] [blame] | 1316 | if (lcdb->secure_mode) |
| 1317 | return 0; |
| 1318 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1319 | mutex_lock(&lcdb->lcdb_mutex); |
| 1320 | rc = qpnp_lcdb_disable(lcdb); |
| 1321 | if (rc < 0) |
| 1322 | pr_err("Failed to disable lcdb rc=%d\n", rc); |
| 1323 | mutex_unlock(&lcdb->lcdb_mutex); |
| 1324 | |
| 1325 | return rc; |
| 1326 | } |
| 1327 | |
| 1328 | static int qpnp_lcdb_ldo_regulator_is_enabled(struct regulator_dev *rdev) |
| 1329 | { |
| 1330 | struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev); |
| 1331 | |
| 1332 | return lcdb->lcdb_enabled; |
| 1333 | } |
| 1334 | |
| 1335 | static int qpnp_lcdb_ldo_regulator_set_voltage(struct regulator_dev *rdev, |
| 1336 | int min_uV, int max_uV, unsigned int *selector) |
| 1337 | { |
| 1338 | int rc = 0; |
| 1339 | struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev); |
| 1340 | |
Kavya Nunna | 80bc150 | 2018-10-01 14:50:23 +0530 | [diff] [blame] | 1341 | if (lcdb->secure_mode) |
| 1342 | return 0; |
| 1343 | |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 1344 | lcdb->ldo.voltage_mv = min_uV / 1000; |
| 1345 | if (lcdb->voltage_step_ramp) |
| 1346 | rc = qpnp_lcdb_set_voltage_step(lcdb, |
| 1347 | lcdb->ldo.prev_voltage_mv + VOLTAGE_STEP_MV, LDO); |
| 1348 | else |
| 1349 | rc = qpnp_lcdb_set_voltage(lcdb, lcdb->ldo.voltage_mv, LDO); |
| 1350 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1351 | if (rc < 0) |
| 1352 | pr_err("Failed to set LDO voltage rc=%c\n", rc); |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1353 | else |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 1354 | lcdb->ldo.prev_voltage_mv = lcdb->ldo.voltage_mv; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1355 | |
| 1356 | return rc; |
| 1357 | } |
| 1358 | |
| 1359 | static int qpnp_lcdb_ldo_regulator_get_voltage(struct regulator_dev *rdev) |
| 1360 | { |
| 1361 | int rc = 0; |
| 1362 | u32 voltage_mv = 0; |
| 1363 | struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev); |
| 1364 | |
| 1365 | rc = qpnp_lcdb_get_voltage(lcdb, &voltage_mv, LDO); |
| 1366 | if (rc < 0) { |
| 1367 | pr_err("Failed to get ldo voltage rc=%d\n", rc); |
| 1368 | return rc; |
| 1369 | } |
| 1370 | |
| 1371 | return voltage_mv * 1000; |
| 1372 | } |
| 1373 | |
| 1374 | static struct regulator_ops qpnp_lcdb_ldo_ops = { |
| 1375 | .enable = qpnp_lcdb_ldo_regulator_enable, |
| 1376 | .disable = qpnp_lcdb_ldo_regulator_disable, |
| 1377 | .is_enabled = qpnp_lcdb_ldo_regulator_is_enabled, |
| 1378 | .set_voltage = qpnp_lcdb_ldo_regulator_set_voltage, |
| 1379 | .get_voltage = qpnp_lcdb_ldo_regulator_get_voltage, |
| 1380 | }; |
| 1381 | |
| 1382 | static int qpnp_lcdb_ncp_regulator_enable(struct regulator_dev *rdev) |
| 1383 | { |
| 1384 | int rc = 0; |
| 1385 | struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev); |
| 1386 | |
Kavya Nunna | 80bc150 | 2018-10-01 14:50:23 +0530 | [diff] [blame] | 1387 | if (lcdb->secure_mode) |
| 1388 | return 0; |
| 1389 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1390 | mutex_lock(&lcdb->lcdb_mutex); |
| 1391 | rc = qpnp_lcdb_enable(lcdb); |
| 1392 | if (rc < 0) |
| 1393 | pr_err("Failed to enable lcdb rc=%d\n", rc); |
| 1394 | mutex_unlock(&lcdb->lcdb_mutex); |
| 1395 | |
| 1396 | return rc; |
| 1397 | } |
| 1398 | |
| 1399 | static int qpnp_lcdb_ncp_regulator_disable(struct regulator_dev *rdev) |
| 1400 | { |
| 1401 | int rc = 0; |
| 1402 | struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev); |
| 1403 | |
Kavya Nunna | 80bc150 | 2018-10-01 14:50:23 +0530 | [diff] [blame] | 1404 | if (lcdb->secure_mode) |
| 1405 | return 0; |
| 1406 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1407 | mutex_lock(&lcdb->lcdb_mutex); |
| 1408 | rc = qpnp_lcdb_disable(lcdb); |
| 1409 | if (rc < 0) |
| 1410 | pr_err("Failed to disable lcdb rc=%d\n", rc); |
| 1411 | mutex_unlock(&lcdb->lcdb_mutex); |
| 1412 | |
| 1413 | return rc; |
| 1414 | } |
| 1415 | |
| 1416 | static int qpnp_lcdb_ncp_regulator_is_enabled(struct regulator_dev *rdev) |
| 1417 | { |
| 1418 | struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev); |
| 1419 | |
| 1420 | return lcdb->lcdb_enabled; |
| 1421 | } |
| 1422 | |
| 1423 | static int qpnp_lcdb_ncp_regulator_set_voltage(struct regulator_dev *rdev, |
| 1424 | int min_uV, int max_uV, unsigned int *selector) |
| 1425 | { |
| 1426 | int rc = 0; |
| 1427 | struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev); |
| 1428 | |
Kavya Nunna | 80bc150 | 2018-10-01 14:50:23 +0530 | [diff] [blame] | 1429 | if (lcdb->secure_mode) |
| 1430 | return 0; |
| 1431 | |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 1432 | lcdb->ncp.voltage_mv = min_uV / 1000; |
| 1433 | if (lcdb->voltage_step_ramp) |
| 1434 | rc = qpnp_lcdb_set_voltage_step(lcdb, |
| 1435 | lcdb->ncp.prev_voltage_mv + VOLTAGE_STEP_MV, NCP); |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1436 | else |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 1437 | rc = qpnp_lcdb_set_voltage(lcdb, lcdb->ncp.voltage_mv, NCP); |
| 1438 | |
| 1439 | if (rc < 0) |
| 1440 | pr_err("Failed to set NCP voltage rc=%c\n", rc); |
| 1441 | else |
| 1442 | lcdb->ncp.prev_voltage_mv = lcdb->ncp.voltage_mv; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1443 | |
| 1444 | return rc; |
| 1445 | } |
| 1446 | |
| 1447 | static int qpnp_lcdb_ncp_regulator_get_voltage(struct regulator_dev *rdev) |
| 1448 | { |
| 1449 | int rc; |
| 1450 | u32 voltage_mv = 0; |
| 1451 | struct qpnp_lcdb *lcdb = rdev_get_drvdata(rdev); |
| 1452 | |
| 1453 | rc = qpnp_lcdb_get_voltage(lcdb, &voltage_mv, NCP); |
| 1454 | if (rc < 0) { |
| 1455 | pr_err("Failed to get ncp voltage rc=%d\n", rc); |
| 1456 | return rc; |
| 1457 | } |
| 1458 | |
| 1459 | return voltage_mv * 1000; |
| 1460 | } |
| 1461 | |
| 1462 | static struct regulator_ops qpnp_lcdb_ncp_ops = { |
| 1463 | .enable = qpnp_lcdb_ncp_regulator_enable, |
| 1464 | .disable = qpnp_lcdb_ncp_regulator_disable, |
| 1465 | .is_enabled = qpnp_lcdb_ncp_regulator_is_enabled, |
| 1466 | .set_voltage = qpnp_lcdb_ncp_regulator_set_voltage, |
| 1467 | .get_voltage = qpnp_lcdb_ncp_regulator_get_voltage, |
| 1468 | }; |
| 1469 | |
| 1470 | static int qpnp_lcdb_regulator_register(struct qpnp_lcdb *lcdb, u8 type) |
| 1471 | { |
Kiran Gunda | df7fa66 | 2018-06-11 12:41:51 +0530 | [diff] [blame] | 1472 | int rc = 0, off_on_delay = 0; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1473 | struct regulator_init_data *init_data; |
| 1474 | struct regulator_config cfg = {}; |
| 1475 | struct regulator_desc *rdesc; |
| 1476 | struct regulator_dev *rdev; |
| 1477 | struct device_node *node; |
| 1478 | |
Kiran Gunda | df7fa66 | 2018-06-11 12:41:51 +0530 | [diff] [blame] | 1479 | if (lcdb->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE) |
| 1480 | off_on_delay = PMIC5_LCDB_OFF_ON_DELAY_US; |
| 1481 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1482 | if (type == LDO) { |
| 1483 | node = lcdb->ldo.node; |
| 1484 | rdesc = &lcdb->ldo.rdesc; |
| 1485 | rdesc->ops = &qpnp_lcdb_ldo_ops; |
Kiran Gunda | df7fa66 | 2018-06-11 12:41:51 +0530 | [diff] [blame] | 1486 | rdesc->off_on_delay = off_on_delay; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1487 | rdev = lcdb->ldo.rdev; |
| 1488 | } else if (type == NCP) { |
| 1489 | node = lcdb->ncp.node; |
| 1490 | rdesc = &lcdb->ncp.rdesc; |
| 1491 | rdesc->ops = &qpnp_lcdb_ncp_ops; |
Kiran Gunda | df7fa66 | 2018-06-11 12:41:51 +0530 | [diff] [blame] | 1492 | rdesc->off_on_delay = off_on_delay; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1493 | rdev = lcdb->ncp.rdev; |
| 1494 | } else { |
| 1495 | pr_err("Invalid regulator type %d\n", type); |
| 1496 | return -EINVAL; |
| 1497 | } |
| 1498 | |
| 1499 | init_data = of_get_regulator_init_data(lcdb->dev, node, rdesc); |
| 1500 | if (!init_data) { |
| 1501 | pr_err("Failed to get regulator_init_data for %s\n", |
| 1502 | (type == LDO) ? "LDO" : "NCP"); |
| 1503 | return -ENOMEM; |
| 1504 | } |
| 1505 | |
| 1506 | if (init_data->constraints.name) { |
| 1507 | rdesc->owner = THIS_MODULE; |
| 1508 | rdesc->type = REGULATOR_VOLTAGE; |
| 1509 | rdesc->name = init_data->constraints.name; |
| 1510 | |
| 1511 | cfg.dev = lcdb->dev; |
| 1512 | cfg.init_data = init_data; |
| 1513 | cfg.driver_data = lcdb; |
| 1514 | cfg.of_node = node; |
| 1515 | |
| 1516 | if (of_get_property(lcdb->dev->of_node, "parent-supply", NULL)) |
| 1517 | init_data->supply_regulator = "parent"; |
| 1518 | |
| 1519 | init_data->constraints.valid_ops_mask |
| 1520 | |= REGULATOR_CHANGE_VOLTAGE |
| 1521 | | REGULATOR_CHANGE_STATUS; |
| 1522 | |
| 1523 | rdev = devm_regulator_register(lcdb->dev, rdesc, &cfg); |
| 1524 | if (IS_ERR(rdev)) { |
| 1525 | rc = PTR_ERR(rdev); |
| 1526 | rdev = NULL; |
| 1527 | pr_err("Failed to register lcdb_%s regulator rc = %d\n", |
| 1528 | (type == LDO) ? "LDO" : "NCP", rc); |
| 1529 | return rc; |
| 1530 | } |
| 1531 | } else { |
| 1532 | pr_err("%s_regulator name missing\n", |
| 1533 | (type == LDO) ? "LDO" : "NCP"); |
| 1534 | return -EINVAL; |
| 1535 | } |
| 1536 | |
| 1537 | return rc; |
| 1538 | } |
| 1539 | |
| 1540 | static int qpnp_lcdb_parse_ttw(struct qpnp_lcdb *lcdb) |
| 1541 | { |
| 1542 | int rc = 0; |
| 1543 | u32 temp; |
| 1544 | u8 val = 0; |
| 1545 | struct device_node *node = lcdb->dev->of_node; |
| 1546 | |
| 1547 | if (of_property_read_bool(node, "qcom,ttw-mode-sw")) { |
| 1548 | lcdb->ttw_mode_sw = true; |
| 1549 | rc = of_property_read_u32(node, "qcom,attw-toff-ms", &temp); |
| 1550 | if (!rc) { |
| 1551 | if (!is_between(temp, ATTW_MIN_MS, ATTW_MAX_MS)) { |
| 1552 | pr_err("Invalid TOFF val %d (min=%d max=%d)\n", |
| 1553 | temp, ATTW_MIN_MS, ATTW_MAX_MS); |
| 1554 | return -EINVAL; |
| 1555 | } |
| 1556 | val = ilog2(temp / 4) << ATTW_TOFF_TIME_SHIFT; |
| 1557 | } else { |
| 1558 | pr_err("qcom,attw-toff-ms not specified for TTW SW mode\n"); |
| 1559 | return rc; |
| 1560 | } |
| 1561 | |
| 1562 | rc = of_property_read_u32(node, "qcom,attw-ton-ms", &temp); |
| 1563 | if (!rc) { |
| 1564 | if (!is_between(temp, ATTW_MIN_MS, ATTW_MAX_MS)) { |
| 1565 | pr_err("Invalid TON value %d (min=%d max=%d)\n", |
| 1566 | temp, ATTW_MIN_MS, ATTW_MAX_MS); |
| 1567 | return -EINVAL; |
| 1568 | } |
| 1569 | val |= ilog2(temp / 4); |
| 1570 | } else { |
| 1571 | pr_err("qcom,attw-ton-ms not specified for TTW SW mode\n"); |
| 1572 | return rc; |
| 1573 | } |
| 1574 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
| 1575 | LCDB_AUTO_TOUCH_WAKE_CTL_REG, |
| 1576 | ATTW_TON_TIME_MASK | ATTW_TOFF_TIME_MASK, val); |
| 1577 | if (rc < 0) { |
| 1578 | pr_err("Failed to write ATTW ON/OFF rc=%d\n", rc); |
| 1579 | return rc; |
| 1580 | } |
| 1581 | } |
| 1582 | |
| 1583 | return 0; |
| 1584 | } |
| 1585 | |
| 1586 | static int qpnp_lcdb_ldo_dt_init(struct qpnp_lcdb *lcdb) |
| 1587 | { |
| 1588 | int rc = 0; |
| 1589 | struct device_node *node = lcdb->ldo.node; |
| 1590 | |
| 1591 | /* LDO output voltage */ |
| 1592 | lcdb->ldo.voltage_mv = -EINVAL; |
| 1593 | rc = of_property_read_u32(node, "qcom,ldo-voltage-mv", |
| 1594 | &lcdb->ldo.voltage_mv); |
| 1595 | if (!rc && !is_between(lcdb->ldo.voltage_mv, MIN_VOLTAGE_MV, |
| 1596 | MAX_VOLTAGE_MV)) { |
| 1597 | pr_err("Invalid LDO voltage %dmv (min=%d max=%d)\n", |
| 1598 | lcdb->ldo.voltage_mv, MIN_VOLTAGE_MV, MAX_VOLTAGE_MV); |
| 1599 | return -EINVAL; |
| 1600 | } |
| 1601 | |
| 1602 | /* LDO PD configuration */ |
| 1603 | lcdb->ldo.pd = -EINVAL; |
| 1604 | of_property_read_u32(node, "qcom,ldo-pd", &lcdb->ldo.pd); |
| 1605 | |
| 1606 | lcdb->ldo.pd_strength = -EINVAL; |
| 1607 | of_property_read_u32(node, "qcom,ldo-pd-strength", |
| 1608 | &lcdb->ldo.pd_strength); |
| 1609 | |
| 1610 | /* LDO ILIM configuration */ |
| 1611 | lcdb->ldo.ilim_ma = -EINVAL; |
| 1612 | rc = of_property_read_u32(node, "qcom,ldo-ilim-ma", &lcdb->ldo.ilim_ma); |
| 1613 | if (!rc && !is_between(lcdb->ldo.ilim_ma, MIN_LDO_ILIM_MA, |
| 1614 | MAX_LDO_ILIM_MA)) { |
| 1615 | pr_err("Invalid ilim_ma %d (min=%d, max=%d)\n", |
| 1616 | lcdb->ldo.ilim_ma, MIN_LDO_ILIM_MA, |
| 1617 | MAX_LDO_ILIM_MA); |
| 1618 | return -EINVAL; |
| 1619 | } |
| 1620 | |
| 1621 | /* LDO soft-start (SS) configuration */ |
| 1622 | lcdb->ldo.soft_start_us = -EINVAL; |
| 1623 | of_property_read_u32(node, "qcom,ldo-soft-start-us", |
| 1624 | &lcdb->ldo.soft_start_us); |
| 1625 | |
| 1626 | return 0; |
| 1627 | } |
| 1628 | |
| 1629 | static int qpnp_lcdb_ncp_dt_init(struct qpnp_lcdb *lcdb) |
| 1630 | { |
| 1631 | int rc = 0; |
| 1632 | struct device_node *node = lcdb->ncp.node; |
| 1633 | |
| 1634 | /* NCP output voltage */ |
| 1635 | lcdb->ncp.voltage_mv = -EINVAL; |
| 1636 | rc = of_property_read_u32(node, "qcom,ncp-voltage-mv", |
| 1637 | &lcdb->ncp.voltage_mv); |
| 1638 | if (!rc && !is_between(lcdb->ncp.voltage_mv, MIN_VOLTAGE_MV, |
| 1639 | MAX_VOLTAGE_MV)) { |
| 1640 | pr_err("Invalid NCP voltage %dmv (min=%d max=%d)\n", |
| 1641 | lcdb->ldo.voltage_mv, MIN_VOLTAGE_MV, MAX_VOLTAGE_MV); |
| 1642 | return -EINVAL; |
| 1643 | } |
| 1644 | |
| 1645 | /* NCP PD configuration */ |
| 1646 | lcdb->ncp.pd = -EINVAL; |
| 1647 | of_property_read_u32(node, "qcom,ncp-pd", &lcdb->ncp.pd); |
| 1648 | |
| 1649 | lcdb->ncp.pd_strength = -EINVAL; |
| 1650 | of_property_read_u32(node, "qcom,ncp-pd-strength", |
| 1651 | &lcdb->ncp.pd_strength); |
| 1652 | |
| 1653 | /* NCP ILIM configuration */ |
| 1654 | lcdb->ncp.ilim_ma = -EINVAL; |
| 1655 | rc = of_property_read_u32(node, "qcom,ncp-ilim-ma", &lcdb->ncp.ilim_ma); |
| 1656 | if (!rc && !is_between(lcdb->ncp.ilim_ma, MIN_NCP_ILIM_MA, |
| 1657 | MAX_NCP_ILIM_MA)) { |
| 1658 | pr_err("Invalid ilim_ma %d (min=%d, max=%d)\n", |
| 1659 | lcdb->ncp.ilim_ma, MIN_NCP_ILIM_MA, MAX_NCP_ILIM_MA); |
| 1660 | return -EINVAL; |
| 1661 | } |
| 1662 | |
| 1663 | /* NCP soft-start (SS) configuration */ |
| 1664 | lcdb->ncp.soft_start_us = -EINVAL; |
| 1665 | of_property_read_u32(node, "qcom,ncp-soft-start-us", |
| 1666 | &lcdb->ncp.soft_start_us); |
| 1667 | |
| 1668 | return 0; |
| 1669 | } |
| 1670 | |
| 1671 | static int qpnp_lcdb_bst_dt_init(struct qpnp_lcdb *lcdb) |
| 1672 | { |
| 1673 | int rc = 0; |
| 1674 | struct device_node *node = lcdb->bst.node; |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 1675 | u16 pmic_subtype = lcdb->pmic_rev_id->pmic_subtype; |
| 1676 | u16 default_headroom_mv; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1677 | |
| 1678 | /* Boost PD configuration */ |
| 1679 | lcdb->bst.pd = -EINVAL; |
| 1680 | of_property_read_u32(node, "qcom,bst-pd", &lcdb->bst.pd); |
| 1681 | |
| 1682 | lcdb->bst.pd_strength = -EINVAL; |
| 1683 | of_property_read_u32(node, "qcom,bst-pd-strength", |
| 1684 | &lcdb->bst.pd_strength); |
| 1685 | |
| 1686 | /* Boost ILIM */ |
| 1687 | lcdb->bst.ilim_ma = -EINVAL; |
| 1688 | rc = of_property_read_u32(node, "qcom,bst-ilim-ma", &lcdb->bst.ilim_ma); |
| 1689 | if (!rc && !is_between(lcdb->bst.ilim_ma, MIN_BST_ILIM_MA, |
| 1690 | MAX_BST_ILIM_MA)) { |
| 1691 | pr_err("Invalid ilim_ma %d (min=%d, max=%d)\n", |
| 1692 | lcdb->bst.ilim_ma, MIN_BST_ILIM_MA, MAX_BST_ILIM_MA); |
| 1693 | return -EINVAL; |
| 1694 | } |
| 1695 | |
| 1696 | /* Boost PS configuration */ |
| 1697 | lcdb->bst.ps = -EINVAL; |
| 1698 | of_property_read_u32(node, "qcom,bst-ps", &lcdb->bst.ps); |
| 1699 | |
| 1700 | lcdb->bst.ps_threshold = -EINVAL; |
| 1701 | rc = of_property_read_u32(node, "qcom,bst-ps-threshold-ma", |
| 1702 | &lcdb->bst.ps_threshold); |
| 1703 | if (!rc && !is_between(lcdb->bst.ps_threshold, |
| 1704 | MIN_BST_PS_MA, MAX_BST_PS_MA)) { |
| 1705 | pr_err("Invalid bst ps_threshold %d (min=%d, max=%d)\n", |
| 1706 | lcdb->bst.ps_threshold, MIN_BST_PS_MA, MAX_BST_PS_MA); |
| 1707 | return -EINVAL; |
| 1708 | } |
| 1709 | |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 1710 | default_headroom_mv = (pmic_subtype == PM660L_SUBTYPE) ? |
| 1711 | PM660_BST_HEADROOM_DEFAULT_MV : |
| 1712 | BST_HEADROOM_DEFAULT_MV; |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1713 | /* Boost head room configuration */ |
| 1714 | of_property_read_u16(node, "qcom,bst-headroom-mv", |
| 1715 | &lcdb->bst.headroom_mv); |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 1716 | if (lcdb->bst.headroom_mv < default_headroom_mv) |
| 1717 | lcdb->bst.headroom_mv = default_headroom_mv; |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 1718 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1719 | return 0; |
| 1720 | } |
| 1721 | |
| 1722 | static int qpnp_lcdb_init_ldo(struct qpnp_lcdb *lcdb) |
| 1723 | { |
| 1724 | int rc = 0, ilim_ma; |
| 1725 | u8 val = 0; |
| 1726 | |
| 1727 | /* configure parameters only if LCDB is disabled */ |
| 1728 | if (!is_lcdb_enabled(lcdb)) { |
| 1729 | if (lcdb->ldo.voltage_mv != -EINVAL) { |
| 1730 | rc = qpnp_lcdb_set_voltage(lcdb, |
| 1731 | lcdb->ldo.voltage_mv, LDO); |
| 1732 | if (rc < 0) { |
| 1733 | pr_err("Failed to set voltage rc=%d\n", rc); |
| 1734 | return rc; |
| 1735 | } |
| 1736 | } |
| 1737 | |
| 1738 | if (lcdb->ldo.pd != -EINVAL) { |
| 1739 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
| 1740 | LCDB_LDO_PD_CTL_REG, LDO_DIS_PULLDOWN_BIT, |
| 1741 | lcdb->ldo.pd ? 0 : LDO_DIS_PULLDOWN_BIT); |
| 1742 | if (rc < 0) { |
| 1743 | pr_err("Failed to configure LDO PD rc=%d\n", |
| 1744 | rc); |
| 1745 | return rc; |
| 1746 | } |
| 1747 | } |
| 1748 | |
| 1749 | if (lcdb->ldo.pd_strength != -EINVAL) { |
| 1750 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
| 1751 | LCDB_LDO_PD_CTL_REG, LDO_PD_STRENGTH_BIT, |
| 1752 | lcdb->ldo.pd_strength ? |
| 1753 | LDO_PD_STRENGTH_BIT : 0); |
| 1754 | if (rc < 0) { |
| 1755 | pr_err("Failed to configure LDO PD strength %s rc=%d", |
| 1756 | lcdb->ldo.pd_strength ? |
| 1757 | "(strong)" : "(weak)", rc); |
| 1758 | return rc; |
| 1759 | } |
| 1760 | } |
| 1761 | |
| 1762 | if (lcdb->ldo.ilim_ma != -EINVAL) { |
| 1763 | ilim_ma = lcdb->ldo.ilim_ma - MIN_LDO_ILIM_MA; |
| 1764 | ilim_ma /= LDO_ILIM_STEP_MA; |
| 1765 | val = (ilim_ma & SET_LDO_ILIM_MASK) | EN_LDO_ILIM_BIT; |
| 1766 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
| 1767 | LCDB_LDO_ILIM_CTL1_REG, |
| 1768 | SET_LDO_ILIM_MASK | EN_LDO_ILIM_BIT, |
| 1769 | val); |
| 1770 | if (rc < 0) { |
| 1771 | pr_err("Failed to configure LDO ilim_ma (CTL1=%d) rc=%d", |
| 1772 | val, rc); |
| 1773 | return rc; |
| 1774 | } |
| 1775 | |
| 1776 | val = ilim_ma & SET_LDO_ILIM_MASK; |
| 1777 | rc = qpnp_lcdb_masked_write(lcdb, |
| 1778 | lcdb->base + LCDB_LDO_ILIM_CTL2_REG, |
| 1779 | SET_LDO_ILIM_MASK, val); |
| 1780 | if (rc < 0) { |
| 1781 | pr_err("Failed to configure LDO ilim_ma (CTL2=%d) rc=%d", |
| 1782 | val, rc); |
| 1783 | return rc; |
| 1784 | } |
| 1785 | } |
| 1786 | |
| 1787 | if (lcdb->ldo.soft_start_us != -EINVAL) { |
| 1788 | rc = qpnp_lcdb_set_soft_start(lcdb, |
| 1789 | lcdb->ldo.soft_start_us, LDO); |
| 1790 | if (rc < 0) { |
| 1791 | pr_err("Failed to set LDO soft_start rc=%d\n", |
| 1792 | rc); |
| 1793 | return rc; |
| 1794 | } |
| 1795 | } |
| 1796 | } |
| 1797 | |
| 1798 | rc = qpnp_lcdb_get_voltage(lcdb, &lcdb->ldo.voltage_mv, LDO); |
| 1799 | if (rc < 0) { |
| 1800 | pr_err("Failed to get LDO volatge rc=%d\n", rc); |
| 1801 | return rc; |
| 1802 | } |
| 1803 | |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 1804 | lcdb->ldo.prev_voltage_mv = lcdb->ldo.voltage_mv; |
| 1805 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1806 | rc = qpnp_lcdb_read(lcdb, lcdb->base + |
| 1807 | LCDB_LDO_VREG_OK_CTL_REG, &val, 1); |
| 1808 | if (rc < 0) { |
| 1809 | pr_err("Failed to read ldo_vreg_ok rc=%d\n", rc); |
| 1810 | return rc; |
| 1811 | } |
| 1812 | lcdb->ldo.vreg_ok_dbc_us = dbc_us[val & VREG_OK_DEB_MASK]; |
| 1813 | |
| 1814 | rc = qpnp_lcdb_read(lcdb, lcdb->base + |
| 1815 | LCDB_LDO_SOFT_START_CTL_REG, &val, 1); |
| 1816 | if (rc < 0) { |
| 1817 | pr_err("Failed to read ldo_soft_start_ctl rc=%d\n", rc); |
| 1818 | return rc; |
| 1819 | } |
| 1820 | lcdb->ldo.soft_start_us = soft_start_us[val & SOFT_START_MASK]; |
| 1821 | |
| 1822 | rc = qpnp_lcdb_regulator_register(lcdb, LDO); |
| 1823 | if (rc < 0) |
| 1824 | pr_err("Failed to register ldo rc=%d\n", rc); |
| 1825 | |
| 1826 | return rc; |
| 1827 | } |
| 1828 | |
| 1829 | static int qpnp_lcdb_init_ncp(struct qpnp_lcdb *lcdb) |
| 1830 | { |
| 1831 | int rc = 0, i = 0; |
| 1832 | u8 val = 0; |
| 1833 | |
| 1834 | /* configure parameters only if LCDB is disabled */ |
| 1835 | if (!is_lcdb_enabled(lcdb)) { |
| 1836 | if (lcdb->ncp.voltage_mv != -EINVAL) { |
| 1837 | rc = qpnp_lcdb_set_voltage(lcdb, |
| 1838 | lcdb->ncp.voltage_mv, NCP); |
| 1839 | if (rc < 0) { |
| 1840 | pr_err("Failed to set voltage rc=%d\n", rc); |
| 1841 | return rc; |
| 1842 | } |
| 1843 | } |
| 1844 | |
| 1845 | if (lcdb->ncp.pd != -EINVAL) { |
| 1846 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
| 1847 | LCDB_NCP_PD_CTL_REG, NCP_DIS_PULLDOWN_BIT, |
| 1848 | lcdb->ncp.pd ? 0 : NCP_DIS_PULLDOWN_BIT); |
| 1849 | if (rc < 0) { |
| 1850 | pr_err("Failed to configure NCP PD rc=%d\n", |
| 1851 | rc); |
| 1852 | return rc; |
| 1853 | } |
| 1854 | } |
| 1855 | |
| 1856 | if (lcdb->ncp.pd_strength != -EINVAL) { |
| 1857 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
| 1858 | LCDB_NCP_PD_CTL_REG, NCP_PD_STRENGTH_BIT, |
| 1859 | lcdb->ncp.pd_strength ? |
| 1860 | NCP_PD_STRENGTH_BIT : 0); |
| 1861 | if (rc < 0) { |
| 1862 | pr_err("Failed to configure NCP PD strength %s rc=%d", |
| 1863 | lcdb->ncp.pd_strength ? |
| 1864 | "(strong)" : "(weak)", rc); |
| 1865 | return rc; |
| 1866 | } |
| 1867 | } |
| 1868 | |
| 1869 | if (lcdb->ncp.ilim_ma != -EINVAL) { |
| 1870 | while (lcdb->ncp.ilim_ma > ncp_ilim_ma[i]) |
| 1871 | i++; |
| 1872 | val = (i == 0) ? 0 : i - 1; |
| 1873 | val = (lcdb->ncp.ilim_ma & SET_NCP_ILIM_MASK) | |
| 1874 | EN_NCP_ILIM_BIT; |
| 1875 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
| 1876 | LCDB_NCP_ILIM_CTL1_REG, |
| 1877 | SET_NCP_ILIM_MASK | EN_NCP_ILIM_BIT, val); |
| 1878 | if (rc < 0) { |
| 1879 | pr_err("Failed to configure NCP ilim_ma (CTL1=%d) rc=%d", |
| 1880 | val, rc); |
| 1881 | return rc; |
| 1882 | } |
| 1883 | val = lcdb->ncp.ilim_ma & SET_NCP_ILIM_MASK; |
| 1884 | rc = qpnp_lcdb_masked_write(lcdb, |
| 1885 | lcdb->base + LCDB_NCP_ILIM_CTL2_REG, |
| 1886 | SET_NCP_ILIM_MASK, val); |
| 1887 | if (rc < 0) { |
| 1888 | pr_err("Failed to configure NCP ilim_ma (CTL2=%d) rc=%d", |
| 1889 | val, rc); |
| 1890 | return rc; |
| 1891 | } |
| 1892 | } |
| 1893 | |
| 1894 | if (lcdb->ncp.soft_start_us != -EINVAL) { |
| 1895 | rc = qpnp_lcdb_set_soft_start(lcdb, |
| 1896 | lcdb->ncp.soft_start_us, NCP); |
| 1897 | if (rc < 0) { |
| 1898 | pr_err("Failed to set NCP soft_start rc=%d\n", |
| 1899 | rc); |
| 1900 | return rc; |
| 1901 | } |
| 1902 | } |
| 1903 | } |
| 1904 | |
| 1905 | rc = qpnp_lcdb_get_voltage(lcdb, &lcdb->ncp.voltage_mv, NCP); |
| 1906 | if (rc < 0) { |
| 1907 | pr_err("Failed to get NCP volatge rc=%d\n", rc); |
| 1908 | return rc; |
| 1909 | } |
| 1910 | |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 1911 | lcdb->ncp.prev_voltage_mv = lcdb->ncp.voltage_mv; |
| 1912 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1913 | rc = qpnp_lcdb_read(lcdb, lcdb->base + |
| 1914 | LCDB_NCP_VREG_OK_CTL_REG, &val, 1); |
| 1915 | if (rc < 0) { |
| 1916 | pr_err("Failed to read ncp_vreg_ok rc=%d\n", rc); |
| 1917 | return rc; |
| 1918 | } |
| 1919 | lcdb->ncp.vreg_ok_dbc_us = dbc_us[val & VREG_OK_DEB_MASK]; |
| 1920 | |
| 1921 | rc = qpnp_lcdb_read(lcdb, lcdb->base + |
| 1922 | LCDB_NCP_SOFT_START_CTL_REG, &val, 1); |
| 1923 | if (rc < 0) { |
| 1924 | pr_err("Failed to read ncp_soft_start_ctl rc=%d\n", rc); |
| 1925 | return rc; |
| 1926 | } |
| 1927 | lcdb->ncp.soft_start_us = soft_start_us[val & SOFT_START_MASK]; |
| 1928 | |
| 1929 | rc = qpnp_lcdb_regulator_register(lcdb, NCP); |
| 1930 | if (rc < 0) |
| 1931 | pr_err("Failed to register NCP rc=%d\n", rc); |
| 1932 | |
| 1933 | return rc; |
| 1934 | } |
| 1935 | |
| 1936 | static int qpnp_lcdb_init_bst(struct qpnp_lcdb *lcdb) |
| 1937 | { |
| 1938 | int rc = 0; |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 1939 | u8 val, mask = 0; |
| 1940 | u16 pmic_subtype = lcdb->pmic_rev_id->pmic_subtype; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1941 | |
| 1942 | /* configure parameters only if LCDB is disabled */ |
| 1943 | if (!is_lcdb_enabled(lcdb)) { |
| 1944 | if (lcdb->bst.pd != -EINVAL) { |
| 1945 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
| 1946 | LCDB_BST_PD_CTL_REG, BOOST_DIS_PULLDOWN_BIT, |
| 1947 | lcdb->bst.pd ? 0 : BOOST_DIS_PULLDOWN_BIT); |
| 1948 | if (rc < 0) { |
| 1949 | pr_err("Failed to configure BST PD rc=%d\n", |
| 1950 | rc); |
| 1951 | return rc; |
| 1952 | } |
| 1953 | } |
| 1954 | |
| 1955 | if (lcdb->bst.pd_strength != -EINVAL) { |
| 1956 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
Kiran Gunda | 64a1d80 | 2018-09-07 18:06:44 +0530 | [diff] [blame] | 1957 | LCDB_BST_PD_CTL_REG, BOOST_PD_STRENGTH_BIT, |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1958 | lcdb->bst.pd_strength ? |
| 1959 | BOOST_PD_STRENGTH_BIT : 0); |
| 1960 | if (rc < 0) { |
| 1961 | pr_err("Failed to configure NCP PD strength %s rc=%d", |
| 1962 | lcdb->bst.pd_strength ? |
| 1963 | "(strong)" : "(weak)", rc); |
| 1964 | return rc; |
| 1965 | } |
| 1966 | } |
| 1967 | |
| 1968 | if (lcdb->bst.ilim_ma != -EINVAL) { |
| 1969 | val = (lcdb->bst.ilim_ma / MIN_BST_ILIM_MA) - 1; |
| 1970 | val = (lcdb->bst.ilim_ma & SET_BST_ILIM_MASK) | |
| 1971 | EN_BST_ILIM_BIT; |
| 1972 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
| 1973 | LCDB_BST_ILIM_CTL_REG, |
| 1974 | SET_BST_ILIM_MASK | EN_BST_ILIM_BIT, val); |
| 1975 | if (rc < 0) { |
| 1976 | pr_err("Failed to configure BST ilim_ma rc=%d", |
| 1977 | rc); |
| 1978 | return rc; |
| 1979 | } |
| 1980 | } |
| 1981 | |
| 1982 | if (lcdb->bst.ps != -EINVAL) { |
| 1983 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
| 1984 | LCDB_PS_CTL_REG, EN_PS_BIT, |
| 1985 | &lcdb->bst.ps ? EN_PS_BIT : 0); |
| 1986 | if (rc < 0) { |
| 1987 | pr_err("Failed to disable BST PS rc=%d", rc); |
| 1988 | return rc; |
| 1989 | } |
| 1990 | } |
| 1991 | |
| 1992 | if (lcdb->bst.ps_threshold != -EINVAL) { |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 1993 | mask = (pmic_subtype == PM660L_SUBTYPE) ? |
| 1994 | PM660_PS_THRESH_MASK : PS_THRESH_MASK; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1995 | val = (lcdb->bst.ps_threshold - MIN_BST_PS_MA) / 10; |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 1996 | val = (lcdb->bst.ps_threshold & mask) | EN_PS_BIT; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 1997 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
| 1998 | LCDB_PS_CTL_REG, |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 1999 | mask | EN_PS_BIT, val); |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2000 | if (rc < 0) { |
| 2001 | pr_err("Failed to configure BST PS threshold rc=%d", |
| 2002 | rc); |
| 2003 | return rc; |
| 2004 | } |
| 2005 | } |
| 2006 | } |
| 2007 | |
| 2008 | rc = qpnp_lcdb_get_voltage(lcdb, &lcdb->bst.voltage_mv, BST); |
| 2009 | if (rc < 0) { |
| 2010 | pr_err("Failed to get BST volatge rc=%d\n", rc); |
| 2011 | return rc; |
| 2012 | } |
| 2013 | |
| 2014 | rc = qpnp_lcdb_read(lcdb, lcdb->base + |
| 2015 | LCDB_BST_VREG_OK_CTL_REG, &val, 1); |
| 2016 | if (rc < 0) { |
| 2017 | pr_err("Failed to read bst_vreg_ok rc=%d\n", rc); |
| 2018 | return rc; |
| 2019 | } |
| 2020 | lcdb->bst.vreg_ok_dbc_us = dbc_us[val & VREG_OK_DEB_MASK]; |
| 2021 | |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 2022 | if (pmic_subtype == PM660L_SUBTYPE) { |
| 2023 | rc = qpnp_lcdb_read(lcdb, lcdb->base + |
| 2024 | LCDB_SOFT_START_CTL_REG, &val, 1); |
| 2025 | if (rc < 0) { |
| 2026 | pr_err("Failed to read lcdb_soft_start_ctl rc=%d\n", |
| 2027 | rc); |
| 2028 | return rc; |
| 2029 | } |
| 2030 | lcdb->bst.soft_start_us = (val & SOFT_START_MASK) * 200 + 200; |
Subbaraman Narayanamurthy | 841eb43 | 2018-04-10 13:20:56 -0700 | [diff] [blame] | 2031 | if (!lcdb->bst.headroom_mv) |
| 2032 | lcdb->bst.headroom_mv = PM660_BST_HEADROOM_DEFAULT_MV; |
Kiran Gunda | 414471a | 2017-12-07 12:50:51 +0530 | [diff] [blame] | 2033 | } else { |
| 2034 | rc = qpnp_lcdb_read(lcdb, lcdb->base + |
| 2035 | LCDB_BST_SS_CTL_REG, &val, 1); |
| 2036 | if (rc < 0) { |
| 2037 | pr_err("Failed to read bst_soft_start_ctl rc=%d\n", rc); |
| 2038 | return rc; |
| 2039 | } |
| 2040 | lcdb->bst.soft_start_us = soft_start_us[val & SOFT_START_MASK]; |
Subbaraman Narayanamurthy | 841eb43 | 2018-04-10 13:20:56 -0700 | [diff] [blame] | 2041 | if (!lcdb->bst.headroom_mv) |
| 2042 | lcdb->bst.headroom_mv = BST_HEADROOM_DEFAULT_MV; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2043 | } |
Kiran Gunda | bcfca13 | 2017-08-08 16:58:47 +0530 | [diff] [blame] | 2044 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2045 | return 0; |
| 2046 | } |
| 2047 | |
Kiran Gunda | a722892 | 2018-06-27 11:14:21 +0530 | [diff] [blame] | 2048 | static void qpnp_lcdb_pmic_config(struct qpnp_lcdb *lcdb) |
| 2049 | { |
| 2050 | switch (lcdb->pmic_rev_id->pmic_subtype) { |
| 2051 | case PM660L_SUBTYPE: |
| 2052 | if (lcdb->pmic_rev_id->rev4 < PM660L_V2P0_REV4) |
| 2053 | lcdb->wa_flags |= NCP_SCP_DISABLE_WA; |
| 2054 | break; |
| 2055 | default: |
| 2056 | break; |
| 2057 | } |
| 2058 | |
| 2059 | pr_debug("LCDB wa_flags = 0x%2x\n", lcdb->wa_flags); |
| 2060 | } |
| 2061 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2062 | static int qpnp_lcdb_hw_init(struct qpnp_lcdb *lcdb) |
| 2063 | { |
| 2064 | int rc = 0; |
| 2065 | u8 val = 0; |
| 2066 | |
Kiran Gunda | a722892 | 2018-06-27 11:14:21 +0530 | [diff] [blame] | 2067 | qpnp_lcdb_pmic_config(lcdb); |
| 2068 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2069 | rc = qpnp_lcdb_init_bst(lcdb); |
| 2070 | if (rc < 0) { |
| 2071 | pr_err("Failed to initialize BOOST rc=%d\n", rc); |
| 2072 | return rc; |
| 2073 | } |
| 2074 | |
| 2075 | rc = qpnp_lcdb_init_ldo(lcdb); |
| 2076 | if (rc < 0) { |
| 2077 | pr_err("Failed to initialize LDO rc=%d\n", rc); |
| 2078 | return rc; |
| 2079 | } |
| 2080 | |
| 2081 | rc = qpnp_lcdb_init_ncp(lcdb); |
| 2082 | if (rc < 0) { |
| 2083 | pr_err("Failed to initialize NCP rc=%d\n", rc); |
| 2084 | return rc; |
| 2085 | } |
| 2086 | |
Kiran Gunda | a722892 | 2018-06-27 11:14:21 +0530 | [diff] [blame] | 2087 | if (lcdb->sc_irq >= 0 && !(lcdb->wa_flags & NCP_SCP_DISABLE_WA)) { |
Anirudh Ghayal | 264f927 | 2017-03-05 22:34:37 +0530 | [diff] [blame] | 2088 | lcdb->sc_count = 0; |
Kavya Nunna | 80bc150 | 2018-10-01 14:50:23 +0530 | [diff] [blame] | 2089 | irq_set_status_flags(lcdb->sc_irq, |
| 2090 | IRQ_DISABLE_UNLAZY); |
Anirudh Ghayal | 264f927 | 2017-03-05 22:34:37 +0530 | [diff] [blame] | 2091 | rc = devm_request_threaded_irq(lcdb->dev, lcdb->sc_irq, |
| 2092 | NULL, qpnp_lcdb_sc_irq_handler, IRQF_ONESHOT, |
| 2093 | "qpnp_lcdb_sc_irq", lcdb); |
| 2094 | if (rc < 0) { |
| 2095 | pr_err("Unable to request sc(%d) irq rc=%d\n", |
| 2096 | lcdb->sc_irq, rc); |
| 2097 | return rc; |
| 2098 | } |
| 2099 | } |
| 2100 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2101 | if (!is_lcdb_enabled(lcdb)) { |
| 2102 | rc = qpnp_lcdb_read(lcdb, lcdb->base + |
| 2103 | LCDB_MODULE_RDY_REG, &val, 1); |
| 2104 | if (rc < 0) { |
| 2105 | pr_err("Failed to read MODULE_RDY rc=%d\n", rc); |
| 2106 | return rc; |
| 2107 | } |
| 2108 | if (!(val & MODULE_RDY_BIT)) { |
| 2109 | rc = qpnp_lcdb_masked_write(lcdb, lcdb->base + |
| 2110 | LCDB_MODULE_RDY_REG, MODULE_RDY_BIT, |
| 2111 | MODULE_RDY_BIT); |
| 2112 | if (rc < 0) { |
| 2113 | pr_err("Failed to set MODULE RDY rc=%d\n", rc); |
| 2114 | return rc; |
| 2115 | } |
| 2116 | } |
| 2117 | } else { |
| 2118 | /* module already enabled */ |
| 2119 | lcdb->lcdb_enabled = true; |
| 2120 | } |
| 2121 | |
| 2122 | return 0; |
| 2123 | } |
| 2124 | |
| 2125 | static int qpnp_lcdb_parse_dt(struct qpnp_lcdb *lcdb) |
| 2126 | { |
| 2127 | int rc = 0; |
| 2128 | const char *label; |
Anirudh Ghayal | 968862c | 2017-03-31 15:34:05 +0530 | [diff] [blame] | 2129 | struct device_node *revid_dev_node, *temp, *node = lcdb->dev->of_node; |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2130 | |
Anirudh Ghayal | 968862c | 2017-03-31 15:34:05 +0530 | [diff] [blame] | 2131 | revid_dev_node = of_parse_phandle(node, "qcom,pmic-revid", 0); |
| 2132 | if (!revid_dev_node) { |
| 2133 | pr_err("Missing qcom,pmic-revid property - fail driver\n"); |
| 2134 | return -EINVAL; |
| 2135 | } |
| 2136 | |
| 2137 | lcdb->pmic_rev_id = get_revid_data(revid_dev_node); |
| 2138 | if (IS_ERR(lcdb->pmic_rev_id)) { |
| 2139 | pr_debug("Unable to get revid data\n"); |
| 2140 | /* |
| 2141 | * revid should to be defined, return -EPROBE_DEFER |
| 2142 | * until the revid module registers. |
| 2143 | */ |
| 2144 | of_node_put(revid_dev_node); |
| 2145 | return -EPROBE_DEFER; |
| 2146 | } |
| 2147 | |
| 2148 | of_node_put(revid_dev_node); |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 2149 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2150 | for_each_available_child_of_node(node, temp) { |
| 2151 | rc = of_property_read_string(temp, "label", &label); |
| 2152 | if (rc < 0) { |
| 2153 | pr_err("Failed to read label rc=%d\n", rc); |
| 2154 | return rc; |
| 2155 | } |
| 2156 | |
| 2157 | if (!strcmp(label, "ldo")) { |
| 2158 | lcdb->ldo.node = temp; |
| 2159 | rc = qpnp_lcdb_ldo_dt_init(lcdb); |
| 2160 | } else if (!strcmp(label, "ncp")) { |
| 2161 | lcdb->ncp.node = temp; |
| 2162 | rc = qpnp_lcdb_ncp_dt_init(lcdb); |
| 2163 | } else if (!strcmp(label, "bst")) { |
| 2164 | lcdb->bst.node = temp; |
| 2165 | rc = qpnp_lcdb_bst_dt_init(lcdb); |
| 2166 | } else { |
| 2167 | pr_err("Failed to identify label %s\n", label); |
| 2168 | return -EINVAL; |
| 2169 | } |
| 2170 | if (rc < 0) { |
| 2171 | pr_err("Failed to register %s module\n", label); |
| 2172 | return rc; |
| 2173 | } |
| 2174 | } |
| 2175 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2176 | if (of_property_read_bool(node, "qcom,ttw-enable")) { |
| 2177 | rc = qpnp_lcdb_parse_ttw(lcdb); |
| 2178 | if (rc < 0) { |
| 2179 | pr_err("Failed to parse ttw-params rc=%d\n", rc); |
| 2180 | return rc; |
| 2181 | } |
| 2182 | lcdb->ttw_enable = true; |
| 2183 | } |
| 2184 | |
Anirudh Ghayal | 264f927 | 2017-03-05 22:34:37 +0530 | [diff] [blame] | 2185 | lcdb->sc_irq = platform_get_irq_byname(lcdb->pdev, "sc-irq"); |
| 2186 | if (lcdb->sc_irq < 0) |
| 2187 | pr_debug("sc irq is not defined\n"); |
| 2188 | |
Kiran Gunda | 08368b3 | 2018-09-10 18:04:43 +0530 | [diff] [blame] | 2189 | lcdb->voltage_step_ramp = |
| 2190 | of_property_read_bool(node, "qcom,voltage-step-ramp"); |
| 2191 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2192 | return rc; |
| 2193 | } |
| 2194 | |
Kavya Nunna | 80bc150 | 2018-10-01 14:50:23 +0530 | [diff] [blame] | 2195 | static ssize_t qpnp_lcdb_irq_control(struct class *c, |
| 2196 | struct class_attribute *attr, |
| 2197 | const char *buf, size_t count) |
| 2198 | { |
| 2199 | struct qpnp_lcdb *lcdb = container_of(c, struct qpnp_lcdb, |
| 2200 | lcdb_class); |
| 2201 | int val, rc; |
| 2202 | |
| 2203 | rc = kstrtouint(buf, 0, &val); |
| 2204 | |
| 2205 | if (rc < 0) |
| 2206 | return rc; |
| 2207 | |
| 2208 | if (val != 0 && val != 1) |
| 2209 | return count; |
| 2210 | |
| 2211 | if (val == 1 && !lcdb->secure_mode) { |
| 2212 | if (lcdb->sc_irq > 0) |
| 2213 | disable_irq(lcdb->sc_irq); |
| 2214 | |
| 2215 | lcdb->secure_mode = true; |
| 2216 | } else if (val == 0 && lcdb->secure_mode) { |
| 2217 | |
| 2218 | if (lcdb->sc_irq > 0) |
| 2219 | enable_irq(lcdb->sc_irq); |
| 2220 | |
| 2221 | lcdb->secure_mode = false; |
| 2222 | } |
| 2223 | |
| 2224 | return count; |
| 2225 | } |
| 2226 | |
| 2227 | static struct class_attribute lcdb_attributes[] = { |
| 2228 | [0] = __ATTR(secure_mode, 0664, NULL, |
| 2229 | qpnp_lcdb_irq_control), |
| 2230 | __ATTR_NULL, |
| 2231 | }; |
| 2232 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2233 | static int qpnp_lcdb_regulator_probe(struct platform_device *pdev) |
| 2234 | { |
| 2235 | int rc; |
| 2236 | struct device_node *node; |
| 2237 | struct qpnp_lcdb *lcdb; |
| 2238 | |
| 2239 | node = pdev->dev.of_node; |
| 2240 | if (!node) { |
| 2241 | pr_err("No nodes defined\n"); |
| 2242 | return -ENODEV; |
| 2243 | } |
| 2244 | |
| 2245 | lcdb = devm_kzalloc(&pdev->dev, sizeof(*lcdb), GFP_KERNEL); |
| 2246 | if (!lcdb) |
| 2247 | return -ENOMEM; |
| 2248 | |
| 2249 | rc = of_property_read_u32(node, "reg", &lcdb->base); |
| 2250 | if (rc < 0) { |
| 2251 | pr_err("Failed to find reg node rc=%d\n", rc); |
| 2252 | return rc; |
| 2253 | } |
| 2254 | |
| 2255 | lcdb->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
| 2256 | if (!lcdb->regmap) { |
| 2257 | pr_err("Failed to get the regmap handle rc=%d\n", rc); |
| 2258 | return -EINVAL; |
| 2259 | } |
| 2260 | |
| 2261 | lcdb->dev = &pdev->dev; |
| 2262 | lcdb->pdev = pdev; |
| 2263 | mutex_init(&lcdb->lcdb_mutex); |
| 2264 | mutex_init(&lcdb->read_write_mutex); |
| 2265 | |
| 2266 | rc = qpnp_lcdb_parse_dt(lcdb); |
| 2267 | if (rc < 0) { |
| 2268 | pr_err("Failed to parse dt rc=%d\n", rc); |
| 2269 | return rc; |
| 2270 | } |
| 2271 | |
Kavya Nunna | 80bc150 | 2018-10-01 14:50:23 +0530 | [diff] [blame] | 2272 | lcdb->lcdb_class.name = "lcd_bias"; |
| 2273 | lcdb->lcdb_class.owner = THIS_MODULE; |
| 2274 | lcdb->lcdb_class.class_attrs = lcdb_attributes; |
| 2275 | |
| 2276 | rc = class_register(&lcdb->lcdb_class); |
| 2277 | if (rc < 0) { |
| 2278 | pr_err("Failed to register lcdb class rc = %d\n", rc); |
| 2279 | return rc; |
| 2280 | } |
| 2281 | |
David Collins | 8885f79 | 2017-01-26 14:36:34 -0800 | [diff] [blame] | 2282 | rc = qpnp_lcdb_hw_init(lcdb); |
| 2283 | if (rc < 0) |
| 2284 | pr_err("Failed to initialize LCDB module rc=%d\n", rc); |
| 2285 | else |
| 2286 | pr_info("LCDB module successfully registered! lcdb_en=%d ldo_voltage=%dmV ncp_voltage=%dmV bst_voltage=%dmV\n", |
| 2287 | lcdb->lcdb_enabled, lcdb->ldo.voltage_mv, |
| 2288 | lcdb->ncp.voltage_mv, lcdb->bst.voltage_mv); |
| 2289 | |
| 2290 | return rc; |
| 2291 | } |
| 2292 | |
| 2293 | static int qpnp_lcdb_regulator_remove(struct platform_device *pdev) |
| 2294 | { |
| 2295 | struct qpnp_lcdb *lcdb = dev_get_drvdata(&pdev->dev); |
| 2296 | |
| 2297 | mutex_destroy(&lcdb->lcdb_mutex); |
| 2298 | mutex_destroy(&lcdb->read_write_mutex); |
| 2299 | |
| 2300 | return 0; |
| 2301 | } |
| 2302 | |
| 2303 | static const struct of_device_id lcdb_match_table[] = { |
| 2304 | { .compatible = QPNP_LCDB_REGULATOR_DRIVER_NAME, }, |
| 2305 | { }, |
| 2306 | }; |
| 2307 | |
| 2308 | static struct platform_driver qpnp_lcdb_regulator_driver = { |
| 2309 | .driver = { |
| 2310 | .name = QPNP_LCDB_REGULATOR_DRIVER_NAME, |
| 2311 | .of_match_table = lcdb_match_table, |
| 2312 | }, |
| 2313 | .probe = qpnp_lcdb_regulator_probe, |
| 2314 | .remove = qpnp_lcdb_regulator_remove, |
| 2315 | }; |
| 2316 | |
| 2317 | static int __init qpnp_lcdb_regulator_init(void) |
| 2318 | { |
| 2319 | return platform_driver_register(&qpnp_lcdb_regulator_driver); |
| 2320 | } |
| 2321 | arch_initcall(qpnp_lcdb_regulator_init); |
| 2322 | |
| 2323 | static void __exit qpnp_lcdb_regulator_exit(void) |
| 2324 | { |
| 2325 | platform_driver_unregister(&qpnp_lcdb_regulator_driver); |
| 2326 | } |
| 2327 | module_exit(qpnp_lcdb_regulator_exit); |
| 2328 | |
| 2329 | MODULE_DESCRIPTION("QPNP LCDB regulator driver"); |
| 2330 | MODULE_LICENSE("GPL v2"); |