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gerrit-public.fairphone.software / kernel / msm-4.9 / b0f7b8bc57ee90138a7c429951457027a90c326f / . / arch / ppc / platforms / 4xx / ppc440spe.c
blob: 6139a0b3393e15291e84d77ce7fe11861d20edb8 [file] [log] [blame]
Roland Dreierb0f7b8b2005-11-07 00:58:13 -0800[diff] [blame^]1/*
2 * arch/ppc/platforms/4xx/ppc440spe.c
3 *
4 * PPC440SPe I/O descriptions
5 *
6 * Roland Dreier <rolandd@cisco.com>
7 * Copyright (c) 2005 Cisco Systems. All rights reserved.
8 *
9 * Matt Porter <mporter@kernel.crashing.org>
10 * Copyright 2002-2005 MontaVista Software Inc.
11 *
12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
13 * Copyright (c) 2003, 2004 Zultys Technologies
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 */
21#include <linux/init.h>
22#include <linux/module.h>
23#include <platforms/4xx/ppc440spe.h>
24#include <asm/ocp.h>
25#include <asm/ppc4xx_pic.h>
26
27static struct ocp_func_emac_data ppc440spe_emac0_def = {
28 .rgmii_idx = -1, /* No RGMII */
29 .rgmii_mux = -1, /* No RGMII */
30 .zmii_idx = -1, /* No ZMII */
31 .zmii_mux = -1, /* No ZMII */
32 .mal_idx = 0, /* MAL device index */
33 .mal_rx_chan = 0, /* MAL rx channel number */
34 .mal_tx_chan = 0, /* MAL tx channel number */
35 .wol_irq = 61, /* WOL interrupt number */
36 .mdio_idx = -1, /* No shared MDIO */
37 .tah_idx = -1, /* No TAH */
38};
39OCP_SYSFS_EMAC_DATA()
40
41static struct ocp_func_mal_data ppc440spe_mal0_def = {
42 .num_tx_chans = 1, /* Number of TX channels */
43 .num_rx_chans = 1, /* Number of RX channels */
44 .txeob_irq = 38, /* TX End Of Buffer IRQ */
45 .rxeob_irq = 39, /* RX End Of Buffer IRQ */
46 .txde_irq = 34, /* TX Descriptor Error IRQ */
47 .rxde_irq = 35, /* RX Descriptor Error IRQ */
48 .serr_irq = 33, /* MAL System Error IRQ */
49 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
50};
51OCP_SYSFS_MAL_DATA()
52
53static struct ocp_func_iic_data ppc440spe_iic0_def = {
54 .fast_mode = 0, /* Use standad mode (100Khz) */
55};
56
57static struct ocp_func_iic_data ppc440spe_iic1_def = {
58 .fast_mode = 0, /* Use standad mode (100Khz) */
59};
60OCP_SYSFS_IIC_DATA()
61
62struct ocp_def core_ocp[] = {
63 { .vendor = OCP_VENDOR_IBM,
64 .function = OCP_FUNC_16550,
65 .index = 0,
66 .paddr = PPC440SPE_UART0_ADDR,
67 .irq = UART0_INT,
68 .pm = IBM_CPM_UART0,
69 },
70 { .vendor = OCP_VENDOR_IBM,
71 .function = OCP_FUNC_16550,
72 .index = 1,
73 .paddr = PPC440SPE_UART1_ADDR,
74 .irq = UART1_INT,
75 .pm = IBM_CPM_UART1,
76 },
77 { .vendor = OCP_VENDOR_IBM,
78 .function = OCP_FUNC_16550,
79 .index = 2,
80 .paddr = PPC440SPE_UART2_ADDR,
81 .irq = UART2_INT,
82 .pm = IBM_CPM_UART2,
83 },
84 { .vendor = OCP_VENDOR_IBM,
85 .function = OCP_FUNC_IIC,
86 .index = 0,
87 .paddr = 0x00000004f0000400ULL,
88 .irq = 2,
89 .pm = IBM_CPM_IIC0,
90 .additions = &ppc440spe_iic0_def,
91 .show = &ocp_show_iic_data
92 },
93 { .vendor = OCP_VENDOR_IBM,
94 .function = OCP_FUNC_IIC,
95 .index = 1,
96 .paddr = 0x00000004f0000500ULL,
97 .irq = 3,
98 .pm = IBM_CPM_IIC1,
99 .additions = &ppc440spe_iic1_def,
100 .show = &ocp_show_iic_data
101 },
102 { .vendor = OCP_VENDOR_IBM,
103 .function = OCP_FUNC_GPIO,
104 .index = 0,
105 .paddr = 0x00000004f0000700ULL,
106 .irq = OCP_IRQ_NA,
107 .pm = IBM_CPM_GPIO0,
108 },
109 { .vendor = OCP_VENDOR_IBM,
110 .function = OCP_FUNC_MAL,
111 .paddr = OCP_PADDR_NA,
112 .irq = OCP_IRQ_NA,
113 .pm = OCP_CPM_NA,
114 .additions = &ppc440spe_mal0_def,
115 .show = &ocp_show_mal_data,
116 },
117 { .vendor = OCP_VENDOR_IBM,
118 .function = OCP_FUNC_EMAC,
119 .index = 0,
120 .paddr = 0x00000004f0000800ULL,
121 .irq = 60,
122 .pm = OCP_CPM_NA,
123 .additions = &ppc440spe_emac0_def,
124 .show = &ocp_show_emac_data,
125 },
126 { .vendor = OCP_VENDOR_INVALID
127 }
128};
129
130/* Polarity and triggering settings for internal interrupt sources */
131struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
132 { .polarity = 0xffffffff,
133 .triggering = 0x010f0004,
134 .ext_irq_mask = 0x00000000,
135 },
136 { .polarity = 0xffffffff,
137 .triggering = 0x001f8040,
138 .ext_irq_mask = 0x00007c30, /* IRQ6 - IRQ7, IRQ8 - IRQ12 */
139 },
140 { .polarity = 0xffffffff,
141 .triggering = 0x00000000,
142 .ext_irq_mask = 0x000000fc, /* IRQ0 - IRQ5 */
143 },
144 { .polarity = 0xffffffff,
145 .triggering = 0x00000000,
146 .ext_irq_mask = 0x00000000,
147 },
148};